2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/platform_data/omap_ocp2scp.h>
25 #include <linux/i2c-omap.h>
27 #include <linux/omap-dma.h>
29 #include <linux/platform_data/spi-omap2-mcspi.h>
30 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <linux/platform_data/iommu-omap.h>
32 #include <plat/dmtimer.h>
34 #include "omap_hwmod.h"
35 #include "omap_hwmod_common_data.h"
39 #include "prm-regbits-44xx.h"
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START 32
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START 1
55 * 'c2c_target_fw' class
56 * instance(s): c2c_target_fw
58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
59 .name = "c2c_target_fw",
63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
64 .name = "c2c_target_fw",
65 .class = &omap44xx_c2c_target_fw_hwmod_class,
66 .clkdm_name = "d2d_clkdm",
69 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
70 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
85 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
89 static struct omap_hwmod omap44xx_dmm_hwmod = {
91 .class = &omap44xx_dmm_hwmod_class,
92 .clkdm_name = "l3_emif_clkdm",
93 .mpu_irqs = omap44xx_dmm_irqs,
96 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
97 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
104 * instance(s): emif_fw
106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
113 .class = &omap44xx_emif_fw_hwmod_class,
114 .clkdm_name = "l3_emif_clkdm",
117 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
118 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
125 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
134 .class = &omap44xx_l3_hwmod_class,
135 .clkdm_name = "l3_instr_clkdm",
138 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
139 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
140 .modulemode = MODULEMODE_HWCTRL,
146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
147 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
148 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
154 .class = &omap44xx_l3_hwmod_class,
155 .clkdm_name = "l3_1_clkdm",
156 .mpu_irqs = omap44xx_l3_main_1_irqs,
159 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
160 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
168 .class = &omap44xx_l3_hwmod_class,
169 .clkdm_name = "l3_2_clkdm",
172 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
173 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
181 .class = &omap44xx_l3_hwmod_class,
182 .clkdm_name = "l3_instr_clkdm",
185 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
186 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
187 .modulemode = MODULEMODE_HWCTRL,
194 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
203 .class = &omap44xx_l4_hwmod_class,
204 .clkdm_name = "abe_clkdm",
207 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
208 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
209 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
210 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
218 .class = &omap44xx_l4_hwmod_class,
219 .clkdm_name = "l4_cfg_clkdm",
222 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
223 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
231 .class = &omap44xx_l4_hwmod_class,
232 .clkdm_name = "l4_per_clkdm",
235 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
236 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
244 .class = &omap44xx_l4_hwmod_class,
245 .clkdm_name = "l4_wkup_clkdm",
248 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
249 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
256 * instance(s): mpu_private
258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
264 .name = "mpu_private",
265 .class = &omap44xx_mpu_bus_hwmod_class,
266 .clkdm_name = "mpuss_clkdm",
269 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
276 * instance(s): ocp_wp_noc
278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
279 .name = "ocp_wp_noc",
283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
284 .name = "ocp_wp_noc",
285 .class = &omap44xx_ocp_wp_noc_hwmod_class,
286 .clkdm_name = "l3_instr_clkdm",
289 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
290 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
291 .modulemode = MODULEMODE_HWCTRL,
297 * Modules omap_hwmod structures
299 * The following IPs are excluded for the moment because:
300 * - They do not need an explicit SW control using omap_hwmod API.
301 * - They still need to be validated with the driver
302 * properly adapted to omap_hwmod / omap_device
309 * audio engine sub system
312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
315 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
316 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
317 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
318 MSTANDBY_SMART_WKUP),
319 .sysc_fields = &omap_hwmod_sysc_type2,
322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
324 .sysc = &omap44xx_aess_sysc,
328 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
329 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
333 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
334 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
335 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
336 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
337 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
338 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
339 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
340 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
341 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
345 static struct omap_hwmod omap44xx_aess_hwmod = {
347 .class = &omap44xx_aess_hwmod_class,
348 .clkdm_name = "abe_clkdm",
349 .mpu_irqs = omap44xx_aess_irqs,
350 .sdma_reqs = omap44xx_aess_sdma_reqs,
351 .main_clk = "aess_fck",
354 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
355 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
356 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
357 .modulemode = MODULEMODE_SWCTRL,
364 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
368 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
373 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
374 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
378 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
379 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
383 static struct omap_hwmod omap44xx_c2c_hwmod = {
385 .class = &omap44xx_c2c_hwmod_class,
386 .clkdm_name = "d2d_clkdm",
387 .mpu_irqs = omap44xx_c2c_irqs,
388 .sdma_reqs = omap44xx_c2c_sdma_reqs,
391 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
392 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
399 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
402 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
405 .sysc_flags = SYSC_HAS_SIDLEMODE,
406 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
407 .sysc_fields = &omap_hwmod_sysc_type1,
410 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
412 .sysc = &omap44xx_counter_sysc,
416 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
417 .name = "counter_32k",
418 .class = &omap44xx_counter_hwmod_class,
419 .clkdm_name = "l4_wkup_clkdm",
420 .flags = HWMOD_SWSUP_SIDLE,
421 .main_clk = "sys_32k_ck",
424 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
425 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
431 * 'ctrl_module' class
432 * attila core control module + core pad control module + wkup pad control
433 * module + attila wkup control module
436 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
439 .sysc_flags = SYSC_HAS_SIDLEMODE,
440 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
442 .sysc_fields = &omap_hwmod_sysc_type2,
445 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
446 .name = "ctrl_module",
447 .sysc = &omap44xx_ctrl_module_sysc,
450 /* ctrl_module_core */
451 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
452 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
456 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
457 .name = "ctrl_module_core",
458 .class = &omap44xx_ctrl_module_hwmod_class,
459 .clkdm_name = "l4_cfg_clkdm",
460 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
463 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
468 /* ctrl_module_pad_core */
469 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
470 .name = "ctrl_module_pad_core",
471 .class = &omap44xx_ctrl_module_hwmod_class,
472 .clkdm_name = "l4_cfg_clkdm",
475 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
480 /* ctrl_module_wkup */
481 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
482 .name = "ctrl_module_wkup",
483 .class = &omap44xx_ctrl_module_hwmod_class,
484 .clkdm_name = "l4_wkup_clkdm",
487 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
492 /* ctrl_module_pad_wkup */
493 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
494 .name = "ctrl_module_pad_wkup",
495 .class = &omap44xx_ctrl_module_hwmod_class,
496 .clkdm_name = "l4_wkup_clkdm",
499 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
506 * debug and emulation sub system
509 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
514 static struct omap_hwmod omap44xx_debugss_hwmod = {
516 .class = &omap44xx_debugss_hwmod_class,
517 .clkdm_name = "emu_sys_clkdm",
518 .main_clk = "trace_clk_div_ck",
521 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
522 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
529 * dma controller for data exchange between memory to memory (i.e. internal or
530 * external memory) and gp peripherals to memory or memory to gp peripherals
533 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
537 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
538 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
539 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
540 SYSS_HAS_RESET_STATUS),
541 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
542 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
543 .sysc_fields = &omap_hwmod_sysc_type1,
546 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
548 .sysc = &omap44xx_dma_sysc,
552 static struct omap_dma_dev_attr dma_dev_attr = {
553 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
554 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
559 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
560 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
561 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
562 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
563 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
567 static struct omap_hwmod omap44xx_dma_system_hwmod = {
568 .name = "dma_system",
569 .class = &omap44xx_dma_hwmod_class,
570 .clkdm_name = "l3_dma_clkdm",
571 .mpu_irqs = omap44xx_dma_system_irqs,
572 .main_clk = "l3_div_ck",
575 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
576 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
579 .dev_attr = &dma_dev_attr,
584 * digital microphone controller
587 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
590 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
591 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
592 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
594 .sysc_fields = &omap_hwmod_sysc_type2,
597 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
599 .sysc = &omap44xx_dmic_sysc,
603 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
604 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
608 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
609 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
613 static struct omap_hwmod omap44xx_dmic_hwmod = {
615 .class = &omap44xx_dmic_hwmod_class,
616 .clkdm_name = "abe_clkdm",
617 .mpu_irqs = omap44xx_dmic_irqs,
618 .sdma_reqs = omap44xx_dmic_sdma_reqs,
619 .main_clk = "dmic_fck",
622 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
623 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
624 .modulemode = MODULEMODE_SWCTRL,
634 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
639 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
640 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
644 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
645 { .name = "dsp", .rst_shift = 0 },
648 static struct omap_hwmod omap44xx_dsp_hwmod = {
650 .class = &omap44xx_dsp_hwmod_class,
651 .clkdm_name = "tesla_clkdm",
652 .mpu_irqs = omap44xx_dsp_irqs,
653 .rst_lines = omap44xx_dsp_resets,
654 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
655 .main_clk = "dpll_iva_m4x2_ck",
658 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
659 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
660 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
661 .modulemode = MODULEMODE_HWCTRL,
671 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
674 .sysc_flags = SYSS_HAS_RESET_STATUS,
677 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
679 .sysc = &omap44xx_dss_sysc,
680 .reset = omap_dss_reset,
684 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
685 { .role = "sys_clk", .clk = "dss_sys_clk" },
686 { .role = "tv_clk", .clk = "dss_tv_clk" },
687 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
690 static struct omap_hwmod omap44xx_dss_hwmod = {
692 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
693 .class = &omap44xx_dss_hwmod_class,
694 .clkdm_name = "l3_dss_clkdm",
695 .main_clk = "dss_dss_clk",
698 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
699 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
702 .opt_clks = dss_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
711 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
715 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
716 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
717 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
718 SYSS_HAS_RESET_STATUS),
719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
720 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
721 .sysc_fields = &omap_hwmod_sysc_type1,
724 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
726 .sysc = &omap44xx_dispc_sysc,
730 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
731 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
735 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
736 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
740 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
742 .has_framedonetv_irq = 1
745 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
747 .class = &omap44xx_dispc_hwmod_class,
748 .clkdm_name = "l3_dss_clkdm",
749 .mpu_irqs = omap44xx_dss_dispc_irqs,
750 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
751 .main_clk = "dss_dss_clk",
754 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
755 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
758 .dev_attr = &omap44xx_dss_dispc_dev_attr
763 * display serial interface controller
766 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
770 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
771 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
772 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
773 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
774 .sysc_fields = &omap_hwmod_sysc_type1,
777 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
779 .sysc = &omap44xx_dsi_sysc,
783 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
784 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
788 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
789 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
793 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
794 { .role = "sys_clk", .clk = "dss_sys_clk" },
797 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
799 .class = &omap44xx_dsi_hwmod_class,
800 .clkdm_name = "l3_dss_clkdm",
801 .mpu_irqs = omap44xx_dss_dsi1_irqs,
802 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
803 .main_clk = "dss_dss_clk",
806 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
807 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
810 .opt_clks = dss_dsi1_opt_clks,
811 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
815 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
816 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
820 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
821 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
825 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
826 { .role = "sys_clk", .clk = "dss_sys_clk" },
829 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
831 .class = &omap44xx_dsi_hwmod_class,
832 .clkdm_name = "l3_dss_clkdm",
833 .mpu_irqs = omap44xx_dss_dsi2_irqs,
834 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
835 .main_clk = "dss_dss_clk",
838 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
839 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
842 .opt_clks = dss_dsi2_opt_clks,
843 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
851 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
854 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
856 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
858 .sysc_fields = &omap_hwmod_sysc_type2,
861 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
863 .sysc = &omap44xx_hdmi_sysc,
867 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
868 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
872 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
873 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
877 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
878 { .role = "sys_clk", .clk = "dss_sys_clk" },
881 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
883 .class = &omap44xx_hdmi_hwmod_class,
884 .clkdm_name = "l3_dss_clkdm",
886 * HDMI audio requires to use no-idle mode. Hence,
887 * set idle mode by software.
889 .flags = HWMOD_SWSUP_SIDLE,
890 .mpu_irqs = omap44xx_dss_hdmi_irqs,
891 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
892 .main_clk = "dss_48mhz_clk",
895 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
896 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
899 .opt_clks = dss_hdmi_opt_clks,
900 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
905 * remote frame buffer interface
908 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
912 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
913 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
914 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
915 .sysc_fields = &omap_hwmod_sysc_type1,
918 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
920 .sysc = &omap44xx_rfbi_sysc,
924 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
925 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
929 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
930 { .role = "ick", .clk = "dss_fck" },
933 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
935 .class = &omap44xx_rfbi_hwmod_class,
936 .clkdm_name = "l3_dss_clkdm",
937 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
938 .main_clk = "dss_dss_clk",
941 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
942 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
945 .opt_clks = dss_rfbi_opt_clks,
946 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
954 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
959 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
961 .class = &omap44xx_venc_hwmod_class,
962 .clkdm_name = "l3_dss_clkdm",
963 .main_clk = "dss_tv_clk",
966 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
967 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
974 * bch error location module
977 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
981 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
982 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
983 SYSS_HAS_RESET_STATUS),
984 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
985 .sysc_fields = &omap_hwmod_sysc_type1,
988 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
990 .sysc = &omap44xx_elm_sysc,
994 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
995 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
999 static struct omap_hwmod omap44xx_elm_hwmod = {
1001 .class = &omap44xx_elm_hwmod_class,
1002 .clkdm_name = "l4_per_clkdm",
1003 .mpu_irqs = omap44xx_elm_irqs,
1006 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1007 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1014 * external memory interface no1
1017 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1021 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1023 .sysc = &omap44xx_emif_sysc,
1027 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1028 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1032 static struct omap_hwmod omap44xx_emif1_hwmod = {
1034 .class = &omap44xx_emif_hwmod_class,
1035 .clkdm_name = "l3_emif_clkdm",
1036 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1037 .mpu_irqs = omap44xx_emif1_irqs,
1038 .main_clk = "ddrphy_ck",
1041 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1042 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1043 .modulemode = MODULEMODE_HWCTRL,
1049 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1050 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1054 static struct omap_hwmod omap44xx_emif2_hwmod = {
1056 .class = &omap44xx_emif_hwmod_class,
1057 .clkdm_name = "l3_emif_clkdm",
1058 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1059 .mpu_irqs = omap44xx_emif2_irqs,
1060 .main_clk = "ddrphy_ck",
1063 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1064 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1065 .modulemode = MODULEMODE_HWCTRL,
1072 * face detection hw accelerator module
1075 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1077 .sysc_offs = 0x0010,
1079 * FDIF needs 100 OCP clk cycles delay after a softreset before
1080 * accessing sysconfig again.
1081 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1082 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1084 * TODO: Indicate errata when available.
1087 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1088 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1089 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091 .sysc_fields = &omap_hwmod_sysc_type2,
1094 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1096 .sysc = &omap44xx_fdif_sysc,
1100 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1101 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1105 static struct omap_hwmod omap44xx_fdif_hwmod = {
1107 .class = &omap44xx_fdif_hwmod_class,
1108 .clkdm_name = "iss_clkdm",
1109 .mpu_irqs = omap44xx_fdif_irqs,
1110 .main_clk = "fdif_fck",
1113 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1114 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1115 .modulemode = MODULEMODE_SWCTRL,
1122 * general purpose io module
1125 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1127 .sysc_offs = 0x0010,
1128 .syss_offs = 0x0114,
1129 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1130 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1131 SYSS_HAS_RESET_STATUS),
1132 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1134 .sysc_fields = &omap_hwmod_sysc_type1,
1137 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1139 .sysc = &omap44xx_gpio_sysc,
1144 static struct omap_gpio_dev_attr gpio_dev_attr = {
1150 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1151 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1155 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1156 { .role = "dbclk", .clk = "gpio1_dbclk" },
1159 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161 .class = &omap44xx_gpio_hwmod_class,
1162 .clkdm_name = "l4_wkup_clkdm",
1163 .mpu_irqs = omap44xx_gpio1_irqs,
1164 .main_clk = "gpio1_ick",
1167 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1168 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1169 .modulemode = MODULEMODE_HWCTRL,
1172 .opt_clks = gpio1_opt_clks,
1173 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1174 .dev_attr = &gpio_dev_attr,
1178 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1179 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1183 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1184 { .role = "dbclk", .clk = "gpio2_dbclk" },
1187 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1189 .class = &omap44xx_gpio_hwmod_class,
1190 .clkdm_name = "l4_per_clkdm",
1191 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192 .mpu_irqs = omap44xx_gpio2_irqs,
1193 .main_clk = "gpio2_ick",
1196 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1197 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1198 .modulemode = MODULEMODE_HWCTRL,
1201 .opt_clks = gpio2_opt_clks,
1202 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1203 .dev_attr = &gpio_dev_attr,
1207 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1208 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1212 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1213 { .role = "dbclk", .clk = "gpio3_dbclk" },
1216 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1218 .class = &omap44xx_gpio_hwmod_class,
1219 .clkdm_name = "l4_per_clkdm",
1220 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221 .mpu_irqs = omap44xx_gpio3_irqs,
1222 .main_clk = "gpio3_ick",
1225 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1226 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_HWCTRL,
1230 .opt_clks = gpio3_opt_clks,
1231 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1232 .dev_attr = &gpio_dev_attr,
1236 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1237 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1241 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1242 { .role = "dbclk", .clk = "gpio4_dbclk" },
1245 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1247 .class = &omap44xx_gpio_hwmod_class,
1248 .clkdm_name = "l4_per_clkdm",
1249 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250 .mpu_irqs = omap44xx_gpio4_irqs,
1251 .main_clk = "gpio4_ick",
1254 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1255 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1256 .modulemode = MODULEMODE_HWCTRL,
1259 .opt_clks = gpio4_opt_clks,
1260 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1261 .dev_attr = &gpio_dev_attr,
1265 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1266 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1270 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1271 { .role = "dbclk", .clk = "gpio5_dbclk" },
1274 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1276 .class = &omap44xx_gpio_hwmod_class,
1277 .clkdm_name = "l4_per_clkdm",
1278 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279 .mpu_irqs = omap44xx_gpio5_irqs,
1280 .main_clk = "gpio5_ick",
1283 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1284 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_HWCTRL,
1288 .opt_clks = gpio5_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1290 .dev_attr = &gpio_dev_attr,
1294 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1295 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1299 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1300 { .role = "dbclk", .clk = "gpio6_dbclk" },
1303 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1305 .class = &omap44xx_gpio_hwmod_class,
1306 .clkdm_name = "l4_per_clkdm",
1307 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1308 .mpu_irqs = omap44xx_gpio6_irqs,
1309 .main_clk = "gpio6_ick",
1312 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1313 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1314 .modulemode = MODULEMODE_HWCTRL,
1317 .opt_clks = gpio6_opt_clks,
1318 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1319 .dev_attr = &gpio_dev_attr,
1324 * general purpose memory controller
1327 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1329 .sysc_offs = 0x0010,
1330 .syss_offs = 0x0014,
1331 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1332 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1333 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1334 .sysc_fields = &omap_hwmod_sysc_type1,
1337 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1339 .sysc = &omap44xx_gpmc_sysc,
1343 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1344 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1348 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1349 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1353 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355 .class = &omap44xx_gpmc_hwmod_class,
1356 .clkdm_name = "l3_2_clkdm",
1358 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1359 * block. It is not being added due to any known bugs with
1360 * resetting the GPMC IP block, but rather because any timings
1361 * set by the bootloader are not being correctly programmed by
1362 * the kernel from the board file or DT data.
1363 * HWMOD_INIT_NO_RESET should be removed ASAP.
1365 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1366 .mpu_irqs = omap44xx_gpmc_irqs,
1367 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1370 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1371 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1372 .modulemode = MODULEMODE_HWCTRL,
1379 * 2d/3d graphics accelerator
1382 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1383 .rev_offs = 0x1fc00,
1384 .sysc_offs = 0x1fc10,
1385 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1386 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1387 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1388 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1389 .sysc_fields = &omap_hwmod_sysc_type2,
1392 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1394 .sysc = &omap44xx_gpu_sysc,
1398 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1399 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1403 static struct omap_hwmod omap44xx_gpu_hwmod = {
1405 .class = &omap44xx_gpu_hwmod_class,
1406 .clkdm_name = "l3_gfx_clkdm",
1407 .mpu_irqs = omap44xx_gpu_irqs,
1408 .main_clk = "gpu_fck",
1411 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1412 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1413 .modulemode = MODULEMODE_SWCTRL,
1420 * hdq / 1-wire serial interface controller
1423 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1425 .sysc_offs = 0x0014,
1426 .syss_offs = 0x0018,
1427 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1428 SYSS_HAS_RESET_STATUS),
1429 .sysc_fields = &omap_hwmod_sysc_type1,
1432 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1434 .sysc = &omap44xx_hdq1w_sysc,
1438 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1439 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1443 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445 .class = &omap44xx_hdq1w_hwmod_class,
1446 .clkdm_name = "l4_per_clkdm",
1447 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1448 .mpu_irqs = omap44xx_hdq1w_irqs,
1449 .main_clk = "hdq1w_fck",
1452 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1453 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1454 .modulemode = MODULEMODE_SWCTRL,
1461 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1465 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1467 .sysc_offs = 0x0010,
1468 .syss_offs = 0x0014,
1469 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1470 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1471 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1472 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1474 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1475 .sysc_fields = &omap_hwmod_sysc_type1,
1478 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1480 .sysc = &omap44xx_hsi_sysc,
1484 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1485 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1486 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1487 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1491 static struct omap_hwmod omap44xx_hsi_hwmod = {
1493 .class = &omap44xx_hsi_hwmod_class,
1494 .clkdm_name = "l3_init_clkdm",
1495 .mpu_irqs = omap44xx_hsi_irqs,
1496 .main_clk = "hsi_fck",
1499 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1500 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1501 .modulemode = MODULEMODE_HWCTRL,
1508 * multimaster high-speed i2c controller
1511 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1512 .sysc_offs = 0x0010,
1513 .syss_offs = 0x0090,
1514 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1515 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1516 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1517 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1519 .clockact = CLOCKACT_TEST_ICLK,
1520 .sysc_fields = &omap_hwmod_sysc_type1,
1523 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1525 .sysc = &omap44xx_i2c_sysc,
1526 .rev = OMAP_I2C_IP_VERSION_2,
1527 .reset = &omap_i2c_reset,
1530 static struct omap_i2c_dev_attr i2c_dev_attr = {
1531 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548 .class = &omap44xx_i2c_hwmod_class,
1549 .clkdm_name = "l4_per_clkdm",
1550 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551 .mpu_irqs = omap44xx_i2c1_irqs,
1552 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1553 .main_clk = "i2c1_fck",
1556 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558 .modulemode = MODULEMODE_SWCTRL,
1561 .dev_attr = &i2c_dev_attr,
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578 .class = &omap44xx_i2c_hwmod_class,
1579 .clkdm_name = "l4_per_clkdm",
1580 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581 .mpu_irqs = omap44xx_i2c2_irqs,
1582 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1583 .main_clk = "i2c2_fck",
1586 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588 .modulemode = MODULEMODE_SWCTRL,
1591 .dev_attr = &i2c_dev_attr,
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608 .class = &omap44xx_i2c_hwmod_class,
1609 .clkdm_name = "l4_per_clkdm",
1610 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611 .mpu_irqs = omap44xx_i2c3_irqs,
1612 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1613 .main_clk = "i2c3_fck",
1616 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618 .modulemode = MODULEMODE_SWCTRL,
1621 .dev_attr = &i2c_dev_attr,
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638 .class = &omap44xx_i2c_hwmod_class,
1639 .clkdm_name = "l4_per_clkdm",
1640 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641 .mpu_irqs = omap44xx_i2c4_irqs,
1642 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1643 .main_clk = "i2c4_fck",
1646 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648 .modulemode = MODULEMODE_SWCTRL,
1651 .dev_attr = &i2c_dev_attr,
1656 * imaging processor unit
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670 { .name = "cpu0", .rst_shift = 0 },
1671 { .name = "cpu1", .rst_shift = 1 },
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676 .class = &omap44xx_ipu_hwmod_class,
1677 .clkdm_name = "ducati_clkdm",
1678 .mpu_irqs = omap44xx_ipu_irqs,
1679 .rst_lines = omap44xx_ipu_resets,
1680 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1681 .main_clk = "ducati_clk_mux_ck",
1684 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687 .modulemode = MODULEMODE_HWCTRL,
1694 * external images sensor pixel data processor
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699 .sysc_offs = 0x0010,
1701 * ISS needs 100 OCP clk cycles delay after a softreset before
1702 * accessing sysconfig again.
1703 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706 * TODO: Indicate errata when available.
1709 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714 .sysc_fields = &omap_hwmod_sysc_type2,
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719 .sysc = &omap44xx_iss_sysc,
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1742 .class = &omap44xx_iss_hwmod_class,
1743 .clkdm_name = "iss_clkdm",
1744 .mpu_irqs = omap44xx_iss_irqs,
1745 .sdma_reqs = omap44xx_iss_sdma_reqs,
1746 .main_clk = "iss_fck",
1749 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751 .modulemode = MODULEMODE_SWCTRL,
1754 .opt_clks = iss_opt_clks,
1755 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1760 * multi-standard video encoder/decoder hardware accelerator
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776 { .name = "seq0", .rst_shift = 0 },
1777 { .name = "seq1", .rst_shift = 1 },
1778 { .name = "logic", .rst_shift = 2 },
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1783 .class = &omap44xx_iva_hwmod_class,
1784 .clkdm_name = "ivahd_clkdm",
1785 .mpu_irqs = omap44xx_iva_irqs,
1786 .rst_lines = omap44xx_iva_resets,
1787 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1788 .main_clk = "iva_fck",
1791 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794 .modulemode = MODULEMODE_HWCTRL,
1801 * keyboard controller
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806 .sysc_offs = 0x0010,
1807 .syss_offs = 0x0014,
1808 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811 SYSS_HAS_RESET_STATUS),
1812 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813 .sysc_fields = &omap_hwmod_sysc_type1,
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818 .sysc = &omap44xx_kbd_sysc,
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829 .class = &omap44xx_kbd_hwmod_class,
1830 .clkdm_name = "l4_wkup_clkdm",
1831 .mpu_irqs = omap44xx_kbd_irqs,
1832 .main_clk = "kbd_fck",
1835 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837 .modulemode = MODULEMODE_SWCTRL,
1844 * mailbox module allowing communication between the on-chip processors using a
1845 * queued mailbox-interrupt mechanism.
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850 .sysc_offs = 0x0010,
1851 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852 SYSC_HAS_SOFTRESET),
1853 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854 .sysc_fields = &omap_hwmod_sysc_type2,
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859 .sysc = &omap44xx_mailbox_sysc,
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870 .class = &omap44xx_mailbox_hwmod_class,
1871 .clkdm_name = "l4_cfg_clkdm",
1872 .mpu_irqs = omap44xx_mailbox_irqs,
1875 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1883 * multi-channel audio serial port controller
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892 .sysc_offs = 0x0004,
1893 .sysc_flags = SYSC_HAS_SIDLEMODE,
1894 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901 .sysc = &omap44xx_mcasp_sysc,
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919 .class = &omap44xx_mcasp_hwmod_class,
1920 .clkdm_name = "abe_clkdm",
1921 .mpu_irqs = omap44xx_mcasp_irqs,
1922 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1923 .main_clk = "mcasp_fck",
1926 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928 .modulemode = MODULEMODE_SWCTRL,
1935 * multi channel buffered serial port controller
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939 .sysc_offs = 0x008c,
1940 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943 .sysc_fields = &omap_hwmod_sysc_type1,
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948 .sysc = &omap44xx_mcbsp_sysc,
1949 .rev = MCBSP_CONFIG_TYPE4,
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965 { .role = "pad_fck", .clk = "pad_clks_ck" },
1966 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971 .class = &omap44xx_mcbsp_hwmod_class,
1972 .clkdm_name = "abe_clkdm",
1973 .mpu_irqs = omap44xx_mcbsp1_irqs,
1974 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
1975 .main_clk = "mcbsp1_fck",
1978 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980 .modulemode = MODULEMODE_SWCTRL,
1983 .opt_clks = mcbsp1_opt_clks,
1984 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000 { .role = "pad_fck", .clk = "pad_clks_ck" },
2001 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006 .class = &omap44xx_mcbsp_hwmod_class,
2007 .clkdm_name = "abe_clkdm",
2008 .mpu_irqs = omap44xx_mcbsp2_irqs,
2009 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2010 .main_clk = "mcbsp2_fck",
2013 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015 .modulemode = MODULEMODE_SWCTRL,
2018 .opt_clks = mcbsp2_opt_clks,
2019 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035 { .role = "pad_fck", .clk = "pad_clks_ck" },
2036 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041 .class = &omap44xx_mcbsp_hwmod_class,
2042 .clkdm_name = "abe_clkdm",
2043 .mpu_irqs = omap44xx_mcbsp3_irqs,
2044 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2045 .main_clk = "mcbsp3_fck",
2048 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050 .modulemode = MODULEMODE_SWCTRL,
2053 .opt_clks = mcbsp3_opt_clks,
2054 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070 { .role = "pad_fck", .clk = "pad_clks_ck" },
2071 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076 .class = &omap44xx_mcbsp_hwmod_class,
2077 .clkdm_name = "l4_per_clkdm",
2078 .mpu_irqs = omap44xx_mcbsp4_irqs,
2079 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2080 .main_clk = "mcbsp4_fck",
2083 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085 .modulemode = MODULEMODE_SWCTRL,
2088 .opt_clks = mcbsp4_opt_clks,
2089 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
2094 * multi channel pdm controller (proprietary interface with phoenix power
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100 .sysc_offs = 0x0010,
2101 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105 .sysc_fields = &omap_hwmod_sysc_type2,
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110 .sysc = &omap44xx_mcpdm_sysc,
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127 .class = &omap44xx_mcpdm_hwmod_class,
2128 .clkdm_name = "abe_clkdm",
2130 * It's suspected that the McPDM requires an off-chip main
2131 * functional clock, controlled via I2C. This IP block is
2132 * currently reset very early during boot, before I2C is
2133 * available, so it doesn't seem that we have any choice in
2134 * the kernel other than to avoid resetting it.
2136 .flags = HWMOD_EXT_OPT_MAIN_CLK,
2137 .mpu_irqs = omap44xx_mcpdm_irqs,
2138 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2139 .main_clk = "mcpdm_fck",
2142 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2143 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2144 .modulemode = MODULEMODE_SWCTRL,
2151 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2155 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2157 .sysc_offs = 0x0010,
2158 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2159 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2162 .sysc_fields = &omap_hwmod_sysc_type2,
2165 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2167 .sysc = &omap44xx_mcspi_sysc,
2168 .rev = OMAP4_MCSPI_REV,
2172 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2173 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2177 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2178 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2179 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2180 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2181 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2182 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2183 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2184 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2185 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2189 /* mcspi1 dev_attr */
2190 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2191 .num_chipselect = 4,
2194 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2196 .class = &omap44xx_mcspi_hwmod_class,
2197 .clkdm_name = "l4_per_clkdm",
2198 .mpu_irqs = omap44xx_mcspi1_irqs,
2199 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2200 .main_clk = "mcspi1_fck",
2203 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2204 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2205 .modulemode = MODULEMODE_SWCTRL,
2208 .dev_attr = &mcspi1_dev_attr,
2212 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2213 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2217 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2218 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2219 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2220 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2221 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2225 /* mcspi2 dev_attr */
2226 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2227 .num_chipselect = 2,
2230 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2232 .class = &omap44xx_mcspi_hwmod_class,
2233 .clkdm_name = "l4_per_clkdm",
2234 .mpu_irqs = omap44xx_mcspi2_irqs,
2235 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2236 .main_clk = "mcspi2_fck",
2239 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2240 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2241 .modulemode = MODULEMODE_SWCTRL,
2244 .dev_attr = &mcspi2_dev_attr,
2248 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2249 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2253 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2254 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2255 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2256 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2257 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2261 /* mcspi3 dev_attr */
2262 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2263 .num_chipselect = 2,
2266 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2268 .class = &omap44xx_mcspi_hwmod_class,
2269 .clkdm_name = "l4_per_clkdm",
2270 .mpu_irqs = omap44xx_mcspi3_irqs,
2271 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2272 .main_clk = "mcspi3_fck",
2275 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2276 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2277 .modulemode = MODULEMODE_SWCTRL,
2280 .dev_attr = &mcspi3_dev_attr,
2284 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2285 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2289 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2290 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2291 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2295 /* mcspi4 dev_attr */
2296 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2297 .num_chipselect = 1,
2300 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2302 .class = &omap44xx_mcspi_hwmod_class,
2303 .clkdm_name = "l4_per_clkdm",
2304 .mpu_irqs = omap44xx_mcspi4_irqs,
2305 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2306 .main_clk = "mcspi4_fck",
2309 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2310 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2311 .modulemode = MODULEMODE_SWCTRL,
2314 .dev_attr = &mcspi4_dev_attr,
2319 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2322 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2324 .sysc_offs = 0x0010,
2325 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2326 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2327 SYSC_HAS_SOFTRESET),
2328 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2329 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2330 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2331 .sysc_fields = &omap_hwmod_sysc_type2,
2334 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2336 .sysc = &omap44xx_mmc_sysc,
2340 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2341 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2345 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2346 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2347 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2352 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2353 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2356 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2358 .class = &omap44xx_mmc_hwmod_class,
2359 .clkdm_name = "l3_init_clkdm",
2360 .mpu_irqs = omap44xx_mmc1_irqs,
2361 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
2362 .main_clk = "mmc1_fck",
2365 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2366 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2367 .modulemode = MODULEMODE_SWCTRL,
2370 .dev_attr = &mmc1_dev_attr,
2374 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2375 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2379 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2380 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2381 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2385 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2387 .class = &omap44xx_mmc_hwmod_class,
2388 .clkdm_name = "l3_init_clkdm",
2389 .mpu_irqs = omap44xx_mmc2_irqs,
2390 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
2391 .main_clk = "mmc2_fck",
2394 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2395 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2396 .modulemode = MODULEMODE_SWCTRL,
2402 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2403 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2407 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2408 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2409 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2413 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2415 .class = &omap44xx_mmc_hwmod_class,
2416 .clkdm_name = "l4_per_clkdm",
2417 .mpu_irqs = omap44xx_mmc3_irqs,
2418 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2419 .main_clk = "mmc3_fck",
2422 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2423 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2424 .modulemode = MODULEMODE_SWCTRL,
2430 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2431 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2435 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2436 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2437 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2441 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2443 .class = &omap44xx_mmc_hwmod_class,
2444 .clkdm_name = "l4_per_clkdm",
2445 .mpu_irqs = omap44xx_mmc4_irqs,
2446 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2447 .main_clk = "mmc4_fck",
2450 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2451 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2452 .modulemode = MODULEMODE_SWCTRL,
2458 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2459 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2463 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2464 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2465 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2469 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2471 .class = &omap44xx_mmc_hwmod_class,
2472 .clkdm_name = "l4_per_clkdm",
2473 .mpu_irqs = omap44xx_mmc5_irqs,
2474 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2475 .main_clk = "mmc5_fck",
2478 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2479 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2480 .modulemode = MODULEMODE_SWCTRL,
2487 * The memory management unit performs virtual to physical address translation
2488 * for its requestors.
2491 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2495 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2496 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2497 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2498 .sysc_fields = &omap_hwmod_sysc_type1,
2501 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2508 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2510 .da_end = 0xfffff000,
2511 .nr_tlb_entries = 32,
2514 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2515 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2516 { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2520 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2521 { .name = "mmu_cache", .rst_shift = 2 },
2524 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2526 .pa_start = 0x55082000,
2527 .pa_end = 0x550820ff,
2528 .flags = ADDR_TYPE_RT,
2533 /* l3_main_2 -> mmu_ipu */
2534 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2535 .master = &omap44xx_l3_main_2_hwmod,
2536 .slave = &omap44xx_mmu_ipu_hwmod,
2538 .addr = omap44xx_mmu_ipu_addrs,
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2542 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2544 .class = &omap44xx_mmu_hwmod_class,
2545 .clkdm_name = "ducati_clkdm",
2546 .mpu_irqs = omap44xx_mmu_ipu_irqs,
2547 .rst_lines = omap44xx_mmu_ipu_resets,
2548 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2549 .main_clk = "ducati_clk_mux_ck",
2552 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2553 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2554 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2555 .modulemode = MODULEMODE_HWCTRL,
2558 .dev_attr = &mmu_ipu_dev_attr,
2563 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2565 .da_end = 0xfffff000,
2566 .nr_tlb_entries = 32,
2569 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2570 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2571 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2575 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2576 { .name = "mmu_cache", .rst_shift = 1 },
2579 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2581 .pa_start = 0x4a066000,
2582 .pa_end = 0x4a0660ff,
2583 .flags = ADDR_TYPE_RT,
2589 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2590 .master = &omap44xx_l4_cfg_hwmod,
2591 .slave = &omap44xx_mmu_dsp_hwmod,
2593 .addr = omap44xx_mmu_dsp_addrs,
2594 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2599 .class = &omap44xx_mmu_hwmod_class,
2600 .clkdm_name = "tesla_clkdm",
2601 .mpu_irqs = omap44xx_mmu_dsp_irqs,
2602 .rst_lines = omap44xx_mmu_dsp_resets,
2603 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2604 .main_clk = "dpll_iva_m4x2_ck",
2607 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2608 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2609 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2610 .modulemode = MODULEMODE_HWCTRL,
2613 .dev_attr = &mmu_dsp_dev_attr,
2621 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2626 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2627 { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2628 { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2629 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2630 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2631 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2635 static struct omap_hwmod omap44xx_mpu_hwmod = {
2637 .class = &omap44xx_mpu_hwmod_class,
2638 .clkdm_name = "mpuss_clkdm",
2639 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2640 .mpu_irqs = omap44xx_mpu_irqs,
2641 .main_clk = "dpll_mpu_m2_ck",
2644 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2645 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2652 * top-level core on-chip ram
2655 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2660 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2662 .class = &omap44xx_ocmc_ram_hwmod_class,
2663 .clkdm_name = "l3_2_clkdm",
2666 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2667 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2674 * bridge to transform ocp interface protocol to scp (serial control port)
2678 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2680 .sysc_offs = 0x0010,
2681 .syss_offs = 0x0014,
2682 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2683 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2684 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2685 .sysc_fields = &omap_hwmod_sysc_type1,
2688 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2690 .sysc = &omap44xx_ocp2scp_sysc,
2693 /* ocp2scp dev_attr */
2694 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2697 .start = 0x4a0ad080,
2699 .flags = IORESOURCE_MEM,
2702 /* XXX: Remove this once control module driver is in place */
2704 .start = 0x4a002300,
2706 .flags = IORESOURCE_MEM,
2711 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2713 .drv_name = "omap-usb2",
2714 .res = omap44xx_usb_phy_and_pll_addrs,
2719 /* ocp2scp_usb_phy */
2720 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2721 .name = "ocp2scp_usb_phy",
2722 .class = &omap44xx_ocp2scp_hwmod_class,
2723 .clkdm_name = "l3_init_clkdm",
2724 .main_clk = "ocp2scp_usb_phy_phy_48m",
2727 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2728 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2729 .modulemode = MODULEMODE_HWCTRL,
2732 .dev_attr = ocp2scp_dev_attr,
2737 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2738 * + clock manager 1 (in always on power domain) + local prm in mpu
2741 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2746 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2748 .class = &omap44xx_prcm_hwmod_class,
2749 .clkdm_name = "l4_wkup_clkdm",
2750 .flags = HWMOD_NO_IDLEST,
2753 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2759 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2760 .name = "cm_core_aon",
2761 .class = &omap44xx_prcm_hwmod_class,
2762 .flags = HWMOD_NO_IDLEST,
2765 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2771 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2773 .class = &omap44xx_prcm_hwmod_class,
2774 .flags = HWMOD_NO_IDLEST,
2777 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2783 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2784 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2788 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2789 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2790 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2793 static struct omap_hwmod omap44xx_prm_hwmod = {
2795 .class = &omap44xx_prcm_hwmod_class,
2796 .mpu_irqs = omap44xx_prm_irqs,
2797 .rst_lines = omap44xx_prm_resets,
2798 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2803 * system clock and reset manager
2806 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2811 static struct omap_hwmod omap44xx_scrm_hwmod = {
2813 .class = &omap44xx_scrm_hwmod_class,
2814 .clkdm_name = "l4_wkup_clkdm",
2817 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2824 * shared level 2 memory interface
2827 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2832 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2834 .class = &omap44xx_sl2if_hwmod_class,
2835 .clkdm_name = "ivahd_clkdm",
2838 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2839 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2840 .modulemode = MODULEMODE_HWCTRL,
2847 * bidirectional, multi-drop, multi-channel two-line serial interface between
2848 * the device and external components
2851 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2853 .sysc_offs = 0x0010,
2854 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2855 SYSC_HAS_SOFTRESET),
2856 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2858 .sysc_fields = &omap_hwmod_sysc_type2,
2861 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2863 .sysc = &omap44xx_slimbus_sysc,
2867 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2868 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2872 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2873 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2874 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2875 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2876 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2877 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2878 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2879 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2880 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2884 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2885 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2886 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2887 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2888 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2891 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2893 .class = &omap44xx_slimbus_hwmod_class,
2894 .clkdm_name = "abe_clkdm",
2895 .mpu_irqs = omap44xx_slimbus1_irqs,
2896 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2899 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2900 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2901 .modulemode = MODULEMODE_SWCTRL,
2904 .opt_clks = slimbus1_opt_clks,
2905 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2909 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2910 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2914 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2915 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2916 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2917 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2918 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2919 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2920 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2921 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2922 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2926 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2927 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2928 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2929 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2932 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2934 .class = &omap44xx_slimbus_hwmod_class,
2935 .clkdm_name = "l4_per_clkdm",
2936 .mpu_irqs = omap44xx_slimbus2_irqs,
2937 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2940 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2941 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2942 .modulemode = MODULEMODE_SWCTRL,
2945 .opt_clks = slimbus2_opt_clks,
2946 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2950 * 'smartreflex' class
2951 * smartreflex module (monitor silicon performance and outputs a measure of
2952 * performance error)
2955 /* The IP is not compliant to type1 / type2 scheme */
2956 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2961 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2962 .sysc_offs = 0x0038,
2963 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2964 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2966 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2969 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2970 .name = "smartreflex",
2971 .sysc = &omap44xx_smartreflex_sysc,
2975 /* smartreflex_core */
2976 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2977 .sensor_voltdm_name = "core",
2980 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2981 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2985 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2986 .name = "smartreflex_core",
2987 .class = &omap44xx_smartreflex_hwmod_class,
2988 .clkdm_name = "l4_ao_clkdm",
2989 .mpu_irqs = omap44xx_smartreflex_core_irqs,
2991 .main_clk = "smartreflex_core_fck",
2994 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2995 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2996 .modulemode = MODULEMODE_SWCTRL,
2999 .dev_attr = &smartreflex_core_dev_attr,
3002 /* smartreflex_iva */
3003 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3004 .sensor_voltdm_name = "iva",
3007 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3008 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3012 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3013 .name = "smartreflex_iva",
3014 .class = &omap44xx_smartreflex_hwmod_class,
3015 .clkdm_name = "l4_ao_clkdm",
3016 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3017 .main_clk = "smartreflex_iva_fck",
3020 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3021 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3022 .modulemode = MODULEMODE_SWCTRL,
3025 .dev_attr = &smartreflex_iva_dev_attr,
3028 /* smartreflex_mpu */
3029 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3030 .sensor_voltdm_name = "mpu",
3033 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3034 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3038 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3039 .name = "smartreflex_mpu",
3040 .class = &omap44xx_smartreflex_hwmod_class,
3041 .clkdm_name = "l4_ao_clkdm",
3042 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3043 .main_clk = "smartreflex_mpu_fck",
3046 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3047 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3048 .modulemode = MODULEMODE_SWCTRL,
3051 .dev_attr = &smartreflex_mpu_dev_attr,
3056 * spinlock provides hardware assistance for synchronizing the processes
3057 * running on multiple processors
3060 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3062 .sysc_offs = 0x0010,
3063 .syss_offs = 0x0014,
3064 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3065 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3066 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3067 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3069 .sysc_fields = &omap_hwmod_sysc_type1,
3072 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3074 .sysc = &omap44xx_spinlock_sysc,
3078 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3080 .class = &omap44xx_spinlock_hwmod_class,
3081 .clkdm_name = "l4_cfg_clkdm",
3084 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3085 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3092 * general purpose timer module with accurate 1ms tick
3093 * This class contains several variants: ['timer_1ms', 'timer']
3096 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3098 .sysc_offs = 0x0010,
3099 .syss_offs = 0x0014,
3100 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3101 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3102 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3103 SYSS_HAS_RESET_STATUS),
3104 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3105 .clockact = CLOCKACT_TEST_ICLK,
3106 .sysc_fields = &omap_hwmod_sysc_type1,
3109 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3111 .sysc = &omap44xx_timer_1ms_sysc,
3114 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3116 .sysc_offs = 0x0010,
3117 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3118 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3119 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3121 .sysc_fields = &omap_hwmod_sysc_type2,
3124 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3126 .sysc = &omap44xx_timer_sysc,
3129 /* always-on timers dev attribute */
3130 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3131 .timer_capability = OMAP_TIMER_ALWON,
3134 /* pwm timers dev attribute */
3135 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3136 .timer_capability = OMAP_TIMER_HAS_PWM,
3139 /* timers with DSP interrupt dev attribute */
3140 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3141 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
3144 /* pwm timers with DSP interrupt dev attribute */
3145 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3146 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3150 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3151 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3155 static struct omap_hwmod omap44xx_timer1_hwmod = {
3157 .class = &omap44xx_timer_1ms_hwmod_class,
3158 .clkdm_name = "l4_wkup_clkdm",
3159 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3160 .mpu_irqs = omap44xx_timer1_irqs,
3161 .main_clk = "timer1_fck",
3164 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3165 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3166 .modulemode = MODULEMODE_SWCTRL,
3169 .dev_attr = &capability_alwon_dev_attr,
3173 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3174 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3178 static struct omap_hwmod omap44xx_timer2_hwmod = {
3180 .class = &omap44xx_timer_1ms_hwmod_class,
3181 .clkdm_name = "l4_per_clkdm",
3182 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3183 .mpu_irqs = omap44xx_timer2_irqs,
3184 .main_clk = "timer2_fck",
3187 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3188 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3189 .modulemode = MODULEMODE_SWCTRL,
3195 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3196 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3200 static struct omap_hwmod omap44xx_timer3_hwmod = {
3202 .class = &omap44xx_timer_hwmod_class,
3203 .clkdm_name = "l4_per_clkdm",
3204 .mpu_irqs = omap44xx_timer3_irqs,
3205 .main_clk = "timer3_fck",
3208 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3209 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3210 .modulemode = MODULEMODE_SWCTRL,
3216 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3217 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3221 static struct omap_hwmod omap44xx_timer4_hwmod = {
3223 .class = &omap44xx_timer_hwmod_class,
3224 .clkdm_name = "l4_per_clkdm",
3225 .mpu_irqs = omap44xx_timer4_irqs,
3226 .main_clk = "timer4_fck",
3229 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3230 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3231 .modulemode = MODULEMODE_SWCTRL,
3237 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3238 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3242 static struct omap_hwmod omap44xx_timer5_hwmod = {
3244 .class = &omap44xx_timer_hwmod_class,
3245 .clkdm_name = "abe_clkdm",
3246 .mpu_irqs = omap44xx_timer5_irqs,
3247 .main_clk = "timer5_fck",
3250 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3251 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3252 .modulemode = MODULEMODE_SWCTRL,
3255 .dev_attr = &capability_dsp_dev_attr,
3259 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3260 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3264 static struct omap_hwmod omap44xx_timer6_hwmod = {
3266 .class = &omap44xx_timer_hwmod_class,
3267 .clkdm_name = "abe_clkdm",
3268 .mpu_irqs = omap44xx_timer6_irqs,
3270 .main_clk = "timer6_fck",
3273 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3274 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3275 .modulemode = MODULEMODE_SWCTRL,
3278 .dev_attr = &capability_dsp_dev_attr,
3282 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3283 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3287 static struct omap_hwmod omap44xx_timer7_hwmod = {
3289 .class = &omap44xx_timer_hwmod_class,
3290 .clkdm_name = "abe_clkdm",
3291 .mpu_irqs = omap44xx_timer7_irqs,
3292 .main_clk = "timer7_fck",
3295 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3296 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3297 .modulemode = MODULEMODE_SWCTRL,
3300 .dev_attr = &capability_dsp_dev_attr,
3304 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3305 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3309 static struct omap_hwmod omap44xx_timer8_hwmod = {
3311 .class = &omap44xx_timer_hwmod_class,
3312 .clkdm_name = "abe_clkdm",
3313 .mpu_irqs = omap44xx_timer8_irqs,
3314 .main_clk = "timer8_fck",
3317 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3318 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3319 .modulemode = MODULEMODE_SWCTRL,
3322 .dev_attr = &capability_dsp_pwm_dev_attr,
3326 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3327 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3331 static struct omap_hwmod omap44xx_timer9_hwmod = {
3333 .class = &omap44xx_timer_hwmod_class,
3334 .clkdm_name = "l4_per_clkdm",
3335 .mpu_irqs = omap44xx_timer9_irqs,
3336 .main_clk = "timer9_fck",
3339 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3340 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3341 .modulemode = MODULEMODE_SWCTRL,
3344 .dev_attr = &capability_pwm_dev_attr,
3348 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3349 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3353 static struct omap_hwmod omap44xx_timer10_hwmod = {
3355 .class = &omap44xx_timer_1ms_hwmod_class,
3356 .clkdm_name = "l4_per_clkdm",
3357 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3358 .mpu_irqs = omap44xx_timer10_irqs,
3359 .main_clk = "timer10_fck",
3362 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3363 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3364 .modulemode = MODULEMODE_SWCTRL,
3367 .dev_attr = &capability_pwm_dev_attr,
3371 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3372 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3376 static struct omap_hwmod omap44xx_timer11_hwmod = {
3378 .class = &omap44xx_timer_hwmod_class,
3379 .clkdm_name = "l4_per_clkdm",
3380 .mpu_irqs = omap44xx_timer11_irqs,
3381 .main_clk = "timer11_fck",
3384 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3385 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3386 .modulemode = MODULEMODE_SWCTRL,
3389 .dev_attr = &capability_pwm_dev_attr,
3394 * universal asynchronous receiver/transmitter (uart)
3397 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3399 .sysc_offs = 0x0054,
3400 .syss_offs = 0x0058,
3401 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3402 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3403 SYSS_HAS_RESET_STATUS),
3404 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3406 .sysc_fields = &omap_hwmod_sysc_type1,
3409 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3411 .sysc = &omap44xx_uart_sysc,
3415 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3416 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3420 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3421 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3422 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3426 static struct omap_hwmod omap44xx_uart1_hwmod = {
3428 .class = &omap44xx_uart_hwmod_class,
3429 .clkdm_name = "l4_per_clkdm",
3430 .mpu_irqs = omap44xx_uart1_irqs,
3431 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3432 .main_clk = "uart1_fck",
3435 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3436 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3437 .modulemode = MODULEMODE_SWCTRL,
3443 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3444 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3448 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3449 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3450 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3454 static struct omap_hwmod omap44xx_uart2_hwmod = {
3456 .class = &omap44xx_uart_hwmod_class,
3457 .clkdm_name = "l4_per_clkdm",
3458 .mpu_irqs = omap44xx_uart2_irqs,
3459 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3460 .main_clk = "uart2_fck",
3463 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3464 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3465 .modulemode = MODULEMODE_SWCTRL,
3471 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3472 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3476 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3477 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3478 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3482 static struct omap_hwmod omap44xx_uart3_hwmod = {
3484 .class = &omap44xx_uart_hwmod_class,
3485 .clkdm_name = "l4_per_clkdm",
3486 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3487 .mpu_irqs = omap44xx_uart3_irqs,
3488 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3489 .main_clk = "uart3_fck",
3492 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3493 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3494 .modulemode = MODULEMODE_SWCTRL,
3500 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3501 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3505 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3506 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3507 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3511 static struct omap_hwmod omap44xx_uart4_hwmod = {
3513 .class = &omap44xx_uart_hwmod_class,
3514 .clkdm_name = "l4_per_clkdm",
3515 .mpu_irqs = omap44xx_uart4_irqs,
3516 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3517 .main_clk = "uart4_fck",
3520 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3521 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3522 .modulemode = MODULEMODE_SWCTRL,
3528 * 'usb_host_fs' class
3529 * full-speed usb host controller
3532 /* The IP is not compliant to type1 / type2 scheme */
3533 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3539 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3541 .sysc_offs = 0x0210,
3542 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3543 SYSC_HAS_SOFTRESET),
3544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3546 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
3549 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3550 .name = "usb_host_fs",
3551 .sysc = &omap44xx_usb_host_fs_sysc,
3555 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3556 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3557 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3561 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3562 .name = "usb_host_fs",
3563 .class = &omap44xx_usb_host_fs_hwmod_class,
3564 .clkdm_name = "l3_init_clkdm",
3565 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3566 .main_clk = "usb_host_fs_fck",
3569 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3570 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3571 .modulemode = MODULEMODE_SWCTRL,
3577 * 'usb_host_hs' class
3578 * high-speed multi-port usb host controller
3581 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3583 .sysc_offs = 0x0010,
3584 .syss_offs = 0x0014,
3585 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3586 SYSC_HAS_SOFTRESET),
3587 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3588 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3589 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3590 .sysc_fields = &omap_hwmod_sysc_type2,
3593 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3594 .name = "usb_host_hs",
3595 .sysc = &omap44xx_usb_host_hs_sysc,
3599 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3600 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3601 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3605 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3606 .name = "usb_host_hs",
3607 .class = &omap44xx_usb_host_hs_hwmod_class,
3608 .clkdm_name = "l3_init_clkdm",
3609 .main_clk = "usb_host_hs_fck",
3612 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3613 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3614 .modulemode = MODULEMODE_SWCTRL,
3617 .mpu_irqs = omap44xx_usb_host_hs_irqs,
3620 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3624 * In the following configuration :
3625 * - USBHOST module is set to smart-idle mode
3626 * - PRCM asserts idle_req to the USBHOST module ( This typically
3627 * happens when the system is going to a low power mode : all ports
3628 * have been suspended, the master part of the USBHOST module has
3629 * entered the standby state, and SW has cut the functional clocks)
3630 * - an USBHOST interrupt occurs before the module is able to answer
3631 * idle_ack, typically a remote wakeup IRQ.
3632 * Then the USB HOST module will enter a deadlock situation where it
3633 * is no more accessible nor functional.
3636 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3640 * Errata: USB host EHCI may stall when entering smart-standby mode
3644 * When the USBHOST module is set to smart-standby mode, and when it is
3645 * ready to enter the standby state (i.e. all ports are suspended and
3646 * all attached devices are in suspend mode), then it can wrongly assert
3647 * the Mstandby signal too early while there are still some residual OCP
3648 * transactions ongoing. If this condition occurs, the internal state
3649 * machine may go to an undefined state and the USB link may be stuck
3650 * upon the next resume.
3653 * Don't use smart standby; use only force standby,
3654 * hence HWMOD_SWSUP_MSTANDBY
3658 * During system boot; If the hwmod framework resets the module
3659 * the module will have smart idle settings; which can lead to deadlock
3660 * (above Errata Id:i660); so, dont reset the module during boot;
3661 * Use HWMOD_INIT_NO_RESET.
3664 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3665 HWMOD_INIT_NO_RESET,
3669 * 'usb_otg_hs' class
3670 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3673 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3675 .sysc_offs = 0x0404,
3676 .syss_offs = 0x0408,
3677 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3678 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3679 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3680 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3681 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3683 .sysc_fields = &omap_hwmod_sysc_type1,
3686 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3687 .name = "usb_otg_hs",
3688 .sysc = &omap44xx_usb_otg_hs_sysc,
3692 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3693 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3694 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3698 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3699 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3702 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3703 .name = "usb_otg_hs",
3704 .class = &omap44xx_usb_otg_hs_hwmod_class,
3705 .clkdm_name = "l3_init_clkdm",
3706 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3707 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
3708 .main_clk = "usb_otg_hs_ick",
3711 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3712 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3713 .modulemode = MODULEMODE_HWCTRL,
3716 .opt_clks = usb_otg_hs_opt_clks,
3717 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3721 * 'usb_tll_hs' class
3722 * usb_tll_hs module is the adapter on the usb_host_hs ports
3725 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3727 .sysc_offs = 0x0010,
3728 .syss_offs = 0x0014,
3729 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3730 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3732 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3733 .sysc_fields = &omap_hwmod_sysc_type1,
3736 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3737 .name = "usb_tll_hs",
3738 .sysc = &omap44xx_usb_tll_hs_sysc,
3741 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3742 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3746 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3747 .name = "usb_tll_hs",
3748 .class = &omap44xx_usb_tll_hs_hwmod_class,
3749 .clkdm_name = "l3_init_clkdm",
3750 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
3751 .main_clk = "usb_tll_hs_ick",
3754 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3755 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3756 .modulemode = MODULEMODE_HWCTRL,
3763 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3764 * overflow condition
3767 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3769 .sysc_offs = 0x0010,
3770 .syss_offs = 0x0014,
3771 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3772 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3773 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3775 .sysc_fields = &omap_hwmod_sysc_type1,
3778 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3780 .sysc = &omap44xx_wd_timer_sysc,
3781 .pre_shutdown = &omap2_wd_timer_disable,
3782 .reset = &omap2_wd_timer_reset,
3786 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3787 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3791 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3792 .name = "wd_timer2",
3793 .class = &omap44xx_wd_timer_hwmod_class,
3794 .clkdm_name = "l4_wkup_clkdm",
3795 .mpu_irqs = omap44xx_wd_timer2_irqs,
3796 .main_clk = "wd_timer2_fck",
3799 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3800 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3801 .modulemode = MODULEMODE_SWCTRL,
3807 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3808 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3812 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3813 .name = "wd_timer3",
3814 .class = &omap44xx_wd_timer_hwmod_class,
3815 .clkdm_name = "abe_clkdm",
3816 .mpu_irqs = omap44xx_wd_timer3_irqs,
3817 .main_clk = "wd_timer3_fck",
3820 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3821 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3822 .modulemode = MODULEMODE_SWCTRL,
3832 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3834 .pa_start = 0x4a204000,
3835 .pa_end = 0x4a2040ff,
3836 .flags = ADDR_TYPE_RT
3841 /* c2c -> c2c_target_fw */
3842 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3843 .master = &omap44xx_c2c_hwmod,
3844 .slave = &omap44xx_c2c_target_fw_hwmod,
3845 .clk = "div_core_ck",
3846 .addr = omap44xx_c2c_target_fw_addrs,
3847 .user = OCP_USER_MPU,
3850 /* l4_cfg -> c2c_target_fw */
3851 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3852 .master = &omap44xx_l4_cfg_hwmod,
3853 .slave = &omap44xx_c2c_target_fw_hwmod,
3855 .user = OCP_USER_MPU | OCP_USER_SDMA,
3858 /* l3_main_1 -> dmm */
3859 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3860 .master = &omap44xx_l3_main_1_hwmod,
3861 .slave = &omap44xx_dmm_hwmod,
3863 .user = OCP_USER_SDMA,
3866 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3868 .pa_start = 0x4e000000,
3869 .pa_end = 0x4e0007ff,
3870 .flags = ADDR_TYPE_RT
3876 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3877 .master = &omap44xx_mpu_hwmod,
3878 .slave = &omap44xx_dmm_hwmod,
3880 .addr = omap44xx_dmm_addrs,
3881 .user = OCP_USER_MPU,
3884 /* c2c -> emif_fw */
3885 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3886 .master = &omap44xx_c2c_hwmod,
3887 .slave = &omap44xx_emif_fw_hwmod,
3888 .clk = "div_core_ck",
3889 .user = OCP_USER_MPU | OCP_USER_SDMA,
3892 /* dmm -> emif_fw */
3893 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3894 .master = &omap44xx_dmm_hwmod,
3895 .slave = &omap44xx_emif_fw_hwmod,
3897 .user = OCP_USER_MPU | OCP_USER_SDMA,
3900 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3902 .pa_start = 0x4a20c000,
3903 .pa_end = 0x4a20c0ff,
3904 .flags = ADDR_TYPE_RT
3909 /* l4_cfg -> emif_fw */
3910 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3911 .master = &omap44xx_l4_cfg_hwmod,
3912 .slave = &omap44xx_emif_fw_hwmod,
3914 .addr = omap44xx_emif_fw_addrs,
3915 .user = OCP_USER_MPU,
3918 /* iva -> l3_instr */
3919 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3920 .master = &omap44xx_iva_hwmod,
3921 .slave = &omap44xx_l3_instr_hwmod,
3923 .user = OCP_USER_MPU | OCP_USER_SDMA,
3926 /* l3_main_3 -> l3_instr */
3927 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3928 .master = &omap44xx_l3_main_3_hwmod,
3929 .slave = &omap44xx_l3_instr_hwmod,
3931 .user = OCP_USER_MPU | OCP_USER_SDMA,
3934 /* ocp_wp_noc -> l3_instr */
3935 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3936 .master = &omap44xx_ocp_wp_noc_hwmod,
3937 .slave = &omap44xx_l3_instr_hwmod,
3939 .user = OCP_USER_MPU | OCP_USER_SDMA,
3942 /* dsp -> l3_main_1 */
3943 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3944 .master = &omap44xx_dsp_hwmod,
3945 .slave = &omap44xx_l3_main_1_hwmod,
3947 .user = OCP_USER_MPU | OCP_USER_SDMA,
3950 /* dss -> l3_main_1 */
3951 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3952 .master = &omap44xx_dss_hwmod,
3953 .slave = &omap44xx_l3_main_1_hwmod,
3955 .user = OCP_USER_MPU | OCP_USER_SDMA,
3958 /* l3_main_2 -> l3_main_1 */
3959 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3960 .master = &omap44xx_l3_main_2_hwmod,
3961 .slave = &omap44xx_l3_main_1_hwmod,
3963 .user = OCP_USER_MPU | OCP_USER_SDMA,
3966 /* l4_cfg -> l3_main_1 */
3967 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3968 .master = &omap44xx_l4_cfg_hwmod,
3969 .slave = &omap44xx_l3_main_1_hwmod,
3971 .user = OCP_USER_MPU | OCP_USER_SDMA,
3974 /* mmc1 -> l3_main_1 */
3975 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3976 .master = &omap44xx_mmc1_hwmod,
3977 .slave = &omap44xx_l3_main_1_hwmod,
3979 .user = OCP_USER_MPU | OCP_USER_SDMA,
3982 /* mmc2 -> l3_main_1 */
3983 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3984 .master = &omap44xx_mmc2_hwmod,
3985 .slave = &omap44xx_l3_main_1_hwmod,
3987 .user = OCP_USER_MPU | OCP_USER_SDMA,
3990 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3992 .pa_start = 0x44000000,
3993 .pa_end = 0x44000fff,
3994 .flags = ADDR_TYPE_RT
3999 /* mpu -> l3_main_1 */
4000 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4001 .master = &omap44xx_mpu_hwmod,
4002 .slave = &omap44xx_l3_main_1_hwmod,
4004 .addr = omap44xx_l3_main_1_addrs,
4005 .user = OCP_USER_MPU,
4008 /* c2c_target_fw -> l3_main_2 */
4009 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4010 .master = &omap44xx_c2c_target_fw_hwmod,
4011 .slave = &omap44xx_l3_main_2_hwmod,
4013 .user = OCP_USER_MPU | OCP_USER_SDMA,
4016 /* debugss -> l3_main_2 */
4017 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4018 .master = &omap44xx_debugss_hwmod,
4019 .slave = &omap44xx_l3_main_2_hwmod,
4020 .clk = "dbgclk_mux_ck",
4021 .user = OCP_USER_MPU | OCP_USER_SDMA,
4024 /* dma_system -> l3_main_2 */
4025 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4026 .master = &omap44xx_dma_system_hwmod,
4027 .slave = &omap44xx_l3_main_2_hwmod,
4029 .user = OCP_USER_MPU | OCP_USER_SDMA,
4032 /* fdif -> l3_main_2 */
4033 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4034 .master = &omap44xx_fdif_hwmod,
4035 .slave = &omap44xx_l3_main_2_hwmod,
4037 .user = OCP_USER_MPU | OCP_USER_SDMA,
4040 /* gpu -> l3_main_2 */
4041 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4042 .master = &omap44xx_gpu_hwmod,
4043 .slave = &omap44xx_l3_main_2_hwmod,
4045 .user = OCP_USER_MPU | OCP_USER_SDMA,
4048 /* hsi -> l3_main_2 */
4049 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4050 .master = &omap44xx_hsi_hwmod,
4051 .slave = &omap44xx_l3_main_2_hwmod,
4053 .user = OCP_USER_MPU | OCP_USER_SDMA,
4056 /* ipu -> l3_main_2 */
4057 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4058 .master = &omap44xx_ipu_hwmod,
4059 .slave = &omap44xx_l3_main_2_hwmod,
4061 .user = OCP_USER_MPU | OCP_USER_SDMA,
4064 /* iss -> l3_main_2 */
4065 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4066 .master = &omap44xx_iss_hwmod,
4067 .slave = &omap44xx_l3_main_2_hwmod,
4069 .user = OCP_USER_MPU | OCP_USER_SDMA,
4072 /* iva -> l3_main_2 */
4073 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4074 .master = &omap44xx_iva_hwmod,
4075 .slave = &omap44xx_l3_main_2_hwmod,
4077 .user = OCP_USER_MPU | OCP_USER_SDMA,
4080 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4082 .pa_start = 0x44800000,
4083 .pa_end = 0x44801fff,
4084 .flags = ADDR_TYPE_RT
4089 /* l3_main_1 -> l3_main_2 */
4090 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4091 .master = &omap44xx_l3_main_1_hwmod,
4092 .slave = &omap44xx_l3_main_2_hwmod,
4094 .addr = omap44xx_l3_main_2_addrs,
4095 .user = OCP_USER_MPU,
4098 /* l4_cfg -> l3_main_2 */
4099 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4100 .master = &omap44xx_l4_cfg_hwmod,
4101 .slave = &omap44xx_l3_main_2_hwmod,
4103 .user = OCP_USER_MPU | OCP_USER_SDMA,
4106 /* usb_host_fs -> l3_main_2 */
4107 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4108 .master = &omap44xx_usb_host_fs_hwmod,
4109 .slave = &omap44xx_l3_main_2_hwmod,
4111 .user = OCP_USER_MPU | OCP_USER_SDMA,
4114 /* usb_host_hs -> l3_main_2 */
4115 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4116 .master = &omap44xx_usb_host_hs_hwmod,
4117 .slave = &omap44xx_l3_main_2_hwmod,
4119 .user = OCP_USER_MPU | OCP_USER_SDMA,
4122 /* usb_otg_hs -> l3_main_2 */
4123 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4124 .master = &omap44xx_usb_otg_hs_hwmod,
4125 .slave = &omap44xx_l3_main_2_hwmod,
4127 .user = OCP_USER_MPU | OCP_USER_SDMA,
4130 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4132 .pa_start = 0x45000000,
4133 .pa_end = 0x45000fff,
4134 .flags = ADDR_TYPE_RT
4139 /* l3_main_1 -> l3_main_3 */
4140 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4141 .master = &omap44xx_l3_main_1_hwmod,
4142 .slave = &omap44xx_l3_main_3_hwmod,
4144 .addr = omap44xx_l3_main_3_addrs,
4145 .user = OCP_USER_MPU,
4148 /* l3_main_2 -> l3_main_3 */
4149 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4150 .master = &omap44xx_l3_main_2_hwmod,
4151 .slave = &omap44xx_l3_main_3_hwmod,
4153 .user = OCP_USER_MPU | OCP_USER_SDMA,
4156 /* l4_cfg -> l3_main_3 */
4157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4158 .master = &omap44xx_l4_cfg_hwmod,
4159 .slave = &omap44xx_l3_main_3_hwmod,
4161 .user = OCP_USER_MPU | OCP_USER_SDMA,
4164 /* aess -> l4_abe */
4165 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4166 .master = &omap44xx_aess_hwmod,
4167 .slave = &omap44xx_l4_abe_hwmod,
4168 .clk = "ocp_abe_iclk",
4169 .user = OCP_USER_MPU | OCP_USER_SDMA,
4173 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4174 .master = &omap44xx_dsp_hwmod,
4175 .slave = &omap44xx_l4_abe_hwmod,
4176 .clk = "ocp_abe_iclk",
4177 .user = OCP_USER_MPU | OCP_USER_SDMA,
4180 /* l3_main_1 -> l4_abe */
4181 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4182 .master = &omap44xx_l3_main_1_hwmod,
4183 .slave = &omap44xx_l4_abe_hwmod,
4185 .user = OCP_USER_MPU | OCP_USER_SDMA,
4189 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4190 .master = &omap44xx_mpu_hwmod,
4191 .slave = &omap44xx_l4_abe_hwmod,
4192 .clk = "ocp_abe_iclk",
4193 .user = OCP_USER_MPU | OCP_USER_SDMA,
4196 /* l3_main_1 -> l4_cfg */
4197 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4198 .master = &omap44xx_l3_main_1_hwmod,
4199 .slave = &omap44xx_l4_cfg_hwmod,
4201 .user = OCP_USER_MPU | OCP_USER_SDMA,
4204 /* l3_main_2 -> l4_per */
4205 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4206 .master = &omap44xx_l3_main_2_hwmod,
4207 .slave = &omap44xx_l4_per_hwmod,
4209 .user = OCP_USER_MPU | OCP_USER_SDMA,
4212 /* l4_cfg -> l4_wkup */
4213 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4214 .master = &omap44xx_l4_cfg_hwmod,
4215 .slave = &omap44xx_l4_wkup_hwmod,
4217 .user = OCP_USER_MPU | OCP_USER_SDMA,
4220 /* mpu -> mpu_private */
4221 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4222 .master = &omap44xx_mpu_hwmod,
4223 .slave = &omap44xx_mpu_private_hwmod,
4225 .user = OCP_USER_MPU | OCP_USER_SDMA,
4228 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4230 .pa_start = 0x4a102000,
4231 .pa_end = 0x4a10207f,
4232 .flags = ADDR_TYPE_RT
4237 /* l4_cfg -> ocp_wp_noc */
4238 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4239 .master = &omap44xx_l4_cfg_hwmod,
4240 .slave = &omap44xx_ocp_wp_noc_hwmod,
4242 .addr = omap44xx_ocp_wp_noc_addrs,
4243 .user = OCP_USER_MPU | OCP_USER_SDMA,
4246 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4248 .pa_start = 0x401f1000,
4249 .pa_end = 0x401f13ff,
4250 .flags = ADDR_TYPE_RT
4255 /* l4_abe -> aess */
4256 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4257 .master = &omap44xx_l4_abe_hwmod,
4258 .slave = &omap44xx_aess_hwmod,
4259 .clk = "ocp_abe_iclk",
4260 .addr = omap44xx_aess_addrs,
4261 .user = OCP_USER_MPU,
4264 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4266 .pa_start = 0x490f1000,
4267 .pa_end = 0x490f13ff,
4268 .flags = ADDR_TYPE_RT
4273 /* l4_abe -> aess (dma) */
4274 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4275 .master = &omap44xx_l4_abe_hwmod,
4276 .slave = &omap44xx_aess_hwmod,
4277 .clk = "ocp_abe_iclk",
4278 .addr = omap44xx_aess_dma_addrs,
4279 .user = OCP_USER_SDMA,
4282 /* l3_main_2 -> c2c */
4283 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4284 .master = &omap44xx_l3_main_2_hwmod,
4285 .slave = &omap44xx_c2c_hwmod,
4287 .user = OCP_USER_MPU | OCP_USER_SDMA,
4290 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4292 .pa_start = 0x4a304000,
4293 .pa_end = 0x4a30401f,
4294 .flags = ADDR_TYPE_RT
4299 /* l4_wkup -> counter_32k */
4300 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4301 .master = &omap44xx_l4_wkup_hwmod,
4302 .slave = &omap44xx_counter_32k_hwmod,
4303 .clk = "l4_wkup_clk_mux_ck",
4304 .addr = omap44xx_counter_32k_addrs,
4305 .user = OCP_USER_MPU | OCP_USER_SDMA,
4308 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4310 .pa_start = 0x4a002000,
4311 .pa_end = 0x4a0027ff,
4312 .flags = ADDR_TYPE_RT
4317 /* l4_cfg -> ctrl_module_core */
4318 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4319 .master = &omap44xx_l4_cfg_hwmod,
4320 .slave = &omap44xx_ctrl_module_core_hwmod,
4322 .addr = omap44xx_ctrl_module_core_addrs,
4323 .user = OCP_USER_MPU | OCP_USER_SDMA,
4326 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4328 .pa_start = 0x4a100000,
4329 .pa_end = 0x4a1007ff,
4330 .flags = ADDR_TYPE_RT
4335 /* l4_cfg -> ctrl_module_pad_core */
4336 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4337 .master = &omap44xx_l4_cfg_hwmod,
4338 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
4340 .addr = omap44xx_ctrl_module_pad_core_addrs,
4341 .user = OCP_USER_MPU | OCP_USER_SDMA,
4344 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4346 .pa_start = 0x4a30c000,
4347 .pa_end = 0x4a30c7ff,
4348 .flags = ADDR_TYPE_RT
4353 /* l4_wkup -> ctrl_module_wkup */
4354 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4355 .master = &omap44xx_l4_wkup_hwmod,
4356 .slave = &omap44xx_ctrl_module_wkup_hwmod,
4357 .clk = "l4_wkup_clk_mux_ck",
4358 .addr = omap44xx_ctrl_module_wkup_addrs,
4359 .user = OCP_USER_MPU | OCP_USER_SDMA,
4362 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4364 .pa_start = 0x4a31e000,
4365 .pa_end = 0x4a31e7ff,
4366 .flags = ADDR_TYPE_RT
4371 /* l4_wkup -> ctrl_module_pad_wkup */
4372 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4373 .master = &omap44xx_l4_wkup_hwmod,
4374 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
4375 .clk = "l4_wkup_clk_mux_ck",
4376 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
4377 .user = OCP_USER_MPU | OCP_USER_SDMA,
4380 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4382 .pa_start = 0x54160000,
4383 .pa_end = 0x54167fff,
4384 .flags = ADDR_TYPE_RT
4389 /* l3_instr -> debugss */
4390 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4391 .master = &omap44xx_l3_instr_hwmod,
4392 .slave = &omap44xx_debugss_hwmod,
4394 .addr = omap44xx_debugss_addrs,
4395 .user = OCP_USER_MPU | OCP_USER_SDMA,
4398 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4400 .pa_start = 0x4a056000,
4401 .pa_end = 0x4a056fff,
4402 .flags = ADDR_TYPE_RT
4407 /* l4_cfg -> dma_system */
4408 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4409 .master = &omap44xx_l4_cfg_hwmod,
4410 .slave = &omap44xx_dma_system_hwmod,
4412 .addr = omap44xx_dma_system_addrs,
4413 .user = OCP_USER_MPU | OCP_USER_SDMA,
4416 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4419 .pa_start = 0x4012e000,
4420 .pa_end = 0x4012e07f,
4421 .flags = ADDR_TYPE_RT
4426 /* l4_abe -> dmic */
4427 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4428 .master = &omap44xx_l4_abe_hwmod,
4429 .slave = &omap44xx_dmic_hwmod,
4430 .clk = "ocp_abe_iclk",
4431 .addr = omap44xx_dmic_addrs,
4432 .user = OCP_USER_MPU,
4435 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4438 .pa_start = 0x4902e000,
4439 .pa_end = 0x4902e07f,
4440 .flags = ADDR_TYPE_RT
4445 /* l4_abe -> dmic (dma) */
4446 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4447 .master = &omap44xx_l4_abe_hwmod,
4448 .slave = &omap44xx_dmic_hwmod,
4449 .clk = "ocp_abe_iclk",
4450 .addr = omap44xx_dmic_dma_addrs,
4451 .user = OCP_USER_SDMA,
4455 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4456 .master = &omap44xx_dsp_hwmod,
4457 .slave = &omap44xx_iva_hwmod,
4458 .clk = "dpll_iva_m5x2_ck",
4459 .user = OCP_USER_DSP,
4463 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4464 .master = &omap44xx_dsp_hwmod,
4465 .slave = &omap44xx_sl2if_hwmod,
4466 .clk = "dpll_iva_m5x2_ck",
4467 .user = OCP_USER_DSP,
4471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4472 .master = &omap44xx_l4_cfg_hwmod,
4473 .slave = &omap44xx_dsp_hwmod,
4475 .user = OCP_USER_MPU | OCP_USER_SDMA,
4478 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4480 .pa_start = 0x58000000,
4481 .pa_end = 0x5800007f,
4482 .flags = ADDR_TYPE_RT
4487 /* l3_main_2 -> dss */
4488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4489 .master = &omap44xx_l3_main_2_hwmod,
4490 .slave = &omap44xx_dss_hwmod,
4492 .addr = omap44xx_dss_dma_addrs,
4493 .user = OCP_USER_SDMA,
4496 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4498 .pa_start = 0x48040000,
4499 .pa_end = 0x4804007f,
4500 .flags = ADDR_TYPE_RT
4506 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4507 .master = &omap44xx_l4_per_hwmod,
4508 .slave = &omap44xx_dss_hwmod,
4510 .addr = omap44xx_dss_addrs,
4511 .user = OCP_USER_MPU,
4514 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4516 .pa_start = 0x58001000,
4517 .pa_end = 0x58001fff,
4518 .flags = ADDR_TYPE_RT
4523 /* l3_main_2 -> dss_dispc */
4524 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4525 .master = &omap44xx_l3_main_2_hwmod,
4526 .slave = &omap44xx_dss_dispc_hwmod,
4528 .addr = omap44xx_dss_dispc_dma_addrs,
4529 .user = OCP_USER_SDMA,
4532 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4534 .pa_start = 0x48041000,
4535 .pa_end = 0x48041fff,
4536 .flags = ADDR_TYPE_RT
4541 /* l4_per -> dss_dispc */
4542 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4543 .master = &omap44xx_l4_per_hwmod,
4544 .slave = &omap44xx_dss_dispc_hwmod,
4546 .addr = omap44xx_dss_dispc_addrs,
4547 .user = OCP_USER_MPU,
4550 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4552 .pa_start = 0x58004000,
4553 .pa_end = 0x580041ff,
4554 .flags = ADDR_TYPE_RT
4559 /* l3_main_2 -> dss_dsi1 */
4560 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4561 .master = &omap44xx_l3_main_2_hwmod,
4562 .slave = &omap44xx_dss_dsi1_hwmod,
4564 .addr = omap44xx_dss_dsi1_dma_addrs,
4565 .user = OCP_USER_SDMA,
4568 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4570 .pa_start = 0x48044000,
4571 .pa_end = 0x480441ff,
4572 .flags = ADDR_TYPE_RT
4577 /* l4_per -> dss_dsi1 */
4578 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4579 .master = &omap44xx_l4_per_hwmod,
4580 .slave = &omap44xx_dss_dsi1_hwmod,
4582 .addr = omap44xx_dss_dsi1_addrs,
4583 .user = OCP_USER_MPU,
4586 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4588 .pa_start = 0x58005000,
4589 .pa_end = 0x580051ff,
4590 .flags = ADDR_TYPE_RT
4595 /* l3_main_2 -> dss_dsi2 */
4596 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4597 .master = &omap44xx_l3_main_2_hwmod,
4598 .slave = &omap44xx_dss_dsi2_hwmod,
4600 .addr = omap44xx_dss_dsi2_dma_addrs,
4601 .user = OCP_USER_SDMA,
4604 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4606 .pa_start = 0x48045000,
4607 .pa_end = 0x480451ff,
4608 .flags = ADDR_TYPE_RT
4613 /* l4_per -> dss_dsi2 */
4614 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4615 .master = &omap44xx_l4_per_hwmod,
4616 .slave = &omap44xx_dss_dsi2_hwmod,
4618 .addr = omap44xx_dss_dsi2_addrs,
4619 .user = OCP_USER_MPU,
4622 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4624 .pa_start = 0x58006000,
4625 .pa_end = 0x58006fff,
4626 .flags = ADDR_TYPE_RT
4631 /* l3_main_2 -> dss_hdmi */
4632 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4633 .master = &omap44xx_l3_main_2_hwmod,
4634 .slave = &omap44xx_dss_hdmi_hwmod,
4636 .addr = omap44xx_dss_hdmi_dma_addrs,
4637 .user = OCP_USER_SDMA,
4640 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4642 .pa_start = 0x48046000,
4643 .pa_end = 0x48046fff,
4644 .flags = ADDR_TYPE_RT
4649 /* l4_per -> dss_hdmi */
4650 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4651 .master = &omap44xx_l4_per_hwmod,
4652 .slave = &omap44xx_dss_hdmi_hwmod,
4654 .addr = omap44xx_dss_hdmi_addrs,
4655 .user = OCP_USER_MPU,
4658 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4660 .pa_start = 0x58002000,
4661 .pa_end = 0x580020ff,
4662 .flags = ADDR_TYPE_RT
4667 /* l3_main_2 -> dss_rfbi */
4668 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4669 .master = &omap44xx_l3_main_2_hwmod,
4670 .slave = &omap44xx_dss_rfbi_hwmod,
4672 .addr = omap44xx_dss_rfbi_dma_addrs,
4673 .user = OCP_USER_SDMA,
4676 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4678 .pa_start = 0x48042000,
4679 .pa_end = 0x480420ff,
4680 .flags = ADDR_TYPE_RT
4685 /* l4_per -> dss_rfbi */
4686 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4687 .master = &omap44xx_l4_per_hwmod,
4688 .slave = &omap44xx_dss_rfbi_hwmod,
4690 .addr = omap44xx_dss_rfbi_addrs,
4691 .user = OCP_USER_MPU,
4694 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4696 .pa_start = 0x58003000,
4697 .pa_end = 0x580030ff,
4698 .flags = ADDR_TYPE_RT
4703 /* l3_main_2 -> dss_venc */
4704 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4705 .master = &omap44xx_l3_main_2_hwmod,
4706 .slave = &omap44xx_dss_venc_hwmod,
4708 .addr = omap44xx_dss_venc_dma_addrs,
4709 .user = OCP_USER_SDMA,
4712 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4714 .pa_start = 0x48043000,
4715 .pa_end = 0x480430ff,
4716 .flags = ADDR_TYPE_RT
4721 /* l4_per -> dss_venc */
4722 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4723 .master = &omap44xx_l4_per_hwmod,
4724 .slave = &omap44xx_dss_venc_hwmod,
4726 .addr = omap44xx_dss_venc_addrs,
4727 .user = OCP_USER_MPU,
4730 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4732 .pa_start = 0x48078000,
4733 .pa_end = 0x48078fff,
4734 .flags = ADDR_TYPE_RT
4740 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4741 .master = &omap44xx_l4_per_hwmod,
4742 .slave = &omap44xx_elm_hwmod,
4744 .addr = omap44xx_elm_addrs,
4745 .user = OCP_USER_MPU | OCP_USER_SDMA,
4748 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4750 .pa_start = 0x4c000000,
4751 .pa_end = 0x4c0000ff,
4752 .flags = ADDR_TYPE_RT
4757 /* emif_fw -> emif1 */
4758 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4759 .master = &omap44xx_emif_fw_hwmod,
4760 .slave = &omap44xx_emif1_hwmod,
4762 .addr = omap44xx_emif1_addrs,
4763 .user = OCP_USER_MPU | OCP_USER_SDMA,
4766 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4768 .pa_start = 0x4d000000,
4769 .pa_end = 0x4d0000ff,
4770 .flags = ADDR_TYPE_RT
4775 /* emif_fw -> emif2 */
4776 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4777 .master = &omap44xx_emif_fw_hwmod,
4778 .slave = &omap44xx_emif2_hwmod,
4780 .addr = omap44xx_emif2_addrs,
4781 .user = OCP_USER_MPU | OCP_USER_SDMA,
4784 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4786 .pa_start = 0x4a10a000,
4787 .pa_end = 0x4a10a1ff,
4788 .flags = ADDR_TYPE_RT
4793 /* l4_cfg -> fdif */
4794 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4795 .master = &omap44xx_l4_cfg_hwmod,
4796 .slave = &omap44xx_fdif_hwmod,
4798 .addr = omap44xx_fdif_addrs,
4799 .user = OCP_USER_MPU | OCP_USER_SDMA,
4802 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4804 .pa_start = 0x4a310000,
4805 .pa_end = 0x4a3101ff,
4806 .flags = ADDR_TYPE_RT
4811 /* l4_wkup -> gpio1 */
4812 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4813 .master = &omap44xx_l4_wkup_hwmod,
4814 .slave = &omap44xx_gpio1_hwmod,
4815 .clk = "l4_wkup_clk_mux_ck",
4816 .addr = omap44xx_gpio1_addrs,
4817 .user = OCP_USER_MPU | OCP_USER_SDMA,
4820 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4822 .pa_start = 0x48055000,
4823 .pa_end = 0x480551ff,
4824 .flags = ADDR_TYPE_RT
4829 /* l4_per -> gpio2 */
4830 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4831 .master = &omap44xx_l4_per_hwmod,
4832 .slave = &omap44xx_gpio2_hwmod,
4834 .addr = omap44xx_gpio2_addrs,
4835 .user = OCP_USER_MPU | OCP_USER_SDMA,
4838 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4840 .pa_start = 0x48057000,
4841 .pa_end = 0x480571ff,
4842 .flags = ADDR_TYPE_RT
4847 /* l4_per -> gpio3 */
4848 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4849 .master = &omap44xx_l4_per_hwmod,
4850 .slave = &omap44xx_gpio3_hwmod,
4852 .addr = omap44xx_gpio3_addrs,
4853 .user = OCP_USER_MPU | OCP_USER_SDMA,
4856 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4858 .pa_start = 0x48059000,
4859 .pa_end = 0x480591ff,
4860 .flags = ADDR_TYPE_RT
4865 /* l4_per -> gpio4 */
4866 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4867 .master = &omap44xx_l4_per_hwmod,
4868 .slave = &omap44xx_gpio4_hwmod,
4870 .addr = omap44xx_gpio4_addrs,
4871 .user = OCP_USER_MPU | OCP_USER_SDMA,
4874 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4876 .pa_start = 0x4805b000,
4877 .pa_end = 0x4805b1ff,
4878 .flags = ADDR_TYPE_RT
4883 /* l4_per -> gpio5 */
4884 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4885 .master = &omap44xx_l4_per_hwmod,
4886 .slave = &omap44xx_gpio5_hwmod,
4888 .addr = omap44xx_gpio5_addrs,
4889 .user = OCP_USER_MPU | OCP_USER_SDMA,
4892 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4894 .pa_start = 0x4805d000,
4895 .pa_end = 0x4805d1ff,
4896 .flags = ADDR_TYPE_RT
4901 /* l4_per -> gpio6 */
4902 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4903 .master = &omap44xx_l4_per_hwmod,
4904 .slave = &omap44xx_gpio6_hwmod,
4906 .addr = omap44xx_gpio6_addrs,
4907 .user = OCP_USER_MPU | OCP_USER_SDMA,
4910 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4912 .pa_start = 0x50000000,
4913 .pa_end = 0x500003ff,
4914 .flags = ADDR_TYPE_RT
4919 /* l3_main_2 -> gpmc */
4920 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4921 .master = &omap44xx_l3_main_2_hwmod,
4922 .slave = &omap44xx_gpmc_hwmod,
4924 .addr = omap44xx_gpmc_addrs,
4925 .user = OCP_USER_MPU | OCP_USER_SDMA,
4928 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4930 .pa_start = 0x56000000,
4931 .pa_end = 0x5600ffff,
4932 .flags = ADDR_TYPE_RT
4937 /* l3_main_2 -> gpu */
4938 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4939 .master = &omap44xx_l3_main_2_hwmod,
4940 .slave = &omap44xx_gpu_hwmod,
4942 .addr = omap44xx_gpu_addrs,
4943 .user = OCP_USER_MPU | OCP_USER_SDMA,
4946 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4948 .pa_start = 0x480b2000,
4949 .pa_end = 0x480b201f,
4950 .flags = ADDR_TYPE_RT
4955 /* l4_per -> hdq1w */
4956 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4957 .master = &omap44xx_l4_per_hwmod,
4958 .slave = &omap44xx_hdq1w_hwmod,
4960 .addr = omap44xx_hdq1w_addrs,
4961 .user = OCP_USER_MPU | OCP_USER_SDMA,
4964 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4966 .pa_start = 0x4a058000,
4967 .pa_end = 0x4a05bfff,
4968 .flags = ADDR_TYPE_RT
4974 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4975 .master = &omap44xx_l4_cfg_hwmod,
4976 .slave = &omap44xx_hsi_hwmod,
4978 .addr = omap44xx_hsi_addrs,
4979 .user = OCP_USER_MPU | OCP_USER_SDMA,
4982 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4984 .pa_start = 0x48070000,
4985 .pa_end = 0x480700ff,
4986 .flags = ADDR_TYPE_RT
4991 /* l4_per -> i2c1 */
4992 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4993 .master = &omap44xx_l4_per_hwmod,
4994 .slave = &omap44xx_i2c1_hwmod,
4996 .addr = omap44xx_i2c1_addrs,
4997 .user = OCP_USER_MPU | OCP_USER_SDMA,
5000 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5002 .pa_start = 0x48072000,
5003 .pa_end = 0x480720ff,
5004 .flags = ADDR_TYPE_RT
5009 /* l4_per -> i2c2 */
5010 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5011 .master = &omap44xx_l4_per_hwmod,
5012 .slave = &omap44xx_i2c2_hwmod,
5014 .addr = omap44xx_i2c2_addrs,
5015 .user = OCP_USER_MPU | OCP_USER_SDMA,
5018 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5020 .pa_start = 0x48060000,
5021 .pa_end = 0x480600ff,
5022 .flags = ADDR_TYPE_RT
5027 /* l4_per -> i2c3 */
5028 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5029 .master = &omap44xx_l4_per_hwmod,
5030 .slave = &omap44xx_i2c3_hwmod,
5032 .addr = omap44xx_i2c3_addrs,
5033 .user = OCP_USER_MPU | OCP_USER_SDMA,
5036 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5038 .pa_start = 0x48350000,
5039 .pa_end = 0x483500ff,
5040 .flags = ADDR_TYPE_RT
5045 /* l4_per -> i2c4 */
5046 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5047 .master = &omap44xx_l4_per_hwmod,
5048 .slave = &omap44xx_i2c4_hwmod,
5050 .addr = omap44xx_i2c4_addrs,
5051 .user = OCP_USER_MPU | OCP_USER_SDMA,
5054 /* l3_main_2 -> ipu */
5055 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5056 .master = &omap44xx_l3_main_2_hwmod,
5057 .slave = &omap44xx_ipu_hwmod,
5059 .user = OCP_USER_MPU | OCP_USER_SDMA,
5062 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5064 .pa_start = 0x52000000,
5065 .pa_end = 0x520000ff,
5066 .flags = ADDR_TYPE_RT
5071 /* l3_main_2 -> iss */
5072 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5073 .master = &omap44xx_l3_main_2_hwmod,
5074 .slave = &omap44xx_iss_hwmod,
5076 .addr = omap44xx_iss_addrs,
5077 .user = OCP_USER_MPU | OCP_USER_SDMA,
5081 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5082 .master = &omap44xx_iva_hwmod,
5083 .slave = &omap44xx_sl2if_hwmod,
5084 .clk = "dpll_iva_m5x2_ck",
5085 .user = OCP_USER_IVA,
5088 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5090 .pa_start = 0x5a000000,
5091 .pa_end = 0x5a07ffff,
5092 .flags = ADDR_TYPE_RT
5097 /* l3_main_2 -> iva */
5098 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5099 .master = &omap44xx_l3_main_2_hwmod,
5100 .slave = &omap44xx_iva_hwmod,
5102 .addr = omap44xx_iva_addrs,
5103 .user = OCP_USER_MPU,
5106 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5108 .pa_start = 0x4a31c000,
5109 .pa_end = 0x4a31c07f,
5110 .flags = ADDR_TYPE_RT
5115 /* l4_wkup -> kbd */
5116 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5117 .master = &omap44xx_l4_wkup_hwmod,
5118 .slave = &omap44xx_kbd_hwmod,
5119 .clk = "l4_wkup_clk_mux_ck",
5120 .addr = omap44xx_kbd_addrs,
5121 .user = OCP_USER_MPU | OCP_USER_SDMA,
5124 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5126 .pa_start = 0x4a0f4000,
5127 .pa_end = 0x4a0f41ff,
5128 .flags = ADDR_TYPE_RT
5133 /* l4_cfg -> mailbox */
5134 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5135 .master = &omap44xx_l4_cfg_hwmod,
5136 .slave = &omap44xx_mailbox_hwmod,
5138 .addr = omap44xx_mailbox_addrs,
5139 .user = OCP_USER_MPU | OCP_USER_SDMA,
5142 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5144 .pa_start = 0x40128000,
5145 .pa_end = 0x401283ff,
5146 .flags = ADDR_TYPE_RT
5151 /* l4_abe -> mcasp */
5152 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5153 .master = &omap44xx_l4_abe_hwmod,
5154 .slave = &omap44xx_mcasp_hwmod,
5155 .clk = "ocp_abe_iclk",
5156 .addr = omap44xx_mcasp_addrs,
5157 .user = OCP_USER_MPU,
5160 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5162 .pa_start = 0x49028000,
5163 .pa_end = 0x490283ff,
5164 .flags = ADDR_TYPE_RT
5169 /* l4_abe -> mcasp (dma) */
5170 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5171 .master = &omap44xx_l4_abe_hwmod,
5172 .slave = &omap44xx_mcasp_hwmod,
5173 .clk = "ocp_abe_iclk",
5174 .addr = omap44xx_mcasp_dma_addrs,
5175 .user = OCP_USER_SDMA,
5178 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5181 .pa_start = 0x40122000,
5182 .pa_end = 0x401220ff,
5183 .flags = ADDR_TYPE_RT
5188 /* l4_abe -> mcbsp1 */
5189 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5190 .master = &omap44xx_l4_abe_hwmod,
5191 .slave = &omap44xx_mcbsp1_hwmod,
5192 .clk = "ocp_abe_iclk",
5193 .addr = omap44xx_mcbsp1_addrs,
5194 .user = OCP_USER_MPU,
5197 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5200 .pa_start = 0x49022000,
5201 .pa_end = 0x490220ff,
5202 .flags = ADDR_TYPE_RT
5207 /* l4_abe -> mcbsp1 (dma) */
5208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5209 .master = &omap44xx_l4_abe_hwmod,
5210 .slave = &omap44xx_mcbsp1_hwmod,
5211 .clk = "ocp_abe_iclk",
5212 .addr = omap44xx_mcbsp1_dma_addrs,
5213 .user = OCP_USER_SDMA,
5216 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5219 .pa_start = 0x40124000,
5220 .pa_end = 0x401240ff,
5221 .flags = ADDR_TYPE_RT
5226 /* l4_abe -> mcbsp2 */
5227 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5228 .master = &omap44xx_l4_abe_hwmod,
5229 .slave = &omap44xx_mcbsp2_hwmod,
5230 .clk = "ocp_abe_iclk",
5231 .addr = omap44xx_mcbsp2_addrs,
5232 .user = OCP_USER_MPU,
5235 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5238 .pa_start = 0x49024000,
5239 .pa_end = 0x490240ff,
5240 .flags = ADDR_TYPE_RT
5245 /* l4_abe -> mcbsp2 (dma) */
5246 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5247 .master = &omap44xx_l4_abe_hwmod,
5248 .slave = &omap44xx_mcbsp2_hwmod,
5249 .clk = "ocp_abe_iclk",
5250 .addr = omap44xx_mcbsp2_dma_addrs,
5251 .user = OCP_USER_SDMA,
5254 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5257 .pa_start = 0x40126000,
5258 .pa_end = 0x401260ff,
5259 .flags = ADDR_TYPE_RT
5264 /* l4_abe -> mcbsp3 */
5265 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5266 .master = &omap44xx_l4_abe_hwmod,
5267 .slave = &omap44xx_mcbsp3_hwmod,
5268 .clk = "ocp_abe_iclk",
5269 .addr = omap44xx_mcbsp3_addrs,
5270 .user = OCP_USER_MPU,
5273 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5276 .pa_start = 0x49026000,
5277 .pa_end = 0x490260ff,
5278 .flags = ADDR_TYPE_RT
5283 /* l4_abe -> mcbsp3 (dma) */
5284 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5285 .master = &omap44xx_l4_abe_hwmod,
5286 .slave = &omap44xx_mcbsp3_hwmod,
5287 .clk = "ocp_abe_iclk",
5288 .addr = omap44xx_mcbsp3_dma_addrs,
5289 .user = OCP_USER_SDMA,
5292 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5294 .pa_start = 0x48096000,
5295 .pa_end = 0x480960ff,
5296 .flags = ADDR_TYPE_RT
5301 /* l4_per -> mcbsp4 */
5302 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5303 .master = &omap44xx_l4_per_hwmod,
5304 .slave = &omap44xx_mcbsp4_hwmod,
5306 .addr = omap44xx_mcbsp4_addrs,
5307 .user = OCP_USER_MPU | OCP_USER_SDMA,
5310 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5313 .pa_start = 0x40132000,
5314 .pa_end = 0x4013207f,
5315 .flags = ADDR_TYPE_RT
5320 /* l4_abe -> mcpdm */
5321 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5322 .master = &omap44xx_l4_abe_hwmod,
5323 .slave = &omap44xx_mcpdm_hwmod,
5324 .clk = "ocp_abe_iclk",
5325 .addr = omap44xx_mcpdm_addrs,
5326 .user = OCP_USER_MPU,
5329 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5332 .pa_start = 0x49032000,
5333 .pa_end = 0x4903207f,
5334 .flags = ADDR_TYPE_RT
5339 /* l4_abe -> mcpdm (dma) */
5340 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5341 .master = &omap44xx_l4_abe_hwmod,
5342 .slave = &omap44xx_mcpdm_hwmod,
5343 .clk = "ocp_abe_iclk",
5344 .addr = omap44xx_mcpdm_dma_addrs,
5345 .user = OCP_USER_SDMA,
5348 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5350 .pa_start = 0x48098000,
5351 .pa_end = 0x480981ff,
5352 .flags = ADDR_TYPE_RT
5357 /* l4_per -> mcspi1 */
5358 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5359 .master = &omap44xx_l4_per_hwmod,
5360 .slave = &omap44xx_mcspi1_hwmod,
5362 .addr = omap44xx_mcspi1_addrs,
5363 .user = OCP_USER_MPU | OCP_USER_SDMA,
5366 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5368 .pa_start = 0x4809a000,
5369 .pa_end = 0x4809a1ff,
5370 .flags = ADDR_TYPE_RT
5375 /* l4_per -> mcspi2 */
5376 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5377 .master = &omap44xx_l4_per_hwmod,
5378 .slave = &omap44xx_mcspi2_hwmod,
5380 .addr = omap44xx_mcspi2_addrs,
5381 .user = OCP_USER_MPU | OCP_USER_SDMA,
5384 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5386 .pa_start = 0x480b8000,
5387 .pa_end = 0x480b81ff,
5388 .flags = ADDR_TYPE_RT
5393 /* l4_per -> mcspi3 */
5394 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5395 .master = &omap44xx_l4_per_hwmod,
5396 .slave = &omap44xx_mcspi3_hwmod,
5398 .addr = omap44xx_mcspi3_addrs,
5399 .user = OCP_USER_MPU | OCP_USER_SDMA,
5402 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5404 .pa_start = 0x480ba000,
5405 .pa_end = 0x480ba1ff,
5406 .flags = ADDR_TYPE_RT
5411 /* l4_per -> mcspi4 */
5412 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5413 .master = &omap44xx_l4_per_hwmod,
5414 .slave = &omap44xx_mcspi4_hwmod,
5416 .addr = omap44xx_mcspi4_addrs,
5417 .user = OCP_USER_MPU | OCP_USER_SDMA,
5420 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5422 .pa_start = 0x4809c000,
5423 .pa_end = 0x4809c3ff,
5424 .flags = ADDR_TYPE_RT
5429 /* l4_per -> mmc1 */
5430 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5431 .master = &omap44xx_l4_per_hwmod,
5432 .slave = &omap44xx_mmc1_hwmod,
5434 .addr = omap44xx_mmc1_addrs,
5435 .user = OCP_USER_MPU | OCP_USER_SDMA,
5438 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5440 .pa_start = 0x480b4000,
5441 .pa_end = 0x480b43ff,
5442 .flags = ADDR_TYPE_RT
5447 /* l4_per -> mmc2 */
5448 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5449 .master = &omap44xx_l4_per_hwmod,
5450 .slave = &omap44xx_mmc2_hwmod,
5452 .addr = omap44xx_mmc2_addrs,
5453 .user = OCP_USER_MPU | OCP_USER_SDMA,
5456 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5458 .pa_start = 0x480ad000,
5459 .pa_end = 0x480ad3ff,
5460 .flags = ADDR_TYPE_RT
5465 /* l4_per -> mmc3 */
5466 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5467 .master = &omap44xx_l4_per_hwmod,
5468 .slave = &omap44xx_mmc3_hwmod,
5470 .addr = omap44xx_mmc3_addrs,
5471 .user = OCP_USER_MPU | OCP_USER_SDMA,
5474 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5476 .pa_start = 0x480d1000,
5477 .pa_end = 0x480d13ff,
5478 .flags = ADDR_TYPE_RT
5483 /* l4_per -> mmc4 */
5484 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5485 .master = &omap44xx_l4_per_hwmod,
5486 .slave = &omap44xx_mmc4_hwmod,
5488 .addr = omap44xx_mmc4_addrs,
5489 .user = OCP_USER_MPU | OCP_USER_SDMA,
5492 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5494 .pa_start = 0x480d5000,
5495 .pa_end = 0x480d53ff,
5496 .flags = ADDR_TYPE_RT
5501 /* l4_per -> mmc5 */
5502 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5503 .master = &omap44xx_l4_per_hwmod,
5504 .slave = &omap44xx_mmc5_hwmod,
5506 .addr = omap44xx_mmc5_addrs,
5507 .user = OCP_USER_MPU | OCP_USER_SDMA,
5510 /* l3_main_2 -> ocmc_ram */
5511 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5512 .master = &omap44xx_l3_main_2_hwmod,
5513 .slave = &omap44xx_ocmc_ram_hwmod,
5515 .user = OCP_USER_MPU | OCP_USER_SDMA,
5518 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5520 .pa_start = 0x4a0ad000,
5521 .pa_end = 0x4a0ad01f,
5522 .flags = ADDR_TYPE_RT
5527 /* l4_cfg -> ocp2scp_usb_phy */
5528 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5529 .master = &omap44xx_l4_cfg_hwmod,
5530 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5532 .addr = omap44xx_ocp2scp_usb_phy_addrs,
5533 .user = OCP_USER_MPU | OCP_USER_SDMA,
5536 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5538 .pa_start = 0x48243000,
5539 .pa_end = 0x48243fff,
5540 .flags = ADDR_TYPE_RT
5545 /* mpu_private -> prcm_mpu */
5546 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5547 .master = &omap44xx_mpu_private_hwmod,
5548 .slave = &omap44xx_prcm_mpu_hwmod,
5550 .addr = omap44xx_prcm_mpu_addrs,
5551 .user = OCP_USER_MPU | OCP_USER_SDMA,
5554 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5556 .pa_start = 0x4a004000,
5557 .pa_end = 0x4a004fff,
5558 .flags = ADDR_TYPE_RT
5563 /* l4_wkup -> cm_core_aon */
5564 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5565 .master = &omap44xx_l4_wkup_hwmod,
5566 .slave = &omap44xx_cm_core_aon_hwmod,
5567 .clk = "l4_wkup_clk_mux_ck",
5568 .addr = omap44xx_cm_core_aon_addrs,
5569 .user = OCP_USER_MPU | OCP_USER_SDMA,
5572 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5574 .pa_start = 0x4a008000,
5575 .pa_end = 0x4a009fff,
5576 .flags = ADDR_TYPE_RT
5581 /* l4_cfg -> cm_core */
5582 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5583 .master = &omap44xx_l4_cfg_hwmod,
5584 .slave = &omap44xx_cm_core_hwmod,
5586 .addr = omap44xx_cm_core_addrs,
5587 .user = OCP_USER_MPU | OCP_USER_SDMA,
5590 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5592 .pa_start = 0x4a306000,
5593 .pa_end = 0x4a307fff,
5594 .flags = ADDR_TYPE_RT
5599 /* l4_wkup -> prm */
5600 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5601 .master = &omap44xx_l4_wkup_hwmod,
5602 .slave = &omap44xx_prm_hwmod,
5603 .clk = "l4_wkup_clk_mux_ck",
5604 .addr = omap44xx_prm_addrs,
5605 .user = OCP_USER_MPU | OCP_USER_SDMA,
5608 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5610 .pa_start = 0x4a30a000,
5611 .pa_end = 0x4a30a7ff,
5612 .flags = ADDR_TYPE_RT
5617 /* l4_wkup -> scrm */
5618 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5619 .master = &omap44xx_l4_wkup_hwmod,
5620 .slave = &omap44xx_scrm_hwmod,
5621 .clk = "l4_wkup_clk_mux_ck",
5622 .addr = omap44xx_scrm_addrs,
5623 .user = OCP_USER_MPU | OCP_USER_SDMA,
5626 /* l3_main_2 -> sl2if */
5627 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5628 .master = &omap44xx_l3_main_2_hwmod,
5629 .slave = &omap44xx_sl2if_hwmod,
5631 .user = OCP_USER_MPU | OCP_USER_SDMA,
5634 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5636 .pa_start = 0x4012c000,
5637 .pa_end = 0x4012c3ff,
5638 .flags = ADDR_TYPE_RT
5643 /* l4_abe -> slimbus1 */
5644 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5645 .master = &omap44xx_l4_abe_hwmod,
5646 .slave = &omap44xx_slimbus1_hwmod,
5647 .clk = "ocp_abe_iclk",
5648 .addr = omap44xx_slimbus1_addrs,
5649 .user = OCP_USER_MPU,
5652 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5654 .pa_start = 0x4902c000,
5655 .pa_end = 0x4902c3ff,
5656 .flags = ADDR_TYPE_RT
5661 /* l4_abe -> slimbus1 (dma) */
5662 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5663 .master = &omap44xx_l4_abe_hwmod,
5664 .slave = &omap44xx_slimbus1_hwmod,
5665 .clk = "ocp_abe_iclk",
5666 .addr = omap44xx_slimbus1_dma_addrs,
5667 .user = OCP_USER_SDMA,
5670 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5672 .pa_start = 0x48076000,
5673 .pa_end = 0x480763ff,
5674 .flags = ADDR_TYPE_RT
5679 /* l4_per -> slimbus2 */
5680 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5681 .master = &omap44xx_l4_per_hwmod,
5682 .slave = &omap44xx_slimbus2_hwmod,
5684 .addr = omap44xx_slimbus2_addrs,
5685 .user = OCP_USER_MPU | OCP_USER_SDMA,
5688 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5690 .pa_start = 0x4a0dd000,
5691 .pa_end = 0x4a0dd03f,
5692 .flags = ADDR_TYPE_RT
5697 /* l4_cfg -> smartreflex_core */
5698 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5699 .master = &omap44xx_l4_cfg_hwmod,
5700 .slave = &omap44xx_smartreflex_core_hwmod,
5702 .addr = omap44xx_smartreflex_core_addrs,
5703 .user = OCP_USER_MPU | OCP_USER_SDMA,
5706 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5708 .pa_start = 0x4a0db000,
5709 .pa_end = 0x4a0db03f,
5710 .flags = ADDR_TYPE_RT
5715 /* l4_cfg -> smartreflex_iva */
5716 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5717 .master = &omap44xx_l4_cfg_hwmod,
5718 .slave = &omap44xx_smartreflex_iva_hwmod,
5720 .addr = omap44xx_smartreflex_iva_addrs,
5721 .user = OCP_USER_MPU | OCP_USER_SDMA,
5724 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5726 .pa_start = 0x4a0d9000,
5727 .pa_end = 0x4a0d903f,
5728 .flags = ADDR_TYPE_RT
5733 /* l4_cfg -> smartreflex_mpu */
5734 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5735 .master = &omap44xx_l4_cfg_hwmod,
5736 .slave = &omap44xx_smartreflex_mpu_hwmod,
5738 .addr = omap44xx_smartreflex_mpu_addrs,
5739 .user = OCP_USER_MPU | OCP_USER_SDMA,
5742 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5744 .pa_start = 0x4a0f6000,
5745 .pa_end = 0x4a0f6fff,
5746 .flags = ADDR_TYPE_RT
5751 /* l4_cfg -> spinlock */
5752 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5753 .master = &omap44xx_l4_cfg_hwmod,
5754 .slave = &omap44xx_spinlock_hwmod,
5756 .addr = omap44xx_spinlock_addrs,
5757 .user = OCP_USER_MPU | OCP_USER_SDMA,
5760 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5762 .pa_start = 0x4a318000,
5763 .pa_end = 0x4a31807f,
5764 .flags = ADDR_TYPE_RT
5769 /* l4_wkup -> timer1 */
5770 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5771 .master = &omap44xx_l4_wkup_hwmod,
5772 .slave = &omap44xx_timer1_hwmod,
5773 .clk = "l4_wkup_clk_mux_ck",
5774 .addr = omap44xx_timer1_addrs,
5775 .user = OCP_USER_MPU | OCP_USER_SDMA,
5778 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5780 .pa_start = 0x48032000,
5781 .pa_end = 0x4803207f,
5782 .flags = ADDR_TYPE_RT
5787 /* l4_per -> timer2 */
5788 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5789 .master = &omap44xx_l4_per_hwmod,
5790 .slave = &omap44xx_timer2_hwmod,
5792 .addr = omap44xx_timer2_addrs,
5793 .user = OCP_USER_MPU | OCP_USER_SDMA,
5796 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5798 .pa_start = 0x48034000,
5799 .pa_end = 0x4803407f,
5800 .flags = ADDR_TYPE_RT
5805 /* l4_per -> timer3 */
5806 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5807 .master = &omap44xx_l4_per_hwmod,
5808 .slave = &omap44xx_timer3_hwmod,
5810 .addr = omap44xx_timer3_addrs,
5811 .user = OCP_USER_MPU | OCP_USER_SDMA,
5814 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5816 .pa_start = 0x48036000,
5817 .pa_end = 0x4803607f,
5818 .flags = ADDR_TYPE_RT
5823 /* l4_per -> timer4 */
5824 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5825 .master = &omap44xx_l4_per_hwmod,
5826 .slave = &omap44xx_timer4_hwmod,
5828 .addr = omap44xx_timer4_addrs,
5829 .user = OCP_USER_MPU | OCP_USER_SDMA,
5832 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5834 .pa_start = 0x40138000,
5835 .pa_end = 0x4013807f,
5836 .flags = ADDR_TYPE_RT
5841 /* l4_abe -> timer5 */
5842 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5843 .master = &omap44xx_l4_abe_hwmod,
5844 .slave = &omap44xx_timer5_hwmod,
5845 .clk = "ocp_abe_iclk",
5846 .addr = omap44xx_timer5_addrs,
5847 .user = OCP_USER_MPU,
5850 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5852 .pa_start = 0x49038000,
5853 .pa_end = 0x4903807f,
5854 .flags = ADDR_TYPE_RT
5859 /* l4_abe -> timer5 (dma) */
5860 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5861 .master = &omap44xx_l4_abe_hwmod,
5862 .slave = &omap44xx_timer5_hwmod,
5863 .clk = "ocp_abe_iclk",
5864 .addr = omap44xx_timer5_dma_addrs,
5865 .user = OCP_USER_SDMA,
5868 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5870 .pa_start = 0x4013a000,
5871 .pa_end = 0x4013a07f,
5872 .flags = ADDR_TYPE_RT
5877 /* l4_abe -> timer6 */
5878 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5879 .master = &omap44xx_l4_abe_hwmod,
5880 .slave = &omap44xx_timer6_hwmod,
5881 .clk = "ocp_abe_iclk",
5882 .addr = omap44xx_timer6_addrs,
5883 .user = OCP_USER_MPU,
5886 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5888 .pa_start = 0x4903a000,
5889 .pa_end = 0x4903a07f,
5890 .flags = ADDR_TYPE_RT
5895 /* l4_abe -> timer6 (dma) */
5896 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5897 .master = &omap44xx_l4_abe_hwmod,
5898 .slave = &omap44xx_timer6_hwmod,
5899 .clk = "ocp_abe_iclk",
5900 .addr = omap44xx_timer6_dma_addrs,
5901 .user = OCP_USER_SDMA,
5904 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5906 .pa_start = 0x4013c000,
5907 .pa_end = 0x4013c07f,
5908 .flags = ADDR_TYPE_RT
5913 /* l4_abe -> timer7 */
5914 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5915 .master = &omap44xx_l4_abe_hwmod,
5916 .slave = &omap44xx_timer7_hwmod,
5917 .clk = "ocp_abe_iclk",
5918 .addr = omap44xx_timer7_addrs,
5919 .user = OCP_USER_MPU,
5922 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5924 .pa_start = 0x4903c000,
5925 .pa_end = 0x4903c07f,
5926 .flags = ADDR_TYPE_RT
5931 /* l4_abe -> timer7 (dma) */
5932 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5933 .master = &omap44xx_l4_abe_hwmod,
5934 .slave = &omap44xx_timer7_hwmod,
5935 .clk = "ocp_abe_iclk",
5936 .addr = omap44xx_timer7_dma_addrs,
5937 .user = OCP_USER_SDMA,
5940 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5942 .pa_start = 0x4013e000,
5943 .pa_end = 0x4013e07f,
5944 .flags = ADDR_TYPE_RT
5949 /* l4_abe -> timer8 */
5950 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5951 .master = &omap44xx_l4_abe_hwmod,
5952 .slave = &omap44xx_timer8_hwmod,
5953 .clk = "ocp_abe_iclk",
5954 .addr = omap44xx_timer8_addrs,
5955 .user = OCP_USER_MPU,
5958 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5960 .pa_start = 0x4903e000,
5961 .pa_end = 0x4903e07f,
5962 .flags = ADDR_TYPE_RT
5967 /* l4_abe -> timer8 (dma) */
5968 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5969 .master = &omap44xx_l4_abe_hwmod,
5970 .slave = &omap44xx_timer8_hwmod,
5971 .clk = "ocp_abe_iclk",
5972 .addr = omap44xx_timer8_dma_addrs,
5973 .user = OCP_USER_SDMA,
5976 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5978 .pa_start = 0x4803e000,
5979 .pa_end = 0x4803e07f,
5980 .flags = ADDR_TYPE_RT
5985 /* l4_per -> timer9 */
5986 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5987 .master = &omap44xx_l4_per_hwmod,
5988 .slave = &omap44xx_timer9_hwmod,
5990 .addr = omap44xx_timer9_addrs,
5991 .user = OCP_USER_MPU | OCP_USER_SDMA,
5994 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5996 .pa_start = 0x48086000,
5997 .pa_end = 0x4808607f,
5998 .flags = ADDR_TYPE_RT
6003 /* l4_per -> timer10 */
6004 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6005 .master = &omap44xx_l4_per_hwmod,
6006 .slave = &omap44xx_timer10_hwmod,
6008 .addr = omap44xx_timer10_addrs,
6009 .user = OCP_USER_MPU | OCP_USER_SDMA,
6012 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6014 .pa_start = 0x48088000,
6015 .pa_end = 0x4808807f,
6016 .flags = ADDR_TYPE_RT
6021 /* l4_per -> timer11 */
6022 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6023 .master = &omap44xx_l4_per_hwmod,
6024 .slave = &omap44xx_timer11_hwmod,
6026 .addr = omap44xx_timer11_addrs,
6027 .user = OCP_USER_MPU | OCP_USER_SDMA,
6030 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6032 .pa_start = 0x4806a000,
6033 .pa_end = 0x4806a0ff,
6034 .flags = ADDR_TYPE_RT
6039 /* l4_per -> uart1 */
6040 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6041 .master = &omap44xx_l4_per_hwmod,
6042 .slave = &omap44xx_uart1_hwmod,
6044 .addr = omap44xx_uart1_addrs,
6045 .user = OCP_USER_MPU | OCP_USER_SDMA,
6048 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6050 .pa_start = 0x4806c000,
6051 .pa_end = 0x4806c0ff,
6052 .flags = ADDR_TYPE_RT
6057 /* l4_per -> uart2 */
6058 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6059 .master = &omap44xx_l4_per_hwmod,
6060 .slave = &omap44xx_uart2_hwmod,
6062 .addr = omap44xx_uart2_addrs,
6063 .user = OCP_USER_MPU | OCP_USER_SDMA,
6066 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6068 .pa_start = 0x48020000,
6069 .pa_end = 0x480200ff,
6070 .flags = ADDR_TYPE_RT
6075 /* l4_per -> uart3 */
6076 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6077 .master = &omap44xx_l4_per_hwmod,
6078 .slave = &omap44xx_uart3_hwmod,
6080 .addr = omap44xx_uart3_addrs,
6081 .user = OCP_USER_MPU | OCP_USER_SDMA,
6084 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6086 .pa_start = 0x4806e000,
6087 .pa_end = 0x4806e0ff,
6088 .flags = ADDR_TYPE_RT
6093 /* l4_per -> uart4 */
6094 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6095 .master = &omap44xx_l4_per_hwmod,
6096 .slave = &omap44xx_uart4_hwmod,
6098 .addr = omap44xx_uart4_addrs,
6099 .user = OCP_USER_MPU | OCP_USER_SDMA,
6102 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6104 .pa_start = 0x4a0a9000,
6105 .pa_end = 0x4a0a93ff,
6106 .flags = ADDR_TYPE_RT
6111 /* l4_cfg -> usb_host_fs */
6112 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6113 .master = &omap44xx_l4_cfg_hwmod,
6114 .slave = &omap44xx_usb_host_fs_hwmod,
6116 .addr = omap44xx_usb_host_fs_addrs,
6117 .user = OCP_USER_MPU | OCP_USER_SDMA,
6120 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6123 .pa_start = 0x4a064000,
6124 .pa_end = 0x4a0647ff,
6125 .flags = ADDR_TYPE_RT
6129 .pa_start = 0x4a064800,
6130 .pa_end = 0x4a064bff,
6134 .pa_start = 0x4a064c00,
6135 .pa_end = 0x4a064fff,
6140 /* l4_cfg -> usb_host_hs */
6141 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6142 .master = &omap44xx_l4_cfg_hwmod,
6143 .slave = &omap44xx_usb_host_hs_hwmod,
6145 .addr = omap44xx_usb_host_hs_addrs,
6146 .user = OCP_USER_MPU | OCP_USER_SDMA,
6149 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6151 .pa_start = 0x4a0ab000,
6152 .pa_end = 0x4a0ab7ff,
6153 .flags = ADDR_TYPE_RT
6156 /* XXX: Remove this once control module driver is in place */
6157 .pa_start = 0x4a00233c,
6158 .pa_end = 0x4a00233f,
6159 .flags = ADDR_TYPE_RT
6164 /* l4_cfg -> usb_otg_hs */
6165 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6166 .master = &omap44xx_l4_cfg_hwmod,
6167 .slave = &omap44xx_usb_otg_hs_hwmod,
6169 .addr = omap44xx_usb_otg_hs_addrs,
6170 .user = OCP_USER_MPU | OCP_USER_SDMA,
6173 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6176 .pa_start = 0x4a062000,
6177 .pa_end = 0x4a063fff,
6178 .flags = ADDR_TYPE_RT
6183 /* l4_cfg -> usb_tll_hs */
6184 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6185 .master = &omap44xx_l4_cfg_hwmod,
6186 .slave = &omap44xx_usb_tll_hs_hwmod,
6188 .addr = omap44xx_usb_tll_hs_addrs,
6189 .user = OCP_USER_MPU | OCP_USER_SDMA,
6192 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6194 .pa_start = 0x4a314000,
6195 .pa_end = 0x4a31407f,
6196 .flags = ADDR_TYPE_RT
6201 /* l4_wkup -> wd_timer2 */
6202 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6203 .master = &omap44xx_l4_wkup_hwmod,
6204 .slave = &omap44xx_wd_timer2_hwmod,
6205 .clk = "l4_wkup_clk_mux_ck",
6206 .addr = omap44xx_wd_timer2_addrs,
6207 .user = OCP_USER_MPU | OCP_USER_SDMA,
6210 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6212 .pa_start = 0x40130000,
6213 .pa_end = 0x4013007f,
6214 .flags = ADDR_TYPE_RT
6219 /* l4_abe -> wd_timer3 */
6220 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6221 .master = &omap44xx_l4_abe_hwmod,
6222 .slave = &omap44xx_wd_timer3_hwmod,
6223 .clk = "ocp_abe_iclk",
6224 .addr = omap44xx_wd_timer3_addrs,
6225 .user = OCP_USER_MPU,
6228 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6230 .pa_start = 0x49030000,
6231 .pa_end = 0x4903007f,
6232 .flags = ADDR_TYPE_RT
6237 /* l4_abe -> wd_timer3 (dma) */
6238 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6239 .master = &omap44xx_l4_abe_hwmod,
6240 .slave = &omap44xx_wd_timer3_hwmod,
6241 .clk = "ocp_abe_iclk",
6242 .addr = omap44xx_wd_timer3_dma_addrs,
6243 .user = OCP_USER_SDMA,
6246 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6247 &omap44xx_c2c__c2c_target_fw,
6248 &omap44xx_l4_cfg__c2c_target_fw,
6249 &omap44xx_l3_main_1__dmm,
6251 &omap44xx_c2c__emif_fw,
6252 &omap44xx_dmm__emif_fw,
6253 &omap44xx_l4_cfg__emif_fw,
6254 &omap44xx_iva__l3_instr,
6255 &omap44xx_l3_main_3__l3_instr,
6256 &omap44xx_ocp_wp_noc__l3_instr,
6257 &omap44xx_dsp__l3_main_1,
6258 &omap44xx_dss__l3_main_1,
6259 &omap44xx_l3_main_2__l3_main_1,
6260 &omap44xx_l4_cfg__l3_main_1,
6261 &omap44xx_mmc1__l3_main_1,
6262 &omap44xx_mmc2__l3_main_1,
6263 &omap44xx_mpu__l3_main_1,
6264 &omap44xx_c2c_target_fw__l3_main_2,
6265 &omap44xx_debugss__l3_main_2,
6266 &omap44xx_dma_system__l3_main_2,
6267 &omap44xx_fdif__l3_main_2,
6268 &omap44xx_gpu__l3_main_2,
6269 &omap44xx_hsi__l3_main_2,
6270 &omap44xx_ipu__l3_main_2,
6271 &omap44xx_iss__l3_main_2,
6272 &omap44xx_iva__l3_main_2,
6273 &omap44xx_l3_main_1__l3_main_2,
6274 &omap44xx_l4_cfg__l3_main_2,
6275 /* &omap44xx_usb_host_fs__l3_main_2, */
6276 &omap44xx_usb_host_hs__l3_main_2,
6277 &omap44xx_usb_otg_hs__l3_main_2,
6278 &omap44xx_l3_main_1__l3_main_3,
6279 &omap44xx_l3_main_2__l3_main_3,
6280 &omap44xx_l4_cfg__l3_main_3,
6281 /* &omap44xx_aess__l4_abe, */
6282 &omap44xx_dsp__l4_abe,
6283 &omap44xx_l3_main_1__l4_abe,
6284 &omap44xx_mpu__l4_abe,
6285 &omap44xx_l3_main_1__l4_cfg,
6286 &omap44xx_l3_main_2__l4_per,
6287 &omap44xx_l4_cfg__l4_wkup,
6288 &omap44xx_mpu__mpu_private,
6289 &omap44xx_l4_cfg__ocp_wp_noc,
6290 /* &omap44xx_l4_abe__aess, */
6291 /* &omap44xx_l4_abe__aess_dma, */
6292 &omap44xx_l3_main_2__c2c,
6293 &omap44xx_l4_wkup__counter_32k,
6294 &omap44xx_l4_cfg__ctrl_module_core,
6295 &omap44xx_l4_cfg__ctrl_module_pad_core,
6296 &omap44xx_l4_wkup__ctrl_module_wkup,
6297 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6298 &omap44xx_l3_instr__debugss,
6299 &omap44xx_l4_cfg__dma_system,
6300 &omap44xx_l4_abe__dmic,
6301 &omap44xx_l4_abe__dmic_dma,
6303 /* &omap44xx_dsp__sl2if, */
6304 &omap44xx_l4_cfg__dsp,
6305 &omap44xx_l3_main_2__dss,
6306 &omap44xx_l4_per__dss,
6307 &omap44xx_l3_main_2__dss_dispc,
6308 &omap44xx_l4_per__dss_dispc,
6309 &omap44xx_l3_main_2__dss_dsi1,
6310 &omap44xx_l4_per__dss_dsi1,
6311 &omap44xx_l3_main_2__dss_dsi2,
6312 &omap44xx_l4_per__dss_dsi2,
6313 &omap44xx_l3_main_2__dss_hdmi,
6314 &omap44xx_l4_per__dss_hdmi,
6315 &omap44xx_l3_main_2__dss_rfbi,
6316 &omap44xx_l4_per__dss_rfbi,
6317 &omap44xx_l3_main_2__dss_venc,
6318 &omap44xx_l4_per__dss_venc,
6319 &omap44xx_l4_per__elm,
6320 &omap44xx_emif_fw__emif1,
6321 &omap44xx_emif_fw__emif2,
6322 &omap44xx_l4_cfg__fdif,
6323 &omap44xx_l4_wkup__gpio1,
6324 &omap44xx_l4_per__gpio2,
6325 &omap44xx_l4_per__gpio3,
6326 &omap44xx_l4_per__gpio4,
6327 &omap44xx_l4_per__gpio5,
6328 &omap44xx_l4_per__gpio6,
6329 &omap44xx_l3_main_2__gpmc,
6330 &omap44xx_l3_main_2__gpu,
6331 &omap44xx_l4_per__hdq1w,
6332 &omap44xx_l4_cfg__hsi,
6333 &omap44xx_l4_per__i2c1,
6334 &omap44xx_l4_per__i2c2,
6335 &omap44xx_l4_per__i2c3,
6336 &omap44xx_l4_per__i2c4,
6337 &omap44xx_l3_main_2__ipu,
6338 &omap44xx_l3_main_2__iss,
6339 /* &omap44xx_iva__sl2if, */
6340 &omap44xx_l3_main_2__iva,
6341 &omap44xx_l4_wkup__kbd,
6342 &omap44xx_l4_cfg__mailbox,
6343 &omap44xx_l4_abe__mcasp,
6344 &omap44xx_l4_abe__mcasp_dma,
6345 &omap44xx_l4_abe__mcbsp1,
6346 &omap44xx_l4_abe__mcbsp1_dma,
6347 &omap44xx_l4_abe__mcbsp2,
6348 &omap44xx_l4_abe__mcbsp2_dma,
6349 &omap44xx_l4_abe__mcbsp3,
6350 &omap44xx_l4_abe__mcbsp3_dma,
6351 &omap44xx_l4_per__mcbsp4,
6352 &omap44xx_l4_abe__mcpdm,
6353 &omap44xx_l4_abe__mcpdm_dma,
6354 &omap44xx_l4_per__mcspi1,
6355 &omap44xx_l4_per__mcspi2,
6356 &omap44xx_l4_per__mcspi3,
6357 &omap44xx_l4_per__mcspi4,
6358 &omap44xx_l4_per__mmc1,
6359 &omap44xx_l4_per__mmc2,
6360 &omap44xx_l4_per__mmc3,
6361 &omap44xx_l4_per__mmc4,
6362 &omap44xx_l4_per__mmc5,
6363 &omap44xx_l3_main_2__mmu_ipu,
6364 &omap44xx_l4_cfg__mmu_dsp,
6365 &omap44xx_l3_main_2__ocmc_ram,
6366 &omap44xx_l4_cfg__ocp2scp_usb_phy,
6367 &omap44xx_mpu_private__prcm_mpu,
6368 &omap44xx_l4_wkup__cm_core_aon,
6369 &omap44xx_l4_cfg__cm_core,
6370 &omap44xx_l4_wkup__prm,
6371 &omap44xx_l4_wkup__scrm,
6372 /* &omap44xx_l3_main_2__sl2if, */
6373 &omap44xx_l4_abe__slimbus1,
6374 &omap44xx_l4_abe__slimbus1_dma,
6375 &omap44xx_l4_per__slimbus2,
6376 &omap44xx_l4_cfg__smartreflex_core,
6377 &omap44xx_l4_cfg__smartreflex_iva,
6378 &omap44xx_l4_cfg__smartreflex_mpu,
6379 &omap44xx_l4_cfg__spinlock,
6380 &omap44xx_l4_wkup__timer1,
6381 &omap44xx_l4_per__timer2,
6382 &omap44xx_l4_per__timer3,
6383 &omap44xx_l4_per__timer4,
6384 &omap44xx_l4_abe__timer5,
6385 &omap44xx_l4_abe__timer5_dma,
6386 &omap44xx_l4_abe__timer6,
6387 &omap44xx_l4_abe__timer6_dma,
6388 &omap44xx_l4_abe__timer7,
6389 &omap44xx_l4_abe__timer7_dma,
6390 &omap44xx_l4_abe__timer8,
6391 &omap44xx_l4_abe__timer8_dma,
6392 &omap44xx_l4_per__timer9,
6393 &omap44xx_l4_per__timer10,
6394 &omap44xx_l4_per__timer11,
6395 &omap44xx_l4_per__uart1,
6396 &omap44xx_l4_per__uart2,
6397 &omap44xx_l4_per__uart3,
6398 &omap44xx_l4_per__uart4,
6399 /* &omap44xx_l4_cfg__usb_host_fs, */
6400 &omap44xx_l4_cfg__usb_host_hs,
6401 &omap44xx_l4_cfg__usb_otg_hs,
6402 &omap44xx_l4_cfg__usb_tll_hs,
6403 &omap44xx_l4_wkup__wd_timer2,
6404 &omap44xx_l4_abe__wd_timer3,
6405 &omap44xx_l4_abe__wd_timer3_dma,
6409 int __init omap44xx_hwmod_init(void)
6412 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);