2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
30 #include <linux/irq.h>
31 #include <linux/time.h>
32 #include <linux/gpio.h>
33 #include <linux/console.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <mach/irqs.h>
40 #include <plat/clock.h>
41 #include <plat/sram.h>
43 #include <plat/board.h>
46 #include "prm2xxx_3xxx.h"
47 #include "prm-regbits-24xx.h"
48 #include "cm2xxx_3xxx.h"
49 #include "cm-regbits-24xx.h"
54 #include "powerdomain.h"
55 #include "clockdomain.h"
58 static suspend_state_t suspend_state = PM_SUSPEND_ON;
59 static inline bool is_suspending(void)
61 return (suspend_state != PM_SUSPEND_ON);
64 static inline bool is_suspending(void)
70 static void (*omap2_sram_idle)(void);
71 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
72 void __iomem *sdrc_power);
74 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
75 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
77 static struct clk *osc_ck, *emul_ck;
79 static int omap2_fclks_active(void)
83 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
84 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
86 /* Ignore UART clocks. These are handled by UART core (serial.c) */
87 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
88 f2 &= ~OMAP24XX_EN_UART3_MASK;
95 static void omap2_enter_full_retention(void)
99 /* There is 1 reference hold for all children of the oscillator
100 * clock, the following will remove it. If no one else uses the
101 * oscillator itself it will be disabled if/when we enter retention
106 /* Clear old wake-up events */
107 /* REVISIT: These write to reserved bits? */
108 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
109 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
110 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
113 * Set MPU powerdomain's next power state to RETENTION;
114 * preserve logic state during retention
116 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
117 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
119 /* Workaround to kill USB */
120 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
121 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
123 omap2_gpio_prepare_for_idle(0);
125 /* One last check for pending IRQs to avoid extra latency due
126 * to sleeping unnecessarily. */
127 if (omap_irq_pending())
130 /* Block console output in case it is on one of the OMAP UARTs */
131 if (!is_suspending())
132 if (!console_trylock())
135 omap_uart_prepare_idle(0);
136 omap_uart_prepare_idle(1);
137 omap_uart_prepare_idle(2);
139 /* Jump to SRAM suspend code */
140 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
141 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
142 OMAP_SDRC_REGADDR(SDRC_POWER));
144 omap_uart_resume_idle(2);
145 omap_uart_resume_idle(1);
146 omap_uart_resume_idle(0);
148 if (!is_suspending())
152 omap2_gpio_resume_after_idle();
156 /* clear CORE wake-up events */
157 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
158 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
160 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
161 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
163 /* MPU domain wake events */
164 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
166 omap2_prm_write_mod_reg(0x01, OCP_MOD,
167 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
169 omap2_prm_write_mod_reg(0x20, OCP_MOD,
170 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
172 /* Mask future PRCM-to-MPU interrupts */
173 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
176 static int omap2_i2c_active(void)
180 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
181 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
184 static int sti_console_enabled;
186 static int omap2_allow_mpu_retention(void)
190 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
191 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
192 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
193 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
194 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
196 /* Check for UART3. */
197 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
198 if (l & OMAP24XX_EN_UART3_MASK)
200 if (sti_console_enabled)
206 static void omap2_enter_mpu_retention(void)
210 /* Putting MPU into the WFI state while a transfer is active
211 * seems to cause the I2C block to timeout. Why? Good question. */
212 if (omap2_i2c_active())
215 /* The peripherals seem not to be able to wake up the MPU when
216 * it is in retention mode. */
217 if (omap2_allow_mpu_retention()) {
218 /* REVISIT: These write to reserved bits? */
219 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
220 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
221 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
223 /* Try to enter MPU retention */
224 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
225 OMAP_LOGICRETSTATE_MASK,
226 MPU_MOD, OMAP2_PM_PWSTCTRL);
228 /* Block MPU retention */
230 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
238 static int omap2_can_sleep(void)
240 if (omap2_fclks_active())
242 if (!omap_uart_can_sleep())
244 if (osc_ck->usecount > 1)
246 if (omap_dma_running())
252 static void omap2_pm_idle(void)
257 if (!omap2_can_sleep()) {
258 if (omap_irq_pending())
260 omap2_enter_mpu_retention();
264 if (omap_irq_pending())
267 omap2_enter_full_retention();
274 #ifdef CONFIG_SUSPEND
275 static int omap2_pm_begin(suspend_state_t state)
278 suspend_state = state;
282 static int omap2_pm_suspend(void)
286 wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
287 wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
288 omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
291 mir1 = omap_readl(0x480fe0a4);
292 omap_writel(1 << 5, 0x480fe0ac);
294 omap_uart_prepare_suspend();
295 omap2_enter_full_retention();
297 omap_writel(mir1, 0x480fe0a4);
298 omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
303 static int omap2_pm_enter(suspend_state_t state)
308 case PM_SUSPEND_STANDBY:
310 ret = omap2_pm_suspend();
319 static void omap2_pm_end(void)
321 suspend_state = PM_SUSPEND_ON;
325 static const struct platform_suspend_ops omap_pm_ops = {
326 .begin = omap2_pm_begin,
327 .enter = omap2_pm_enter,
329 .valid = suspend_valid_only_mem,
332 static const struct platform_suspend_ops __initdata omap_pm_ops;
333 #endif /* CONFIG_SUSPEND */
335 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
336 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
338 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
339 clkdm_allow_idle(clkdm);
340 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
341 atomic_read(&clkdm->usecount) == 0)
346 static void __init prcm_setup_regs(void)
348 int i, num_mem_banks;
349 struct powerdomain *pwrdm;
353 * XXX This should be handled by hwmod code or PRCM init code
355 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
356 OMAP2_PRCM_SYSCONFIG_OFFSET);
359 * Set CORE powerdomain memory banks to retain their contents
362 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
363 for (i = 0; i < num_mem_banks; i++)
364 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
366 /* Set CORE powerdomain's next power state to RETENTION */
367 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
370 * Set MPU powerdomain's next power state to RETENTION;
371 * preserve logic state during retention
373 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
374 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
376 /* Force-power down DSP, GFX powerdomains */
378 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
379 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
380 clkdm_sleep(dsp_clkdm);
382 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
383 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
384 clkdm_sleep(gfx_clkdm);
386 /* Enable hardware-supervised idle for all clkdms */
387 clkdm_for_each(clkdms_setup, NULL);
388 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
390 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
392 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
393 OMAP2_PRCM_CLKSSETUP_OFFSET);
395 /* Configure automatic voltage transition */
396 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
397 OMAP2_PRCM_VOLTSETUP_OFFSET);
398 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
399 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
400 OMAP24XX_MEMRETCTRL_MASK |
401 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
402 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
403 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
405 /* Enable wake-up events */
406 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
410 static int __init omap2_pm_init(void)
414 if (!cpu_is_omap24xx())
417 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
418 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
419 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
421 /* Look up important powerdomains */
423 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
425 pr_err("PM: mpu_pwrdm not found\n");
427 core_pwrdm = pwrdm_lookup("core_pwrdm");
429 pr_err("PM: core_pwrdm not found\n");
431 /* Look up important clockdomains */
433 mpu_clkdm = clkdm_lookup("mpu_clkdm");
435 pr_err("PM: mpu_clkdm not found\n");
437 wkup_clkdm = clkdm_lookup("wkup_clkdm");
439 pr_err("PM: wkup_clkdm not found\n");
441 dsp_clkdm = clkdm_lookup("dsp_clkdm");
443 pr_err("PM: dsp_clkdm not found\n");
445 gfx_clkdm = clkdm_lookup("gfx_clkdm");
447 pr_err("PM: gfx_clkdm not found\n");
450 osc_ck = clk_get(NULL, "osc_ck");
451 if (IS_ERR(osc_ck)) {
452 printk(KERN_ERR "could not get osc_ck\n");
456 if (cpu_is_omap242x()) {
457 emul_ck = clk_get(NULL, "emul_ck");
458 if (IS_ERR(emul_ck)) {
459 printk(KERN_ERR "could not get emul_ck\n");
467 /* Hack to prevent MPU retention when STI console is enabled. */
469 const struct omap_sti_console_config *sti;
471 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
472 struct omap_sti_console_config);
473 if (sti != NULL && sti->enable)
474 sti_console_enabled = 1;
478 * We copy the assembler sleep/wakeup routines to SRAM.
479 * These routines need to be in SRAM as that's the only
480 * memory the MPU can see when it wakes up.
482 if (cpu_is_omap24xx()) {
483 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
484 omap24xx_idle_loop_suspend_sz);
486 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
487 omap24xx_cpu_suspend_sz);
490 suspend_set_ops(&omap_pm_ops);
491 pm_idle = omap2_pm_idle;
496 late_initcall(omap2_pm_init);