arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <plat/clock.h>
  39 #include <plat/sram.h>
  40 #include <plat/dma.h>
  41 #include <plat/board.h>
  42
  43 #include <mach/irqs.h>
  44
  45 #include "iomap.h"
  46 #include "common.h"
  47 #include "prm2xxx_3xxx.h"
  48 #include "prm-regbits-24xx.h"
  49 #include "cm2xxx_3xxx.h"
  50 #include "cm-regbits-24xx.h"
  51 #include "sdrc.h"
  52 #include "pm.h"
  53 #include "control.h"
  54 #include "powerdomain.h"
  55 #include "clockdomain.h"
  56
  57 #ifdef CONFIG_SUSPEND
  58 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  59 static inline bool is_suspending(void)
  60 {
  61         return (suspend_state != PM_SUSPEND_ON);
  62 }
  63 #else
  64 static inline bool is_suspending(void)
  65 {
  66         return false;
  67 }
  68 #endif
  69
  70 static void (*omap2_sram_idle)(void);
  71 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  72                                   void __iomem *sdrc_power);
  73
  74 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  75 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  76
  77 static struct clk *osc_ck, *emul_ck;
  78
  79 static int omap2_fclks_active(void)
  80 {
  81         u32 f1, f2;
  82
  83         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  84         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  85
  86         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
  87         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
  88         f2 &= ~OMAP24XX_EN_UART3_MASK;
  89
  90         if (f1 | f2)
  91                 return 1;
  92         return 0;
  93 }
  94
  95 static void omap2_enter_full_retention(void)
  96 {
  97         u32 l;
  98
  99         /* There is 1 reference hold for all children of the oscillator
 100          * clock, the following will remove it. If no one else uses the
 101          * oscillator itself it will be disabled if/when we enter retention
 102          * mode.
 103          */
 104         clk_disable(osc_ck);
 105
 106         /* Clear old wake-up events */
 107         /* REVISIT: These write to reserved bits? */
 108         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 109         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 110         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 111
 112         /*
 113          * Set MPU powerdomain's next power state to RETENTION;
 114          * preserve logic state during retention
 115          */
 116         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 117         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 118
 119         /* Workaround to kill USB */
 120         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 121         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 122
 123         omap2_gpio_prepare_for_idle(0);
 124
 125         /* One last check for pending IRQs to avoid extra latency due
 126          * to sleeping unnecessarily. */
 127         if (omap_irq_pending())
 128                 goto no_sleep;
 129
 130         /* Jump to SRAM suspend code */
 131         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 132                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 133                            OMAP_SDRC_REGADDR(SDRC_POWER));
 134
 135 no_sleep:
 136         omap2_gpio_resume_after_idle();
 137
 138         clk_enable(osc_ck);
 139
 140         /* clear CORE wake-up events */
 141         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 142         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 143
 144         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 145         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 146
 147         /* MPU domain wake events */
 148         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 149         if (l & 0x01)
 150                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 151                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 152         if (l & 0x20)
 153                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 154                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 155
 156         /* Mask future PRCM-to-MPU interrupts */
 157         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 158 }
 159
 160 static int omap2_i2c_active(void)
 161 {
 162         u32 l;
 163
 164         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 165         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 166 }
 167
 168 static int sti_console_enabled;
 169
 170 static int omap2_allow_mpu_retention(void)
 171 {
 172         u32 l;
 173
 174         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 175         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 176         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 177                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 178                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 179                 return 0;
 180         /* Check for UART3. */
 181         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 182         if (l & OMAP24XX_EN_UART3_MASK)
 183                 return 0;
 184         if (sti_console_enabled)
 185                 return 0;
 186
 187         return 1;
 188 }
 189
 190 static void omap2_enter_mpu_retention(void)
 191 {
 192         int only_idle = 0;
 193
 194         /* Putting MPU into the WFI state while a transfer is active
 195          * seems to cause the I2C block to timeout. Why? Good question. */
 196         if (omap2_i2c_active())
 197                 return;
 198
 199         /* The peripherals seem not to be able to wake up the MPU when
 200          * it is in retention mode. */
 201         if (omap2_allow_mpu_retention()) {
 202                 /* REVISIT: These write to reserved bits? */
 203                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 204                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 205                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 206
 207                 /* Try to enter MPU retention */
 208                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 209                                   OMAP_LOGICRETSTATE_MASK,
 210                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 211         } else {
 212                 /* Block MPU retention */
 213
 214                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 215                                                  OMAP2_PM_PWSTCTRL);
 216                 only_idle = 1;
 217         }
 218
 219         omap2_sram_idle();
 220 }
 221
 222 static int omap2_can_sleep(void)
 223 {
 224         if (omap2_fclks_active())
 225                 return 0;
 226         if (osc_ck->usecount > 1)
 227                 return 0;
 228         if (omap_dma_running())
 229                 return 0;
 230
 231         return 1;
 232 }
 233
 234 static void omap2_pm_idle(void)
 235 {
 236         local_irq_disable();
 237         local_fiq_disable();
 238
 239         if (!omap2_can_sleep()) {
 240                 if (omap_irq_pending())
 241                         goto out;
 242                 omap2_enter_mpu_retention();
 243                 goto out;
 244         }
 245
 246         if (omap_irq_pending())
 247                 goto out;
 248
 249         omap2_enter_full_retention();
 250
 251 out:
 252         local_fiq_enable();
 253         local_irq_enable();
 254 }
 255
 256 #ifdef CONFIG_SUSPEND
 257 static int omap2_pm_begin(suspend_state_t state)
 258 {
 259         disable_hlt();
 260         suspend_state = state;
 261         return 0;
 262 }
 263
 264 static int omap2_pm_enter(suspend_state_t state)
 265 {
 266         int ret = 0;
 267
 268         switch (state) {
 269         case PM_SUSPEND_STANDBY:
 270         case PM_SUSPEND_MEM:
 271                 omap2_enter_full_retention();
 272                 break;
 273         default:
 274                 ret = -EINVAL;
 275         }
 276
 277         return ret;
 278 }
 279
 280 static void omap2_pm_end(void)
 281 {
 282         suspend_state = PM_SUSPEND_ON;
 283         enable_hlt();
 284 }
 285
 286 static const struct platform_suspend_ops omap_pm_ops = {
 287         .begin          = omap2_pm_begin,
 288         .enter          = omap2_pm_enter,
 289         .end            = omap2_pm_end,
 290         .valid          = suspend_valid_only_mem,
 291 };
 292 #else
 293 static const struct platform_suspend_ops __initdata omap_pm_ops;
 294 #endif /* CONFIG_SUSPEND */
 295
 296 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 297 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 298 {
 299         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 300                 clkdm_allow_idle(clkdm);
 301         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 302                  atomic_read(&clkdm->usecount) == 0)
 303                 clkdm_sleep(clkdm);
 304         return 0;
 305 }
 306
 307 static void __init prcm_setup_regs(void)
 308 {
 309         int i, num_mem_banks;
 310         struct powerdomain *pwrdm;
 311
 312         /*
 313          * Enable autoidle
 314          * XXX This should be handled by hwmod code or PRCM init code
 315          */
 316         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 317                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 318
 319         /*
 320          * Set CORE powerdomain memory banks to retain their contents
 321          * during RETENTION
 322          */
 323         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 324         for (i = 0; i < num_mem_banks; i++)
 325                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 326
 327         /* Set CORE powerdomain's next power state to RETENTION */
 328         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 329
 330         /*
 331          * Set MPU powerdomain's next power state to RETENTION;
 332          * preserve logic state during retention
 333          */
 334         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 335         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 336
 337         /* Force-power down DSP, GFX powerdomains */
 338
 339         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 340         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 341         clkdm_sleep(dsp_clkdm);
 342
 343         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 344         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 345         clkdm_sleep(gfx_clkdm);
 346
 347         /* Enable hardware-supervised idle for all clkdms */
 348         clkdm_for_each(clkdms_setup, NULL);
 349         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 350
 351         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 352          * stabilisation */
 353         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 354                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 355
 356         /* Configure automatic voltage transition */
 357         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 358                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 359         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 360                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 361                                 OMAP24XX_MEMRETCTRL_MASK |
 362                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 363                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 364                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 365
 366         /* Enable wake-up events */
 367         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 368                                 WKUP_MOD, PM_WKEN);
 369 }
 370
 371 static int __init omap2_pm_init(void)
 372 {
 373         u32 l;
 374
 375         if (!cpu_is_omap24xx())
 376                 return -ENODEV;
 377
 378         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 379         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 380         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 381
 382         /* Look up important powerdomains */
 383
 384         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 385         if (!mpu_pwrdm)
 386                 pr_err("PM: mpu_pwrdm not found\n");
 387
 388         core_pwrdm = pwrdm_lookup("core_pwrdm");
 389         if (!core_pwrdm)
 390                 pr_err("PM: core_pwrdm not found\n");
 391
 392         /* Look up important clockdomains */
 393
 394         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 395         if (!mpu_clkdm)
 396                 pr_err("PM: mpu_clkdm not found\n");
 397
 398         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 399         if (!wkup_clkdm)
 400                 pr_err("PM: wkup_clkdm not found\n");
 401
 402         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 403         if (!dsp_clkdm)
 404                 pr_err("PM: dsp_clkdm not found\n");
 405
 406         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 407         if (!gfx_clkdm)
 408                 pr_err("PM: gfx_clkdm not found\n");
 409
 410
 411         osc_ck = clk_get(NULL, "osc_ck");
 412         if (IS_ERR(osc_ck)) {
 413                 printk(KERN_ERR "could not get osc_ck\n");
 414                 return -ENODEV;
 415         }
 416
 417         if (cpu_is_omap242x()) {
 418                 emul_ck = clk_get(NULL, "emul_ck");
 419                 if (IS_ERR(emul_ck)) {
 420                         printk(KERN_ERR "could not get emul_ck\n");
 421                         clk_put(osc_ck);
 422                         return -ENODEV;
 423                 }
 424         }
 425
 426         prcm_setup_regs();
 427
 428         /* Hack to prevent MPU retention when STI console is enabled. */
 429         {
 430                 const struct omap_sti_console_config *sti;
 431
 432                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 433                                       struct omap_sti_console_config);
 434                 if (sti != NULL && sti->enable)
 435                         sti_console_enabled = 1;
 436         }
 437
 438         /*
 439          * We copy the assembler sleep/wakeup routines to SRAM.
 440          * These routines need to be in SRAM as that's the only
 441          * memory the MPU can see when it wakes up.
 442          */
 443         if (cpu_is_omap24xx()) {
 444                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 445                                                  omap24xx_idle_loop_suspend_sz);
 446
 447                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 448                                                     omap24xx_cpu_suspend_sz);
 449         }
 450
 451         suspend_set_ops(&omap_pm_ops);
 452         pm_idle = omap2_pm_idle;
 453
 454         return 0;
 455 }
 456
 457 late_initcall(omap2_pm_init);