arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28
  29 #include <plat/sram.h>
  30 #include <plat/clockdomain.h>
  31 #include <plat/powerdomain.h>
  32 #include <plat/control.h>
  33 #include <plat/serial.h>
  34 #include <plat/sdrc.h>
  35 #include <plat/prcm.h>
  36 #include <plat/gpmc.h>
  37 #include <plat/dma.h>
  38
  39 #include <asm/tlbflush.h>
  40
  41 #include "cm.h"
  42 #include "cm-regbits-34xx.h"
  43 #include "prm-regbits-34xx.h"
  44
  45 #include "prm.h"
  46 #include "pm.h"
  47
  48 /* Scratchpad offsets */
  49 #define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
  50 #define OMAP343X_TABLE_VALUE_OFFSET        0x30
  51 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
  52
  53 struct power_state {
  54         struct powerdomain *pwrdm;
  55         u32 next_state;
  56 #ifdef CONFIG_SUSPEND
  57         u32 saved_state;
  58 #endif
  59         struct list_head node;
  60 };
  61
  62 static LIST_HEAD(pwrst_list);
  63
  64 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  65
  66 static int (*_omap_save_secure_sram)(u32 *addr);
  67
  68 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  69 static struct powerdomain *core_pwrdm, *per_pwrdm;
  70
  71 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
  72
  73 static inline void omap3_per_save_context(void)
  74 {
  75         omap_gpio_save_context();
  76 }
  77
  78 static inline void omap3_per_restore_context(void)
  79 {
  80         omap_gpio_restore_context();
  81 }
  82
  83 static void omap3_core_save_context(void)
  84 {
  85         u32 control_padconf_off;
  86
  87         /* Save the padconf registers */
  88         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
  89         control_padconf_off |= START_PADCONF_SAVE;
  90         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
  91         /* wait for the save to complete */
  92         while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
  93                         & PADCONF_SAVE_DONE)
  94                 ;
  95         /* Save the Interrupt controller context */
  96         omap_intc_save_context();
  97         /* Save the GPMC context */
  98         omap3_gpmc_save_context();
  99         /* Save the system control module context, padconf already save above*/
 100         omap3_control_save_context();
 101         omap_dma_global_context_save();
 102 }
 103
 104 static void omap3_core_restore_context(void)
 105 {
 106         /* Restore the control module context, padconf restored by h/w */
 107         omap3_control_restore_context();
 108         /* Restore the GPMC context */
 109         omap3_gpmc_restore_context();
 110         /* Restore the interrupt controller context */
 111         omap_intc_restore_context();
 112         omap_dma_global_context_restore();
 113 }
 114
 115 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 116 {
 117         u32 ret;
 118
 119         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 120                 /* Disable dma irq before calling secure rom code API */
 121                 omap_dma_disable_irq(0);
 122                 omap_dma_disable_irq(1);
 123                 /*
 124                  * MPU next state must be set to POWER_ON temporarily,
 125                  * otherwise the WFI executed inside the ROM code
 126                  * will hang the system.
 127                  */
 128                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 129                 ret = _omap_save_secure_sram((u32 *)
 130                                 __pa(omap3_secure_ram_storage));
 131                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 132                 /* Following is for error tracking, it should not happen */
 133                 if (ret) {
 134                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 135                                 ret);
 136                         while (1)
 137                                 ;
 138                 }
 139         }
 140 }
 141
 142 /*
 143  * PRCM Interrupt Handler Helper Function
 144  *
 145  * The purpose of this function is to clear any wake-up events latched
 146  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 147  * may occur whilst attempting to clear a PM_WKST_x register and thus
 148  * set another bit in this register. A while loop is used to ensure
 149  * that any peripheral wake-up events occurring while attempting to
 150  * clear the PM_WKST_x are detected and cleared.
 151  */
 152 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 153 {
 154         u32 wkst, fclk, iclk, clken;
 155         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 156         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 157         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 158         u16 grpsel_off = (regs == 3) ?
 159                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 160         int c = 0;
 161
 162         wkst = prm_read_mod_reg(module, wkst_off);
 163         wkst &= prm_read_mod_reg(module, grpsel_off);
 164         if (wkst) {
 165                 iclk = cm_read_mod_reg(module, iclk_off);
 166                 fclk = cm_read_mod_reg(module, fclk_off);
 167                 while (wkst) {
 168                         clken = wkst;
 169                         cm_set_mod_reg_bits(clken, module, iclk_off);
 170                         /*
 171                          * For USBHOST, we don't know whether HOST1 or
 172                          * HOST2 woke us up, so enable both f-clocks
 173                          */
 174                         if (module == OMAP3430ES2_USBHOST_MOD)
 175                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 176                         cm_set_mod_reg_bits(clken, module, fclk_off);
 177                         prm_write_mod_reg(wkst, module, wkst_off);
 178                         wkst = prm_read_mod_reg(module, wkst_off);
 179                         c++;
 180                 }
 181                 cm_write_mod_reg(iclk, module, iclk_off);
 182                 cm_write_mod_reg(fclk, module, fclk_off);
 183         }
 184
 185         return c;
 186 }
 187
 188 static int _prcm_int_handle_wakeup(void)
 189 {
 190         int c;
 191
 192         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 193         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 194         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 195         if (omap_rev() > OMAP3430_REV_ES1_0) {
 196                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 197                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 198         }
 199
 200         return c;
 201 }
 202
 203 /*
 204  * PRCM Interrupt Handler
 205  *
 206  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 207  * interrupts from the PRCM for the MPU. These bits must be cleared in
 208  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 209  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 210  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 211  * register indicates that a wake-up event is pending for the MPU and
 212  * this bit can only be cleared if the all the wake-up events latched
 213  * in the various PM_WKST_x registers have been cleared. The interrupt
 214  * handler is implemented using a do-while loop so that if a wake-up
 215  * event occurred during the processing of the prcm interrupt handler
 216  * (setting a bit in the corresponding PM_WKST_x register and thus
 217  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 218  * this would be handled.
 219  */
 220 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 221 {
 222         u32 irqstatus_mpu;
 223         int c = 0;
 224
 225         do {
 226                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 227                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 228
 229                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 230                         c = _prcm_int_handle_wakeup();
 231
 232                         /*
 233                          * Is the MPU PRCM interrupt handler racing with the
 234                          * IVA2 PRCM interrupt handler ?
 235                          */
 236                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 237                              "but no wakeup sources are marked\n");
 238                 } else {
 239                         /* XXX we need to expand our PRCM interrupt handler */
 240                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 241                              "no code to handle it (%08x)\n", irqstatus_mpu);
 242                 }
 243
 244                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 245                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 246
 247         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 248
 249         return IRQ_HANDLED;
 250 }
 251
 252 static void restore_control_register(u32 val)
 253 {
 254         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 255 }
 256
 257 /* Function to restore the table entry that was modified for enabling MMU */
 258 static void restore_table_entry(void)
 259 {
 260         u32 *scratchpad_address;
 261         u32 previous_value, control_reg_value;
 262         u32 *address;
 263
 264         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 265
 266         /* Get address of entry that was modified */
 267         address = (u32 *)__raw_readl(scratchpad_address +
 268                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 269         /* Get the previous value which needs to be restored */
 270         previous_value = __raw_readl(scratchpad_address +
 271                                      OMAP343X_TABLE_VALUE_OFFSET);
 272         address = __va(address);
 273         *address = previous_value;
 274         flush_tlb_all();
 275         control_reg_value = __raw_readl(scratchpad_address
 276                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 277         /* This will enable caches and prediction */
 278         restore_control_register(control_reg_value);
 279 }
 280
 281 static void omap_sram_idle(void)
 282 {
 283         /* Variable to tell what needs to be saved and restored
 284          * in omap_sram_idle*/
 285         /* save_state = 0 => Nothing to save and restored */
 286         /* save_state = 1 => Only L1 and logic lost */
 287         /* save_state = 2 => Only L2 lost */
 288         /* save_state = 3 => L1, L2 and logic lost */
 289         int save_state = 0;
 290         int mpu_next_state = PWRDM_POWER_ON;
 291         int per_next_state = PWRDM_POWER_ON;
 292         int core_next_state = PWRDM_POWER_ON;
 293         int core_prev_state, per_prev_state;
 294
 295         if (!_omap_sram_idle)
 296                 return;
 297
 298         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 299         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 300         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 301         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 302
 303         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 304         switch (mpu_next_state) {
 305         case PWRDM_POWER_ON:
 306         case PWRDM_POWER_RET:
 307                 /* No need to save context */
 308                 save_state = 0;
 309                 break;
 310         case PWRDM_POWER_OFF:
 311                 save_state = 3;
 312                 break;
 313         default:
 314                 /* Invalid state */
 315                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 316                 return;
 317         }
 318         pwrdm_pre_transition();
 319
 320         /* NEON control */
 321         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 322                 set_pwrdm_state(neon_pwrdm, mpu_next_state);
 323
 324         /* CORE & PER */
 325         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 326         if (core_next_state < PWRDM_POWER_ON) {
 327                 omap2_gpio_prepare_for_retention();
 328                 omap_uart_prepare_idle(0);
 329                 omap_uart_prepare_idle(1);
 330                 /* PER changes only with core */
 331                 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 332                 if (per_next_state < PWRDM_POWER_ON) {
 333                         omap_uart_prepare_idle(2);
 334                         if (per_next_state == PWRDM_POWER_OFF)
 335                                 omap3_per_save_context();
 336                 }
 337                 if (core_next_state == PWRDM_POWER_OFF) {
 338                         omap3_core_save_context();
 339                         omap3_prcm_save_context();
 340                         omap3_save_secure_ram_context(mpu_next_state);
 341                 }
 342                 /* Enable IO-PAD wakeup */
 343                 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 344         }
 345
 346         /*
 347          * omap3_arm_context is the location where ARM registers
 348          * get saved. The restore path then reads from this
 349          * location and restores them back.
 350          */
 351         _omap_sram_idle(omap3_arm_context, save_state);
 352         cpu_init();
 353
 354         /* Restore table entry modified during MMU restoration */
 355         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 356                 restore_table_entry();
 357
 358         if (core_next_state < PWRDM_POWER_ON) {
 359                 if (per_next_state < PWRDM_POWER_ON)
 360                         omap_uart_resume_idle(2);
 361                 omap_uart_resume_idle(1);
 362                 omap_uart_resume_idle(0);
 363
 364                 /* Disable IO-PAD wakeup */
 365                 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 366                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 367                 if (core_prev_state == PWRDM_POWER_OFF) {
 368                         omap3_core_restore_context();
 369                         omap3_prcm_restore_context();
 370                         omap3_sram_restore_context();
 371                 }
 372                 if (per_next_state < PWRDM_POWER_ON) {
 373                         per_prev_state =
 374                                 pwrdm_read_prev_pwrst(per_pwrdm);
 375                         if (per_prev_state == PWRDM_POWER_OFF)
 376                                 omap3_per_restore_context();
 377                 }
 378                 omap2_gpio_resume_after_retention();
 379         }
 380
 381         pwrdm_post_transition();
 382
 383 }
 384
 385 /*
 386  * Check if functional clocks are enabled before entering
 387  * sleep. This function could be behind CONFIG_PM_DEBUG
 388  * when all drivers are configuring their sysconfig registers
 389  * properly and using their clocks properly.
 390  */
 391 static int omap3_fclks_active(void)
 392 {
 393         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 394                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 395
 396         fck_core1 = cm_read_mod_reg(CORE_MOD,
 397                                     CM_FCLKEN1);
 398         if (omap_rev() > OMAP3430_REV_ES1_0) {
 399                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 400                                             OMAP3430ES2_CM_FCLKEN3);
 401                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 402                                           CM_FCLKEN);
 403                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 404                                               CM_FCLKEN);
 405         } else
 406                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 407                                           OMAP3430ES2_CM_FCLKEN3);
 408         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 409                                   CM_FCLKEN);
 410         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 411                                   CM_FCLKEN);
 412         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 413                                   CM_FCLKEN);
 414
 415         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 416         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 417         fck_per &= ~OMAP3430_EN_UART3;
 418
 419         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 420             fck_cam | fck_per | fck_usbhost)
 421                 return 1;
 422         return 0;
 423 }
 424
 425 static int omap3_can_sleep(void)
 426 {
 427         if (!omap_uart_can_sleep())
 428                 return 0;
 429         if (omap3_fclks_active())
 430                 return 0;
 431         return 1;
 432 }
 433
 434 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 435  * RET are supported. Function is assuming that clkdm doesn't have
 436  * hw_sup mode enabled. */
 437 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 438 {
 439         u32 cur_state;
 440         int sleep_switch = 0;
 441         int ret = 0;
 442
 443         if (pwrdm == NULL || IS_ERR(pwrdm))
 444                 return -EINVAL;
 445
 446         while (!(pwrdm->pwrsts & (1 << state))) {
 447                 if (state == PWRDM_POWER_OFF)
 448                         return ret;
 449                 state--;
 450         }
 451
 452         cur_state = pwrdm_read_next_pwrst(pwrdm);
 453         if (cur_state == state)
 454                 return ret;
 455
 456         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 457                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 458                 sleep_switch = 1;
 459                 pwrdm_wait_transition(pwrdm);
 460         }
 461
 462         ret = pwrdm_set_next_pwrst(pwrdm, state);
 463         if (ret) {
 464                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 465                        pwrdm->name);
 466                 goto err;
 467         }
 468
 469         if (sleep_switch) {
 470                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 471                 pwrdm_wait_transition(pwrdm);
 472                 pwrdm_state_switch(pwrdm);
 473         }
 474
 475 err:
 476         return ret;
 477 }
 478
 479 static void omap3_pm_idle(void)
 480 {
 481         local_irq_disable();
 482         local_fiq_disable();
 483
 484         if (!omap3_can_sleep())
 485                 goto out;
 486
 487         if (omap_irq_pending())
 488                 goto out;
 489
 490         omap_sram_idle();
 491
 492 out:
 493         local_fiq_enable();
 494         local_irq_enable();
 495 }
 496
 497 #ifdef CONFIG_SUSPEND
 498 static suspend_state_t suspend_state;
 499
 500 static int omap3_pm_prepare(void)
 501 {
 502         disable_hlt();
 503         return 0;
 504 }
 505
 506 static int omap3_pm_suspend(void)
 507 {
 508         struct power_state *pwrst;
 509         int state, ret = 0;
 510
 511         /* Read current next_pwrsts */
 512         list_for_each_entry(pwrst, &pwrst_list, node)
 513                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 514         /* Set ones wanted by suspend */
 515         list_for_each_entry(pwrst, &pwrst_list, node) {
 516                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 517                         goto restore;
 518                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 519                         goto restore;
 520         }
 521
 522         omap_uart_prepare_suspend();
 523         omap_sram_idle();
 524
 525 restore:
 526         /* Restore next_pwrsts */
 527         list_for_each_entry(pwrst, &pwrst_list, node) {
 528                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 529                 if (state > pwrst->next_state) {
 530                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 531                                "target state %d\n",
 532                                pwrst->pwrdm->name, pwrst->next_state);
 533                         ret = -1;
 534                 }
 535                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 536         }
 537         if (ret)
 538                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 539         else
 540                 printk(KERN_INFO "Successfully put all powerdomains "
 541                        "to target state\n");
 542
 543         return ret;
 544 }
 545
 546 static int omap3_pm_enter(suspend_state_t unused)
 547 {
 548         int ret = 0;
 549
 550         switch (suspend_state) {
 551         case PM_SUSPEND_STANDBY:
 552         case PM_SUSPEND_MEM:
 553                 ret = omap3_pm_suspend();
 554                 break;
 555         default:
 556                 ret = -EINVAL;
 557         }
 558
 559         return ret;
 560 }
 561
 562 static void omap3_pm_finish(void)
 563 {
 564         enable_hlt();
 565 }
 566
 567 /* Hooks to enable / disable UART interrupts during suspend */
 568 static int omap3_pm_begin(suspend_state_t state)
 569 {
 570         suspend_state = state;
 571         omap_uart_enable_irqs(0);
 572         return 0;
 573 }
 574
 575 static void omap3_pm_end(void)
 576 {
 577         suspend_state = PM_SUSPEND_ON;
 578         omap_uart_enable_irqs(1);
 579         return;
 580 }
 581
 582 static struct platform_suspend_ops omap_pm_ops = {
 583         .begin          = omap3_pm_begin,
 584         .end            = omap3_pm_end,
 585         .prepare        = omap3_pm_prepare,
 586         .enter          = omap3_pm_enter,
 587         .finish         = omap3_pm_finish,
 588         .valid          = suspend_valid_only_mem,
 589 };
 590 #endif /* CONFIG_SUSPEND */
 591
 592
 593 /**
 594  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 595  *                   retention
 596  *
 597  * In cases where IVA2 is activated by bootcode, it may prevent
 598  * full-chip retention or off-mode because it is not idle.  This
 599  * function forces the IVA2 into idle state so it can go
 600  * into retention/off and thus allow full-chip retention/off.
 601  *
 602  **/
 603 static void __init omap3_iva_idle(void)
 604 {
 605         /* ensure IVA2 clock is disabled */
 606         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 607
 608         /* if no clock activity, nothing else to do */
 609         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 610               OMAP3430_CLKACTIVITY_IVA2_MASK))
 611                 return;
 612
 613         /* Reset IVA2 */
 614         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 615                           OMAP3430_RST2_IVA2 |
 616                           OMAP3430_RST3_IVA2,
 617                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 618
 619         /* Enable IVA2 clock */
 620         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 621                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 622
 623         /* Set IVA2 boot mode to 'idle' */
 624         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 625                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 626
 627         /* Un-reset IVA2 */
 628         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 629
 630         /* Disable IVA2 clock */
 631         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 632
 633         /* Reset IVA2 */
 634         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 635                           OMAP3430_RST2_IVA2 |
 636                           OMAP3430_RST3_IVA2,
 637                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 638 }
 639
 640 static void __init omap3_d2d_idle(void)
 641 {
 642         u16 mask, padconf;
 643
 644         /* In a stand alone OMAP3430 where there is not a stacked
 645          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 646          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 647          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 648         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 649         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 650         padconf |= mask;
 651         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 652
 653         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 654         padconf |= mask;
 655         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 656
 657         /* reset modem */
 658         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 659                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 660                           CORE_MOD, RM_RSTCTRL);
 661         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 662 }
 663
 664 static void __init prcm_setup_regs(void)
 665 {
 666         /* XXX Reset all wkdeps. This should be done when initializing
 667          * powerdomains */
 668         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 669         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 670         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 671         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 672         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 673         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 674         if (omap_rev() > OMAP3430_REV_ES1_0) {
 675                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 676                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 677         } else
 678                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 679
 680         /*
 681          * Enable interface clock autoidle for all modules.
 682          * Note that in the long run this should be done by clockfw
 683          */
 684         cm_write_mod_reg(
 685                 OMAP3430_AUTO_MODEM |
 686                 OMAP3430ES2_AUTO_MMC3 |
 687                 OMAP3430ES2_AUTO_ICR |
 688                 OMAP3430_AUTO_AES2 |
 689                 OMAP3430_AUTO_SHA12 |
 690                 OMAP3430_AUTO_DES2 |
 691                 OMAP3430_AUTO_MMC2 |
 692                 OMAP3430_AUTO_MMC1 |
 693                 OMAP3430_AUTO_MSPRO |
 694                 OMAP3430_AUTO_HDQ |
 695                 OMAP3430_AUTO_MCSPI4 |
 696                 OMAP3430_AUTO_MCSPI3 |
 697                 OMAP3430_AUTO_MCSPI2 |
 698                 OMAP3430_AUTO_MCSPI1 |
 699                 OMAP3430_AUTO_I2C3 |
 700                 OMAP3430_AUTO_I2C2 |
 701                 OMAP3430_AUTO_I2C1 |
 702                 OMAP3430_AUTO_UART2 |
 703                 OMAP3430_AUTO_UART1 |
 704                 OMAP3430_AUTO_GPT11 |
 705                 OMAP3430_AUTO_GPT10 |
 706                 OMAP3430_AUTO_MCBSP5 |
 707                 OMAP3430_AUTO_MCBSP1 |
 708                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 709                 OMAP3430_AUTO_MAILBOXES |
 710                 OMAP3430_AUTO_OMAPCTRL |
 711                 OMAP3430ES1_AUTO_FSHOSTUSB |
 712                 OMAP3430_AUTO_HSOTGUSB |
 713                 OMAP3430_AUTO_SAD2D |
 714                 OMAP3430_AUTO_SSI,
 715                 CORE_MOD, CM_AUTOIDLE1);
 716
 717         cm_write_mod_reg(
 718                 OMAP3430_AUTO_PKA |
 719                 OMAP3430_AUTO_AES1 |
 720                 OMAP3430_AUTO_RNG |
 721                 OMAP3430_AUTO_SHA11 |
 722                 OMAP3430_AUTO_DES1,
 723                 CORE_MOD, CM_AUTOIDLE2);
 724
 725         if (omap_rev() > OMAP3430_REV_ES1_0) {
 726                 cm_write_mod_reg(
 727                         OMAP3430_AUTO_MAD2D |
 728                         OMAP3430ES2_AUTO_USBTLL,
 729                         CORE_MOD, CM_AUTOIDLE3);
 730         }
 731
 732         cm_write_mod_reg(
 733                 OMAP3430_AUTO_WDT2 |
 734                 OMAP3430_AUTO_WDT1 |
 735                 OMAP3430_AUTO_GPIO1 |
 736                 OMAP3430_AUTO_32KSYNC |
 737                 OMAP3430_AUTO_GPT12 |
 738                 OMAP3430_AUTO_GPT1 ,
 739                 WKUP_MOD, CM_AUTOIDLE);
 740
 741         cm_write_mod_reg(
 742                 OMAP3430_AUTO_DSS,
 743                 OMAP3430_DSS_MOD,
 744                 CM_AUTOIDLE);
 745
 746         cm_write_mod_reg(
 747                 OMAP3430_AUTO_CAM,
 748                 OMAP3430_CAM_MOD,
 749                 CM_AUTOIDLE);
 750
 751         cm_write_mod_reg(
 752                 OMAP3430_AUTO_GPIO6 |
 753                 OMAP3430_AUTO_GPIO5 |
 754                 OMAP3430_AUTO_GPIO4 |
 755                 OMAP3430_AUTO_GPIO3 |
 756                 OMAP3430_AUTO_GPIO2 |
 757                 OMAP3430_AUTO_WDT3 |
 758                 OMAP3430_AUTO_UART3 |
 759                 OMAP3430_AUTO_GPT9 |
 760                 OMAP3430_AUTO_GPT8 |
 761                 OMAP3430_AUTO_GPT7 |
 762                 OMAP3430_AUTO_GPT6 |
 763                 OMAP3430_AUTO_GPT5 |
 764                 OMAP3430_AUTO_GPT4 |
 765                 OMAP3430_AUTO_GPT3 |
 766                 OMAP3430_AUTO_GPT2 |
 767                 OMAP3430_AUTO_MCBSP4 |
 768                 OMAP3430_AUTO_MCBSP3 |
 769                 OMAP3430_AUTO_MCBSP2,
 770                 OMAP3430_PER_MOD,
 771                 CM_AUTOIDLE);
 772
 773         if (omap_rev() > OMAP3430_REV_ES1_0) {
 774                 cm_write_mod_reg(
 775                         OMAP3430ES2_AUTO_USBHOST,
 776                         OMAP3430ES2_USBHOST_MOD,
 777                         CM_AUTOIDLE);
 778         }
 779
 780         /*
 781          * Set all plls to autoidle. This is needed until autoidle is
 782          * enabled by clockfw
 783          */
 784         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 785                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 786         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 787                          MPU_MOD,
 788                          CM_AUTOIDLE2);
 789         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 790                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 791                          PLL_MOD,
 792                          CM_AUTOIDLE);
 793         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 794                          PLL_MOD,
 795                          CM_AUTOIDLE2);
 796
 797         /*
 798          * Enable control of expternal oscillator through
 799          * sys_clkreq. In the long run clock framework should
 800          * take care of this.
 801          */
 802         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 803                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 804                              OMAP3430_GR_MOD,
 805                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 806
 807         /* setup wakup source */
 808         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 809                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 810                           WKUP_MOD, PM_WKEN);
 811         /* No need to write EN_IO, that is always enabled */
 812         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 813                           OMAP3430_EN_GPT12,
 814                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 815         /* For some reason IO doesn't generate wakeup event even if
 816          * it is selected to mpu wakeup goup */
 817         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 818                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 819
 820         /* Enable wakeups in PER */
 821         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 822                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 823                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
 824                           OMAP3430_PER_MOD, PM_WKEN);
 825         /* and allow them to wake up MPU */
 826         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 827                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 828                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
 829                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 830
 831         /* Don't attach IVA interrupts */
 832         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 833         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 834         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 835         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 836
 837         /* Clear any pending 'reset' flags */
 838         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 839         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 840         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 841         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 842         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 843         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 844         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 845
 846         /* Clear any pending PRCM interrupts */
 847         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 848
 849         /* Don't attach IVA interrupts */
 850         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 851         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 852         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 853         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 854
 855         /* Clear any pending 'reset' flags */
 856         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 857         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 858         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 859         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 860         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 861         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 862         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 863
 864         /* Clear any pending PRCM interrupts */
 865         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 866
 867         omap3_iva_idle();
 868         omap3_d2d_idle();
 869 }
 870
 871 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 872 {
 873         struct power_state *pwrst;
 874
 875         list_for_each_entry(pwrst, &pwrst_list, node) {
 876                 if (pwrst->pwrdm == pwrdm)
 877                         return pwrst->next_state;
 878         }
 879         return -EINVAL;
 880 }
 881
 882 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 883 {
 884         struct power_state *pwrst;
 885
 886         list_for_each_entry(pwrst, &pwrst_list, node) {
 887                 if (pwrst->pwrdm == pwrdm) {
 888                         pwrst->next_state = state;
 889                         return 0;
 890                 }
 891         }
 892         return -EINVAL;
 893 }
 894
 895 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 896 {
 897         struct power_state *pwrst;
 898
 899         if (!pwrdm->pwrsts)
 900                 return 0;
 901
 902         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 903         if (!pwrst)
 904                 return -ENOMEM;
 905         pwrst->pwrdm = pwrdm;
 906         pwrst->next_state = PWRDM_POWER_RET;
 907         list_add(&pwrst->node, &pwrst_list);
 908
 909         if (pwrdm_has_hdwr_sar(pwrdm))
 910                 pwrdm_enable_hdwr_sar(pwrdm);
 911
 912         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 913 }
 914
 915 /*
 916  * Enable hw supervised mode for all clockdomains if it's
 917  * supported. Initiate sleep transition for other clockdomains, if
 918  * they are not used
 919  */
 920 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 921 {
 922         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 923                 omap2_clkdm_allow_idle(clkdm);
 924         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 925                  atomic_read(&clkdm->usecount) == 0)
 926                 omap2_clkdm_sleep(clkdm);
 927         return 0;
 928 }
 929
 930 void omap_push_sram_idle(void)
 931 {
 932         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 933                                         omap34xx_cpu_suspend_sz);
 934         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 935                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 936                                 save_secure_ram_context_sz);
 937 }
 938
 939 static int __init omap3_pm_init(void)
 940 {
 941         struct power_state *pwrst, *tmp;
 942         int ret;
 943
 944         if (!cpu_is_omap34xx())
 945                 return -ENODEV;
 946
 947         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 948
 949         /* XXX prcm_setup_regs needs to be before enabling hw
 950          * supervised mode for powerdomains */
 951         prcm_setup_regs();
 952
 953         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 954                           (irq_handler_t)prcm_interrupt_handler,
 955                           IRQF_DISABLED, "prcm", NULL);
 956         if (ret) {
 957                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 958                        INT_34XX_PRCM_MPU_IRQ);
 959                 goto err1;
 960         }
 961
 962         ret = pwrdm_for_each(pwrdms_setup, NULL);
 963         if (ret) {
 964                 printk(KERN_ERR "Failed to setup powerdomains\n");
 965                 goto err2;
 966         }
 967
 968         (void) clkdm_for_each(clkdms_setup, NULL);
 969
 970         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 971         if (mpu_pwrdm == NULL) {
 972                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 973                 goto err2;
 974         }
 975
 976         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 977         per_pwrdm = pwrdm_lookup("per_pwrdm");
 978         core_pwrdm = pwrdm_lookup("core_pwrdm");
 979
 980         omap_push_sram_idle();
 981 #ifdef CONFIG_SUSPEND
 982         suspend_set_ops(&omap_pm_ops);
 983 #endif /* CONFIG_SUSPEND */
 984
 985         pm_idle = omap3_pm_idle;
 986
 987         pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
 988         /*
 989          * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
 990          * IO-pad wakeup.  Otherwise it will unnecessarily waste power
 991          * waking up PER with every CORE wakeup - see
 992          * http://marc.info/?l=linux-omap&m=121852150710062&w=2
 993         */
 994         pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
 995
 996         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 997                 omap3_secure_ram_storage =
 998                         kmalloc(0x803F, GFP_KERNEL);
 999                 if (!omap3_secure_ram_storage)
1000                         printk(KERN_ERR "Memory allocation failed when"
1001                                         "allocating for secure sram context\n");
1002         }
1003         omap3_save_scratchpad_contents();
1004
1005 err1:
1006         return ret;
1007 err2:
1008         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1009         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1010                 list_del(&pwrst->node);
1011                 kfree(pwrst);
1012         }
1013         return ret;
1014 }
1015
1016 late_initcall(omap3_pm_init);