2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
29 #include <plat/sram.h>
30 #include <plat/clockdomain.h>
31 #include <plat/powerdomain.h>
32 #include <plat/control.h>
33 #include <plat/serial.h>
34 #include <plat/sdrc.h>
35 #include <plat/prcm.h>
36 #include <plat/gpmc.h>
39 #include <asm/tlbflush.h>
42 #include "cm-regbits-34xx.h"
43 #include "prm-regbits-34xx.h"
48 /* Scratchpad offsets */
49 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
50 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
51 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
54 struct powerdomain *pwrdm;
59 struct list_head node;
62 static LIST_HEAD(pwrst_list);
64 static void (*_omap_sram_idle)(u32 *addr, int save_state);
66 static int (*_omap_save_secure_sram)(u32 *addr);
68 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
69 static struct powerdomain *core_pwrdm, *per_pwrdm;
71 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
73 static inline void omap3_per_save_context(void)
75 omap_gpio_save_context();
78 static inline void omap3_per_restore_context(void)
80 omap_gpio_restore_context();
83 static void omap3_core_save_context(void)
85 u32 control_padconf_off;
87 /* Save the padconf registers */
88 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
89 control_padconf_off |= START_PADCONF_SAVE;
90 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
91 /* wait for the save to complete */
92 while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
95 /* Save the Interrupt controller context */
96 omap_intc_save_context();
97 /* Save the GPMC context */
98 omap3_gpmc_save_context();
99 /* Save the system control module context, padconf already save above*/
100 omap3_control_save_context();
101 omap_dma_global_context_save();
104 static void omap3_core_restore_context(void)
106 /* Restore the control module context, padconf restored by h/w */
107 omap3_control_restore_context();
108 /* Restore the GPMC context */
109 omap3_gpmc_restore_context();
110 /* Restore the interrupt controller context */
111 omap_intc_restore_context();
112 omap_dma_global_context_restore();
115 static void omap3_save_secure_ram_context(u32 target_mpu_state)
119 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
120 /* Disable dma irq before calling secure rom code API */
121 omap_dma_disable_irq(0);
122 omap_dma_disable_irq(1);
124 * MPU next state must be set to POWER_ON temporarily,
125 * otherwise the WFI executed inside the ROM code
126 * will hang the system.
128 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
129 ret = _omap_save_secure_sram((u32 *)
130 __pa(omap3_secure_ram_storage));
131 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
132 /* Following is for error tracking, it should not happen */
134 printk(KERN_ERR "save_secure_sram() returns %08x\n",
143 * PRCM Interrupt Handler Helper Function
145 * The purpose of this function is to clear any wake-up events latched
146 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
147 * may occur whilst attempting to clear a PM_WKST_x register and thus
148 * set another bit in this register. A while loop is used to ensure
149 * that any peripheral wake-up events occurring while attempting to
150 * clear the PM_WKST_x are detected and cleared.
152 static int prcm_clear_mod_irqs(s16 module, u8 regs)
154 u32 wkst, fclk, iclk, clken;
155 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
156 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
157 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
158 u16 grpsel_off = (regs == 3) ?
159 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
162 wkst = prm_read_mod_reg(module, wkst_off);
163 wkst &= prm_read_mod_reg(module, grpsel_off);
165 iclk = cm_read_mod_reg(module, iclk_off);
166 fclk = cm_read_mod_reg(module, fclk_off);
169 cm_set_mod_reg_bits(clken, module, iclk_off);
171 * For USBHOST, we don't know whether HOST1 or
172 * HOST2 woke us up, so enable both f-clocks
174 if (module == OMAP3430ES2_USBHOST_MOD)
175 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
176 cm_set_mod_reg_bits(clken, module, fclk_off);
177 prm_write_mod_reg(wkst, module, wkst_off);
178 wkst = prm_read_mod_reg(module, wkst_off);
181 cm_write_mod_reg(iclk, module, iclk_off);
182 cm_write_mod_reg(fclk, module, fclk_off);
188 static int _prcm_int_handle_wakeup(void)
192 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
193 c += prcm_clear_mod_irqs(CORE_MOD, 1);
194 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
195 if (omap_rev() > OMAP3430_REV_ES1_0) {
196 c += prcm_clear_mod_irqs(CORE_MOD, 3);
197 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
204 * PRCM Interrupt Handler
206 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
207 * interrupts from the PRCM for the MPU. These bits must be cleared in
208 * order to clear the PRCM interrupt. The PRCM interrupt handler is
209 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
210 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
211 * register indicates that a wake-up event is pending for the MPU and
212 * this bit can only be cleared if the all the wake-up events latched
213 * in the various PM_WKST_x registers have been cleared. The interrupt
214 * handler is implemented using a do-while loop so that if a wake-up
215 * event occurred during the processing of the prcm interrupt handler
216 * (setting a bit in the corresponding PM_WKST_x register and thus
217 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
218 * this would be handled.
220 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
226 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
227 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
229 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
230 c = _prcm_int_handle_wakeup();
233 * Is the MPU PRCM interrupt handler racing with the
234 * IVA2 PRCM interrupt handler ?
236 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
237 "but no wakeup sources are marked\n");
239 /* XXX we need to expand our PRCM interrupt handler */
240 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
241 "no code to handle it (%08x)\n", irqstatus_mpu);
244 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
245 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
247 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
252 static void restore_control_register(u32 val)
254 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
257 /* Function to restore the table entry that was modified for enabling MMU */
258 static void restore_table_entry(void)
260 u32 *scratchpad_address;
261 u32 previous_value, control_reg_value;
264 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
266 /* Get address of entry that was modified */
267 address = (u32 *)__raw_readl(scratchpad_address +
268 OMAP343X_TABLE_ADDRESS_OFFSET);
269 /* Get the previous value which needs to be restored */
270 previous_value = __raw_readl(scratchpad_address +
271 OMAP343X_TABLE_VALUE_OFFSET);
272 address = __va(address);
273 *address = previous_value;
275 control_reg_value = __raw_readl(scratchpad_address
276 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
277 /* This will enable caches and prediction */
278 restore_control_register(control_reg_value);
281 static void omap_sram_idle(void)
283 /* Variable to tell what needs to be saved and restored
284 * in omap_sram_idle*/
285 /* save_state = 0 => Nothing to save and restored */
286 /* save_state = 1 => Only L1 and logic lost */
287 /* save_state = 2 => Only L2 lost */
288 /* save_state = 3 => L1, L2 and logic lost */
290 int mpu_next_state = PWRDM_POWER_ON;
291 int per_next_state = PWRDM_POWER_ON;
292 int core_next_state = PWRDM_POWER_ON;
293 int core_prev_state, per_prev_state;
295 if (!_omap_sram_idle)
298 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
299 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
300 pwrdm_clear_all_prev_pwrst(core_pwrdm);
301 pwrdm_clear_all_prev_pwrst(per_pwrdm);
303 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
304 switch (mpu_next_state) {
306 case PWRDM_POWER_RET:
307 /* No need to save context */
310 case PWRDM_POWER_OFF:
315 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
318 pwrdm_pre_transition();
321 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
322 set_pwrdm_state(neon_pwrdm, mpu_next_state);
325 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
326 if (core_next_state < PWRDM_POWER_ON) {
327 omap2_gpio_prepare_for_retention();
328 omap_uart_prepare_idle(0);
329 omap_uart_prepare_idle(1);
330 /* PER changes only with core */
331 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
332 if (per_next_state < PWRDM_POWER_ON) {
333 omap_uart_prepare_idle(2);
334 if (per_next_state == PWRDM_POWER_OFF)
335 omap3_per_save_context();
337 if (core_next_state == PWRDM_POWER_OFF) {
338 omap3_core_save_context();
339 omap3_prcm_save_context();
340 omap3_save_secure_ram_context(mpu_next_state);
342 /* Enable IO-PAD wakeup */
343 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
347 * omap3_arm_context is the location where ARM registers
348 * get saved. The restore path then reads from this
349 * location and restores them back.
351 _omap_sram_idle(omap3_arm_context, save_state);
354 /* Restore table entry modified during MMU restoration */
355 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
356 restore_table_entry();
358 if (core_next_state < PWRDM_POWER_ON) {
359 if (per_next_state < PWRDM_POWER_ON)
360 omap_uart_resume_idle(2);
361 omap_uart_resume_idle(1);
362 omap_uart_resume_idle(0);
364 /* Disable IO-PAD wakeup */
365 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
366 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
367 if (core_prev_state == PWRDM_POWER_OFF) {
368 omap3_core_restore_context();
369 omap3_prcm_restore_context();
370 omap3_sram_restore_context();
372 if (per_next_state < PWRDM_POWER_ON) {
374 pwrdm_read_prev_pwrst(per_pwrdm);
375 if (per_prev_state == PWRDM_POWER_OFF)
376 omap3_per_restore_context();
378 omap2_gpio_resume_after_retention();
381 pwrdm_post_transition();
386 * Check if functional clocks are enabled before entering
387 * sleep. This function could be behind CONFIG_PM_DEBUG
388 * when all drivers are configuring their sysconfig registers
389 * properly and using their clocks properly.
391 static int omap3_fclks_active(void)
393 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
394 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
396 fck_core1 = cm_read_mod_reg(CORE_MOD,
398 if (omap_rev() > OMAP3430_REV_ES1_0) {
399 fck_core3 = cm_read_mod_reg(CORE_MOD,
400 OMAP3430ES2_CM_FCLKEN3);
401 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
403 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
406 fck_sgx = cm_read_mod_reg(GFX_MOD,
407 OMAP3430ES2_CM_FCLKEN3);
408 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
410 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
412 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
415 /* Ignore UART clocks. These are handled by UART core (serial.c) */
416 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
417 fck_per &= ~OMAP3430_EN_UART3;
419 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
420 fck_cam | fck_per | fck_usbhost)
425 static int omap3_can_sleep(void)
427 if (!omap_uart_can_sleep())
429 if (omap3_fclks_active())
434 /* This sets pwrdm state (other than mpu & core. Currently only ON &
435 * RET are supported. Function is assuming that clkdm doesn't have
436 * hw_sup mode enabled. */
437 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
440 int sleep_switch = 0;
443 if (pwrdm == NULL || IS_ERR(pwrdm))
446 while (!(pwrdm->pwrsts & (1 << state))) {
447 if (state == PWRDM_POWER_OFF)
452 cur_state = pwrdm_read_next_pwrst(pwrdm);
453 if (cur_state == state)
456 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
457 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
459 pwrdm_wait_transition(pwrdm);
462 ret = pwrdm_set_next_pwrst(pwrdm, state);
464 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
470 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
471 pwrdm_wait_transition(pwrdm);
472 pwrdm_state_switch(pwrdm);
479 static void omap3_pm_idle(void)
484 if (!omap3_can_sleep())
487 if (omap_irq_pending())
497 #ifdef CONFIG_SUSPEND
498 static suspend_state_t suspend_state;
500 static int omap3_pm_prepare(void)
506 static int omap3_pm_suspend(void)
508 struct power_state *pwrst;
511 /* Read current next_pwrsts */
512 list_for_each_entry(pwrst, &pwrst_list, node)
513 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
514 /* Set ones wanted by suspend */
515 list_for_each_entry(pwrst, &pwrst_list, node) {
516 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
518 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
522 omap_uart_prepare_suspend();
526 /* Restore next_pwrsts */
527 list_for_each_entry(pwrst, &pwrst_list, node) {
528 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
529 if (state > pwrst->next_state) {
530 printk(KERN_INFO "Powerdomain (%s) didn't enter "
532 pwrst->pwrdm->name, pwrst->next_state);
535 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
538 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
540 printk(KERN_INFO "Successfully put all powerdomains "
541 "to target state\n");
546 static int omap3_pm_enter(suspend_state_t unused)
550 switch (suspend_state) {
551 case PM_SUSPEND_STANDBY:
553 ret = omap3_pm_suspend();
562 static void omap3_pm_finish(void)
567 /* Hooks to enable / disable UART interrupts during suspend */
568 static int omap3_pm_begin(suspend_state_t state)
570 suspend_state = state;
571 omap_uart_enable_irqs(0);
575 static void omap3_pm_end(void)
577 suspend_state = PM_SUSPEND_ON;
578 omap_uart_enable_irqs(1);
582 static struct platform_suspend_ops omap_pm_ops = {
583 .begin = omap3_pm_begin,
585 .prepare = omap3_pm_prepare,
586 .enter = omap3_pm_enter,
587 .finish = omap3_pm_finish,
588 .valid = suspend_valid_only_mem,
590 #endif /* CONFIG_SUSPEND */
594 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
597 * In cases where IVA2 is activated by bootcode, it may prevent
598 * full-chip retention or off-mode because it is not idle. This
599 * function forces the IVA2 into idle state so it can go
600 * into retention/off and thus allow full-chip retention/off.
603 static void __init omap3_iva_idle(void)
605 /* ensure IVA2 clock is disabled */
606 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
608 /* if no clock activity, nothing else to do */
609 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
610 OMAP3430_CLKACTIVITY_IVA2_MASK))
614 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
617 OMAP3430_IVA2_MOD, RM_RSTCTRL);
619 /* Enable IVA2 clock */
620 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
621 OMAP3430_IVA2_MOD, CM_FCLKEN);
623 /* Set IVA2 boot mode to 'idle' */
624 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
625 OMAP343X_CONTROL_IVA2_BOOTMOD);
628 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
630 /* Disable IVA2 clock */
631 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
634 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
637 OMAP3430_IVA2_MOD, RM_RSTCTRL);
640 static void __init omap3_d2d_idle(void)
644 /* In a stand alone OMAP3430 where there is not a stacked
645 * modem for the D2D Idle Ack and D2D MStandby must be pulled
646 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
647 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
648 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
649 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
651 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
653 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
655 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
658 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
659 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
660 CORE_MOD, RM_RSTCTRL);
661 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
664 static void __init prcm_setup_regs(void)
666 /* XXX Reset all wkdeps. This should be done when initializing
668 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
669 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
670 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
671 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
672 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
673 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
674 if (omap_rev() > OMAP3430_REV_ES1_0) {
675 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
676 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
678 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
681 * Enable interface clock autoidle for all modules.
682 * Note that in the long run this should be done by clockfw
685 OMAP3430_AUTO_MODEM |
686 OMAP3430ES2_AUTO_MMC3 |
687 OMAP3430ES2_AUTO_ICR |
689 OMAP3430_AUTO_SHA12 |
693 OMAP3430_AUTO_MSPRO |
695 OMAP3430_AUTO_MCSPI4 |
696 OMAP3430_AUTO_MCSPI3 |
697 OMAP3430_AUTO_MCSPI2 |
698 OMAP3430_AUTO_MCSPI1 |
702 OMAP3430_AUTO_UART2 |
703 OMAP3430_AUTO_UART1 |
704 OMAP3430_AUTO_GPT11 |
705 OMAP3430_AUTO_GPT10 |
706 OMAP3430_AUTO_MCBSP5 |
707 OMAP3430_AUTO_MCBSP1 |
708 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
709 OMAP3430_AUTO_MAILBOXES |
710 OMAP3430_AUTO_OMAPCTRL |
711 OMAP3430ES1_AUTO_FSHOSTUSB |
712 OMAP3430_AUTO_HSOTGUSB |
713 OMAP3430_AUTO_SAD2D |
715 CORE_MOD, CM_AUTOIDLE1);
721 OMAP3430_AUTO_SHA11 |
723 CORE_MOD, CM_AUTOIDLE2);
725 if (omap_rev() > OMAP3430_REV_ES1_0) {
727 OMAP3430_AUTO_MAD2D |
728 OMAP3430ES2_AUTO_USBTLL,
729 CORE_MOD, CM_AUTOIDLE3);
735 OMAP3430_AUTO_GPIO1 |
736 OMAP3430_AUTO_32KSYNC |
737 OMAP3430_AUTO_GPT12 |
739 WKUP_MOD, CM_AUTOIDLE);
752 OMAP3430_AUTO_GPIO6 |
753 OMAP3430_AUTO_GPIO5 |
754 OMAP3430_AUTO_GPIO4 |
755 OMAP3430_AUTO_GPIO3 |
756 OMAP3430_AUTO_GPIO2 |
758 OMAP3430_AUTO_UART3 |
767 OMAP3430_AUTO_MCBSP4 |
768 OMAP3430_AUTO_MCBSP3 |
769 OMAP3430_AUTO_MCBSP2,
773 if (omap_rev() > OMAP3430_REV_ES1_0) {
775 OMAP3430ES2_AUTO_USBHOST,
776 OMAP3430ES2_USBHOST_MOD,
781 * Set all plls to autoidle. This is needed until autoidle is
784 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
785 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
786 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
789 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
790 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
793 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
798 * Enable control of expternal oscillator through
799 * sys_clkreq. In the long run clock framework should
802 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
803 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
805 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
807 /* setup wakup source */
808 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
809 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
811 /* No need to write EN_IO, that is always enabled */
812 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
814 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
815 /* For some reason IO doesn't generate wakeup event even if
816 * it is selected to mpu wakeup goup */
817 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
818 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
820 /* Enable wakeups in PER */
821 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
822 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
823 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
824 OMAP3430_PER_MOD, PM_WKEN);
825 /* and allow them to wake up MPU */
826 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
827 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
828 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
829 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
831 /* Don't attach IVA interrupts */
832 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
833 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
834 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
835 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
837 /* Clear any pending 'reset' flags */
838 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
839 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
840 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
841 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
842 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
843 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
844 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
846 /* Clear any pending PRCM interrupts */
847 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
849 /* Don't attach IVA interrupts */
850 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
851 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
852 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
853 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
855 /* Clear any pending 'reset' flags */
856 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
857 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
858 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
859 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
860 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
861 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
862 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
864 /* Clear any pending PRCM interrupts */
865 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
871 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
873 struct power_state *pwrst;
875 list_for_each_entry(pwrst, &pwrst_list, node) {
876 if (pwrst->pwrdm == pwrdm)
877 return pwrst->next_state;
882 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
884 struct power_state *pwrst;
886 list_for_each_entry(pwrst, &pwrst_list, node) {
887 if (pwrst->pwrdm == pwrdm) {
888 pwrst->next_state = state;
895 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
897 struct power_state *pwrst;
902 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
905 pwrst->pwrdm = pwrdm;
906 pwrst->next_state = PWRDM_POWER_RET;
907 list_add(&pwrst->node, &pwrst_list);
909 if (pwrdm_has_hdwr_sar(pwrdm))
910 pwrdm_enable_hdwr_sar(pwrdm);
912 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
916 * Enable hw supervised mode for all clockdomains if it's
917 * supported. Initiate sleep transition for other clockdomains, if
920 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
922 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
923 omap2_clkdm_allow_idle(clkdm);
924 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
925 atomic_read(&clkdm->usecount) == 0)
926 omap2_clkdm_sleep(clkdm);
930 void omap_push_sram_idle(void)
932 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
933 omap34xx_cpu_suspend_sz);
934 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
935 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
936 save_secure_ram_context_sz);
939 static int __init omap3_pm_init(void)
941 struct power_state *pwrst, *tmp;
944 if (!cpu_is_omap34xx())
947 printk(KERN_ERR "Power Management for TI OMAP3.\n");
949 /* XXX prcm_setup_regs needs to be before enabling hw
950 * supervised mode for powerdomains */
953 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
954 (irq_handler_t)prcm_interrupt_handler,
955 IRQF_DISABLED, "prcm", NULL);
957 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
958 INT_34XX_PRCM_MPU_IRQ);
962 ret = pwrdm_for_each(pwrdms_setup, NULL);
964 printk(KERN_ERR "Failed to setup powerdomains\n");
968 (void) clkdm_for_each(clkdms_setup, NULL);
970 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
971 if (mpu_pwrdm == NULL) {
972 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
976 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
977 per_pwrdm = pwrdm_lookup("per_pwrdm");
978 core_pwrdm = pwrdm_lookup("core_pwrdm");
980 omap_push_sram_idle();
981 #ifdef CONFIG_SUSPEND
982 suspend_set_ops(&omap_pm_ops);
983 #endif /* CONFIG_SUSPEND */
985 pm_idle = omap3_pm_idle;
987 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
989 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
990 * IO-pad wakeup. Otherwise it will unnecessarily waste power
991 * waking up PER with every CORE wakeup - see
992 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
994 pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
996 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
997 omap3_secure_ram_storage =
998 kmalloc(0x803F, GFP_KERNEL);
999 if (!omap3_secure_ram_storage)
1000 printk(KERN_ERR "Memory allocation failed when"
1001 "allocating for secure sram context\n");
1003 omap3_save_scratchpad_contents();
1008 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1009 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1010 list_del(&pwrst->node);
1016 late_initcall(omap3_pm_init);