2 * OMAP2+ common Power & Reset Management (PRM) IP block functions
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Tero Kristo <t-kristo@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 * For historical purposes, the API used to configure the PRM
13 * interrupt handler refers to it as the "PRCM interrupt." The
14 * underlying registers are located in the PRM on OMAP3/4.
16 * XXX This code should eventually be moved to a PRM driver.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
27 #include <mach/system.h>
28 #include <plat/common.h>
29 #include <plat/prcm.h>
30 #include <plat/irqs.h>
32 #include "prm2xxx_3xxx.h"
36 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
37 * XXX this is technically not needed, since
38 * omap_prcm_register_chain_handler() could allocate this based on the
39 * actual amount of memory needed for the SoC
41 #define OMAP_PRCM_MAX_NR_PENDING_REG 2
44 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
45 * by the PRCM interrupt handler code. There will be one 'chip' per
46 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
47 * one "chip" and OMAP4 will have two.)
49 static struct irq_chip_generic **prcm_irq_chips;
52 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
53 * is currently running on. Defined and passed by initialization code
54 * that calls omap_prcm_register_chain_handler().
56 static struct omap_prcm_irq_setup *prcm_irq_setup;
58 /* Private functions */
61 * Move priority events from events to priority_events array
63 static void omap_prcm_events_filter_priority(unsigned long *events,
64 unsigned long *priority_events)
68 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
70 events[i] & prcm_irq_setup->priority_mask[i];
71 events[i] ^= priority_events[i];
76 * PRCM Interrupt Handler
78 * This is a common handler for the OMAP PRCM interrupts. Pending
79 * interrupts are detected by a call to prcm_pending_events and
80 * dispatched accordingly. Clearing of the wakeup events should be
81 * done by the SoC specific individual handlers.
83 static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
85 unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
86 unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
87 struct irq_chip *chip = irq_desc_get_chip(desc);
89 int nr_irqs = prcm_irq_setup->nr_regs * 32;
92 * Loop until all pending irqs are handled, since
93 * generic_handle_irq() can cause new irqs to come
96 prcm_irq_setup->read_pending_irqs(pending);
98 /* No bit set, then all IRQs are handled */
99 if (find_first_bit(pending, nr_irqs) >= nr_irqs)
102 omap_prcm_events_filter_priority(pending, priority_pending);
105 * Loop on all currently pending irqs so that new irqs
106 * cannot starve previously pending irqs
109 /* Serve priority events first */
110 for_each_set_bit(virtirq, priority_pending, nr_irqs)
111 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
113 /* Serve normal events next */
114 for_each_set_bit(virtirq, pending, nr_irqs)
115 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
118 chip->irq_ack(&desc->irq_data);
120 chip->irq_eoi(&desc->irq_data);
121 chip->irq_unmask(&desc->irq_data);
123 prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
126 /* Public functions */
129 * omap_prcm_event_to_irq - given a PRCM event name, returns the
130 * corresponding IRQ on which the handler should be registered
131 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
133 * Returns the Linux internal IRQ ID corresponding to @name upon success,
134 * or -ENOENT upon failure.
136 int omap_prcm_event_to_irq(const char *name)
140 if (!prcm_irq_setup || !name)
143 for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
144 if (!strcmp(prcm_irq_setup->irqs[i].name, name))
145 return prcm_irq_setup->base_irq +
146 prcm_irq_setup->irqs[i].offset;
152 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
153 * done by omap_prcm_register_chain_handler()
157 void omap_prcm_irq_cleanup(void)
161 if (!prcm_irq_setup) {
162 pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
166 if (prcm_irq_chips) {
167 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
168 if (prcm_irq_chips[i])
169 irq_remove_generic_chip(prcm_irq_chips[i],
171 prcm_irq_chips[i] = NULL;
173 kfree(prcm_irq_chips);
174 prcm_irq_chips = NULL;
177 kfree(prcm_irq_setup->priority_mask);
178 prcm_irq_setup->priority_mask = NULL;
180 irq_set_chained_handler(prcm_irq_setup->irq, NULL);
182 if (prcm_irq_setup->base_irq > 0)
183 irq_free_descs(prcm_irq_setup->base_irq,
184 prcm_irq_setup->nr_regs * 32);
185 prcm_irq_setup->base_irq = 0;
189 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
190 * handler based on provided parameters
191 * @irq_setup: hardware data about the underlying PRM/PRCM
193 * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
194 * one generic IRQ chip per PRM interrupt status/enable register pair.
195 * Returns 0 upon success, -EINVAL if called twice or if invalid
196 * arguments are passed, or -ENOMEM on any other error.
198 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
200 int nr_regs = irq_setup->nr_regs;
201 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
203 struct irq_chip_generic *gc;
204 struct irq_chip_type *ct;
209 if (prcm_irq_setup) {
210 pr_err("PRCM: already initialized; won't reinitialize\n");
214 if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
215 pr_err("PRCM: nr_regs too large\n");
219 prcm_irq_setup = irq_setup;
221 prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
222 prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
225 if (!prcm_irq_chips || !prcm_irq_setup->priority_mask) {
226 pr_err("PRCM: kzalloc failed\n");
230 memset(mask, 0, sizeof(mask));
232 for (i = 0; i < irq_setup->nr_irqs; i++) {
233 offset = irq_setup->irqs[i].offset;
234 mask[offset >> 5] |= 1 << (offset & 0x1f);
235 if (irq_setup->irqs[i].priority)
236 irq_setup->priority_mask[offset >> 5] |=
237 1 << (offset & 0x1f);
240 irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
242 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
245 if (irq_setup->base_irq < 0) {
246 pr_err("PRCM: failed to allocate irq descs: %d\n",
247 irq_setup->base_irq);
251 for (i = 0; i <= irq_setup->nr_regs; i++) {
252 gc = irq_alloc_generic_chip("PRCM", 1,
253 irq_setup->base_irq + i * 32, prm_base,
257 pr_err("PRCM: failed to allocate generic chip\n");
261 ct->chip.irq_ack = irq_gc_ack_set_bit;
262 ct->chip.irq_mask = irq_gc_mask_clr_bit;
263 ct->chip.irq_unmask = irq_gc_mask_set_bit;
265 ct->regs.ack = irq_setup->ack + i * 4;
266 ct->regs.mask = irq_setup->mask + i * 4;
268 irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
269 prcm_irq_chips[i] = gc;
275 omap_prcm_irq_cleanup();