2 * OMAP2+ common Power & Reset Management (PRM) IP block functions
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Tero Kristo <t-kristo@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 * For historical purposes, the API used to configure the PRM
13 * interrupt handler refers to it as the "PRCM interrupt." The
14 * underlying registers are located in the PRM on OMAP3/4.
16 * XXX This code should eventually be moved to a PRM driver.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
27 #include <plat/common.h>
28 #include <plat/prcm.h>
30 #include "prm2xxx_3xxx.h"
34 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
35 * XXX this is technically not needed, since
36 * omap_prcm_register_chain_handler() could allocate this based on the
37 * actual amount of memory needed for the SoC
39 #define OMAP_PRCM_MAX_NR_PENDING_REG 2
42 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
43 * by the PRCM interrupt handler code. There will be one 'chip' per
44 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
45 * one "chip" and OMAP4 will have two.)
47 static struct irq_chip_generic **prcm_irq_chips;
50 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
51 * is currently running on. Defined and passed by initialization code
52 * that calls omap_prcm_register_chain_handler().
54 static struct omap_prcm_irq_setup *prcm_irq_setup;
56 /* Private functions */
59 * Move priority events from events to priority_events array
61 static void omap_prcm_events_filter_priority(unsigned long *events,
62 unsigned long *priority_events)
66 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
68 events[i] & prcm_irq_setup->priority_mask[i];
69 events[i] ^= priority_events[i];
74 * PRCM Interrupt Handler
76 * This is a common handler for the OMAP PRCM interrupts. Pending
77 * interrupts are detected by a call to prcm_pending_events and
78 * dispatched accordingly. Clearing of the wakeup events should be
79 * done by the SoC specific individual handlers.
81 static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
83 unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
84 unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
85 struct irq_chip *chip = irq_desc_get_chip(desc);
87 int nr_irq = prcm_irq_setup->nr_regs * 32;
90 * If we are suspended, mask all interrupts from PRCM level,
91 * this does not ack them, and they will be pending until we
92 * re-enable the interrupts, at which point the
93 * omap_prcm_irq_handler will be executed again. The
94 * _save_and_clear_irqen() function must ensure that the PRM
95 * write to disable all IRQs has reached the PRM before
96 * returning, or spurious PRCM interrupts may occur during
99 if (prcm_irq_setup->suspended) {
100 prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
101 prcm_irq_setup->suspend_save_flag = true;
105 * Loop until all pending irqs are handled, since
106 * generic_handle_irq() can cause new irqs to come
108 while (!prcm_irq_setup->suspended) {
109 prcm_irq_setup->read_pending_irqs(pending);
111 /* No bit set, then all IRQs are handled */
112 if (find_first_bit(pending, nr_irq) >= nr_irq)
115 omap_prcm_events_filter_priority(pending, priority_pending);
118 * Loop on all currently pending irqs so that new irqs
119 * cannot starve previously pending irqs
122 /* Serve priority events first */
123 for_each_set_bit(virtirq, priority_pending, nr_irq)
124 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
126 /* Serve normal events next */
127 for_each_set_bit(virtirq, pending, nr_irq)
128 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
131 chip->irq_ack(&desc->irq_data);
133 chip->irq_eoi(&desc->irq_data);
134 chip->irq_unmask(&desc->irq_data);
136 prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
139 /* Public functions */
142 * omap_prcm_event_to_irq - given a PRCM event name, returns the
143 * corresponding IRQ on which the handler should be registered
144 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
146 * Returns the Linux internal IRQ ID corresponding to @name upon success,
147 * or -ENOENT upon failure.
149 int omap_prcm_event_to_irq(const char *name)
153 if (!prcm_irq_setup || !name)
156 for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
157 if (!strcmp(prcm_irq_setup->irqs[i].name, name))
158 return prcm_irq_setup->base_irq +
159 prcm_irq_setup->irqs[i].offset;
165 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
166 * done by omap_prcm_register_chain_handler()
170 void omap_prcm_irq_cleanup(void)
174 if (!prcm_irq_setup) {
175 pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
179 if (prcm_irq_chips) {
180 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
181 if (prcm_irq_chips[i])
182 irq_remove_generic_chip(prcm_irq_chips[i],
184 prcm_irq_chips[i] = NULL;
186 kfree(prcm_irq_chips);
187 prcm_irq_chips = NULL;
190 kfree(prcm_irq_setup->saved_mask);
191 prcm_irq_setup->saved_mask = NULL;
193 kfree(prcm_irq_setup->priority_mask);
194 prcm_irq_setup->priority_mask = NULL;
196 irq_set_chained_handler(prcm_irq_setup->irq, NULL);
198 if (prcm_irq_setup->base_irq > 0)
199 irq_free_descs(prcm_irq_setup->base_irq,
200 prcm_irq_setup->nr_regs * 32);
201 prcm_irq_setup->base_irq = 0;
204 void omap_prcm_irq_prepare(void)
206 prcm_irq_setup->suspended = true;
209 void omap_prcm_irq_complete(void)
211 prcm_irq_setup->suspended = false;
213 /* If we have not saved the masks, do not attempt to restore */
214 if (!prcm_irq_setup->suspend_save_flag)
217 prcm_irq_setup->suspend_save_flag = false;
220 * Re-enable all masked PRCM irq sources, this causes the PRCM
221 * interrupt to fire immediately if the events were masked
222 * previously in the chain handler
224 prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
228 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
229 * handler based on provided parameters
230 * @irq_setup: hardware data about the underlying PRM/PRCM
232 * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
233 * one generic IRQ chip per PRM interrupt status/enable register pair.
234 * Returns 0 upon success, -EINVAL if called twice or if invalid
235 * arguments are passed, or -ENOMEM on any other error.
237 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
240 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
242 struct irq_chip_generic *gc;
243 struct irq_chip_type *ct;
248 nr_regs = irq_setup->nr_regs;
250 if (prcm_irq_setup) {
251 pr_err("PRCM: already initialized; won't reinitialize\n");
255 if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
256 pr_err("PRCM: nr_regs too large\n");
260 prcm_irq_setup = irq_setup;
262 prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
263 prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
264 prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
267 if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
268 !prcm_irq_setup->priority_mask) {
269 pr_err("PRCM: kzalloc failed\n");
273 memset(mask, 0, sizeof(mask));
275 for (i = 0; i < irq_setup->nr_irqs; i++) {
276 offset = irq_setup->irqs[i].offset;
277 mask[offset >> 5] |= 1 << (offset & 0x1f);
278 if (irq_setup->irqs[i].priority)
279 irq_setup->priority_mask[offset >> 5] |=
280 1 << (offset & 0x1f);
283 irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
285 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
288 if (irq_setup->base_irq < 0) {
289 pr_err("PRCM: failed to allocate irq descs: %d\n",
290 irq_setup->base_irq);
294 for (i = 0; i < irq_setup->nr_regs; i++) {
295 gc = irq_alloc_generic_chip("PRCM", 1,
296 irq_setup->base_irq + i * 32, prm_base,
300 pr_err("PRCM: failed to allocate generic chip\n");
304 ct->chip.irq_ack = irq_gc_ack_set_bit;
305 ct->chip.irq_mask = irq_gc_mask_clr_bit;
306 ct->chip.irq_unmask = irq_gc_mask_set_bit;
308 ct->regs.ack = irq_setup->ack + i * 4;
309 ct->regs.mask = irq_setup->mask + i * 4;
311 irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
312 prcm_irq_chips[i] = gc;
318 omap_prcm_irq_cleanup();
323 * Stubbed functions so that common files continue to build when
324 * custom builds are used
325 * XXX These are temporary and should be removed at the earliest possible
328 u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx)
330 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
334 void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
336 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
339 u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
342 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
346 u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
348 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
352 u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
354 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
358 u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
360 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
364 int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
366 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
370 int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
372 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
376 int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
379 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");