arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/delay.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/console.h>
  29
  30 #include <plat/omap-serial.h>
  31 #include "common.h"
  32 #include <plat/board.h>
  33 #include <plat/dma.h>
  34 #include <plat/omap_hwmod.h>
  35 #include <plat/omap_device.h>
  36
  37 #include "prm2xxx_3xxx.h"
  38 #include "pm.h"
  39 #include "cm2xxx_3xxx.h"
  40 #include "prm-regbits-34xx.h"
  41 #include "control.h"
  42 #include "mux.h"
  43
  44 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  45
  46 #define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
  47
  48 /*
  49  * NOTE: By default the serial timeout is disabled as it causes lost characters
  50  * over the serial ports. This means that the UART clocks will stay on until
  51  * disabled via sysfs. This also causes that any deeper omap sleep states are
  52  * blocked.
  53  */
  54 #define DEFAULT_TIMEOUT 0
  55
  56 #define MAX_UART_HWMOD_NAME_LEN         16
  57
  58 struct omap_uart_state {
  59         int num;
  60         int can_sleep;
  61
  62         void __iomem *wk_st;
  63         void __iomem *wk_en;
  64         u32 wk_mask;
  65         u32 dma_enabled;
  66
  67         int clocked;
  68
  69         int regshift;
  70         void __iomem *membase;
  71         resource_size_t mapbase;
  72
  73         struct list_head node;
  74         struct omap_hwmod *oh;
  75         struct platform_device *pdev;
  76
  77         u32 errata;
  78 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  79         int context_valid;
  80
  81         /* Registers to be saved/restored for OFF-mode */
  82         u16 dll;
  83         u16 dlh;
  84         u16 ier;
  85         u16 sysc;
  86         u16 scr;
  87         u16 wer;
  88         u16 mcr;
  89 #endif
  90 };
  91
  92 static LIST_HEAD(uart_list);
  93 static u8 num_uarts;
  94
  95 static inline unsigned int __serial_read_reg(struct uart_port *up,
  96                                              int offset)
  97 {
  98         offset <<= up->regshift;
  99         return (unsigned int)__raw_readb(up->membase + offset);
 100 }
 101
 102 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
 103                                            int offset)
 104 {
 105         offset <<= uart->regshift;
 106         return (unsigned int)__raw_readb(uart->membase + offset);
 107 }
 108
 109 static inline void __serial_write_reg(struct uart_port *up, int offset,
 110                 int value)
 111 {
 112         offset <<= up->regshift;
 113         __raw_writeb(value, up->membase + offset);
 114 }
 115
 116 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
 117                                     int value)
 118 {
 119         offset <<= uart->regshift;
 120         __raw_writeb(value, uart->membase + offset);
 121 }
 122
 123 /*
 124  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 125  * properly. Note that the TX watermark initialization may not be needed
 126  * once the 8250.c watermark handling code is merged.
 127  */
 128
 129 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 130 {
 131         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 132         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
 133         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
 134 }
 135
 136 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 137
 138 /*
 139  * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
 140  * The access to uart register after MDR1 Access
 141  * causes UART to corrupt data.
 142  *
 143  * Need a delay =
 144  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 145  * give 10 times as much
 146  */
 147 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 148                 u8 fcr_val)
 149 {
 150         u8 timeout = 255;
 151
 152         serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
 153         udelay(2);
 154         serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
 155                         UART_FCR_CLEAR_RCVR);
 156         /*
 157          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 158          * TX_FIFO_E bit is 1.
 159          */
 160         while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
 161                                 (UART_LSR_THRE | UART_LSR_DR))) {
 162                 timeout--;
 163                 if (!timeout) {
 164                         /* Should *never* happen. we warn and carry on */
 165                         dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
 166                         serial_read_reg(uart, UART_LSR));
 167                         break;
 168                 }
 169                 udelay(1);
 170         }
 171 }
 172
 173 static void omap_uart_save_context(struct omap_uart_state *uart)
 174 {
 175         u16 lcr = 0;
 176
 177         if (!enable_off_mode)
 178                 return;
 179
 180         lcr = serial_read_reg(uart, UART_LCR);
 181         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 182         uart->dll = serial_read_reg(uart, UART_DLL);
 183         uart->dlh = serial_read_reg(uart, UART_DLM);
 184         serial_write_reg(uart, UART_LCR, lcr);
 185         uart->ier = serial_read_reg(uart, UART_IER);
 186         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
 187         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
 188         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
 189         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 190         uart->mcr = serial_read_reg(uart, UART_MCR);
 191         serial_write_reg(uart, UART_LCR, lcr);
 192
 193         uart->context_valid = 1;
 194 }
 195
 196 static void omap_uart_restore_context(struct omap_uart_state *uart)
 197 {
 198         u16 efr = 0;
 199
 200         if (!enable_off_mode)
 201                 return;
 202
 203         if (!uart->context_valid)
 204                 return;
 205
 206         uart->context_valid = 0;
 207
 208         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 209                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
 210         else
 211                 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 212
 213         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 214         efr = serial_read_reg(uart, UART_EFR);
 215         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
 216         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 217         serial_write_reg(uart, UART_IER, 0x0);
 218         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 219         serial_write_reg(uart, UART_DLL, uart->dll);
 220         serial_write_reg(uart, UART_DLM, uart->dlh);
 221         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 222         serial_write_reg(uart, UART_IER, uart->ier);
 223         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 224         serial_write_reg(uart, UART_MCR, uart->mcr);
 225         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 226         serial_write_reg(uart, UART_EFR, efr);
 227         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
 228         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
 229         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
 230         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
 231
 232         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 233                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
 234         else
 235                 /* UART 16x mode */
 236                 serial_write_reg(uart, UART_OMAP_MDR1,
 237                                 UART_OMAP_MDR1_16X_MODE);
 238 }
 239 #else
 240 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 241 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 242 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 243
 244 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 245 {
 246         if (uart->clocked)
 247                 return;
 248
 249         omap_device_enable(uart->pdev);
 250         uart->clocked = 1;
 251         omap_uart_restore_context(uart);
 252 }
 253
 254 #ifdef CONFIG_PM
 255
 256 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 257 {
 258         if (!uart->clocked)
 259                 return;
 260
 261         omap_uart_save_context(uart);
 262         uart->clocked = 0;
 263         omap_device_idle(uart->pdev);
 264 }
 265
 266 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 267 {
 268         /* Set wake-enable bit */
 269         if (uart->wk_en && uart->wk_mask) {
 270                 u32 v = __raw_readl(uart->wk_en);
 271                 v |= uart->wk_mask;
 272                 __raw_writel(v, uart->wk_en);
 273         }
 274 }
 275
 276 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 277 {
 278         /* Clear wake-enable bit */
 279         if (uart->wk_en && uart->wk_mask) {
 280                 u32 v = __raw_readl(uart->wk_en);
 281                 v &= ~uart->wk_mask;
 282                 __raw_writel(v, uart->wk_en);
 283         }
 284 }
 285
 286 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 287                                                int enable)
 288 {
 289         u8 idlemode;
 290
 291         if (enable) {
 292                 /**
 293                  * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
 294                  * in Smartidle Mode When Configured for DMA Operations.
 295                  */
 296                 if (uart->dma_enabled)
 297                         idlemode = HWMOD_IDLEMODE_FORCE;
 298                 else
 299                         idlemode = HWMOD_IDLEMODE_SMART;
 300         } else {
 301                 idlemode = HWMOD_IDLEMODE_NO;
 302         }
 303
 304         omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 305 }
 306
 307 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 308 {
 309         omap_uart_enable_clocks(uart);
 310
 311         omap_uart_smart_idle_enable(uart, 0);
 312         uart->can_sleep = 0;
 313 }
 314
 315 int omap_uart_can_sleep(void)
 316 {
 317         struct omap_uart_state *uart;
 318         int can_sleep = 1;
 319
 320         list_for_each_entry(uart, &uart_list, node) {
 321                 if (!uart->clocked)
 322                         continue;
 323
 324                 if (!uart->can_sleep) {
 325                         can_sleep = 0;
 326                         continue;
 327                 }
 328
 329                 /* This UART can now safely sleep. */
 330                 omap_uart_allow_sleep(uart);
 331         }
 332
 333         return can_sleep;
 334 }
 335
 336 static void omap_uart_idle_init(struct omap_uart_state *uart)
 337 {
 338         int ret;
 339
 340         uart->can_sleep = 0;
 341         omap_uart_smart_idle_enable(uart, 0);
 342
 343         if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) {
 344                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 345                 u32 wk_mask = 0;
 346
 347                 /* XXX These PRM accesses do not belong here */
 348                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 349                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 350                 switch (uart->num) {
 351                 case 0:
 352                         wk_mask = OMAP3430_ST_UART1_MASK;
 353                         break;
 354                 case 1:
 355                         wk_mask = OMAP3430_ST_UART2_MASK;
 356                         break;
 357                 case 2:
 358                         wk_mask = OMAP3430_ST_UART3_MASK;
 359                         break;
 360                 case 3:
 361                         wk_mask = OMAP3630_ST_UART4_MASK;
 362                         break;
 363                 }
 364                 uart->wk_mask = wk_mask;
 365         } else if (cpu_is_omap24xx()) {
 366                 u32 wk_mask = 0;
 367                 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 368
 369                 switch (uart->num) {
 370                 case 0:
 371                         wk_mask = OMAP24XX_ST_UART1_MASK;
 372                         break;
 373                 case 1:
 374                         wk_mask = OMAP24XX_ST_UART2_MASK;
 375                         break;
 376                 case 2:
 377                         wk_en = OMAP24XX_PM_WKEN2;
 378                         wk_st = OMAP24XX_PM_WKST2;
 379                         wk_mask = OMAP24XX_ST_UART3_MASK;
 380                         break;
 381                 }
 382                 uart->wk_mask = wk_mask;
 383                 if (cpu_is_omap2430()) {
 384                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
 385                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
 386                 } else if (cpu_is_omap2420()) {
 387                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
 388                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
 389                 }
 390         } else {
 391                 uart->wk_en = NULL;
 392                 uart->wk_st = NULL;
 393                 uart->wk_mask = 0;
 394         }
 395 }
 396
 397 #else
 398 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 399 {
 400         /* Needed to enable UART clocks when built without CONFIG_PM */
 401         omap_uart_enable_clocks(uart);
 402 }
 403 #endif /* CONFIG_PM */
 404
 405 #ifdef CONFIG_OMAP_MUX
 406 static struct omap_device_pad default_uart1_pads[] __initdata = {
 407         {
 408                 .name   = "uart1_cts.uart1_cts",
 409                 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
 410         },
 411         {
 412                 .name   = "uart1_rts.uart1_rts",
 413                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 414         },
 415         {
 416                 .name   = "uart1_tx.uart1_tx",
 417                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 418         },
 419         {
 420                 .name   = "uart1_rx.uart1_rx",
 421                 .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
 422                 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
 423                 .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
 424         },
 425 };
 426
 427 static struct omap_device_pad default_uart2_pads[] __initdata = {
 428         {
 429                 .name   = "uart2_cts.uart2_cts",
 430                 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
 431         },
 432         {
 433                 .name   = "uart2_rts.uart2_rts",
 434                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 435         },
 436         {
 437                 .name   = "uart2_tx.uart2_tx",
 438                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 439         },
 440         {
 441                 .name   = "uart2_rx.uart2_rx",
 442                 .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
 443                 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
 444                 .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
 445         },
 446 };
 447
 448 static struct omap_device_pad default_uart3_pads[] __initdata = {
 449         {
 450                 .name   = "uart3_cts_rctx.uart3_cts_rctx",
 451                 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
 452         },
 453         {
 454                 .name   = "uart3_rts_sd.uart3_rts_sd",
 455                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 456         },
 457         {
 458                 .name   = "uart3_tx_irtx.uart3_tx_irtx",
 459                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 460         },
 461         {
 462                 .name   = "uart3_rx_irrx.uart3_rx_irrx",
 463                 .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
 464                 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
 465                 .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
 466         },
 467 };
 468
 469 static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
 470         {
 471                 .name   = "gpmc_wait2.uart4_tx",
 472                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 473         },
 474         {
 475                 .name   = "gpmc_wait3.uart4_rx",
 476                 .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
 477                 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
 478                 .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
 479         },
 480 };
 481
 482 static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
 483         {
 484                 .name   = "uart4_tx.uart4_tx",
 485                 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 486         },
 487         {
 488                 .name   = "uart4_rx.uart4_rx",
 489                 .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
 490                 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
 491                 .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
 492         },
 493 };
 494
 495 static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 496 {
 497         switch (bdata->id) {
 498         case 0:
 499                 bdata->pads = default_uart1_pads;
 500                 bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
 501                 break;
 502         case 1:
 503                 bdata->pads = default_uart2_pads;
 504                 bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
 505                 break;
 506         case 2:
 507                 bdata->pads = default_uart3_pads;
 508                 bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
 509                 break;
 510         case 3:
 511                 if (cpu_is_omap44xx()) {
 512                         bdata->pads = default_omap4_uart4_pads;
 513                         bdata->pads_cnt =
 514                                 ARRAY_SIZE(default_omap4_uart4_pads);
 515                 } else if (cpu_is_omap3630()) {
 516                         bdata->pads = default_omap36xx_uart4_pads;
 517                         bdata->pads_cnt =
 518                                 ARRAY_SIZE(default_omap36xx_uart4_pads);
 519                 }
 520                 break;
 521         default:
 522                 break;
 523         }
 524 }
 525 #else
 526 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
 527 #endif
 528
 529 static int __init omap_serial_early_init(void)
 530 {
 531         int i = 0;
 532
 533         do {
 534                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
 535                 struct omap_hwmod *oh;
 536                 struct omap_uart_state *uart;
 537
 538                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
 539                          "uart%d", i + 1);
 540                 oh = omap_hwmod_lookup(oh_name);
 541                 if (!oh)
 542                         break;
 543
 544                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
 545                 if (WARN_ON(!uart))
 546                         return -ENODEV;
 547
 548                 uart->oh = oh;
 549                 uart->num = i++;
 550                 list_add_tail(&uart->node, &uart_list);
 551                 num_uarts++;
 552
 553                 /*
 554                  * NOTE: omap_hwmod_setup*() has not yet been called,
 555                  *       so no hwmod functions will work yet.
 556                  */
 557
 558                 /*
 559                  * During UART early init, device need to be probed
 560                  * to determine SoC specific init before omap_device
 561                  * is ready.  Therefore, don't allow idle here
 562                  */
 563                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
 564         } while (1);
 565
 566         return 0;
 567 }
 568 core_initcall(omap_serial_early_init);
 569
 570 /**
 571  * omap_serial_init_port() - initialize single serial port
 572  * @bdata: port specific board data pointer
 573  *
 574  * This function initialies serial driver for given port only.
 575  * Platforms can call this function instead of omap_serial_init()
 576  * if they don't plan to use all available UARTs as serial ports.
 577  *
 578  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 579  * use only one of the two.
 580  */
 581 void __init omap_serial_init_port(struct omap_board_data *bdata)
 582 {
 583         struct omap_uart_state *uart;
 584         struct omap_hwmod *oh;
 585         struct platform_device *pdev;
 586         void *pdata = NULL;
 587         u32 pdata_size = 0;
 588         char *name;
 589         struct omap_uart_port_info omap_up;
 590
 591         if (WARN_ON(!bdata))
 592                 return;
 593         if (WARN_ON(bdata->id < 0))
 594                 return;
 595         if (WARN_ON(bdata->id >= num_uarts))
 596                 return;
 597
 598         list_for_each_entry(uart, &uart_list, node)
 599                 if (bdata->id == uart->num)
 600                         break;
 601
 602         oh = uart->oh;
 603         uart->dma_enabled = 0;
 604         name = DRIVER_NAME;
 605
 606         omap_up.dma_enabled = uart->dma_enabled;
 607         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
 608         omap_up.flags = UPF_BOOT_AUTOCONF;
 609
 610         pdata = &omap_up;
 611         pdata_size = sizeof(struct omap_uart_port_info);
 612
 613         if (WARN_ON(!oh))
 614                 return;
 615
 616         pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
 617                                  NULL, 0, false);
 618         WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
 619              name, oh->name);
 620
 621         omap_device_disable_idle_on_suspend(pdev);
 622         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 623
 624         uart->regshift = 2;
 625         uart->mapbase = oh->slaves[0]->addr->pa_start;
 626         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
 627         uart->pdev = pdev;
 628
 629         oh->dev_attr = uart;
 630
 631         console_lock(); /* in case the earlycon is on the UART */
 632
 633         /*
 634          * Because of early UART probing, UART did not get idled
 635          * on init.  Now that omap_device is ready, ensure full idle
 636          * before doing omap_device_enable().
 637          */
 638         omap_hwmod_idle(uart->oh);
 639
 640         omap_device_enable(uart->pdev);
 641         omap_uart_idle_init(uart);
 642         omap_uart_reset(uart);
 643         omap_hwmod_enable_wakeup(uart->oh);
 644         omap_device_idle(uart->pdev);
 645
 646         omap_uart_block_sleep(uart);
 647         console_unlock();
 648
 649         if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads) ||
 650                 (pdata->wk_en && pdata->wk_mask))
 651                 device_init_wakeup(&pdev->dev, true);
 652
 653         /* Enable the MDR1 errata for OMAP3 */
 654         if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx()))
 655                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 656 }
 657
 658 /**
 659  * omap_serial_init() - initialize all supported serial ports
 660  *
 661  * Initializes all available UARTs as serial ports. Platforms
 662  * can call this function when they want to have default behaviour
 663  * for serial ports (e.g initialize them all as serial ports).
 664  */
 665 void __init omap_serial_init(void)
 666 {
 667         struct omap_uart_state *uart;
 668         struct omap_board_data bdata;
 669
 670         list_for_each_entry(uart, &uart_list, node) {
 671                 bdata.id = uart->num;
 672                 bdata.flags = 0;
 673                 bdata.pads = NULL;
 674                 bdata.pads_cnt = 0;
 675
 676                 if (cpu_is_omap44xx() || cpu_is_omap34xx())
 677                         omap_serial_fill_default_pads(&bdata);
 678
 679                 omap_serial_init_port(&bdata);
 680
 681         }
 682 }