2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/console.h>
30 #include <plat/omap-serial.h>
32 #include <plat/board.h>
34 #include <plat/omap_hwmod.h>
35 #include <plat/omap_device.h>
37 #include "prm2xxx_3xxx.h"
39 #include "cm2xxx_3xxx.h"
40 #include "prm-regbits-34xx.h"
44 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
46 #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
49 * NOTE: By default the serial timeout is disabled as it causes lost characters
50 * over the serial ports. This means that the UART clocks will stay on until
51 * disabled via sysfs. This also causes that any deeper omap sleep states are
54 #define DEFAULT_TIMEOUT 0
56 #define MAX_UART_HWMOD_NAME_LEN 16
58 struct omap_uart_state {
70 void __iomem *membase;
71 resource_size_t mapbase;
73 struct list_head node;
74 struct omap_hwmod *oh;
75 struct platform_device *pdev;
78 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
81 /* Registers to be saved/restored for OFF-mode */
92 static LIST_HEAD(uart_list);
95 static inline unsigned int __serial_read_reg(struct uart_port *up,
98 offset <<= up->regshift;
99 return (unsigned int)__raw_readb(up->membase + offset);
102 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
105 offset <<= uart->regshift;
106 return (unsigned int)__raw_readb(uart->membase + offset);
109 static inline void __serial_write_reg(struct uart_port *up, int offset,
112 offset <<= up->regshift;
113 __raw_writeb(value, up->membase + offset);
116 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
119 offset <<= uart->regshift;
120 __raw_writeb(value, uart->membase + offset);
124 * Internal UARTs need to be initialized for the 8250 autoconfig to work
125 * properly. Note that the TX watermark initialization may not be needed
126 * once the 8250.c watermark handling code is merged.
129 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
131 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
132 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
133 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
136 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
139 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
140 * The access to uart register after MDR1 Access
141 * causes UART to corrupt data.
144 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
145 * give 10 times as much
147 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
152 serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
154 serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
155 UART_FCR_CLEAR_RCVR);
157 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
158 * TX_FIFO_E bit is 1.
160 while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
161 (UART_LSR_THRE | UART_LSR_DR))) {
164 /* Should *never* happen. we warn and carry on */
165 dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
166 serial_read_reg(uart, UART_LSR));
173 static void omap_uart_save_context(struct omap_uart_state *uart)
177 if (!enable_off_mode)
180 lcr = serial_read_reg(uart, UART_LCR);
181 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
182 uart->dll = serial_read_reg(uart, UART_DLL);
183 uart->dlh = serial_read_reg(uart, UART_DLM);
184 serial_write_reg(uart, UART_LCR, lcr);
185 uart->ier = serial_read_reg(uart, UART_IER);
186 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
187 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
188 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
189 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
190 uart->mcr = serial_read_reg(uart, UART_MCR);
191 serial_write_reg(uart, UART_LCR, lcr);
193 uart->context_valid = 1;
196 static void omap_uart_restore_context(struct omap_uart_state *uart)
200 if (!enable_off_mode)
203 if (!uart->context_valid)
206 uart->context_valid = 0;
208 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
209 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
211 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
213 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
214 efr = serial_read_reg(uart, UART_EFR);
215 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
216 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
217 serial_write_reg(uart, UART_IER, 0x0);
218 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
219 serial_write_reg(uart, UART_DLL, uart->dll);
220 serial_write_reg(uart, UART_DLM, uart->dlh);
221 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
222 serial_write_reg(uart, UART_IER, uart->ier);
223 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
224 serial_write_reg(uart, UART_MCR, uart->mcr);
225 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
226 serial_write_reg(uart, UART_EFR, efr);
227 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
228 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
229 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
230 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
232 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
233 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
236 serial_write_reg(uart, UART_OMAP_MDR1,
237 UART_OMAP_MDR1_16X_MODE);
240 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
241 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
242 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
244 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
249 omap_device_enable(uart->pdev);
251 omap_uart_restore_context(uart);
256 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
261 omap_uart_save_context(uart);
263 omap_device_idle(uart->pdev);
266 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
268 /* Set wake-enable bit */
269 if (uart->wk_en && uart->wk_mask) {
270 u32 v = __raw_readl(uart->wk_en);
272 __raw_writel(v, uart->wk_en);
276 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
278 /* Clear wake-enable bit */
279 if (uart->wk_en && uart->wk_mask) {
280 u32 v = __raw_readl(uart->wk_en);
282 __raw_writel(v, uart->wk_en);
286 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
293 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
294 * in Smartidle Mode When Configured for DMA Operations.
296 if (uart->dma_enabled)
297 idlemode = HWMOD_IDLEMODE_FORCE;
299 idlemode = HWMOD_IDLEMODE_SMART;
301 idlemode = HWMOD_IDLEMODE_NO;
304 omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
307 static void omap_uart_block_sleep(struct omap_uart_state *uart)
309 omap_uart_enable_clocks(uart);
311 omap_uart_smart_idle_enable(uart, 0);
315 int omap_uart_can_sleep(void)
317 struct omap_uart_state *uart;
320 list_for_each_entry(uart, &uart_list, node) {
324 if (!uart->can_sleep) {
329 /* This UART can now safely sleep. */
330 omap_uart_allow_sleep(uart);
336 static void omap_uart_idle_init(struct omap_uart_state *uart)
341 omap_uart_smart_idle_enable(uart, 0);
343 if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) {
344 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
347 /* XXX These PRM accesses do not belong here */
348 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
349 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
352 wk_mask = OMAP3430_ST_UART1_MASK;
355 wk_mask = OMAP3430_ST_UART2_MASK;
358 wk_mask = OMAP3430_ST_UART3_MASK;
361 wk_mask = OMAP3630_ST_UART4_MASK;
364 uart->wk_mask = wk_mask;
365 } else if (cpu_is_omap24xx()) {
367 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
371 wk_mask = OMAP24XX_ST_UART1_MASK;
374 wk_mask = OMAP24XX_ST_UART2_MASK;
377 wk_en = OMAP24XX_PM_WKEN2;
378 wk_st = OMAP24XX_PM_WKST2;
379 wk_mask = OMAP24XX_ST_UART3_MASK;
382 uart->wk_mask = wk_mask;
383 if (cpu_is_omap2430()) {
384 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
385 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
386 } else if (cpu_is_omap2420()) {
387 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
388 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
398 static void omap_uart_block_sleep(struct omap_uart_state *uart)
400 /* Needed to enable UART clocks when built without CONFIG_PM */
401 omap_uart_enable_clocks(uart);
403 #endif /* CONFIG_PM */
405 #ifdef CONFIG_OMAP_MUX
406 static struct omap_device_pad default_uart1_pads[] __initdata = {
408 .name = "uart1_cts.uart1_cts",
409 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
412 .name = "uart1_rts.uart1_rts",
413 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
416 .name = "uart1_tx.uart1_tx",
417 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
420 .name = "uart1_rx.uart1_rx",
421 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
422 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
423 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
427 static struct omap_device_pad default_uart2_pads[] __initdata = {
429 .name = "uart2_cts.uart2_cts",
430 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
433 .name = "uart2_rts.uart2_rts",
434 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
437 .name = "uart2_tx.uart2_tx",
438 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
441 .name = "uart2_rx.uart2_rx",
442 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
443 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
444 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
448 static struct omap_device_pad default_uart3_pads[] __initdata = {
450 .name = "uart3_cts_rctx.uart3_cts_rctx",
451 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
454 .name = "uart3_rts_sd.uart3_rts_sd",
455 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
458 .name = "uart3_tx_irtx.uart3_tx_irtx",
459 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
462 .name = "uart3_rx_irrx.uart3_rx_irrx",
463 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
464 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
465 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
469 static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
471 .name = "gpmc_wait2.uart4_tx",
472 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
475 .name = "gpmc_wait3.uart4_rx",
476 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
477 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
478 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
482 static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
484 .name = "uart4_tx.uart4_tx",
485 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
488 .name = "uart4_rx.uart4_rx",
489 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
490 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
491 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
495 static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
499 bdata->pads = default_uart1_pads;
500 bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
503 bdata->pads = default_uart2_pads;
504 bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
507 bdata->pads = default_uart3_pads;
508 bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
511 if (cpu_is_omap44xx()) {
512 bdata->pads = default_omap4_uart4_pads;
514 ARRAY_SIZE(default_omap4_uart4_pads);
515 } else if (cpu_is_omap3630()) {
516 bdata->pads = default_omap36xx_uart4_pads;
518 ARRAY_SIZE(default_omap36xx_uart4_pads);
526 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
529 static int __init omap_serial_early_init(void)
534 char oh_name[MAX_UART_HWMOD_NAME_LEN];
535 struct omap_hwmod *oh;
536 struct omap_uart_state *uart;
538 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
540 oh = omap_hwmod_lookup(oh_name);
544 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
550 list_add_tail(&uart->node, &uart_list);
554 * NOTE: omap_hwmod_setup*() has not yet been called,
555 * so no hwmod functions will work yet.
559 * During UART early init, device need to be probed
560 * to determine SoC specific init before omap_device
561 * is ready. Therefore, don't allow idle here
563 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
568 core_initcall(omap_serial_early_init);
571 * omap_serial_init_port() - initialize single serial port
572 * @bdata: port specific board data pointer
574 * This function initialies serial driver for given port only.
575 * Platforms can call this function instead of omap_serial_init()
576 * if they don't plan to use all available UARTs as serial ports.
578 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
579 * use only one of the two.
581 void __init omap_serial_init_port(struct omap_board_data *bdata)
583 struct omap_uart_state *uart;
584 struct omap_hwmod *oh;
585 struct platform_device *pdev;
589 struct omap_uart_port_info omap_up;
593 if (WARN_ON(bdata->id < 0))
595 if (WARN_ON(bdata->id >= num_uarts))
598 list_for_each_entry(uart, &uart_list, node)
599 if (bdata->id == uart->num)
603 uart->dma_enabled = 0;
606 omap_up.dma_enabled = uart->dma_enabled;
607 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
608 omap_up.mapbase = oh->slaves[0]->addr->pa_start;
609 omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
610 omap_up.flags = UPF_BOOT_AUTOCONF;
613 pdata_size = sizeof(struct omap_uart_port_info);
618 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
620 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
623 omap_device_disable_idle_on_suspend(pdev);
624 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
627 uart->mapbase = oh->slaves[0]->addr->pa_start;
628 uart->membase = omap_hwmod_get_mpu_rt_va(oh);
633 console_lock(); /* in case the earlycon is on the UART */
636 * Because of early UART probing, UART did not get idled
637 * on init. Now that omap_device is ready, ensure full idle
638 * before doing omap_device_enable().
640 omap_hwmod_idle(uart->oh);
642 omap_device_enable(uart->pdev);
643 omap_uart_idle_init(uart);
644 omap_uart_reset(uart);
645 omap_hwmod_enable_wakeup(uart->oh);
646 omap_device_idle(uart->pdev);
648 omap_uart_block_sleep(uart);
651 if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads) ||
652 (pdata->wk_en && pdata->wk_mask))
653 device_init_wakeup(&pdev->dev, true);
655 /* Enable the MDR1 errata for OMAP3 */
656 if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx()))
657 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
661 * omap_serial_init() - initialize all supported serial ports
663 * Initializes all available UARTs as serial ports. Platforms
664 * can call this function when they want to have default behaviour
665 * for serial ports (e.g initialize them all as serial ports).
667 void __init omap_serial_init(void)
669 struct omap_uart_state *uart;
670 struct omap_board_data bdata;
672 list_for_each_entry(uart, &uart_list, node) {
673 bdata.id = uart->num;
678 if (cpu_is_omap44xx() || cpu_is_omap34xx())
679 omap_serial_fill_default_pads(&bdata);
681 omap_serial_init_port(&bdata);