2 * linux/arch/arm/mach-omap2/timer-gp.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
39 #include <asm/mach/time.h>
40 #include <plat/dmtimer.h>
41 #include <asm/localtimer.h>
42 #include <asm/sched_clock.h>
43 #include <plat/common.h>
44 #include <plat/omap_hwmod.h>
48 /* Parent clocks, eventually these will come from the clock framework */
50 #define OMAP2_MPU_SOURCE "sys_ck"
51 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
52 #define OMAP4_MPU_SOURCE "sys_clkin_ck"
53 #define OMAP2_32K_SOURCE "func_32k_ck"
54 #define OMAP3_32K_SOURCE "omap_32k_fck"
55 #define OMAP4_32K_SOURCE "sys_32k_ck"
57 #ifdef CONFIG_OMAP_32K_TIMER
58 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
59 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
60 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
61 #define OMAP3_SECURE_TIMER 12
63 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
64 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
65 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
66 #define OMAP3_SECURE_TIMER 1
69 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
70 #define MAX_GPTIMER_ID 12
74 static struct omap_dm_timer clkev;
75 static struct clock_event_device clockevent_gpt;
76 static u8 __initdata gptimer_id = 1;
77 static u8 __initdata inited;
79 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
81 struct clock_event_device *evt = &clockevent_gpt;
83 __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
85 evt->event_handler(evt);
89 static struct irqaction omap2_gp_timer_irq = {
91 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
92 .handler = omap2_gp_timer_interrupt,
95 static int omap2_gp_timer_set_next_event(unsigned long cycles,
96 struct clock_event_device *evt)
98 __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
99 0xffffffff - cycles, 1);
104 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
105 struct clock_event_device *evt)
109 __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
112 case CLOCK_EVT_MODE_PERIODIC:
113 period = clkev.rate / HZ;
115 /* Looks like we need to first set the load value separately */
116 __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
117 0xffffffff - period, 1);
118 __omap_dm_timer_load_start(clkev.io_base,
119 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
120 0xffffffff - period, 1);
122 case CLOCK_EVT_MODE_ONESHOT:
124 case CLOCK_EVT_MODE_UNUSED:
125 case CLOCK_EVT_MODE_SHUTDOWN:
126 case CLOCK_EVT_MODE_RESUME:
131 static struct clock_event_device clockevent_gpt = {
133 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
135 .set_next_event = omap2_gp_timer_set_next_event,
136 .set_mode = omap2_gp_timer_set_mode,
140 * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
141 * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
143 * Define the GPTIMER that the system should use for the tick timer.
144 * Meant to be called from board-*.c files in the event that GPTIMER1, the
145 * default, is unsuitable. Returns -EINVAL on error or 0 on success.
147 int __init omap2_gp_clockevent_set_gptimer(u8 id)
149 if (id < 1 || id > MAX_GPTIMER_ID)
159 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
161 const char *fck_source)
163 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
164 struct omap_hwmod *oh;
168 sprintf(name, "timer%d", gptimer_id);
169 omap_hwmod_setup_one(name);
170 oh = omap_hwmod_lookup(name);
174 timer->irq = oh->mpu_irqs[0].irq;
175 timer->phys_base = oh->slaves[0]->addr->pa_start;
176 size = oh->slaves[0]->addr->pa_end - timer->phys_base;
178 /* Static mapping, never released */
179 timer->io_base = ioremap(timer->phys_base, size);
183 /* After the dmtimer is using hwmod these clocks won't be needed */
184 sprintf(name, "gpt%d_fck", gptimer_id);
185 timer->fclk = clk_get(NULL, name);
186 if (IS_ERR(timer->fclk))
189 sprintf(name, "gpt%d_ick", gptimer_id);
190 timer->iclk = clk_get(NULL, name);
191 if (IS_ERR(timer->iclk)) {
192 clk_put(timer->fclk);
196 omap_hwmod_enable(oh);
198 if (gptimer_id != 12) {
201 src = clk_get(NULL, fck_source);
205 res = __omap_dm_timer_set_source(timer->fclk, src);
206 if (IS_ERR_VALUE(res))
207 pr_warning("%s: timer%i cannot set source\n",
208 __func__, gptimer_id);
212 __omap_dm_timer_reset(timer->io_base, 1, 1);
215 timer->rate = clk_get_rate(timer->fclk);
222 static void __init omap2_gp_clockevent_init(int gptimer_id,
223 const char *fck_source)
229 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
232 omap2_gp_timer_irq.dev_id = (void *)&clkev;
233 setup_irq(clkev.irq, &omap2_gp_timer_irq);
235 __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
237 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
238 clockevent_gpt.shift);
239 clockevent_gpt.max_delta_ns =
240 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
241 clockevent_gpt.min_delta_ns =
242 clockevent_delta2ns(3, &clockevent_gpt);
243 /* Timer internal resynch latency. */
245 clockevent_gpt.cpumask = cpumask_of(0);
246 clockevents_register_device(&clockevent_gpt);
248 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
249 gptimer_id, clkev.rate);
252 /* Clocksource code */
254 #ifdef CONFIG_OMAP_32K_TIMER
256 * When 32k-timer is enabled, don't use GPTimer for clocksource
257 * instead, just leave default clocksource which uses the 32k
258 * sync counter. See clocksource setup in plat-omap/counter_32k.c
261 static void __init omap2_gp_clocksource_init(void)
263 omap_init_clocksource_32k();
270 static DEFINE_CLOCK_DATA(cd);
271 static struct omap_dm_timer *gpt_clocksource;
272 static cycle_t clocksource_read_cycles(struct clocksource *cs)
274 return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
277 static struct clocksource clocksource_gpt = {
280 .read = clocksource_read_cycles,
281 .mask = CLOCKSOURCE_MASK(32),
282 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
285 static void notrace dmtimer_update_sched_clock(void)
289 cyc = omap_dm_timer_read_counter(gpt_clocksource);
291 update_sched_clock(&cd, cyc, (u32)~0);
294 /* Setup free-running counter for clocksource */
295 static void __init omap2_gp_clocksource_init(void)
297 static struct omap_dm_timer *gpt;
299 static char err1[] __initdata = KERN_ERR
300 "%s: failed to request dm-timer\n";
301 static char err2[] __initdata = KERN_ERR
302 "%s: can't register clocksource!\n";
304 gpt = omap_dm_timer_request();
306 printk(err1, clocksource_gpt.name);
307 gpt_clocksource = gpt;
309 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
310 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
312 omap_dm_timer_set_load_start(gpt, 1, 0);
314 init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
316 if (clocksource_register_hz(&clocksource_gpt, tick_rate))
317 printk(err2, clocksource_gpt.name);
321 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src) \
322 static void __init omap##name##_timer_init(void) \
324 omap_dm_timer_init(); \
325 omap2_gp_clockevent_init((clkev_nr), clkev_src); \
326 omap2_gp_clocksource_init(); \
329 #define OMAP_SYS_TIMER(name) \
330 struct sys_timer omap##name##_timer = { \
331 .init = omap##name##_timer_init, \
334 #ifdef CONFIG_ARCH_OMAP2
335 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE)
339 #ifdef CONFIG_ARCH_OMAP3
340 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE)
342 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE)
343 OMAP_SYS_TIMER(3_secure)
346 #ifdef CONFIG_ARCH_OMAP4
347 static void __init omap4_timer_init(void)
349 #ifdef CONFIG_LOCAL_TIMERS
350 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
353 omap_dm_timer_init();
354 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
355 omap2_gp_clocksource_init();