2 * Entry of the second core for CSR Marco dual-core SMP SoCs
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/linkage.h>
10 #include <linux/init.h>
15 * Cold boot and hardware reset show different behaviour,
16 * system will be always panic if we warm-reset the board
17 * Here we invalidate L1 of CPU1 to make sure there isn't
18 * uninitialized data written into memory later
20 ENTRY(v7_invalidate_l1)
22 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
23 mcr p15, 2, r0, c0, c0, 0
24 mrc p15, 1, r0, c0, c0, 0
27 and r2, r1, r0, lsr #13
31 and r3, r1, r0, lsr #3 @ NumWays - 1
32 add r2, r2, #1 @ NumSets
35 add r0, r0, #4 @ SetShift
38 add r4, r3, #1 @ NumWays
39 1: sub r2, r2, #1 @ NumSets--
40 mov r3, r4 @ Temp = NumWays
41 2: subs r3, r3, #1 @ Temp--
44 orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
45 mcr p15, 0, r5, c7, c6, 2
52 ENDPROC(v7_invalidate_l1)
55 * SIRFSOC specific entry point for secondary CPUs. This provides
56 * a "holding pen" into which all secondary cores are held until we're
57 * ready for them to initialise.
59 ENTRY(sirfsoc_secondary_startup)
61 mrc p15, 0, r0, c0, c0, 5
72 * we've been released from the holding pen: secondary_stack
73 * should now contain the SVC stack for this core
76 ENDPROC(sirfsoc_secondary_startup)