2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <linux/sysdev.h>
25 #include <asm/mach/map.h>
26 #include <mach/hardware.h>
27 #include <mach/gpio.h>
28 #include <mach/pxa3xx-regs.h>
29 #include <mach/reset.h>
30 #include <mach/ohci.h>
33 #include <mach/regs-intc.h>
34 #include <mach/smemc.h>
41 #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
42 #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
44 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
45 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
46 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
47 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
48 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
49 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
50 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
51 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
52 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
53 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
54 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
55 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
56 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
57 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
58 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
59 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
61 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
62 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
63 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
64 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
65 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
67 static struct clk_lookup pxa3xx_clkregs[] = {
68 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
69 /* Power I2C clock is always on */
70 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
71 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
72 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
73 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
74 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
75 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
76 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
77 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
78 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
79 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
80 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
81 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
82 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
83 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
84 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
85 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
86 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
87 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
88 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
89 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
90 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
91 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
96 #define ISRAM_START 0x5c000000
97 #define ISRAM_SIZE SZ_256K
99 static void __iomem *sram;
100 static unsigned long wakeup_src;
103 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
104 * memory controller has to be reinitialised, so we place some code
105 * in the SRAM to perform this function.
107 * We disable FIQs across the standby - otherwise, we might receive a
108 * FIQ while the SDRAM is unavailable.
110 static void pxa3xx_cpu_standby(unsigned int pwrmode)
112 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
113 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
115 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
116 pm_enter_standby_end - pm_enter_standby_start);
120 AD2D0ER = wakeup_src;
134 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
135 * PXA3xx development kits assumes that the resuming process continues
136 * with the address stored within the first 4 bytes of SDRAM. The PSPR
137 * register is used privately by BootROM and OBM, and _must_ be set to
138 * 0x5c014000 for the moment.
140 static void pxa3xx_cpu_pm_suspend(void)
142 volatile unsigned long *p = (volatile void *)0xc0000000;
143 unsigned long saved_data = *p;
145 extern void pxa3xx_cpu_suspend(void);
146 extern void pxa3xx_cpu_resume(void);
148 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
149 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
150 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
152 /* clear and setup wakeup source */
158 PCFR |= (1u << 13); /* L1_DIS */
159 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
163 /* overwrite with the resume address */
164 *p = virt_to_phys(pxa3xx_cpu_resume);
166 pxa3xx_cpu_suspend();
173 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
176 * Don't sleep if no wakeup sources are defined
178 if (wakeup_src == 0) {
179 printk(KERN_ERR "Not suspending: no wakeup sources\n");
184 case PM_SUSPEND_STANDBY:
185 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
189 pxa3xx_cpu_pm_suspend();
194 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
196 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
199 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
200 .valid = pxa3xx_cpu_pm_valid,
201 .enter = pxa3xx_cpu_pm_enter,
204 static void __init pxa3xx_init_pm(void)
206 sram = ioremap(ISRAM_START, ISRAM_SIZE);
208 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
213 * Since we copy wakeup code into the SRAM, we need to ensure
214 * that it is preserved over the low power modes. Note: bit 8
215 * is undocumented in the developer manual, but must be set.
217 AD1R |= ADXR_L2 | ADXR_R0;
218 AD2R |= ADXR_L2 | ADXR_R0;
219 AD3R |= ADXR_L2 | ADXR_R0;
222 * Clear the resume enable registers.
229 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
232 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
234 unsigned long flags, mask = 0;
238 mask = ADXER_MFP_WSSP3;
251 mask = ADXER_MFP_WAC97;
257 mask = ADXER_MFP_WSSP2;
260 mask = ADXER_MFP_WI2C;
263 mask = ADXER_MFP_WUART3;
266 mask = ADXER_MFP_WUART2;
269 mask = ADXER_MFP_WUART1;
272 mask = ADXER_MFP_WMMC1;
275 mask = ADXER_MFP_WSSP1;
281 mask = ADXER_MFP_WSSP4;
290 mask = ADXER_MFP_WMMC2;
293 mask = ADXER_MFP_WFLASH;
299 mask = ADXER_WEXTWAKE0;
302 mask = ADXER_WEXTWAKE1;
305 mask = ADXER_MFP_GEN12;
311 local_irq_save(flags);
316 local_irq_restore(flags);
321 static inline void pxa3xx_init_pm(void) {}
322 #define pxa3xx_set_wake NULL
325 static void pxa_ack_ext_wakeup(struct irq_data *d)
327 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
330 static void pxa_mask_ext_wakeup(struct irq_data *d)
332 ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f));
333 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
336 static void pxa_unmask_ext_wakeup(struct irq_data *d)
338 ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f);
339 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
342 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
344 if (flow_type & IRQ_TYPE_EDGE_RISING)
345 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
347 if (flow_type & IRQ_TYPE_EDGE_FALLING)
348 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
353 static struct irq_chip pxa_ext_wakeup_chip = {
355 .irq_ack = pxa_ack_ext_wakeup,
356 .irq_mask = pxa_mask_ext_wakeup,
357 .irq_unmask = pxa_unmask_ext_wakeup,
358 .irq_set_type = pxa_set_ext_wakeup_type,
361 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
365 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
366 set_irq_chip(irq, &pxa_ext_wakeup_chip);
367 set_irq_handler(irq, handle_edge_irq);
368 set_irq_flags(irq, IRQF_VALID);
371 pxa_ext_wakeup_chip.irq_set_wake = fn;
374 void __init pxa3xx_init_irq(void)
376 /* enable CP6 access */
378 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
380 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
382 pxa_init_irq(56, pxa3xx_set_wake);
383 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
384 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
387 static struct map_desc pxa3xx_io_desc[] __initdata = {
389 .virtual = SMEMC_VIRT,
390 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
391 .length = 0x00200000,
396 void __init pxa3xx_map_io(void)
399 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
400 pxa3xx_get_clk_frequency_khz(1);
404 * device registration specific to PXA3xx.
407 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
409 pxa_register_device(&pxa3xx_device_i2c_power, info);
412 static struct platform_device *devices[] __initdata = {
416 &pxa_device_asoc_ssp1,
417 &pxa_device_asoc_ssp2,
418 &pxa_device_asoc_ssp3,
419 &pxa_device_asoc_ssp4,
420 &pxa_device_asoc_platform,
431 static struct sys_device pxa3xx_sysdev[] = {
433 .cls = &pxa_irq_sysclass,
435 .cls = &pxa3xx_mfp_sysclass,
437 .cls = &pxa_gpio_sysclass,
439 .cls = &pxa3xx_clock_sysclass,
443 static int __init pxa3xx_init(void)
447 if (cpu_is_pxa3xx()) {
452 * clear RDH bit every time after reset
454 * Note: the last 3 bits DxS are write-1-to-clear so carefully
455 * preserve them here in case they will be referenced later
457 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
459 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
461 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
466 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
467 ret = sysdev_register(&pxa3xx_sysdev[i]);
469 pr_err("failed to register sysdev[%d]\n", i);
472 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
478 postcore_initcall(pxa3xx_init);