2 defines of FPGA chip ICE65L08's register
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8 #define SPI_FPGA_INT_PIN RK2818_PIN_PA4
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9 #define SPI_DPRAM_BUSY_PIN RK2818_PIN_PA2
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10 #define SPI_FPGA_STANDBY_PIN RK2818_PIN_PH7
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12 #define SPI_FPGA_TEST_DEBUG 0
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13 #if SPI_FPGA_TEST_DEBUG
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14 #define SPI_FPGA_TEST_DEBUG_PIN RK2818_PIN_PE0
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15 extern int spi_test_wrong_handle(void);
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18 struct uart_icount {
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33 struct workqueue_struct *spi_uart_workqueue;
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34 struct work_struct spi_uart_work;
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35 struct timer_list uart_timer;
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36 struct tty_struct *tty;
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38 struct mutex open_lock;
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39 struct task_struct *in_spi_uart_irq;
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40 struct circ_buf xmit;
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41 struct uart_icount icount;
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42 spinlock_t write_lock;
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43 spinlock_t irq_lock;
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45 unsigned int opened;
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46 unsigned int regs_offset;
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47 unsigned int uartclk;
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49 unsigned int read_status_mask;
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50 unsigned int ignore_status_mask;
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51 unsigned char x_char;
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59 struct workqueue_struct *spi_gpio_workqueue;
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60 struct work_struct spi_gpio_work;
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61 struct timer_list gpio_timer;
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67 struct workqueue_struct *spi_i2c_workqueue;
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68 struct work_struct spi_i2c_work;
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69 struct timer_list i2c_timer;
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70 struct i2c_adapter *adapter;
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71 struct i2c_client *client;
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72 spinlock_t i2c_lock ;
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73 unsigned char interrupt;
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74 unsigned char i2c_data_width[2];
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75 unsigned int speed[2];
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80 struct workqueue_struct *spi_dpram_workqueue;
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81 struct work_struct spi_dpram_work;
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82 struct workqueue_struct *spi_dpram_busy_workqueue;
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83 struct work_struct spi_dpram_busy_work;
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84 struct timer_list dpram_timer;
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87 unsigned int rec_len;
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88 unsigned int send_len;
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89 unsigned int max_rec_len;
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90 unsigned int max_send_len;
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91 volatile int apwrite_en;
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92 unsigned short int dpram_addr;
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93 struct semaphore rec_sem;
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94 struct semaphore send_sem;
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95 wait_queue_head_t recq, sendq;
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96 struct miscdevice miscdev;
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98 int (*write_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len);
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99 int (*read_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len);
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100 int (*write_ptr)(struct spi_dpram *, unsigned short int addr, unsigned int size);
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101 int (*read_ptr)(struct spi_dpram *, unsigned short int addr);
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102 int (*write_mailbox)(struct spi_dpram *, unsigned int mailbox);
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103 int (*read_mailbox)(struct spi_dpram *);
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107 struct spi_fpga_port {
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109 struct spi_device *spi;
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110 struct mutex spi_lock;
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111 struct workqueue_struct *fpga_irq_workqueue;
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112 struct work_struct fpga_irq_work;
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113 struct timer_list fpga_timer;
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115 #ifdef CONFIG_SPI_UART
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116 struct spi_uart uart;
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119 #ifdef CONFIG_SPI_GPIO
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120 struct spi_gpio gpio;
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123 #ifdef CONFIG_SPI_I2C
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124 struct spi_i2c i2c;
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127 #ifdef CONFIG_SPI_DPRAM
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128 struct spi_dpram dpram;
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135 #define ICE_CC196 1
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136 #define FPGA_TYPE ICE_CC196
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140 #define SEL_DPRAM 3
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141 #define READ_TOP_INT 4
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144 #define ICE_SEL_UART (SEL_UART<<6)
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145 #define ICE_SEL_GPIO (SEL_GPIO<<6)
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146 #define ICE_SEL_I2C (SEL_I2C<<6)
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147 #define ICE_SEL_DPRAM (SEL_DPRAM<<6)
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149 #define ICE_SEL_WRITE (~(1<<5))
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150 #define ICE_SEL_READ (1<<5)
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152 #define ICE_SEL_UART_CH(ch) ((ch&0x03)<<3)
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153 #define ICE_SEL_READ_INT_TYPE (3<<3)
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156 #define ICE_INT_TYPE_UART0 (~(1<<0))
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157 #define ICE_INT_TYPE_UART1 (~(1<<1))
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158 #define ICE_INT_TYPE_UART2 (~(1<<2))
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159 #define ICE_INT_TYPE_I2C2 (~(1<<3))
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160 #define ICE_INT_TYPE_I2C3 (~(1<<4))
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161 #define ICE_INT_TYPE_GPIO (~(1<<5))
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162 #define ICE_INT_TYPE_DPRAM (~(1<<6))
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164 #define ICE_INT_I2C_ACK (~(1<<0))
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165 #define ICE_INT_I2C_READ (~(1<<1))
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166 #define ICE_INT_I2C_WRITE (~(1<<2))
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169 #define ICE_RXFIFO_FULL (1<<8)
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170 #define ICE_RXFIFO_NOT_FULL (~(1<<8))
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171 #define ICE_RXFIFO_EMPTY (1<<9)
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172 #define ICE_RXFIFO_NOT_EMPTY (~(1<<9))
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173 #define ICE_TXFIFO_FULL (1<<10)
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174 #define ICE_TXFIFO_NOT_FULL (~(1<<10))
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175 #define ICE_TXFIFO_EMPTY (1<<11)
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176 #define ICE_TXFIFO_NOT_EMPTY (~(1<<11))
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180 #define ICE_SEL_GPIO0 (0X00<<3) //INT/GPIO0
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181 #define ICE_SEL_GPIO1 (0X02<<2) //GPIO1
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182 #define ICE_SEL_GPIO2 (0X03<<2)
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183 #define ICE_SEL_GPIO3 (0X04<<2)
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184 #define ICE_SEL_GPIO4 (0X05<<2)
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185 #define ICE_SEL_GPIO5 (0X06<<2)
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187 #define ICE_SEL_GPIO0_TYPE (0X00)
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188 #define ICE_SEL_GPIO0_DIR (0X01)
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189 #define ICE_SEL_GPIO0_DATA (0X02)
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190 #define ICE_SEL_GPIO0_INT_EN (0X03)
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191 #define ICE_SEL_GPIO0_INT_TRI (0X04)
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192 #define ICE_SEL_GPIO0_INT_STATE (0X05)
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194 #define ICE_SEL_GPIO_DIR (0X01)
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195 #define ICE_SEL_GPIO_DATA (0X02)
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199 typedef enum I2C_ch
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206 typedef enum eI2CReadMode
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212 typedef enum eI2RegType
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218 #define ICE_SEL_I2C_START (0<<0)
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219 #define ICE_SEL_I2C_STOP (1<<0)
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220 #define ICE_SEL_I2C_RESTART (2<<0)
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221 #define ICE_SEL_I2C_TRANS (3<<0)
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222 #define ICE_SEL_I2C_SMASK (~(3<<0))
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223 #define ICE_SEL_I2C_CH2 (0<<2)
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224 #define ICE_SEL_I2C_CH3 (1<<2)
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225 #define ICE_SEL_I2C_DEFMODE (0<<3)
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226 #define ICE_SEL_I2C_FIFO (1<<3)
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227 #define ICE_SEL_I2C_SPEED (2<<3)
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228 #define ICE_SEL_I2C_INT (3<<3)
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229 #define ICE_SEL_I2C_MMASK (~(3<<3))
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231 #define ICE_I2C_SLAVE_WRITE (0<<0)
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232 #define ICE_I2C_SLAVE_READ (1<<0)
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236 #define ICE_SEL_I2C_W8BIT (0<<2)
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237 #define ICE_SEL_I2C_W16BIT (1<<2)
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238 #define ICE_SEL_I2C_DWIDTH (2<<2)
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240 #define ICE_I2C_AD_ACK (~(1<<0))
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241 #define ICE_I2C_WRITE_ACK (~(1<<1))
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242 #define ICE_I2C_READ_ACK (~(1<<2))
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244 #define ICE_SEL_I2C_CH2_8BIT (0<<2)
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245 #define ICE_SEL_I2C_CH2_16BIT (1<<2)
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246 #define ICE_SEL_I2C_CH2_MIX (2<<2)
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248 #define ICE_SEL_I2C_CH3_8BIT (4<<2)
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249 #define ICE_SEL_I2C_CH3_16BIT (5<<2)
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250 #define ICE_SEL_I2C_CH3_MIX (6<<2)
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251 #define ICE_SEL_I2C_RD_A (7<<2)
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252 #define ICE_SEL_I2C_MASK (7<<2)
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253 #define ICE_SEL_I2C_ACK3 (1<<1)
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254 #define ICE_SEL_I2C_ACK2 (0<<1)
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256 #define INT_I2C_WRITE_ACK (2)
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257 #define INT_I2C_WRITE_NACK (3)
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258 #define INT_I2C_READ_ACK (4)
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259 #define INT_I2C_READ_NACK (5)
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260 #define INT_I2C_WRITE_MASK (~(1<<1))
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261 #define INT_I2C_READ_MASK (~(1<<2))
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263 #define ICE_SET_10K_I2C_SPEED (0x01)
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264 #define ICE_SET_100K_I2C_SPEED (0x02)
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265 #define ICE_SET_200K_I2C_SPEED (0x04)
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266 #define ICE_SET_300K_I2C_SPEED (0x08)
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267 #define ICE_SET_400K_I2C_SPEED (0x10)
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271 #define ICE_SEL_DPRAM_NOMAL (~(1<<5))
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272 #define ICE_SEL_DPRAM_SEM (1<<5)
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273 #define ICE_SEL_DPRAM_READ (~(1<<4))
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274 #define ICE_SEL_DPRAM_WRITE (1<<4)
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275 #define ICE_SEL_DPRAM_BL1 (0)
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276 #define ICE_SEL_DPRAM_BL32 (1)
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277 #define ICE_SEL_DPRAM_BL64 (2)
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278 #define ICE_SEL_DPRAM_BL128 (3)
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279 #define ICE_SEL_DPRAM_FULL (4)
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281 #define ICE_SEL_SEM_WRITE (0x7F)
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282 #define ICE_SEL_SEM_READ (0xBF)
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283 #define ICE_SEL_SEM_WRRD (0x3F)
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285 typedef void (*pSpiFunc)(void); //¶¨Ò庯ÊýÖ¸Õë, ÓÃÓÚµ÷Óþø¶ÔµØÖ·
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286 typedef void (*pSpiFuncIntr)(int,void *);
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289 pSpiFuncIntr gpio_vector;
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294 typedef enum eSpiGpioTypeSel
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296 SPI_GPIO0_IS_GPIO = 0,
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298 }eSpiGpioTypeSel_t;
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302 typedef enum eSpiGpioPinInt
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304 SPI_GPIO_INT_DISABLE = 0,
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305 SPI_GPIO_INT_ENABLE,
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309 typedef enum eSpiGpioIntType
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311 SPI_GPIO_EDGE_FALLING = 0,
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312 SPI_GPIO_EDGE_RISING,
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313 }eSpiGpioIntType_t;
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315 typedef enum eSpiGpioPinDirection
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320 }eSpiGpioPinDirection_t;
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323 typedef enum eSpiGpioPinLevel
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327 SPI_GPIO_LEVEL_ERR,
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328 }eSpiGpioPinLevel_t;
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330 #if (FPGA_TYPE == ICE_CC72)
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331 typedef enum eSpiGpioPinNum
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333 SPI_GPIO_P0_00 = 0, //GPIO0[0]
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349 SPI_GPIO_P2_09 = 15, //GPIO0[15],the last interrupt/gpio pin
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351 SPI_GPIO_P3_00 = 16, //GPIO1[0]
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361 SPI_GPIO_P0_06 = 26,
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369 #elif (FPGA_TYPE == ICE_CC196)
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371 typedef enum eSpiGpioPinNum
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374 SPI_GPIO_P6_00 = 0, //HS_DET input
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378 SPI_GPIO_P6_04, //CM3605_POUT_L_INT input
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380 SPI_GPIO_P6_06, //CHG_OK input
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381 SPI_GPIO_P6_07, //HP_HOOK input
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384 SPI_GPIO_P6_10, //DEFSEL input
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385 SPI_GPIO_P6_11, //FLASH_WP_INT input
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386 SPI_GPIO_P6_12, //LOW_BATT_INT input
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387 SPI_GPIO_P6_13, //DC_DET input
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389 SPI_GPIO_P3_09 = 15,
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392 SPI_GPIO_P1_00 = 16, //LCD_ON output
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393 SPI_GPIO_P1_01, //LCD_PWR_CTRL output
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394 SPI_GPIO_P1_02, //SD_POW_ON output
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395 SPI_GPIO_P1_03, //WL_RST_N/WIFI_EN output
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396 SPI_GPIO_P1_04, //HARDO,input
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397 SPI_GPIO_P1_05, //SENSOR_PWDN output
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398 SPI_GPIO_P1_06, //BT_PWR_EN output
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399 SPI_GPIO_P1_07, //BT_RST output
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400 SPI_GPIO_P1_08, //BT_WAKE_B output
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401 SPI_GPIO_P1_09, //LCD_DISP_ON output
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402 SPI_GPIO_P1_10, //WM_PWR_EN output
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403 SPI_GPIO_P1_11, //HARD1,input
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404 SPI_GPIO_P1_12, //VIB_MOTO output
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405 SPI_GPIO_P1_13, //KEYLED_EN output
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406 SPI_GPIO_P1_14, //CAM_RST output
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407 SPI_GPIO_P1_15 = 31, //WL_WAKE_B output
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410 SPI_GPIO_P2_00 = 32, //Y+YD input
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411 SPI_GPIO_P2_01, //Y-YU input
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412 SPI_GPIO_P2_02, //AP_TD_UNDIFED input
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413 SPI_GPIO_P2_03, //AP_PW_EN_TD output
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414 SPI_GPIO_P2_04, //AP_RESET_TD output
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415 SPI_GPIO_P2_05, //AP_SHUTDOWN_TD_PMU output
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416 SPI_GPIO_P2_06, //AP_RESET_CMMB output
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417 SPI_GPIO_P2_07, //AP_CHECK_TD_STATUS input
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418 SPI_GPIO_P2_08, //CHARGE_CURRENT_SEL output
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419 SPI_GPIO_P2_09, //AP_PWD_CMMB output
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420 SPI_GPIO_P2_10, //X-XL input
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421 SPI_GPIO_P2_11, //X+XR input
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422 SPI_GPIO_P2_12, //LCD_RESET output
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423 SPI_GPIO_P2_13, //USB_PWR_EN output
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424 SPI_GPIO_P2_14, //WL_HOST_WAKE_B output
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425 SPI_GPIO_P2_15 = 47, //TOUCH_SCREEN_RST output
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428 SPI_GPIO_P0_00 = 48, //
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437 SPI_GPIO_P0_09, //FPGAС°å¸ÃÒý½ÅδÒý³ö C5
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443 SPI_GPIO_P0_15 = 63,
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446 SPI_GPIO_P4_00 = 64,
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452 SPI_GPIO_P4_06, //CHARGER_INT_END input
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453 SPI_GPIO_P4_07, //CM3605_PWD output
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461 SPI_GPIO_P3_07 = 79,
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464 SPI_GPIO_P4_08 = 80, //CM3605_PS_SHUTDOWN
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465 SPI_GPIO_P0_TXD2, //temp
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472 typedef enum eSpiGpioPinIntIsr
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474 SPI_GPIO_IS_INT = 0,
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476 }eSpiGpioPinIntIsr_t;
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478 extern struct spi_fpga_port *pFpgaPort;
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479 extern unsigned int spi_in(struct spi_fpga_port *port, int reg, int type);
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480 extern void spi_out(struct spi_fpga_port *port, int reg, int value, int type);
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482 #if defined(CONFIG_SPI_UART)
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483 extern void spi_uart_handle_irq(struct spi_device *spi);
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484 extern int spi_uart_register(struct spi_fpga_port *port);
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485 extern int spi_uart_unregister(struct spi_fpga_port *port);
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487 #if defined(CONFIG_SPI_GPIO)
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488 extern int spi_gpio_int_sel(eSpiGpioPinNum_t PinNum,eSpiGpioTypeSel_t type);
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489 extern int spi_gpio_set_pindirection(eSpiGpioPinNum_t PinNum,eSpiGpioPinDirection_t direction);
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490 extern int spi_gpio_set_pinlevel(eSpiGpioPinNum_t PinNum, eSpiGpioPinLevel_t PinLevel);
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491 extern eSpiGpioPinLevel_t spi_gpio_get_pinlevel(eSpiGpioPinNum_t PinNum);
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492 extern int spi_gpio_enable_int(eSpiGpioPinNum_t PinNum);
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493 extern int spi_gpio_disable_int(eSpiGpioPinNum_t PinNum);
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494 extern int spi_gpio_set_int_trigger(eSpiGpioPinNum_t PinNum,eSpiGpioIntType_t IntType);
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495 extern int spi_gpio_read_iir(void);
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496 extern int spi_request_gpio_irq(eSpiGpioPinNum_t PinNum, pSpiFunc Routine, eSpiGpioIntType_t IntType,void *dev_id);
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497 extern int spi_free_gpio_irq(eSpiGpioPinNum_t PinNum);
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498 extern int spi_gpio_handle_irq(struct spi_device *spi);
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499 extern int spi_gpio_init(void);
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500 extern int spi_gpio_register(struct spi_fpga_port *port);
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501 extern int spi_gpio_unregister(struct spi_fpga_port *port);
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503 #if defined(CONFIG_SPI_I2C)
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504 extern int spi_i2c_handle_irq(struct spi_fpga_port *port,unsigned char channel);
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505 extern int spi_i2c_register(struct spi_fpga_port *port,int num);
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506 extern int spi_i2c_unregister(struct spi_fpga_port *port);
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508 #if defined(CONFIG_SPI_DPRAM)
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509 extern int spi_dpram_handle_irq(struct spi_device *spi);
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510 extern int spi_dpram_register(struct spi_fpga_port *port);
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511 extern int spi_dpram_unregister(struct spi_fpga_port *port);
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