arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33 #include <mach/pmu.h>
  34 #include <mach/sram.h>
  35 #include <mach/board.h>
  36 #include <mach/clock.h>
  37
  38
  39 /* Clock flags */
  40 /* bit 0 is free */
  41 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  42 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  43 #define IS_PD                   (1 << 2)        /* Power Domain */
  44
  45 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  46 #define pmu_readl(offset)       readl(RK29_PMU_BASE + offset)
  47
  48 #define MHZ                     (1000*1000)
  49 #define KHZ                     1000
  50
  51 struct clk {
  52         struct list_head        node;
  53         const char              *name;
  54         struct clk              *parent;
  55         struct list_head        children;
  56         struct list_head        sibling;        /* node for children */
  57         unsigned long           rate;
  58         u32                     flags;
  59         int                     (*mode)(struct clk *clk, int on);
  60         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  61         int                     (*set_rate)(struct clk *, unsigned long);
  62         long                    (*round_rate)(struct clk *, unsigned long);
  63         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
  64         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
  65         s16                     usecount;
  66         u16                     notifier_count;
  67         u8                      gate_idx;
  68         u8                      pll_idx;
  69         u8                      clksel_con;
  70         u8                      clksel_mask;
  71         u8                      clksel_shift;
  72         u8                      clksel_maxdiv;
  73         u8                      clksel_parent_mask;
  74         u8                      clksel_parent_shift;
  75         struct clk              **parents;
  76 };
  77
  78 static void clk_notify(struct clk *clk, unsigned long msg,
  79                        unsigned long old_rate, unsigned long new_rate);
  80 static int clk_enable_nolock(struct clk *clk);
  81 static void clk_disable_nolock(struct clk *clk);
  82 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
  83 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
  84 static void __clk_reparent(struct clk *child, struct clk *parent);
  85 static void __propagate_rate(struct clk *tclk);
  86 static struct clk codec_pll_clk;
  87 static struct clk general_pll_clk;
  88 static bool has_xin27m = true;
  89
  90 static unsigned long clksel_recalc_div(struct clk *clk)
  91 {
  92         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
  93         unsigned long rate = clk->parent->rate / div;
  94         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
  95         return rate;
  96 }
  97
  98 static unsigned long clksel_recalc_shift(struct clk *clk)
  99 {
 100         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
 101         unsigned long rate = clk->parent->rate >> shift;
 102         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 103         return rate;
 104 }
 105
 106 static unsigned long clksel_recalc_frac(struct clk *clk)
 107 {
 108         unsigned long rate;
 109         u64 rate64;
 110         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 111         if (r == 0) // FPGA ?
 112                 return clk->parent->rate;
 113         numerator = r >> 16;
 114         denominator = r & 0xFFFF;
 115         rate64 = (u64)clk->parent->rate * numerator;
 116         do_div(rate64, denominator);
 117         rate = rate64;
 118         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 119         return rate;
 120 }
 121
 122 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 123 {
 124         u32 div;
 125
 126         for (div = 0; div <= clk->clksel_mask; div++) {
 127                 u32 new_rate = clk->parent->rate / (div + 1);
 128                 if (new_rate <= rate) {
 129                         u32 v = cru_readl(clk->clksel_con);
 130                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 131                         v |= div << clk->clksel_shift;
 132                         cru_writel(v, clk->clksel_con);
 133                         clk->rate = new_rate;
 134                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 135                         return 0;
 136                 }
 137         }
 138
 139         return -ENOENT;
 140 }
 141
 142 static long clksel_round_rate_div_by_parent(struct clk *clk, unsigned long rate, struct clk *parent, unsigned long max_rate)
 143 {
 144         u32 div;
 145         unsigned long prev = ULONG_MAX, actual;
 146
 147         if (max_rate < rate)
 148                 max_rate = rate;
 149         for (div = 0; div <= clk->clksel_mask; div++) {
 150                 actual = parent->rate / (div + 1);
 151                 if (actual > max_rate)
 152                         continue;
 153                 if (actual > rate)
 154                         prev = actual;
 155                 if (actual && actual <= rate) {
 156                         if ((prev - rate) <= (rate - actual)) {
 157                                 actual = prev;
 158                                 div--;
 159                         }
 160                         break;
 161                 }
 162         }
 163         if (div > clk->clksel_mask)
 164                 div = clk->clksel_mask;
 165         pr_debug("clock %s, target rate %ld, max rate %ld, rounded rate %ld (div %d)\n", clk->name, rate, max_rate, actual, div + 1);
 166
 167         return actual;
 168 }
 169
 170 #if 0
 171 static long clksel_round_rate_div(struct clk *clk, unsigned long rate)
 172 {
 173         return clksel_round_rate_div_by_parent(clk, rate, clk->parent, ULONG_MAX);
 174 }
 175 #endif
 176
 177 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 178 {
 179         u32 shift;
 180
 181         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 182                 u32 new_rate = clk->parent->rate >> shift;
 183                 if (new_rate <= rate) {
 184                         u32 v = cru_readl(clk->clksel_con);
 185                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 186                         v |= shift << clk->clksel_shift;
 187                         cru_writel(v, clk->clksel_con);
 188                         clk->rate = new_rate;
 189                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 190                         return 0;
 191                 }
 192         }
 193
 194         return -ENOENT;
 195 }
 196
 197 static struct clk* clksel_get_parent(struct clk *clk)
 198 {
 199         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 200 }
 201
 202 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 203 {
 204         struct clk **p = clk->parents;
 205         u32 i;
 206
 207         if (unlikely(!p))
 208                 return -EINVAL;
 209         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 210                 u32 v;
 211                 if (*p != parent)
 212                         continue;
 213                 v = cru_readl(clk->clksel_con);
 214                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 215                 v |= (i << clk->clksel_parent_shift);
 216                 cru_writel(v, clk->clksel_con);
 217                 return 0;
 218         }
 219         return -EINVAL;
 220 }
 221
 222 /* Work around CRU_CLKGATE3_CON bit21~20 bug */
 223 volatile u32 cru_clkgate3_con_mirror;
 224
 225 static int gate_mode(struct clk *clk, int on)
 226 {
 227         unsigned long flags;
 228         u32 reg;
 229         int idx = clk->gate_idx;
 230         u32 v;
 231
 232         if (idx >= CLK_GATE_MAX)
 233                 return -EINVAL;
 234
 235         reg = CRU_CLKGATE0_CON;
 236         reg += (idx >> 5) << 2;
 237         idx &= 0x1F;
 238
 239         /* ddr reconfig may change gate */
 240         local_irq_save(flags);
 241
 242         if (reg == CRU_CLKGATE3_CON)
 243                 v = cru_clkgate3_con_mirror;
 244         else
 245                 v = cru_readl(reg);
 246
 247         if (on)
 248                 v &= ~(1 << idx);       // clear bit
 249         else
 250                 v |= (1 << idx);        // set bit
 251
 252         if (reg == CRU_CLKGATE3_CON)
 253                 cru_clkgate3_con_mirror = v;
 254         cru_writel(v, reg);
 255
 256         local_irq_restore(flags);
 257         return 0;
 258 }
 259
 260 /* Work around CRU_SOFTRST0_CON bit29~27 bug */
 261 static volatile u32 cru_softrst0_con_mirror;
 262
 263 void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 264 {
 265         unsigned long flags;
 266         u32 reg = CRU_SOFTRST0_CON + ((idx >> 5) << 2);
 267         u32 mask = 1 << (idx & 31);
 268         u32 v;
 269
 270         if (idx >= SOFT_RST_MAX)
 271                 return;
 272
 273         local_irq_save(flags);
 274
 275         if (reg == CRU_SOFTRST0_CON)
 276                 v = cru_softrst0_con_mirror;
 277         else
 278                 v = cru_readl(reg);
 279
 280         if (on)
 281                 v |= mask;
 282         else
 283                 v &= ~mask;
 284
 285         if (reg == CRU_SOFTRST0_CON)
 286                 cru_softrst0_con_mirror = v;
 287         cru_writel(v, reg);
 288
 289         local_irq_restore(flags);
 290 }
 291
 292 static struct clk xin24m = {
 293         .name           = "xin24m",
 294         .rate           = 24 * MHZ,
 295         .flags          = RATE_FIXED,
 296 };
 297
 298 static struct clk clk_12m = {
 299         .name           = "clk_12m",
 300         .rate           = 12 * MHZ,
 301         .parent         = &xin24m,
 302         .flags          = RATE_FIXED,
 303 };
 304
 305 static struct clk xin27m = {
 306         .name           = "xin27m",
 307         .rate           = 27 * MHZ,
 308         .flags          = RATE_FIXED,
 309 };
 310
 311 static struct clk otgphy0_clkin = {
 312         .name           = "otgphy0_clkin",
 313         .rate           = 480 * MHZ,
 314         .flags          = RATE_FIXED,
 315 };
 316
 317 static struct clk otgphy1_clkin = {
 318         .name           = "otgphy1_clkin",
 319         .rate           = 480 * MHZ,
 320         .flags          = RATE_FIXED,
 321 };
 322
 323
 324 static noinline void delay_500ns(void)
 325 {
 326         udelay(1);
 327 }
 328
 329 static noinline void delay_300us(void)
 330 {
 331         udelay(300);
 332 }
 333
 334 #define GENERAL_PLL_IDX     0
 335 #define CODEC_PLL_IDX      1
 336 #define ARM_PLL_IDX        2
 337 #define DDR_PLL_IDX        3
 338
 339 #define GRF_SOC_CON0       0xbc
 340 static void pll_wait_lock(int pll_idx)
 341 {
 342         u32 bit = 0x2000000u << pll_idx;
 343         int delay = 2400000;
 344         while (delay > 0) {
 345                 if (regfile_readl(GRF_SOC_CON0) & bit)
 346                         break;
 347                 delay--;
 348         }
 349         if (delay == 0) {
 350                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 351         }
 352 }
 353
 354 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 355 {
 356         unsigned long rate;
 357
 358         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 359                 u32 v = cru_readl(CRU_APLL_CON);
 360                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 361                 do_div(rate64, PLL_NR(v));
 362                 rate = rate64 >> PLL_NO_SHIFT(v);
 363                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 364         } else {
 365                 rate = clk->parent->rate;
 366                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 367         }
 368
 369         return rate;
 370 }
 371
 372 struct arm_pll_set {
 373         unsigned long rate;
 374         u32 apll_con;
 375         u32 clksel0_con;
 376         unsigned long lpj;
 377 };
 378
 379 #define CORE_ACLK_11    (0 << 5)
 380 #define CORE_ACLK_21    (1 << 5)
 381 #define CORE_ACLK_31    (2 << 5)
 382 #define CORE_ACLK_41    (3 << 5)
 383 #define CORE_ACLK_81    (4 << 5)
 384 #define CORE_ACLK_MASK  (7 << 5)
 385
 386 #define ACLK_HCLK_11    (0 << 8)
 387 #define ACLK_HCLK_21    (1 << 8)
 388 #define ACLK_HCLK_41    (2 << 8)
 389 #define ACLK_HCLK_MASK  (3 << 8)
 390
 391 #define ACLK_PCLK_11    (0 << 10)
 392 #define ACLK_PCLK_21    (1 << 10)
 393 #define ACLK_PCLK_41    (2 << 10)
 394 #define ACLK_PCLK_81    (3 << 10)
 395 #define ACLK_PCLK_MASK  (3 << 10)
 396
 397 #define LPJ_600MHZ      2998368ULL
 398 static unsigned long lpj_gpll;
 399
 400 #define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 401 { \
 402         .rate           = _mhz * MHZ, \
 403         .apll_con       = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 404         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 405         .lpj            = LPJ_600MHZ * _mhz / 600, \
 406 }
 407
 408 static const struct arm_pll_set arm_pll[] = {
 409         // rate = 24 * NF / (NR * NO)
 410         //      rate NR  NF NO adiv hdiv pdiv
 411         ARM_PLL(1200, 1, 50, 1, 21, 21, 81),
 412         ARM_PLL(1176, 2, 98, 1, 21, 21, 81),
 413         ARM_PLL(1104, 1, 46, 1, 21, 21, 81),
 414         ARM_PLL(1008, 1, 42, 1, 21, 21, 81),
 415         ARM_PLL( 912, 1, 38, 1, 21, 21, 81),
 416         ARM_PLL( 888, 2, 74, 1, 21, 21, 81),
 417         ARM_PLL( 816, 1, 34, 1, 21, 21, 81),
 418         ARM_PLL( 696, 1, 58, 2, 21, 21, 81),
 419         ARM_PLL( 624, 1, 52, 2, 21, 21, 81),
 420         ARM_PLL( 600, 1, 50, 2, 21, 21, 81),
 421         ARM_PLL( 504, 1, 42, 2, 21, 21, 81),
 422         ARM_PLL( 408, 1, 34, 2, 21, 21, 81),
 423         ARM_PLL( 300, 1, 50, 4, 21, 21, 41),
 424         ARM_PLL( 204, 1, 34, 4, 21, 21, 41),
 425         ARM_PLL( 102, 1, 34, 8, 21, 21, 41),
 426         // last item, pll power down.
 427         ARM_PLL(  24, 1, 64, 8, 21, 21, 41),
 428 };
 429
 430 #define CORE_PARENT_MASK        (3 << 23)
 431 #define CORE_PARENT_ARM_PLL     (0 << 23)
 432 #define CORE_PARENT_GENERAL_PLL (1 << 23)
 433
 434 static const struct arm_pll_set* arm_pll_clk_get_best_pll_set(unsigned long rate)
 435 {
 436         const struct arm_pll_set *ps, *pt;
 437
 438         /* find the arm_pll we want. */
 439         ps = pt = &arm_pll[0];
 440         while (1) {
 441                 if (pt->rate == rate) {
 442                         ps = pt;
 443                         break;
 444                 }
 445                 // we are sorted, and ps->rate > pt->rate.
 446                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 447                         ps = pt;
 448                 if (pt->rate < rate || pt->rate == 24 * MHZ)
 449                         break;
 450                 pt++;
 451         }
 452
 453         return ps;
 454 }
 455
 456 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 457 {
 458         unsigned long flags;
 459         const struct arm_pll_set *ps;
 460         u32 clksel0_con;
 461         bool aclk_limit = rate & 1;
 462
 463         rate &= ~1;
 464         ps = arm_pll_clk_get_best_pll_set(rate);
 465         clksel0_con = ps->clksel0_con;
 466
 467         if (aclk_limit) {
 468                 u32 aclk_div = clksel0_con & CORE_ACLK_MASK;
 469                 if (rate > 408 * MHZ && aclk_div < CORE_ACLK_41)
 470                         aclk_div = CORE_ACLK_41;
 471                 clksel0_con = (clksel0_con & ~CORE_ACLK_MASK) | aclk_div;
 472         }
 473
 474         if (ps->apll_con == cru_readl(CRU_APLL_CON)) {
 475                 cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | clksel0_con, CRU_CLKSEL0_CON);
 476                 return 0;
 477         }
 478
 479         local_irq_save(flags);
 480         /* make aclk safe & reparent to general pll */
 481         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_GENERAL_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 482         loops_per_jiffy = lpj_gpll;
 483
 484         /* enter slow mode */
 485         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 486
 487         /* power down */
 488         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 489         local_irq_restore(flags);
 490
 491         delay_500ns();
 492
 493         cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
 494
 495         delay_500ns();
 496
 497         /* power up */
 498         cru_writel(ps->apll_con, CRU_APLL_CON);
 499
 500         delay_300us();
 501         pll_wait_lock(ARM_PLL_IDX);
 502
 503         local_irq_save(flags);
 504         /* enter normal mode */
 505         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 506
 507         loops_per_jiffy = ps->lpj;
 508         /* reparent to arm pll & set aclk/hclk/pclk */
 509         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | clksel0_con, CRU_CLKSEL0_CON);
 510         local_irq_restore(flags);
 511
 512         return 0;
 513 }
 514
 515 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 516 {
 517         return arm_pll_clk_get_best_pll_set(rate)->rate;
 518 }
 519
 520 static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
 521
 522 static struct clk arm_pll_clk = {
 523         .name           = "arm_pll",
 524         .parent         = &xin24m,
 525         .recalc         = arm_pll_clk_recalc,
 526         .set_rate       = arm_pll_clk_set_rate,
 527         .round_rate     = arm_pll_clk_round_rate,
 528         .clksel_con     = CRU_MODE_CON,
 529         .clksel_parent_mask     = 1,
 530         .clksel_parent_shift    = 8,
 531         .parents        = arm_pll_parents,
 532 };
 533
 534 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 535 {
 536         unsigned long rate;
 537
 538         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 539                 u32 v = cru_readl(CRU_DPLL_CON);
 540                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 541                 do_div(rate64, PLL_NR(v));
 542                 rate = rate64 >> PLL_NO_SHIFT(v);
 543                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 544         } else {
 545                 rate = clk->parent->rate;
 546                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 547         }
 548
 549         return rate;
 550 }
 551
 552 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 553 {
 554         /* do nothing here */
 555         return 0;
 556 }
 557
 558 static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &general_pll_clk };
 559
 560 static struct clk ddr_pll_clk = {
 561         .name           = "ddr_pll",
 562         .parent         = &xin24m,
 563         .recalc         = ddr_pll_clk_recalc,
 564         .set_rate       = ddr_pll_clk_set_rate,
 565         .clksel_con     = CRU_MODE_CON,
 566         .clksel_parent_mask     = 3,
 567         .clksel_parent_shift    = 13,
 568         .parents        = ddr_pll_parents,
 569 };
 570
 571
 572 static int codec_pll_clk_mode(struct clk *clk, int on)
 573 {
 574         u32 cpll = cru_readl(CRU_CPLL_CON);
 575         if (on) {
 576                 cru_writel(cpll & ~(PLL_PD | PLL_BYPASS), CRU_CPLL_CON);
 577                 delay_300us();
 578                 pll_wait_lock(CODEC_PLL_IDX);
 579                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
 580         } else {
 581                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 582                 cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 583                 cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 584                 delay_500ns();
 585         }
 586         return 0;
 587 }
 588
 589 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 590 {
 591         unsigned long rate;
 592         u32 v = cru_readl(CRU_CPLL_CON);
 593         u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 594         do_div(rate64, PLL_NR(v));
 595         rate = rate64 >> PLL_NO_SHIFT(v);
 596         pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 597         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) != CRU_CODEC_MODE_NORMAL)
 598                 pr_debug("%s rate is %ld (slow mode) actually\n", clk->name, clk->parent->rate);
 599         return rate;
 600 }
 601
 602 #define CODEC_PLL_PARENT_MASK   (3 << 11)
 603 #define CODEC_PLL_PARENT_XIN24M (0 << 11)
 604 #define CODEC_PLL_PARENT_XIN27M (1 << 11)
 605 #define CODEC_PLL_PARENT_DDR_PLL        (2 << 11)
 606 #define CODEC_PLL_PARENT_GENERAL_PLL    (3 << 11)
 607
 608 struct codec_pll_set {
 609         unsigned long rate;
 610         u32 pll_con;
 611         u32 parent_con;
 612 };
 613
 614 #define CODEC_PLL(_khz, _parent, band, nr, nf, no) \
 615 { \
 616         .rate           = _khz * KHZ, \
 617         .pll_con        = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
 618         .parent_con     = CODEC_PLL_PARENT_XIN##_parent##M, \
 619 }
 620
 621 static const struct codec_pll_set codec_pll[] = {
 622         //        rate parent band NR  NF NO
 623         CODEC_PLL(108000, 24,  LOW, 1, 18, 4),  // for TV
 624         CODEC_PLL(648000, 24, HIGH, 1, 27, 1),
 625         CODEC_PLL(148500, 27,  LOW, 1, 22, 4),  // for HDMI
 626         CODEC_PLL(297000, 27,  LOW, 1, 22, 2),
 627         CODEC_PLL(445500, 27,  LOW, 2, 33, 1),
 628         CODEC_PLL(594000, 27, HIGH, 1, 22, 1),
 629         CODEC_PLL(891000, 27, HIGH, 1, 33, 1),
 630         CODEC_PLL(300000, 24,  LOW, 1, 25, 2),  // for GPU
 631         CODEC_PLL(360000, 24,  LOW, 1, 15, 1),
 632         CODEC_PLL(408000, 24,  LOW, 1, 17, 1),
 633         CODEC_PLL(456000, 24,  LOW, 1, 19, 1),
 634         CODEC_PLL(504000, 24,  LOW, 1, 21, 1),
 635         CODEC_PLL(552000, 24,  LOW, 1, 23, 1),
 636         CODEC_PLL(600000, 24, HIGH, 1, 25, 1),
 637 };
 638
 639 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 640 {
 641         int i;
 642         u32 work_mode;
 643
 644         const struct codec_pll_set *ps = NULL;
 645
 646         for (i = 0; i < ARRAY_SIZE(codec_pll); i++) {
 647                 if (codec_pll[i].rate == rate) {
 648                         ps = &codec_pll[i];
 649                         break;
 650                 }
 651         }
 652         if (!ps)
 653                 return -ENOENT;
 654
 655         if (!has_xin27m && ps->parent_con == CODEC_PLL_PARENT_XIN27M)
 656                 return -ENOENT;
 657
 658         work_mode = cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK;
 659
 660         /* enter slow mode */
 661         cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | ps->parent_con, CRU_MODE_CON);
 662
 663         /* power down */
 664         cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
 665
 666         delay_500ns();
 667
 668         cru_writel(ps->pll_con | PLL_PD, CRU_CPLL_CON);
 669
 670         delay_500ns();
 671
 672         /* power up */
 673         cru_writel(ps->pll_con, CRU_CPLL_CON);
 674
 675         delay_300us();
 676         pll_wait_lock(CODEC_PLL_IDX);
 677
 678         /* enter normal mode */
 679         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | work_mode, CRU_MODE_CON);
 680
 681         clk_set_parent_nolock(clk, ps->parent_con == CODEC_PLL_PARENT_XIN24M ? &xin24m : &xin27m);
 682
 683         return 0;
 684 }
 685
 686 static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &general_pll_clk };
 687
 688 static struct clk codec_pll_clk = {
 689         .name           = "codec_pll",
 690         .parent         = &xin24m,
 691         .mode           = codec_pll_clk_mode,
 692         .recalc         = codec_pll_clk_recalc,
 693         .set_rate       = codec_pll_clk_set_rate,
 694         .clksel_con     = CRU_MODE_CON,
 695         .clksel_parent_mask     = 3,
 696         .clksel_parent_shift    = 11,
 697         .parents        = codec_pll_parents,
 698 };
 699
 700
 701 static unsigned long general_pll_clk_recalc(struct clk *clk)
 702 {
 703         unsigned long rate;
 704
 705         if ((cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) == CRU_GENERAL_MODE_NORMAL) {
 706                 u32 v = cru_readl(CRU_GPLL_CON);
 707                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 708                 do_div(rate64, PLL_NR(v));
 709                 rate = rate64 >> PLL_NO_SHIFT(v);
 710                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 711         } else {
 712                 rate = clk->parent->rate;
 713                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 714         }
 715
 716         return rate;
 717 }
 718
 719 static int general_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 720 {
 721         u32 pll_con;
 722
 723         switch (rate) {
 724         case 96 * MHZ:
 725                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 726                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(16) | PLL_NO_4;
 727         break;
 728         case 144*MHZ:
 729                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 730                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_4;
 731         break;
 732         case 288 * MHZ:
 733                 /* 288M: low-band, NR=1, NF=24, NO=2 */
 734                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_2;
 735                 break;
 736         case 300 * MHZ:
 737                 /* 300M: low-band, NR=1, NF=25, NO=2 */
 738                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(25) | PLL_NO_2;
 739         break;
 740         case 624 * MHZ:
 741                 /* 624M: high-band, NR=1, NF=26, NO=1 */
 742                 pll_con = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 743                 break;
 744         default:
 745                 return -ENOENT;
 746                 break;
 747         }
 748
 749         /* enter slow mode */
 750         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 751
 752         /* power down */
 753         cru_writel(cru_readl(CRU_GPLL_CON) | PLL_PD, CRU_GPLL_CON);
 754
 755         delay_500ns();
 756
 757         cru_writel(pll_con | PLL_PD, CRU_GPLL_CON);
 758
 759         delay_500ns();
 760
 761         /* power up */
 762         cru_writel(pll_con, CRU_GPLL_CON);
 763
 764         delay_300us();
 765         pll_wait_lock(GENERAL_PLL_IDX);
 766
 767         /* enter normal mode */
 768         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_NORMAL, CRU_MODE_CON);
 769
 770         return 0;
 771 }
 772
 773 static struct clk *general_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
 774
 775 static struct clk general_pll_clk = {
 776         .name           = "general_pll",
 777         .parent         = &xin24m,
 778         .recalc         = general_pll_clk_recalc,
 779         .set_rate       = general_pll_clk_set_rate,
 780         .clksel_con     = CRU_MODE_CON,
 781         .clksel_parent_mask     = 3,
 782         .clksel_parent_shift    = 9,
 783         .parents        = general_pll_parents,
 784 };
 785
 786
 787 static struct clk *clk_core_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 788
 789 static struct clk clk_core = {
 790         .name           = "core",
 791         .parent         = &arm_pll_clk,
 792         .recalc         = clksel_recalc_div,
 793         .clksel_con     = CRU_CLKSEL0_CON,
 794         .clksel_mask    = 0x1F,
 795         .clksel_shift   = 0,
 796         .clksel_parent_mask     = 3,
 797         .clksel_parent_shift    = 23,
 798         .parents        = clk_core_parents,
 799 };
 800
 801 static unsigned long aclk_cpu_recalc(struct clk *clk)
 802 {
 803         unsigned long rate;
 804         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 805
 806         BUG_ON(div > 5);
 807         if (div >= 5)
 808                 div = 8;
 809         rate = clk->parent->rate / div;
 810         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 811
 812         return rate;
 813 }
 814
 815 static struct clk aclk_cpu = {
 816         .name           = "aclk_cpu",
 817         .parent         = &clk_core,
 818         .recalc         = aclk_cpu_recalc,
 819 };
 820
 821 static struct clk hclk_cpu = {
 822         .name           = "hclk_cpu",
 823         .parent         = &aclk_cpu,
 824         .recalc         = clksel_recalc_shift,
 825         .set_rate       = clksel_set_rate_shift,
 826         .clksel_con     = CRU_CLKSEL0_CON,
 827         .clksel_mask    = 3,
 828         .clksel_shift   = 8,
 829         .clksel_maxdiv  = 4,
 830 };
 831
 832 static struct clk pclk_cpu = {
 833         .name           = "pclk_cpu",
 834         .parent         = &aclk_cpu,
 835         .recalc         = clksel_recalc_shift,
 836         .set_rate       = clksel_set_rate_shift,
 837         .clksel_con     = CRU_CLKSEL0_CON,
 838         .clksel_mask    = 3,
 839         .clksel_shift   = 10,
 840         .clksel_maxdiv  = 8,
 841 };
 842
 843 static struct clk *aclk_periph_parents[4] = { &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
 844
 845 static struct clk aclk_periph = {
 846         .name           = "aclk_periph",
 847         .mode           = gate_mode,
 848         .gate_idx       = CLK_GATE_ACLK_PEIRPH,
 849         .recalc         = clksel_recalc_div,
 850         .set_rate       = clksel_set_rate_div,
 851         .clksel_con     = CRU_CLKSEL0_CON,
 852         .clksel_mask    = 0x1F,
 853         .clksel_shift   = 14,
 854         .clksel_parent_mask     = 3,
 855         .clksel_parent_shift    = 12,
 856         .parents        = aclk_periph_parents,
 857 };
 858
 859 static struct clk pclk_periph = {
 860         .name           = "pclk_periph",
 861         .mode           = gate_mode,
 862         .gate_idx       = CLK_GATE_PCLK_PEIRPH,
 863         .parent         = &aclk_periph,
 864         .recalc         = clksel_recalc_shift,
 865         .set_rate       = clksel_set_rate_shift,
 866         .clksel_con     = CRU_CLKSEL0_CON,
 867         .clksel_mask    = 3,
 868         .clksel_shift   = 19,
 869         .clksel_maxdiv  = 8,
 870 };
 871
 872 static struct clk hclk_periph = {
 873         .name           = "hclk_periph",
 874         .mode           = gate_mode,
 875         .gate_idx       = CLK_GATE_HCLK_PEIRPH,
 876         .parent         = &aclk_periph,
 877         .recalc         = clksel_recalc_shift,
 878         .set_rate       = clksel_set_rate_shift,
 879         .clksel_con     = CRU_CLKSEL0_CON,
 880         .clksel_mask    = 3,
 881         .clksel_shift   = 21,
 882         .clksel_maxdiv  = 4,
 883 };
 884
 885
 886 static unsigned long uhost_recalc(struct clk *clk)
 887 {
 888         unsigned long rate = clksel_recalc_div(clk);
 889         if (rate != 48 * MHZ) {
 890                 clksel_set_rate_div(clk, 48 * MHZ);
 891                 rate = clksel_recalc_div(clk);
 892         }
 893         return rate;
 894 }
 895
 896 static struct clk *clk_uhost_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 897
 898 static struct clk clk_uhost = {
 899         .name           = "uhost",
 900         .mode           = gate_mode,
 901         .recalc         = uhost_recalc,
 902         .set_rate       = clksel_set_rate_div,
 903         .gate_idx       = CLK_GATE_UHOST,
 904         .clksel_con     = CRU_CLKSEL1_CON,
 905         .clksel_mask    = 0x1F,
 906         .clksel_shift   = 16,
 907         .clksel_parent_mask     = 7,
 908         .clksel_parent_shift    = 13,
 909         .parents        = clk_uhost_parents,
 910 };
 911
 912 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 913
 914 static struct clk clk_otgphy0 = {
 915         .name           = "otgphy0",
 916         .mode           = gate_mode,
 917         .gate_idx       = CLK_GATE_USBPHY0,
 918         .clksel_con     = CRU_CLKSEL1_CON,
 919         .clksel_parent_mask     = 3,
 920         .clksel_parent_shift    = 9,
 921         .parents        = clk_otgphy_parents,
 922 };
 923
 924 static struct clk clk_otgphy1 = {
 925         .name           = "otgphy1",
 926         .mode           = gate_mode,
 927         .gate_idx       = CLK_GATE_USBPHY1,
 928         .clksel_con     = CRU_CLKSEL1_CON,
 929         .clksel_parent_mask     = 3,
 930         .clksel_parent_shift    = 11,
 931         .parents        = clk_otgphy_parents,
 932 };
 933
 934
 935 static struct clk rmii_clkin = {
 936         .name           = "rmii_clkin",
 937 };
 938
 939 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 940
 941 static struct clk clk_mac_ref_div = {
 942         .name           = "mac_ref_div",
 943         .recalc         = clksel_recalc_div,
 944         .set_rate       = clksel_set_rate_div,
 945         .clksel_con     = CRU_CLKSEL1_CON,
 946         .clksel_mask    = 0x1F,
 947         .clksel_shift   = 23,
 948         .clksel_parent_mask     = 3,
 949         .clksel_parent_shift    = 21,
 950         .parents        = clk_mac_ref_div_parents,
 951 };
 952
 953 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 954
 955 static struct clk clk_mac_ref = {
 956         .name           = "mac_ref",
 957         .mode           = gate_mode,
 958         .gate_idx       = CLK_GATE_MAC_REF,
 959         .clksel_con     = CRU_CLKSEL1_CON,
 960         .clksel_parent_mask     = 1,
 961         .clksel_parent_shift    = 28,
 962         .parents        = clk_mac_ref_parents,
 963 };
 964
 965
 966 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 967
 968 static struct clk clk_i2s0_div = {
 969         .name           = "i2s0_div",
 970         .recalc         = clksel_recalc_div,
 971         .set_rate       = clksel_set_rate_div,
 972         .clksel_con     = CRU_CLKSEL2_CON,
 973         .clksel_mask    = 0x1F,
 974         .clksel_shift   = 3,
 975         .clksel_parent_mask     = 7,
 976         .clksel_parent_shift    = 0,
 977         .parents        = clk_i2s_div_parents,
 978 };
 979
 980 static struct clk clk_i2s1_div = {
 981         .name           = "i2s1_div",
 982         .recalc         = clksel_recalc_div,
 983         .set_rate       = clksel_set_rate_div,
 984         .clksel_con     = CRU_CLKSEL2_CON,
 985         .clksel_mask    = 0x1F,
 986         .clksel_shift   = 13,
 987         .clksel_parent_mask     = 7,
 988         .clksel_parent_shift    = 10,
 989         .parents        = clk_i2s_div_parents,
 990 };
 991
 992 static struct clk clk_spdif_div = {
 993         .name           = "spdif_div",
 994         .recalc         = clksel_recalc_div,
 995         .set_rate       = clksel_set_rate_div,
 996         .clksel_con     = CRU_CLKSEL2_CON,
 997         .clksel_mask    = 0x1F,
 998         .clksel_shift   = 23,
 999         .clksel_parent_mask     = 7,
1000         .clksel_parent_shift    = 20,
1001         .parents        = clk_i2s_div_parents,
1002 };
1003
1004 static u32 clk_gcd(u32 numerator, u32 denominator)
1005 {
1006         u32 a, b;
1007
1008         if (!numerator || !denominator)
1009                 return 0;
1010         if (numerator > denominator) {
1011                 a = numerator;
1012                 b = denominator;
1013         } else {
1014                 a = denominator;
1015                 b = numerator;
1016         }
1017         while (b != 0) {
1018                 int r = b;
1019                 b = a % b;
1020                 a = r;
1021         }
1022
1023         return a;
1024 }
1025
1026 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
1027 {
1028         u32 numerator, denominator;
1029         u32 gcd;
1030
1031         gcd = clk_gcd(rate, clk->parent->rate);
1032         pr_debug("i2s rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
1033         if (!gcd) {
1034                 pr_err("gcd=0, i2s frac div is not be supported\n");
1035                 return -ENOENT;
1036         }
1037
1038         numerator = rate / gcd;
1039         denominator = clk->parent->rate / gcd;
1040         pr_debug("i2s numerator=%d,denominator=%d,times=%d\n",
1041                 numerator, denominator, denominator / numerator);
1042         if (numerator > 0xffff || denominator > 0xffff) {
1043                 pr_err("i2s can't get a available nume and deno\n");
1044                 return -ENOENT;
1045         }
1046
1047         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1048         cru_writel(numerator << 16 | denominator, clk->clksel_con);
1049
1050         return 0;
1051 }
1052
1053 static struct clk clk_i2s0_frac_div = {
1054         .name           = "i2s0_frac_div",
1055         .parent         = &clk_i2s0_div,
1056         .recalc         = clksel_recalc_frac,
1057         .set_rate       = clk_i2s_frac_div_set_rate,
1058         .clksel_con     = CRU_CLKSEL3_CON,
1059 };
1060
1061 static struct clk clk_i2s1_frac_div = {
1062         .name           = "i2s1_frac_div",
1063         .parent         = &clk_i2s1_div,
1064         .recalc         = clksel_recalc_frac,
1065         .set_rate       = clk_i2s_frac_div_set_rate,
1066         .clksel_con     = CRU_CLKSEL4_CON,
1067 };
1068
1069 static struct clk clk_spdif_frac_div = {
1070         .name           = "spdif_frac_div",
1071         .parent         = &clk_spdif_div,
1072         .recalc         = clksel_recalc_frac,
1073         .set_rate       = clk_i2s_frac_div_set_rate,
1074         .clksel_con     = CRU_CLKSEL5_CON,
1075 };
1076
1077 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1078 {
1079         int ret = 0;
1080         struct clk *parent;
1081
1082         if (rate == 12 * MHZ) {
1083                 parent = &clk_12m;
1084         } else {
1085                 parent = clk->parents[1]; /* frac div */
1086                 ret = clk_set_rate_nolock(parent, rate);
1087                 if (ret)
1088                         return ret;
1089         }
1090         if (clk->parent != parent)
1091                 ret = clk_set_parent_nolock(clk, parent);
1092
1093         return ret;
1094 }
1095
1096 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
1097
1098 static struct clk clk_i2s0 = {
1099         .name           = "i2s0",
1100         .mode           = gate_mode,
1101         .gate_idx       = CLK_GATE_I2S0,
1102         .set_rate       = i2s_set_rate,
1103         .clksel_con     = CRU_CLKSEL2_CON,
1104         .clksel_parent_mask     = 3,
1105         .clksel_parent_shift    = 8,
1106         .parents        = clk_i2s0_parents,
1107 };
1108
1109 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
1110
1111 static struct clk clk_i2s1 = {
1112         .name           = "i2s1",
1113         .mode           = gate_mode,
1114         .gate_idx       = CLK_GATE_I2S1,
1115         .set_rate       = i2s_set_rate,
1116         .clksel_con     = CRU_CLKSEL2_CON,
1117         .clksel_parent_mask     = 3,
1118         .clksel_parent_shift    = 18,
1119         .parents        = clk_i2s1_parents,
1120 };
1121
1122 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
1123
1124 static struct clk clk_spdif = {
1125         .name           = "spdif",
1126         .mode           = gate_mode,
1127         .gate_idx       = CLK_GATE_SPDIF,
1128         .set_rate       = i2s_set_rate,
1129         .clksel_con     = CRU_CLKSEL2_CON,
1130         .clksel_parent_mask     = 3,
1131         .clksel_parent_shift    = 28,
1132         .parents        = clk_spdif_parents,
1133 };
1134
1135
1136 static struct clk *clk_spi_src_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1137
1138 static struct clk clk_spi_src = {
1139         .name           = "spi_src",
1140         .clksel_con     = CRU_CLKSEL6_CON,
1141         .clksel_parent_mask     = 3,
1142         .clksel_parent_shift    = 0,
1143         .parents        = clk_spi_src_parents,
1144 };
1145
1146 static struct clk clk_spi0 = {
1147         .name           = "spi0",
1148         .parent         = &clk_spi_src,
1149         .mode           = gate_mode,
1150         .recalc         = clksel_recalc_div,
1151         .set_rate       = clksel_set_rate_div,
1152         .gate_idx       = CLK_GATE_SPI0,
1153         .clksel_con     = CRU_CLKSEL6_CON,
1154         .clksel_mask    = 0x7F,
1155         .clksel_shift   = 2,
1156 };
1157
1158 static struct clk clk_spi1 = {
1159         .name           = "spi1",
1160         .parent         = &clk_spi_src,
1161         .mode           = gate_mode,
1162         .recalc         = clksel_recalc_div,
1163         .set_rate       = clksel_set_rate_div,
1164         .gate_idx       = CLK_GATE_SPI1,
1165         .clksel_con     = CRU_CLKSEL6_CON,
1166         .clksel_mask    = 0x7F,
1167         .clksel_shift   = 11,
1168 };
1169
1170
1171 static struct clk clk_saradc = {
1172         .name           = "saradc",
1173         .parent         = &pclk_periph,
1174         .mode           = gate_mode,
1175         .recalc         = clksel_recalc_div,
1176         .set_rate       = clksel_set_rate_div,
1177         .gate_idx       = CLK_GATE_SARADC,
1178         .clksel_con     = CRU_CLKSEL6_CON,
1179         .clksel_mask    = 0xFF,
1180         .clksel_shift   = 18,
1181 };
1182
1183
1184 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
1185
1186 static struct clk clk_timer0 = {
1187         .name           = "timer0",
1188         .mode           = gate_mode,
1189         .gate_idx       = CLK_GATE_TIMER0,
1190         .clksel_con     = CRU_CLKSEL6_CON,
1191         .clksel_parent_mask     = 1,
1192         .clksel_parent_shift    = 26,
1193         .parents        = clk_cpu_timer_parents,
1194 };
1195
1196 static struct clk clk_timer1 = {
1197         .name           = "timer1",
1198         .mode           = gate_mode,
1199         .gate_idx       = CLK_GATE_TIMER1,
1200         .clksel_con     = CRU_CLKSEL6_CON,
1201         .clksel_parent_mask     = 1,
1202         .clksel_parent_shift    = 27,
1203         .parents        = clk_cpu_timer_parents,
1204 };
1205
1206 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
1207
1208 static struct clk clk_timer2 = {
1209         .name           = "timer2",
1210         .mode           = gate_mode,
1211         .gate_idx       = CLK_GATE_TIMER2,
1212         .clksel_con     = CRU_CLKSEL6_CON,
1213         .clksel_parent_mask     = 1,
1214         .clksel_parent_shift    = 28,
1215         .parents        = clk_periph_timer_parents,
1216 };
1217
1218 static struct clk clk_timer3 = {
1219         .name           = "timer3",
1220         .mode           = gate_mode,
1221         .gate_idx       = CLK_GATE_TIMER3,
1222         .clksel_con     = CRU_CLKSEL6_CON,
1223         .clksel_parent_mask     = 1,
1224         .clksel_parent_shift    = 29,
1225         .parents        = clk_periph_timer_parents,
1226 };
1227
1228
1229 static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1230
1231 static struct clk clk_mmc_src = {
1232         .name           = "mmc_src",
1233         .clksel_con     = CRU_CLKSEL7_CON,
1234         .clksel_parent_mask     = 3,
1235         .clksel_parent_shift    = 0,
1236         .parents        = clk_mmc_src_parents,
1237 };
1238
1239 static struct clk clk_mmc0 = {
1240         .name           = "mmc0",
1241         .parent         = &clk_mmc_src,
1242         .mode           = gate_mode,
1243         .recalc         = clksel_recalc_div,
1244         .set_rate       = clksel_set_rate_div,
1245         .gate_idx       = CLK_GATE_MMC0,
1246         .clksel_con     = CRU_CLKSEL7_CON,
1247         .clksel_mask    = 0x3F,
1248         .clksel_shift   = 2,
1249 };
1250
1251 static struct clk clk_mmc1 = {
1252         .name           = "mmc1",
1253         .parent         = &clk_mmc_src,
1254         .mode           = gate_mode,
1255         .recalc         = clksel_recalc_div,
1256         .set_rate       = clksel_set_rate_div,
1257         .gate_idx       = CLK_GATE_MMC1,
1258         .clksel_con     = CRU_CLKSEL7_CON,
1259         .clksel_mask    = 0x3F,
1260         .clksel_shift   = 10,
1261 };
1262
1263 static struct clk clk_emmc = {
1264         .name           = "emmc",
1265         .parent         = &clk_mmc_src,
1266         .mode           = gate_mode,
1267         .recalc         = clksel_recalc_div,
1268         .set_rate       = clksel_set_rate_div,
1269         .gate_idx       = CLK_GATE_EMMC,
1270         .clksel_con     = CRU_CLKSEL7_CON,
1271         .clksel_mask    = 0x3F,
1272         .clksel_shift   = 18,
1273 };
1274
1275
1276 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &general_pll_clk, &codec_pll_clk, &arm_pll_clk };
1277
1278 static struct clk clk_ddr = {
1279         .name           = "ddr",
1280         .recalc         = clksel_recalc_shift,
1281         .clksel_con     = CRU_CLKSEL7_CON,
1282         .clksel_mask    = 7,
1283         .clksel_shift   = 26,
1284         .clksel_maxdiv  = 32,
1285         .clksel_parent_mask     = 3,
1286         .clksel_parent_shift    = 24,
1287         .parents        = clk_ddr_parents,
1288 };
1289
1290
1291 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1292 {
1293         int ret = 0;
1294         struct clk *parent;
1295         struct clk *clk_div = clk->parents[0];
1296
1297         switch (rate) {
1298         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
1299                 parent = clk->parents[2]; /* xin24m */
1300                 break;
1301         case 19200*16:
1302         case 38400*16:
1303         case 57600*16:
1304         case 115200*16:
1305         case 230400*16:
1306         case 460800*16:
1307         case 576000*16:
1308                 parent = clk->parents[1]; /* frac div */
1309                 /* reset div to 1 */
1310                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1311                 if (ret)
1312                         return ret;
1313                 break;
1314         default:
1315                 parent = clk_div;
1316                 break;
1317         }
1318
1319         if (parent->set_rate) {
1320                 ret = clk_set_rate_nolock(parent, rate);
1321                 if (ret)
1322                         return ret;
1323         }
1324
1325         if (clk->parent != parent)
1326                 ret = clk_set_parent_nolock(clk, parent);
1327
1328         return ret;
1329 }
1330
1331 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1332 {
1333         u32 numerator, denominator;
1334         u32 gcd;
1335
1336         gcd = clk_gcd(rate, clk->parent->rate);
1337         pr_debug("uart rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
1338         if (!gcd) {
1339                 pr_err("gcd=0, uart frac div is not be supported\n");
1340                 return -ENOENT;
1341         }
1342
1343         numerator = rate / gcd;
1344         denominator = clk->parent->rate / gcd;
1345         pr_debug("uart numerator=%d,denominator=%d,times=%d\n",
1346                 numerator, denominator, denominator / numerator);
1347         if (numerator > 0xffff || denominator > 0xffff) {
1348                 pr_err("uart_frac can't get a available nume and deno\n");
1349                 return -ENOENT;
1350         }
1351
1352         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1353         cru_writel(numerator << 16 | denominator, clk->clksel_con);
1354
1355         return 0;
1356 }
1357
1358 static struct clk *clk_uart_src_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1359
1360 static struct clk clk_uart01_src = {
1361         .name           = "uart01_src",
1362         .clksel_con     = CRU_CLKSEL8_CON,
1363         .clksel_parent_mask     = 7,
1364         .clksel_parent_shift    = 0,
1365         .parents        = clk_uart_src_parents,
1366 };
1367
1368 static struct clk clk_uart0_div = {
1369         .name           = "uart0_div",
1370         .parent         = &clk_uart01_src,
1371         .recalc         = clksel_recalc_div,
1372         .set_rate       = clksel_set_rate_div,
1373         .clksel_con     = CRU_CLKSEL8_CON,
1374         .clksel_mask    = 0x3F,
1375         .clksel_shift   = 3,
1376 };
1377
1378 static struct clk clk_uart0_frac_div = {
1379         .name           = "uart0_frac_div",
1380         .parent         = &clk_uart0_div,
1381         .recalc         = clksel_recalc_frac,
1382         .set_rate       = clk_uart_frac_div_set_rate,
1383         .clksel_con     = CRU_CLKSEL10_CON,
1384 };
1385
1386 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1387
1388 static struct clk clk_uart0 = {
1389         .name           = "uart0",
1390         .mode           = gate_mode,
1391         .set_rate       = clk_uart_set_rate,
1392         .gate_idx       = CLK_GATE_UART0,
1393         .clksel_con     = CRU_CLKSEL8_CON,
1394         .clksel_parent_mask     = 3,
1395         .clksel_parent_shift    = 9,
1396         .parents        = clk_uart0_parents,
1397 };
1398
1399 static struct clk clk_uart1_div = {
1400         .name           = "uart1_div",
1401         .parent         = &clk_uart01_src,
1402         .recalc         = clksel_recalc_div,
1403         .set_rate       = clksel_set_rate_div,
1404         .clksel_con     = CRU_CLKSEL8_CON,
1405         .clksel_mask    = 0x3F,
1406         .clksel_shift   = 14,
1407 };
1408
1409 static struct clk clk_uart1_frac_div = {
1410         .name           = "uart1_frac_div",
1411         .parent         = &clk_uart1_div,
1412         .recalc         = clksel_recalc_frac,
1413         .set_rate       = clk_uart_frac_div_set_rate,
1414         .clksel_con     = CRU_CLKSEL11_CON,
1415 };
1416
1417 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1418
1419 static struct clk clk_uart1 = {
1420         .name           = "uart1",
1421         .mode           = gate_mode,
1422         .set_rate       = clk_uart_set_rate,
1423         .gate_idx       = CLK_GATE_UART1,
1424         .clksel_con     = CRU_CLKSEL8_CON,
1425         .clksel_parent_mask     = 3,
1426         .clksel_parent_shift    = 20,
1427         .parents        = clk_uart1_parents,
1428 };
1429
1430 static struct clk clk_uart23_src = {
1431         .name           = "uart23_src",
1432         .clksel_con     = CRU_CLKSEL9_CON,
1433         .clksel_parent_mask     = 7,
1434         .clksel_parent_shift    = 0,
1435         .parents        = clk_uart_src_parents,
1436 };
1437
1438 static struct clk clk_uart2_div = {
1439         .name           = "uart2_div",
1440         .parent         = &clk_uart23_src,
1441         .recalc         = clksel_recalc_div,
1442         .set_rate       = clksel_set_rate_div,
1443         .clksel_con     = CRU_CLKSEL9_CON,
1444         .clksel_mask    = 0x3F,
1445         .clksel_shift   = 3,
1446 };
1447
1448 static struct clk clk_uart2_frac_div = {
1449         .name           = "uart2_frac_div",
1450         .parent         = &clk_uart2_div,
1451         .recalc         = clksel_recalc_frac,
1452         .set_rate       = clk_uart_frac_div_set_rate,
1453         .clksel_con     = CRU_CLKSEL12_CON,
1454 };
1455
1456 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1457
1458 static struct clk clk_uart2 = {
1459         .name           = "uart2",
1460         .mode           = gate_mode,
1461         .set_rate       = clk_uart_set_rate,
1462         .gate_idx       = CLK_GATE_UART2,
1463         .clksel_con     = CRU_CLKSEL9_CON,
1464         .clksel_parent_mask     = 3,
1465         .clksel_parent_shift    = 9,
1466         .parents        = clk_uart2_parents,
1467 };
1468
1469 static struct clk clk_uart3_div = {
1470         .name           = "uart3_div",
1471         .parent         = &clk_uart23_src,
1472         .recalc         = clksel_recalc_div,
1473         .set_rate       = clksel_set_rate_div,
1474         .clksel_con     = CRU_CLKSEL9_CON,
1475         .clksel_mask    = 0x3F,
1476         .clksel_shift   = 14,
1477 };
1478
1479 static struct clk clk_uart3_frac_div = {
1480         .name           = "uart3_frac_div",
1481         .parent         = &clk_uart3_div,
1482         .recalc         = clksel_recalc_frac,
1483         .set_rate       = clk_uart_frac_div_set_rate,
1484         .clksel_con     = CRU_CLKSEL13_CON,
1485 };
1486
1487 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1488
1489 static struct clk clk_uart3 = {
1490         .name           = "uart3",
1491         .mode           = gate_mode,
1492         .set_rate       = clk_uart_set_rate,
1493         .gate_idx       = CLK_GATE_UART3,
1494         .clksel_con     = CRU_CLKSEL9_CON,
1495         .clksel_parent_mask     = 3,
1496         .clksel_parent_shift    = 20,
1497         .parents        = clk_uart3_parents,
1498 };
1499
1500
1501 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1502
1503 static struct clk clk_hsadc_div = {
1504         .name           = "hsadc_div",
1505         .recalc         = clksel_recalc_div,
1506         .set_rate       = clksel_set_rate_div,
1507         .clksel_con     = CRU_CLKSEL14_CON,
1508         .clksel_mask    = 0xFF,
1509         .clksel_shift   = 10,
1510         .clksel_parent_mask     = 7,
1511         .clksel_parent_shift    = 7,
1512         .parents        = clk_hsadc_div_parents,
1513 };
1514
1515 static struct clk clk_hsadc_frac_div = {
1516         .name           = "hsadc_frac_div",
1517         .parent         = &clk_hsadc_div,
1518         .recalc         = clksel_recalc_frac,
1519         .clksel_con     = CRU_CLKSEL15_CON,
1520 };
1521
1522 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
1523
1524 static struct clk clk_demod = {
1525         .name           = "demod",
1526         .clksel_con     = CRU_CLKSEL14_CON,
1527         .clksel_parent_mask     = 3,
1528         .clksel_parent_shift    = 18,
1529         .parents        = clk_demod_parents,
1530 };
1531
1532 static struct clk gpsclk = {
1533         .name           = "gpsclk",
1534 };
1535
1536 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1537
1538 static struct clk clk_hsadc = {
1539         .name           = "hsadc",
1540         .mode           = gate_mode,
1541         .gate_idx       = CLK_GATE_HSADC,
1542         .clksel_con     = CRU_CLKSEL14_CON,
1543         .clksel_parent_mask     = 1,
1544         .clksel_parent_shift    = 21,
1545         .parents        = clk_hsadc_parents,
1546 };
1547
1548 static unsigned long div2_recalc(struct clk *clk)
1549 {
1550         return clk->parent->rate >> 1;
1551 }
1552
1553 static struct clk clk_hsadc_div2 = {
1554         .name           = "hsadc_div2",
1555         .parent         = &clk_demod,
1556         .recalc         = div2_recalc,
1557 };
1558
1559 static struct clk clk_hsadc_div2_inv = {
1560         .name           = "hsadc_div2_inv",
1561         .parent         = &clk_demod,
1562         .recalc         = div2_recalc,
1563 };
1564
1565 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1566
1567 static struct clk clk_hsadc_out = {
1568         .name           = "hsadc_out",
1569         .clksel_con     = CRU_CLKSEL14_CON,
1570         .clksel_parent_mask     = 1,
1571         .clksel_parent_shift    = 20,
1572         .parents        = clk_hsadc_out_parents,
1573 };
1574
1575
1576 static int dclk_lcdc_div_set_rate(struct clk *clk, unsigned long rate)
1577 {
1578         struct clk *parent;
1579
1580         switch (rate) {
1581         case 27000 * KHZ:
1582         case 74250 * KHZ:
1583         case 148500 * KHZ:
1584         case 297 * MHZ:
1585         case 594 * MHZ:
1586                 parent = &codec_pll_clk;
1587                 break;
1588         default:
1589                 parent = &general_pll_clk;
1590                 break;
1591         }
1592         if (clk->parent != parent)
1593                 clk_set_parent_nolock(clk, parent);
1594
1595         return clksel_set_rate_div(clk, rate);
1596 }
1597
1598 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
1599
1600 static struct clk dclk_lcdc_div = {
1601         .name           = "dclk_lcdc_div",
1602         .recalc         = clksel_recalc_div,
1603         .set_rate       = dclk_lcdc_div_set_rate,
1604         .clksel_con     = CRU_CLKSEL16_CON,
1605         .clksel_mask    = 0xFF,
1606         .clksel_shift   = 2,
1607         .clksel_parent_mask     = 3,
1608         .clksel_parent_shift    = 0,
1609         .parents        = dclk_lcdc_div_parents,
1610 };
1611
1612 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1613 {
1614         int ret = 0;
1615         struct clk *parent;
1616
1617         if (rate == 27 * MHZ && has_xin27m) {
1618                 parent = &xin27m;
1619         } else {
1620                 parent = &dclk_lcdc_div;
1621                 ret = clk_set_rate_nolock(parent, rate);
1622                 if (ret)
1623                         return ret;
1624         }
1625         if (clk->parent != parent)
1626                 ret = clk_set_parent_nolock(clk, parent);
1627
1628         return ret;
1629 }
1630
1631 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
1632
1633 static struct clk dclk_lcdc = {
1634         .name           = "dclk_lcdc",
1635         .mode           = gate_mode,
1636         .set_rate       = dclk_lcdc_set_rate,
1637         .gate_idx       = CLK_GATE_DCLK_LCDC,
1638         .clksel_con     = CRU_CLKSEL16_CON,
1639         .clksel_parent_mask     = 1,
1640         .clksel_parent_shift    = 10,
1641         .parents        = dclk_lcdc_parents,
1642 };
1643
1644 static struct clk dclk_ebook = {
1645         .name           = "dclk_ebook",
1646         .mode           = gate_mode,
1647         .gate_idx       = CLK_GATE_DCLK_EBOOK,
1648         .recalc         = clksel_recalc_div,
1649         .set_rate       = clksel_set_rate_div,
1650         .clksel_con     = CRU_CLKSEL16_CON,
1651         .clksel_mask    = 0x1F,
1652         .clksel_shift   = 13,
1653         .clksel_parent_mask     = 3,
1654         .clksel_parent_shift    = 11,
1655         .parents        = dclk_lcdc_div_parents,
1656 };
1657
1658 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &general_pll_clk, &arm_pll_clk };
1659
1660 static struct clk aclk_lcdc = {
1661         .name           = "aclk_lcdc",
1662         .mode           = gate_mode,
1663         .gate_idx       = CLK_GATE_ACLK_LCDC,
1664         .recalc         = clksel_recalc_div,
1665         .set_rate       = clksel_set_rate_div,
1666         .clksel_con     = CRU_CLKSEL16_CON,
1667         .clksel_mask    = 0x1F,
1668         .clksel_shift   = 20,
1669         .clksel_parent_mask     = 3,
1670         .clksel_parent_shift    = 18,
1671         .parents        = aclk_lcdc_parents,
1672 };
1673
1674 static struct clk hclk_lcdc = {
1675         .name           = "hclk_lcdc",
1676         .mode           = gate_mode,
1677         .gate_idx       = CLK_GATE_HCLK_LCDC,
1678         .parent         = &aclk_lcdc,
1679         .clksel_con     = CRU_CLKSEL16_CON,
1680         .recalc         = clksel_recalc_shift,
1681         .set_rate       = clksel_set_rate_shift,
1682         .clksel_mask    = 3,
1683         .clksel_shift   = 25,
1684         .clksel_maxdiv  = 4,
1685 };
1686
1687 static struct clk *xpu_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1688
1689 static struct clk aclk_vepu = {
1690         .name           = "aclk_vepu",
1691         .mode           = gate_mode,
1692         .recalc         = clksel_recalc_div,
1693         .set_rate       = clksel_set_rate_div,
1694         .gate_idx       = CLK_GATE_ACLK_VEPU,
1695         .clksel_con     = CRU_CLKSEL17_CON,
1696         .clksel_mask    = 0x1F,
1697         .clksel_shift   = 2,
1698         .clksel_parent_mask     = 3,
1699         .clksel_parent_shift    = 0,
1700         .parents        = xpu_parents,
1701 };
1702
1703 static struct clk hclk_vepu = {
1704         .name           = "hclk_vepu",
1705         .parent         = &aclk_vepu,
1706         .mode           = gate_mode,
1707         .recalc         = clksel_recalc_shift,
1708         .set_rate       = clksel_set_rate_shift,
1709         .gate_idx       = CLK_GATE_HCLK_VEPU,
1710         .clksel_con     = CRU_CLKSEL17_CON,
1711         .clksel_mask    = 3,
1712         .clksel_shift   = 28,
1713         .clksel_maxdiv  = 4,
1714 };
1715
1716 static struct clk aclk_vdpu = {
1717         .name           = "aclk_vdpu",
1718         .parent         = &general_pll_clk,
1719         .mode           = gate_mode,
1720         .recalc         = clksel_recalc_div,
1721         .set_rate       = clksel_set_rate_div,
1722         .gate_idx       = CLK_GATE_ACLK_VDPU,
1723         .clksel_con     = CRU_CLKSEL17_CON,
1724         .clksel_mask    = 0x1F,
1725         .clksel_shift   = 9,
1726         .clksel_parent_mask     = 3,
1727         .clksel_parent_shift    = 7,
1728         .parents        = xpu_parents,
1729 };
1730
1731 static struct clk hclk_vdpu = {
1732         .name           = "hclk_vdpu",
1733         .parent         = &aclk_vdpu,
1734         .mode           = gate_mode,
1735         .recalc         = clksel_recalc_shift,
1736         .set_rate       = clksel_set_rate_shift,
1737         .gate_idx       = CLK_GATE_HCLK_VDPU,
1738         .clksel_con     = CRU_CLKSEL17_CON,
1739         .clksel_mask    = 3,
1740         .clksel_shift   = 30,
1741         .clksel_maxdiv  = 4,
1742 };
1743
1744 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1745 {
1746         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1747         struct clk *parents[] = { &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1748         int i;
1749         unsigned long best_rate = 0;
1750         struct clk *best_parent = clk->parent;
1751
1752         for (i = 0; i < ARRAY_SIZE(parents); i++) {
1753                 unsigned long new_rate = clksel_round_rate_div_by_parent(clk, rate, parents[i], max_rate);
1754                 if (new_rate == rate) {
1755                         best_rate = new_rate;
1756                         best_parent = parents[i];
1757                         break;
1758                 }
1759                 if (new_rate > max_rate)
1760                         continue;
1761                 if (new_rate > best_rate) {
1762                         best_rate = new_rate;
1763                         best_parent = parents[i];
1764                 }
1765         }
1766         if (!best_rate)
1767                 return -ENOENT;
1768         if (best_parent != clk->parent)
1769                 clk_set_parent_nolock(clk, best_parent);
1770         return clksel_set_rate_div(clk, best_rate);
1771 }
1772
1773 static struct clk clk_gpu = {
1774         .name           = "gpu",
1775         .mode           = gate_mode,
1776         .gate_idx       = CLK_GATE_GPU,
1777         .recalc         = clksel_recalc_div,
1778         .set_rate       = clk_gpu_set_rate,
1779         .clksel_con     = CRU_CLKSEL17_CON,
1780         .clksel_mask    = 0x1F,
1781         .clksel_shift   = 16,
1782         .clksel_parent_mask     = 3,
1783         .clksel_parent_shift    = 14,
1784         .parents        = xpu_parents,
1785 };
1786
1787 static struct clk aclk_gpu = {
1788         .name           = "aclk_gpu",
1789         .mode           = gate_mode,
1790         .gate_idx       = CLK_GATE_ACLK_GPU,
1791         .recalc         = clksel_recalc_div,
1792         .set_rate       = clksel_set_rate_div,
1793         .clksel_con     = CRU_CLKSEL17_CON,
1794         .clksel_mask    = 0x1F,
1795         .clksel_shift   = 23,
1796         .clksel_parent_mask     = 3,
1797         .clksel_parent_shift    = 21,
1798         .parents        = xpu_parents,
1799 };
1800
1801
1802 static struct clk vip_clkin = {
1803         .name           = "vip_clkin",
1804 };
1805
1806 static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
1807
1808 static struct clk clk_vip_out = {
1809         .name           = "vip_out",
1810         .mode           = gate_mode,
1811         .gate_idx       = CLK_GATE_VIP_OUT,
1812         .clksel_con     = CRU_CLKSEL1_CON,
1813         .clksel_parent_mask     = 3,
1814         .clksel_parent_shift    = 7,
1815         .parents        = clk_vip_parents,
1816 };
1817
1818
1819 #define GATE_CLK(NAME,PARENT,ID) \
1820 static struct clk clk_##NAME = { \
1821         .name           = #NAME, \
1822         .parent         = &PARENT, \
1823         .mode           = gate_mode, \
1824         .gate_idx       = CLK_GATE_##ID, \
1825 }
1826
1827 GATE_CLK(i2c0, pclk_cpu, I2C0);
1828 GATE_CLK(i2c1, pclk_periph, I2C1);
1829 GATE_CLK(i2c2, pclk_periph, I2C2);
1830 GATE_CLK(i2c3, pclk_periph, I2C3);
1831
1832 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1833 GATE_CLK(gpio1, pclk_periph, GPIO1);
1834 GATE_CLK(gpio2, pclk_periph, GPIO2);
1835 GATE_CLK(gpio3, pclk_periph, GPIO3);
1836 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1837 GATE_CLK(gpio5, pclk_periph, GPIO5);
1838 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1839
1840 GATE_CLK(dma1, aclk_cpu, DMA1);
1841 GATE_CLK(dma2, aclk_periph, DMA2);
1842
1843 GATE_CLK(gic, aclk_cpu, GIC);
1844 GATE_CLK(intmem, aclk_cpu, INTMEM);
1845 GATE_CLK(rom, hclk_cpu, ROM);
1846 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1847 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1848 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1849 GATE_CLK(efuse, pclk_cpu, EFUSE);
1850 GATE_CLK(tzpc, pclk_cpu, TZPC);
1851 GATE_CLK(debug, pclk_cpu, DEBUG);
1852 GATE_CLK(tpiu, pclk_cpu, TPIU);
1853 GATE_CLK(rtc, pclk_cpu, RTC);
1854 GATE_CLK(pmu, pclk_cpu, PMU);
1855 GATE_CLK(grf, pclk_cpu, GRF);
1856
1857 GATE_CLK(emem, hclk_periph, EMEM);
1858 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
1859 GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
1860 GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
1861 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
1862 GATE_CLK(smc, pclk_periph, SMC);
1863 GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
1864 GATE_CLK(mii_tx, hclk_periph, MII_TX);
1865 GATE_CLK(mii_rx, hclk_periph, MII_RX);
1866 GATE_CLK(hif, hclk_periph, HIF);
1867 GATE_CLK(nandc, hclk_periph, NANDC);
1868 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
1869 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1870 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1871 GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
1872 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1873
1874 GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
1875 GATE_CLK(wdt, pclk_periph, WDT);
1876 GATE_CLK(pwm, pclk_periph, PWM);
1877 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1878 GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
1879 GATE_CLK(vip_input, vip_clkin, VIP_INPUT);
1880 GATE_CLK(jtag, aclk_cpu, JTAG);
1881
1882 GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
1883 GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
1884 GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
1885 GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
1886 GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
1887 GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
1888 GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
1889 GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
1890 GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
1891 GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
1892 GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
1893 GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
1894
1895 GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
1896 GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
1897 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
1898
1899
1900 static void __sramfunc pmu_set_power_domain_sram(enum pmu_power_domain pd, bool on)
1901 {
1902         if (on)
1903                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1904         else
1905                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) |  (1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1906         dsb();
1907
1908         while (pmu_power_domain_is_on(pd) != on)
1909                 ;
1910 }
1911
1912 static noinline void do_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1913 {
1914         static unsigned long save_sp;
1915
1916         DDR_SAVE_SP(save_sp);
1917         pmu_set_power_domain_sram(pd, on);
1918         DDR_RESTORE_SP(save_sp);
1919 }
1920
1921 void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1922 {
1923         unsigned long flags;
1924
1925         mdelay(10);
1926         local_irq_save(flags);
1927         do_pmu_set_power_domain(pd, on);
1928         local_irq_restore(flags);
1929         mdelay(10);
1930 }
1931
1932 static int pd_vcodec_mode(struct clk *clk, int on)
1933 {
1934         if (on) {
1935                 u32 gate;
1936
1937                 gate = cru_clkgate3_con_mirror;
1938                 gate |= (1 << CLK_GATE_ACLK_DDR_VEPU % 32);
1939                 gate &= ~((1 << CLK_GATE_ACLK_VEPU % 32)
1940                         | (1 << CLK_GATE_HCLK_VEPU % 32)
1941                         | (1 << CLK_GATE_HCLK_CPU_VCODEC % 32));
1942                 cru_writel(gate, CRU_CLKGATE3_CON);
1943
1944                 pmu_set_power_domain(PD_VCODEC, true);
1945
1946                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1947         } else {
1948                 pmu_set_power_domain(PD_VCODEC, false);
1949         }
1950
1951         return 0;
1952 }
1953
1954 static struct clk pd_vcodec = {
1955         .name   = "pd_vcodec",
1956         .flags  = IS_PD,
1957         .mode   = pd_vcodec_mode,
1958         .gate_idx       = PD_VCODEC,
1959 };
1960
1961 static int pd_display_mode(struct clk *clk, int on)
1962 {
1963 #if 0   /* display power domain is buggy, always keep it on.  */
1964         if (on) {
1965                 u32 gate, gate2;
1966
1967                 gate = cru_clkgate3_con_mirror;
1968                 gate |= (1 << CLK_GATE_ACLK_DDR_LCDC % 32);
1969                 gate &= ~((1 << CLK_GATE_HCLK_CPU_DISPLAY % 32)
1970                         | (1 << CLK_GATE_HCLK_DISP_MATRIX % 32)
1971                         | (1 << CLK_GATE_ACLK_DISP_MATRIX % 32)
1972                         | (1 << CLK_GATE_DCLK_EBOOK % 32)
1973                         | (1 << CLK_GATE_HCLK_EBOOK % 32)
1974                         | (1 << CLK_GATE_HCLK_IPP % 32)
1975                         | (1 << CLK_GATE_ACLK_IPP % 32)
1976                         | (1 << CLK_GATE_DCLK_LCDC % 32)
1977                         | (1 << CLK_GATE_HCLK_LCDC % 32)
1978                         | (1 << CLK_GATE_ACLK_LCDC % 32));
1979                 cru_writel(gate, CRU_CLKGATE3_CON);
1980
1981                 gate2 = cru_readl(CRU_CLKGATE2_CON);
1982                 gate = gate2;
1983                 gate &= ~((1 << CLK_GATE_VIP_OUT % 32)
1984                         | (1 << CLK_GATE_VIP_SLAVE % 32)
1985                         | (1 << CLK_GATE_VIP_MATRIX % 32)
1986                         | (1 << CLK_GATE_VIP_BUS % 32));
1987                 cru_writel(gate, CRU_CLKGATE2_CON);
1988
1989                 pmu_set_power_domain(PD_DISPLAY, true);
1990
1991                 cru_writel(gate2, CRU_CLKGATE2_CON);
1992                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1993         } else {
1994                 pmu_set_power_domain(PD_DISPLAY, false);
1995         }
1996 #endif
1997
1998         return 0;
1999 }
2000
2001 static struct clk pd_display = {
2002         .name   = "pd_display",
2003         .flags  = IS_PD,
2004         .mode   = pd_display_mode,
2005         .gate_idx       = PD_DISPLAY,
2006 };
2007
2008 static int pd_gpu_mode(struct clk *clk, int on)
2009 {
2010         if (on) {
2011                 pmu_set_power_domain(PD_GPU, true);
2012         } else {
2013                 pmu_set_power_domain(PD_GPU, false);
2014         }
2015
2016         return 0;
2017 }
2018
2019 static struct clk pd_gpu = {
2020         .name   = "pd_gpu",
2021         .flags  = IS_PD,
2022         .mode   = pd_gpu_mode,
2023         .gate_idx       = PD_GPU,
2024 };
2025
2026
2027 #define CLK(dev, con, ck) \
2028         { \
2029                 .dev_id = dev, \
2030                 .con_id = con, \
2031                 .clk = ck, \
2032         }
2033
2034 #define CLK1(name) \
2035         { \
2036                 .dev_id = NULL, \
2037                 .con_id = #name, \
2038                 .clk = &clk_##name, \
2039         }
2040
2041 static struct clk_lookup clks[] = {
2042         CLK(NULL, "xin24m", &xin24m),
2043         CLK(NULL, "xin27m", &xin27m),
2044         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
2045         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
2046         CLK(NULL, "gpsclk", &gpsclk),
2047         CLK(NULL, "vip_clkin", &vip_clkin),
2048
2049         CLK1(12m),
2050         CLK(NULL, "arm_pll", &arm_pll_clk),
2051         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2052         CLK(NULL, "codec_pll", &codec_pll_clk),
2053         CLK(NULL, "general_pll", &general_pll_clk),
2054
2055         CLK1(core),
2056         CLK(NULL, "aclk_cpu", &aclk_cpu),
2057         CLK(NULL, "hclk_cpu", &hclk_cpu),
2058         CLK(NULL, "pclk_cpu", &pclk_cpu),
2059
2060         CLK(NULL, "aclk_periph", &aclk_periph),
2061         CLK(NULL, "hclk_periph", &hclk_periph),
2062         CLK(NULL, "pclk_periph", &pclk_periph),
2063
2064         CLK1(vip_out),
2065         CLK1(otgphy0),
2066         CLK1(otgphy1),
2067         CLK1(uhost),
2068         CLK1(mac_ref_div),
2069         CLK1(mac_ref),
2070
2071         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2072         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2073         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2074         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
2075         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
2076         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
2077         CLK(NULL, "spdif_div", &clk_spdif_div),
2078         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
2079         CLK(NULL, "spdif", &clk_spdif),
2080
2081         CLK1(spi_src),
2082         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2083         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2084
2085         CLK1(saradc),
2086         CLK1(timer0),
2087         CLK1(timer1),
2088         CLK1(timer2),
2089         CLK1(timer3),
2090
2091         CLK1(mmc_src),
2092         CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
2093         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
2094         CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
2095         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
2096         CLK1(emmc),
2097         CLK1(hclk_emmc),
2098         CLK1(ddr),
2099
2100         CLK1(uart01_src),
2101         CLK("rk29_serial.0", "uart", &clk_uart0),
2102         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
2103         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2104         CLK("rk29_serial.1", "uart", &clk_uart1),
2105         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
2106         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2107
2108         CLK1(uart23_src),
2109         CLK("rk29_serial.2", "uart", &clk_uart2),
2110         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
2111         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2112         CLK("rk29_serial.3", "uart", &clk_uart3),
2113         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
2114         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2115
2116         CLK1(hsadc_div),
2117         CLK1(hsadc_frac_div),
2118         CLK1(demod),
2119         CLK1(hsadc),
2120         CLK1(hsadc_div2),
2121         CLK1(hsadc_div2_inv),
2122         CLK1(hsadc_out),
2123
2124         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
2125         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
2126         CLK(NULL, "dclk_ebook", &dclk_ebook),
2127         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
2128         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
2129
2130         CLK(NULL, "aclk_vepu", &aclk_vepu),
2131         CLK(NULL, "hclk_vepu", &hclk_vepu),
2132         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
2133         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
2134         CLK1(gpu),
2135         CLK(NULL, "aclk_gpu", &aclk_gpu),
2136
2137         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
2138         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
2139         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
2140         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
2141
2142         CLK1(gpio0),
2143         CLK1(gpio1),
2144         CLK1(gpio2),
2145         CLK1(gpio3),
2146         CLK1(gpio4),
2147         CLK1(gpio5),
2148         CLK1(gpio6),
2149
2150         CLK1(dma1),
2151         CLK1(dma2),
2152
2153         CLK1(gic),
2154         CLK1(intmem),
2155         CLK1(rom),
2156         CLK1(ddr_phy),
2157         CLK1(ddr_reg),
2158         CLK1(ddr_cpu),
2159         CLK1(efuse),
2160         CLK1(tzpc),
2161         CLK1(debug),
2162         CLK1(tpiu),
2163         CLK1(rtc),
2164         CLK1(pmu),
2165         CLK1(grf),
2166
2167         CLK1(emem),
2168         CLK1(hclk_usb_peri),
2169         CLK1(aclk_ddr_peri),
2170         CLK1(aclk_cpu_peri),
2171         CLK1(aclk_smc),
2172         CLK1(smc),
2173         CLK1(hclk_mac),
2174         CLK1(mii_tx),
2175         CLK1(mii_rx),
2176         CLK1(hif),
2177         CLK1(nandc),
2178         CLK1(hclk_hsadc),
2179         CLK1(usbotg0),
2180         CLK1(usbotg1),
2181         CLK1(hclk_uhost),
2182         CLK1(pid_filter),
2183
2184         CLK1(vip_slave),
2185         CLK1(wdt),
2186         CLK1(pwm),
2187         CLK1(vip_bus),
2188         CLK1(vip_matrix),
2189         CLK1(vip_input),
2190         CLK1(jtag),
2191
2192         CLK1(aclk_ddr_lcdc),
2193         CLK1(aclk_ipp),
2194         CLK1(hclk_ipp),
2195         CLK1(hclk_ebook),
2196         CLK1(aclk_disp_matrix),
2197         CLK1(hclk_disp_matrix),
2198         CLK1(aclk_ddr_vepu),
2199         CLK1(aclk_ddr_vdpu),
2200         CLK1(aclk_ddr_gpu),
2201         CLK1(hclk_gpu),
2202         CLK1(hclk_cpu_vcodec),
2203         CLK1(hclk_cpu_display),
2204
2205         CLK(NULL, "pd_vcodec", &pd_vcodec),
2206         CLK(NULL, "pd_display", &pd_display),
2207         CLK(NULL, "pd_gpu", &pd_gpu),
2208 };
2209
2210 static LIST_HEAD(clocks);
2211 static DEFINE_MUTEX(clocks_mutex);
2212 static DEFINE_SPINLOCK(clockfw_lock);
2213 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
2214 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
2215
2216 static int clk_enable_nolock(struct clk *clk)
2217 {
2218         int ret = 0;
2219
2220         if (clk->usecount == 0) {
2221                 if (clk->parent) {
2222                         ret = clk_enable_nolock(clk->parent);
2223                         if (ret)
2224                                 return ret;
2225                 }
2226
2227                 if (clk->notifier_count)
2228                         clk_notify(clk, CLK_PRE_ENABLE, clk->rate, clk->rate);
2229                 if (clk->mode)
2230                         ret = clk->mode(clk, 1);
2231                 if (clk->notifier_count)
2232                         clk_notify(clk, ret ? CLK_ABORT_ENABLE : CLK_POST_ENABLE, clk->rate, clk->rate);
2233                 if (ret) {
2234                         if (clk->parent)
2235                                 clk_disable_nolock(clk->parent);
2236                         return ret;
2237                 }
2238                 pr_debug("%s enabled\n", clk->name);
2239         }
2240         clk->usecount++;
2241
2242         return ret;
2243 }
2244
2245 int clk_enable(struct clk *clk)
2246 {
2247         int ret = 0;
2248
2249         if (clk == NULL || IS_ERR(clk))
2250                 return -EINVAL;
2251
2252         LOCK();
2253         ret = clk_enable_nolock(clk);
2254         UNLOCK();
2255
2256         return ret;
2257 }
2258 EXPORT_SYMBOL(clk_enable);
2259
2260 static void clk_disable_nolock(struct clk *clk)
2261 {
2262         if (clk->usecount == 0) {
2263                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
2264                 WARN_ON(1);
2265                 return;
2266         }
2267
2268         if (--clk->usecount == 0) {
2269                 int ret = 0;
2270                 if (clk->notifier_count)
2271                         clk_notify(clk, CLK_PRE_DISABLE, clk->rate, clk->rate);
2272                 if (clk->mode)
2273                         ret = clk->mode(clk, 0);
2274                 if (clk->notifier_count)
2275                         clk_notify(clk, ret ? CLK_ABORT_DISABLE : CLK_POST_DISABLE, clk->rate, clk->rate);
2276                 pr_debug("%s disabled\n", clk->name);
2277                 if (ret == 0 && clk->parent)
2278                         clk_disable_nolock(clk->parent);
2279         }
2280 }
2281
2282 void clk_disable(struct clk *clk)
2283 {
2284         if (clk == NULL || IS_ERR(clk))
2285                 return;
2286
2287         LOCK();
2288         clk_disable_nolock(clk);
2289         UNLOCK();
2290 }
2291 EXPORT_SYMBOL(clk_disable);
2292
2293 unsigned long clk_get_rate(struct clk *clk)
2294 {
2295         if (clk == NULL || IS_ERR(clk))
2296                 return 0;
2297
2298         return clk->rate;
2299 }
2300 EXPORT_SYMBOL(clk_get_rate);
2301
2302 /*-------------------------------------------------------------------------
2303  * Optional clock functions defined in include/linux/clk.h
2304  *-------------------------------------------------------------------------*/
2305
2306 /* Given a clock and a rate apply a clock specific rounding function */
2307 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
2308 {
2309         if (clk->round_rate)
2310                 return clk->round_rate(clk, rate);
2311
2312         if (clk->flags & RATE_FIXED)
2313                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
2314
2315         return clk->rate;
2316 }
2317
2318 long clk_round_rate(struct clk *clk, unsigned long rate)
2319 {
2320         long ret = 0;
2321
2322         if (clk == NULL || IS_ERR(clk))
2323                 return ret;
2324
2325         LOCK();
2326         ret = clk_round_rate_nolock(clk, rate);
2327         UNLOCK();
2328
2329         return ret;
2330 }
2331 EXPORT_SYMBOL(clk_round_rate);
2332
2333 static void __clk_recalc(struct clk *clk)
2334 {
2335         if (unlikely(clk->flags & RATE_FIXED))
2336                 return;
2337         if (clk->recalc)
2338                 clk->rate = clk->recalc(clk);
2339         else if (clk->parent)
2340                 clk->rate = clk->parent->rate;
2341         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
2342 }
2343
2344 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
2345 {
2346         int ret;
2347         unsigned long old_rate;
2348
2349         if (rate == clk->rate)
2350                 return 0;
2351
2352         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
2353
2354         if (clk->flags & CONFIG_PARTICIPANT)
2355                 return -EINVAL;
2356
2357         if (!clk->set_rate)
2358                 return -EINVAL;
2359
2360         old_rate = clk->rate;
2361         if (clk->notifier_count)
2362                 clk_notify(clk, CLK_PRE_RATE_CHANGE, old_rate, rate);
2363
2364         ret = clk->set_rate(clk, rate);
2365
2366         if (ret == 0) {
2367                 __clk_recalc(clk);
2368                 __propagate_rate(clk);
2369         }
2370
2371         if (clk->notifier_count)
2372                 clk_notify(clk, ret ? CLK_ABORT_RATE_CHANGE : CLK_POST_RATE_CHANGE, old_rate, clk->rate);
2373
2374         return ret;
2375 }
2376
2377 /* Set the clock rate for a clock source */
2378 int clk_set_rate(struct clk *clk, unsigned long rate)
2379 {
2380         int ret = -EINVAL;
2381
2382         if (clk == NULL || IS_ERR(clk))
2383                 return ret;
2384
2385         LOCK();
2386         ret = clk_set_rate_nolock(clk, rate);
2387         UNLOCK();
2388
2389         return ret;
2390 }
2391 EXPORT_SYMBOL(clk_set_rate);
2392
2393 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
2394 {
2395         int ret;
2396         int enabled = clk->usecount > 0;
2397         struct clk *old_parent = clk->parent;
2398
2399         if (clk->parent == parent)
2400                 return 0;
2401
2402         /* if clk is already enabled, enable new parent first and disable old parent later. */
2403         if (enabled)
2404                 clk_enable_nolock(parent);
2405
2406         if (clk->set_parent)
2407                 ret = clk->set_parent(clk, parent);
2408         else
2409                 ret = clksel_set_parent(clk, parent);
2410
2411         if (ret == 0) {
2412                 /* OK */
2413                 __clk_reparent(clk, parent);
2414                 __clk_recalc(clk);
2415                 __propagate_rate(clk);
2416                 if (enabled)
2417                         clk_disable_nolock(old_parent);
2418         } else {
2419                 if (enabled)
2420                         clk_disable_nolock(parent);
2421         }
2422
2423         return ret;
2424 }
2425
2426 int clk_set_parent(struct clk *clk, struct clk *parent)
2427 {
2428         int ret = -EINVAL;
2429
2430         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
2431                 return ret;
2432
2433         if (clk->set_parent == NULL && clk->parents == NULL)
2434                 return ret;
2435
2436         LOCK();
2437         if (clk->usecount == 0)
2438                 ret = clk_set_parent_nolock(clk, parent);
2439         else
2440                 ret = -EBUSY;
2441         UNLOCK();
2442
2443         return ret;
2444 }
2445 EXPORT_SYMBOL(clk_set_parent);
2446
2447 struct clk *clk_get_parent(struct clk *clk)
2448 {
2449         return clk->parent;
2450 }
2451 EXPORT_SYMBOL(clk_get_parent);
2452
2453 static void __clk_reparent(struct clk *child, struct clk *parent)
2454 {
2455         if (child->parent == parent)
2456                 return;
2457         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
2458
2459         list_del_init(&child->sibling);
2460         if (parent)
2461                 list_add(&child->sibling, &parent->children);
2462         child->parent = parent;
2463 }
2464
2465 /* Propagate rate to children */
2466 static void __propagate_rate(struct clk *tclk)
2467 {
2468         struct clk *clkp;
2469
2470         list_for_each_entry(clkp, &tclk->children, sibling) {
2471                 __clk_recalc(clkp);
2472                 __propagate_rate(clkp);
2473         }
2474 }
2475
2476 static LIST_HEAD(root_clks);
2477
2478 /**
2479  * recalculate_root_clocks - recalculate and propagate all root clocks
2480  *
2481  * Recalculates all root clocks (clocks with no parent), which if the
2482  * clock's .recalc is set correctly, should also propagate their rates.
2483  * Called at init.
2484  */
2485 static void clk_recalculate_root_clocks_nolock(void)
2486 {
2487         struct clk *clkp;
2488
2489         list_for_each_entry(clkp, &root_clks, sibling) {
2490                 __clk_recalc(clkp);
2491                 __propagate_rate(clkp);
2492         }
2493 }
2494
2495 void clk_recalculate_root_clocks(void)
2496 {
2497         LOCK();
2498         clk_recalculate_root_clocks_nolock();
2499         UNLOCK();
2500 }
2501
2502
2503 /**
2504  * clk_preinit - initialize any fields in the struct clk before clk init
2505  * @clk: struct clk * to initialize
2506  *
2507  * Initialize any struct clk fields needed before normal clk initialization
2508  * can run.  No return value.
2509  */
2510 static void clk_preinit(struct clk *clk)
2511 {
2512         INIT_LIST_HEAD(&clk->children);
2513 }
2514
2515 static int clk_register(struct clk *clk)
2516 {
2517         if (clk == NULL || IS_ERR(clk))
2518                 return -EINVAL;
2519
2520         /*
2521          * trap out already registered clocks
2522          */
2523         if (clk->node.next || clk->node.prev)
2524                 return 0;
2525
2526         mutex_lock(&clocks_mutex);
2527
2528         if (clk->get_parent)
2529                 clk->parent = clk->get_parent(clk);
2530         else if (clk->parents)
2531                 clk->parent = clksel_get_parent(clk);
2532
2533         if (clk->parent)
2534                 list_add(&clk->sibling, &clk->parent->children);
2535         else
2536                 list_add(&clk->sibling, &root_clks);
2537
2538         list_add(&clk->node, &clocks);
2539
2540         mutex_unlock(&clocks_mutex);
2541
2542         return 0;
2543 }
2544
2545 static unsigned int __initdata armclk = 300 * MHZ;
2546
2547 /*
2548  * You can override arm_clk rate with armclk= cmdline option.
2549  */
2550 static int __init armclk_setup(char *str)
2551 {
2552         get_option(&str, &armclk);
2553
2554         if (!armclk)
2555                 return 0;
2556
2557         if (armclk < 10000)
2558                 armclk *= MHZ;
2559
2560         clk_set_rate_nolock(&arm_pll_clk, armclk);
2561         return 0;
2562 }
2563 early_param("armclk", armclk_setup);
2564
2565 static void __init rk29_clock_common_init(unsigned long ppll_rate, unsigned long cpll_rate)
2566 {
2567         unsigned long aclk_p, hclk_p, pclk_p;
2568         struct clk *aclk_vepu_parent, *aclk_vdpu_parent, *aclk_gpu_parent;
2569
2570         /* general pll */
2571         switch (ppll_rate) {
2572         case 96 * MHZ:
2573                 aclk_p = 96 * MHZ;
2574                 hclk_p = 48 * MHZ;
2575                 pclk_p = 24 * MHZ;
2576                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
2577                 break;
2578         case 144 * MHZ:
2579                 aclk_p = 144 * MHZ;
2580                 hclk_p = 72 * MHZ;
2581                 pclk_p = 36 * MHZ;
2582                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
2583                 break;
2584         default:
2585                 ppll_rate = 288 * MHZ;
2586         case 288 * MHZ:
2587         case 300 * MHZ:
2588                 aclk_p = ppll_rate / 2;
2589                 hclk_p = ppll_rate / 2;
2590                 pclk_p = ppll_rate / 8;
2591                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &general_pll_clk;
2592                 break;
2593         }
2594
2595         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
2596         lpj_gpll = div_u64(LPJ_600MHZ * general_pll_clk.rate, 600 * MHZ);
2597         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2598         clk_set_rate_nolock(&aclk_periph, aclk_p);
2599         clk_set_rate_nolock(&hclk_periph, hclk_p);
2600         clk_set_rate_nolock(&pclk_periph, pclk_p);
2601         clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
2602         clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2603         if (clk_uhost.rate != 48 * MHZ)
2604                 clk_set_parent_nolock(&clk_uhost, &otgphy1_clkin);
2605         clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
2606         clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
2607         clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
2608         clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
2609         clk_set_rate_nolock(&clk_spi0, 40 * MHZ);
2610         clk_set_rate_nolock(&clk_spi1, 40 * MHZ);
2611         clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
2612         clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
2613         clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
2614         clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
2615         clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
2616         clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
2617
2618         /* codec pll */
2619         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
2620         clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
2621
2622         /* ddr pll */
2623         clk_set_parent_nolock(&aclk_lcdc, &ddr_pll_clk);
2624
2625         /* arm pll */
2626         clk_set_rate_nolock(&arm_pll_clk, armclk);
2627
2628         /*you can choose clk parent form codec pll or periph pll for following logic*/
2629         clk_set_parent_nolock(&aclk_vepu, aclk_vepu_parent);
2630         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
2631         clk_set_rate_nolock(&clk_aclk_ddr_vepu, 300 * MHZ);
2632         clk_set_rate_nolock(&hclk_vepu, 150 * MHZ);
2633         clk_set_parent_nolock(&aclk_vdpu, aclk_vdpu_parent);
2634         clk_set_parent_nolock(&aclk_gpu, aclk_gpu_parent);
2635         clk_set_rate_nolock(&aclk_gpu, 300 * MHZ);
2636 }
2637
2638 static void __init clk_enable_init_clocks(void)
2639 {
2640         clk_enable_nolock(&hclk_cpu);
2641         clk_enable_nolock(&pclk_cpu);
2642         clk_enable_nolock(&hclk_periph);
2643         clk_enable_nolock(&pclk_periph);
2644         clk_enable_nolock(&clk_nandc);
2645         clk_enable_nolock(&clk_aclk_cpu_peri);
2646         clk_enable_nolock(&clk_aclk_ddr_peri);
2647         clk_enable_nolock(&clk_grf);
2648         clk_enable_nolock(&clk_pmu);
2649         clk_enable_nolock(&clk_ddr_cpu);
2650         clk_enable_nolock(&clk_ddr_reg);
2651         clk_enable_nolock(&clk_ddr_phy);
2652         clk_enable_nolock(&clk_gic);
2653         clk_enable_nolock(&clk_dma2);
2654         clk_enable_nolock(&clk_dma1);
2655         clk_enable_nolock(&clk_emem);
2656         clk_enable_nolock(&clk_intmem);
2657         clk_enable_nolock(&clk_ddr);
2658         clk_enable_nolock(&clk_debug);
2659         clk_enable_nolock(&clk_tpiu);
2660         clk_enable_nolock(&clk_jtag);
2661         clk_enable_nolock(&clk_uart1);
2662 }
2663
2664 static int __init clk_disable_unused(void)
2665 {
2666         struct clk *ck;
2667
2668         list_for_each_entry(ck, &clocks, node) {
2669                 if (ck->usecount > 0 || ck->mode == NULL || (ck->flags & IS_PD))
2670                         continue;
2671
2672                 LOCK();
2673                 clk_enable_nolock(ck);
2674                 clk_disable_nolock(ck);
2675                 UNLOCK();
2676         }
2677
2678         return 0;
2679 }
2680
2681 void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate, bool _has_xin27m)
2682 {
2683         struct clk_lookup *lk;
2684
2685         has_xin27m = _has_xin27m;
2686
2687         cru_clkgate3_con_mirror = cru_readl(CRU_CLKGATE3_CON);
2688         cru_softrst0_con_mirror = cru_readl(CRU_SOFTRST0_CON);
2689
2690         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2691                 clk_preinit(lk->clk);
2692
2693         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2694                 clkdev_add(lk);
2695                 clk_register(lk->clk);
2696         }
2697
2698         clk_recalculate_root_clocks_nolock();
2699
2700         loops_per_jiffy = div_u64(LPJ_600MHZ * arm_pll_clk.rate, 600 * MHZ);
2701
2702         /*
2703          * Only enable those clocks we will need, let the drivers
2704          * enable other clocks as necessary
2705          */
2706         clk_enable_init_clocks();
2707
2708         /*
2709          * Disable any unused clocks left on by the bootloader
2710          */
2711         clk_disable_unused();
2712
2713         rk29_clock_common_init(ppll_rate, cpll_rate);
2714
2715         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz",
2716                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
2717                aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
2718         printk(KERN_CONT " (20110812)\n");
2719
2720         preset_lpj = loops_per_jiffy;
2721 }
2722
2723 void __init rk29_clock_init(enum periph_pll ppll_rate)
2724 {
2725         rk29_clock_init2(ppll_rate, codec_pll_297mhz, true);
2726 }
2727
2728 #ifdef CONFIG_PROC_FS
2729 #include <linux/proc_fs.h>
2730 #include <linux/seq_file.h>
2731
2732 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2733 {
2734         struct clk* ck;
2735         int i;
2736         unsigned long rate = clk->rate;
2737
2738         for (i = 0; i < deep; i++)
2739                 seq_printf(s, "    ");
2740
2741         seq_printf(s, "%-11s ", clk->name);
2742
2743         if (clk->flags & IS_PD) {
2744                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
2745         }
2746
2747         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
2748                 u32 reg;
2749                 int idx = clk->gate_idx;
2750                 u32 v;
2751
2752                 reg = CRU_CLKGATE0_CON;
2753                 reg += (idx >> 5) << 2;
2754                 idx &= 0x1F;
2755
2756                 if (reg == CRU_CLKGATE3_CON)
2757                         v = cru_clkgate3_con_mirror & (1 << idx);
2758                 else
2759                         v = cru_readl(reg) & (1 << idx);
2760
2761                 seq_printf(s, "%s ", v ? "off" : "on ");
2762         }
2763
2764         if (clk == &arm_pll_clk) {
2765                 switch (cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) {
2766                 case CRU_CPU_MODE_SLOW:   seq_printf(s, "slow   "); break;
2767                 case CRU_CPU_MODE_NORMAL: seq_printf(s, "normal "); break;
2768                 case CRU_CPU_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2769                 }
2770                 if (cru_readl(CRU_APLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2771         } else if (clk == &ddr_pll_clk) {
2772                 switch (cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) {
2773                 case CRU_DDR_MODE_SLOW:   seq_printf(s, "slow   "); break;
2774                 case CRU_DDR_MODE_NORMAL: seq_printf(s, "normal "); break;
2775                 case CRU_DDR_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2776                 }
2777                 if (cru_readl(CRU_DPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2778         } else if (clk == &codec_pll_clk) {
2779                 switch (cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) {
2780                 case CRU_CODEC_MODE_SLOW:   seq_printf(s, "slow   "); break;
2781                 case CRU_CODEC_MODE_NORMAL: seq_printf(s, "normal "); break;
2782                 case CRU_CODEC_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2783                 }
2784                 if (cru_readl(CRU_CPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2785         } else if (clk == &general_pll_clk) {
2786                 switch (cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) {
2787                 case CRU_GENERAL_MODE_SLOW:   seq_printf(s, "slow   "); break;
2788                 case CRU_GENERAL_MODE_NORMAL: seq_printf(s, "normal "); break;
2789                 case CRU_GENERAL_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2790                 }
2791                 if (cru_readl(CRU_GPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2792         }
2793
2794         if (rate >= MHZ) {
2795                 if (rate % MHZ)
2796                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2797                 else
2798                         seq_printf(s, "%ld MHz", rate / MHZ);
2799         } else if (rate >= KHZ) {
2800                 if (rate % KHZ)
2801                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2802                 else
2803                         seq_printf(s, "%ld KHz", rate / KHZ);
2804         } else {
2805                 seq_printf(s, "%ld Hz", rate);
2806         }
2807
2808         seq_printf(s, " usecount = %d", clk->usecount);
2809
2810         if (clk->parent)
2811                 seq_printf(s, " parent = %s", clk->parent->name);
2812
2813         seq_printf(s, "\n");
2814
2815         list_for_each_entry(ck, &clocks, node) {
2816                 if (ck->parent == clk)
2817                         dump_clock(s, ck, deep + 1);
2818         }
2819 }
2820
2821 static int proc_clk_show(struct seq_file *s, void *v)
2822 {
2823         struct clk* clk;
2824
2825         mutex_lock(&clocks_mutex);
2826         list_for_each_entry(clk, &clocks, node) {
2827                 if (!clk->parent)
2828                         dump_clock(s, clk, 0);
2829         }
2830         mutex_unlock(&clocks_mutex);
2831
2832         seq_printf(s, "\nCRU Registers:\n");
2833         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2834         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2835         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2836         seq_printf(s, "GPLL     : 0x%08x\n", cru_readl(CRU_GPLL_CON));
2837         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2838         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2839         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2840         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2841         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2842         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2843         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2844         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2845         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2846         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2847         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2848         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2849         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2850         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2851         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2852         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2853         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2854         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2855         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2856         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2857         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2858         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2859         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2860         seq_printf(s, "CLKGATE3M: 0x%08x\n", cru_clkgate3_con_mirror);
2861         seq_printf(s, "SOFTRST0 : 0x%08x\n", cru_readl(CRU_SOFTRST0_CON));
2862         seq_printf(s, "SOFTRST0M: 0x%08x\n", cru_softrst0_con_mirror);
2863         seq_printf(s, "SOFTRST1 : 0x%08x\n", cru_readl(CRU_SOFTRST1_CON));
2864         seq_printf(s, "SOFTRST2 : 0x%08x\n", cru_readl(CRU_SOFTRST2_CON));
2865
2866         seq_printf(s, "\nPMU Registers:\n");
2867         seq_printf(s, "WAKEUP_EN0 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN0));
2868         seq_printf(s, "WAKEUP_EN1 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN1));
2869         seq_printf(s, "WAKEUP_EN2 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN2));
2870         seq_printf(s, "PD_CON     : 0x%08x\n", pmu_readl(PMU_PD_CON));
2871         seq_printf(s, "MISC_CON   : 0x%08x\n", pmu_readl(PMU_MISC_CON));
2872         seq_printf(s, "PLL_CNT    : 0x%08x\n", pmu_readl(PMU_PLL_CNT));
2873         seq_printf(s, "PD_ST      : 0x%08x\n", pmu_readl(PMU_PD_ST));
2874         seq_printf(s, "INT_ST     : 0x%08x\n", pmu_readl(PMU_INT_ST));
2875
2876         return 0;
2877 }
2878
2879 static int proc_clk_open(struct inode *inode, struct file *file)
2880 {
2881         return single_open(file, proc_clk_show, NULL);
2882 }
2883
2884 static const struct file_operations proc_clk_fops = {
2885         .open           = proc_clk_open,
2886         .read           = seq_read,
2887         .llseek         = seq_lseek,
2888         .release        = single_release,
2889 };
2890
2891 static int __init clk_proc_init(void)
2892 {
2893         proc_create("clocks", 0, NULL, &proc_clk_fops);
2894         return 0;
2895
2896 }
2897 late_initcall(clk_proc_init);
2898 #endif /* CONFIG_PROC_FS */
2899
2900 /* Clk notifier implementation */
2901
2902 /**
2903  * struct clk_notifier - associate a clk with a notifier
2904  * @clk: struct clk * to associate the notifier with
2905  * @notifier_head: a atomic_notifier_head for this clk
2906  * @node: linked list pointers
2907  *
2908  * A list of struct clk_notifier is maintained by the notifier code.
2909  * An entry is created whenever code registers the first notifier on a
2910  * particular @clk.  Future notifiers on that @clk are added to the
2911  * @notifier_head.
2912  */
2913 struct clk_notifier {
2914         struct clk                      *clk;
2915         struct atomic_notifier_head     notifier_head;
2916         struct list_head                node;
2917 };
2918
2919 static LIST_HEAD(clk_notifier_list);
2920
2921 /**
2922  * _clk_free_notifier_chain - safely remove struct clk_notifier
2923  * @cn: struct clk_notifier *
2924  *
2925  * Removes the struct clk_notifier @cn from the clk_notifier_list and
2926  * frees it.
2927  */
2928 static void _clk_free_notifier_chain(struct clk_notifier *cn)
2929 {
2930         list_del(&cn->node);
2931         kfree(cn);
2932 }
2933
2934 /**
2935  * clk_notify - call clk notifier chain
2936  * @clk: struct clk * that is changing rate
2937  * @msg: clk notifier type (i.e., CLK_POST_RATE_CHANGE; see mach/clock.h)
2938  * @old_rate: old rate
2939  * @new_rate: new rate
2940  *
2941  * Triggers a notifier call chain on the post-clk-rate-change notifier
2942  * for clock 'clk'.  Passes a pointer to the struct clk and the
2943  * previous and current rates to the notifier callback.  Intended to be
2944  * called by internal clock code only.  No return value.
2945  */
2946 static void clk_notify(struct clk *clk, unsigned long msg,
2947                        unsigned long old_rate, unsigned long new_rate)
2948 {
2949         struct clk_notifier *cn;
2950         struct clk_notifier_data cnd;
2951
2952         cnd.clk = clk;
2953         cnd.old_rate = old_rate;
2954         cnd.new_rate = new_rate;
2955
2956         list_for_each_entry(cn, &clk_notifier_list, node) {
2957                 if (cn->clk == clk) {
2958                         pr_debug("%s msg %lu rate %lu -> %lu\n", clk->name, msg, old_rate, new_rate);
2959                         atomic_notifier_call_chain(&cn->notifier_head, msg, &cnd);
2960                         break;
2961                 }
2962         }
2963 }
2964
2965 /**
2966  * clk_notifier_register - add a clock parameter change notifier
2967  * @clk: struct clk * to watch
2968  * @nb: struct notifier_block * with callback info
2969  *
2970  * Request notification for changes to the clock 'clk'.  This uses a
2971  * blocking notifier.  Callback code must not call into the clock
2972  * framework, as clocks_mutex is held.  Pre-notifier callbacks will be
2973  * passed the previous and new rate of the clock.
2974  *
2975  * clk_notifier_register() must be called from process
2976  * context.  Returns -EINVAL if called with null arguments, -ENOMEM
2977  * upon allocation failure; otherwise, passes along the return value
2978  * of blocking_notifier_chain_register().
2979  */
2980 int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2981 {
2982         struct clk_notifier *cn = NULL, *cn_new = NULL;
2983         int r;
2984         struct clk *clkp;
2985
2986         if (!clk || !nb)
2987                 return -EINVAL;
2988
2989         mutex_lock(&clocks_mutex);
2990
2991         list_for_each_entry(cn, &clk_notifier_list, node)
2992                 if (cn->clk == clk)
2993                         break;
2994
2995         if (cn->clk != clk) {
2996                 cn_new = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2997                 if (!cn_new) {
2998                         r = -ENOMEM;
2999                         goto cnr_out;
3000                 };
3001
3002                 cn_new->clk = clk;
3003                 ATOMIC_INIT_NOTIFIER_HEAD(&cn_new->notifier_head);
3004
3005                 list_add(&cn_new->node, &clk_notifier_list);
3006                 cn = cn_new;
3007         }
3008
3009         r = atomic_notifier_chain_register(&cn->notifier_head, nb);
3010         if (!IS_ERR_VALUE(r)) {
3011                 clkp = clk;
3012                 do {
3013                         clkp->notifier_count++;
3014                 } while ((clkp = clkp->parent));
3015         } else {
3016                 if (cn_new)
3017                         _clk_free_notifier_chain(cn);
3018         }
3019
3020 cnr_out:
3021         mutex_unlock(&clocks_mutex);
3022
3023         return r;
3024 }
3025 EXPORT_SYMBOL(clk_notifier_register);
3026
3027 /**
3028  * clk_notifier_unregister - remove a clock change notifier
3029  * @clk: struct clk *
3030  * @nb: struct notifier_block * with callback info
3031  *
3032  * Request no further notification for changes to clock 'clk'.
3033  * Returns -EINVAL if called with null arguments; otherwise, passes
3034  * along the return value of blocking_notifier_chain_unregister().
3035  */
3036 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
3037 {
3038         struct clk_notifier *cn = NULL;
3039         struct clk *clkp;
3040         int r = -EINVAL;
3041
3042         if (!clk || !nb)
3043                 return -EINVAL;
3044
3045         mutex_lock(&clocks_mutex);
3046
3047         list_for_each_entry(cn, &clk_notifier_list, node)
3048                 if (cn->clk == clk)
3049                         break;
3050
3051         if (cn->clk != clk) {
3052                 r = -ENOENT;
3053                 goto cnu_out;
3054         };
3055
3056         r = atomic_notifier_chain_unregister(&cn->notifier_head, nb);
3057         if (!IS_ERR_VALUE(r)) {
3058                 clkp = clk;
3059                 do {
3060                         clkp->notifier_count--;
3061                 } while ((clkp = clkp->parent));
3062         }
3063
3064         /*
3065          * XXX ugh, layering violation.  There should be some
3066          * support in the notifier code for this.
3067          */
3068         if (!cn->notifier_head.head)
3069                 _clk_free_notifier_chain(cn);
3070
3071 cnu_out:
3072         mutex_unlock(&clocks_mutex);
3073
3074         return r;
3075 }
3076 EXPORT_SYMBOL(clk_notifier_unregister);
3077