arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33 #include <mach/pmu.h>
  34 #include <mach/sram.h>
  35 #include <mach/board.h>
  36
  37
  38 /* Clock flags */
  39 /* bit 0 is free */
  40 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  41 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  42 #define IS_PD                   (1 << 2)        /* Power Domain */
  43
  44 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  45 #define pmu_readl(offset)       readl(RK29_PMU_BASE + offset)
  46
  47 #define MHZ                     (1000*1000)
  48 #define KHZ                     1000
  49
  50 struct clk {
  51         struct list_head        node;
  52         const char              *name;
  53         struct clk              *parent;
  54         struct list_head        children;
  55         struct list_head        sibling;        /* node for children */
  56         unsigned long           rate;
  57         u32                     flags;
  58         int                     (*mode)(struct clk *clk, int on);
  59         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  60         int                     (*set_rate)(struct clk *, unsigned long);
  61         long                    (*round_rate)(struct clk *, unsigned long);
  62         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
  63         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
  64         s32                     usecount;
  65         u8                      gate_idx;
  66         u8                      pll_idx;
  67         u8                      clksel_con;
  68         u8                      clksel_mask;
  69         u8                      clksel_shift;
  70         u8                      clksel_maxdiv;
  71         u8                      clksel_parent_mask;
  72         u8                      clksel_parent_shift;
  73         struct clk              **parents;
  74 };
  75
  76 static int clk_enable_nolock(struct clk *clk);
  77 static void clk_disable_nolock(struct clk *clk);
  78 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
  79 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
  80 static void __clk_reparent(struct clk *child, struct clk *parent);
  81 static void __propagate_rate(struct clk *tclk);
  82 static struct clk codec_pll_clk;
  83 static struct clk general_pll_clk;
  84 static bool has_xin27m = true;
  85
  86 static unsigned long clksel_recalc_div(struct clk *clk)
  87 {
  88         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
  89         unsigned long rate = clk->parent->rate / div;
  90         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
  91         return rate;
  92 }
  93
  94 static unsigned long clksel_recalc_shift(struct clk *clk)
  95 {
  96         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
  97         unsigned long rate = clk->parent->rate >> shift;
  98         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
  99         return rate;
 100 }
 101
 102 static unsigned long clksel_recalc_frac(struct clk *clk)
 103 {
 104         unsigned long rate;
 105         u64 rate64;
 106         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 107         if (r == 0) // FPGA ?
 108                 return clk->parent->rate;
 109         numerator = r >> 16;
 110         denominator = r & 0xFFFF;
 111         rate64 = (u64)clk->parent->rate * numerator;
 112         do_div(rate64, denominator);
 113         rate = rate64;
 114         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 115         return rate;
 116 }
 117
 118 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 119 {
 120         u32 div;
 121
 122         for (div = 0; div <= clk->clksel_mask; div++) {
 123                 u32 new_rate = clk->parent->rate / (div + 1);
 124                 if (new_rate <= rate) {
 125                         u32 v = cru_readl(clk->clksel_con);
 126                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 127                         v |= div << clk->clksel_shift;
 128                         cru_writel(v, clk->clksel_con);
 129                         clk->rate = new_rate;
 130                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 131                         return 0;
 132                 }
 133         }
 134
 135         return -ENOENT;
 136 }
 137
 138 static long clksel_round_rate_div(struct clk *clk, unsigned long rate)
 139 {
 140         u32 div;
 141         unsigned long prev = ULONG_MAX, actual;
 142
 143         for (div = 0; div <= clk->clksel_mask; div++) {
 144                 actual = clk->parent->rate / (div + 1);
 145                 if (actual > rate)
 146                         prev = actual;
 147                 if (actual && actual <= rate) {
 148                         if ((prev - rate) <= (rate - actual)) {
 149                                 actual = prev;
 150                                 div--;
 151                         }
 152                         break;
 153                 }
 154         }
 155         if (div > clk->clksel_mask)
 156                 div = clk->clksel_mask;
 157         pr_debug("clock %s, target rate %ld, rounded rate %ld (div %d)\n", clk->name, rate, actual, div + 1);
 158
 159         return actual;
 160 }
 161
 162 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 163 {
 164         u32 shift;
 165
 166         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 167                 u32 new_rate = clk->parent->rate >> shift;
 168                 if (new_rate <= rate) {
 169                         u32 v = cru_readl(clk->clksel_con);
 170                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 171                         v |= shift << clk->clksel_shift;
 172                         cru_writel(v, clk->clksel_con);
 173                         clk->rate = new_rate;
 174                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 175                         return 0;
 176                 }
 177         }
 178
 179         return -ENOENT;
 180 }
 181
 182 static struct clk* clksel_get_parent(struct clk *clk)
 183 {
 184         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 185 }
 186
 187 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 188 {
 189         struct clk **p = clk->parents;
 190         u32 i;
 191
 192         if (unlikely(!p))
 193                 return -EINVAL;
 194         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 195                 u32 v;
 196                 if (*p != parent)
 197                         continue;
 198                 v = cru_readl(clk->clksel_con);
 199                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 200                 v |= (i << clk->clksel_parent_shift);
 201                 cru_writel(v, clk->clksel_con);
 202                 return 0;
 203         }
 204         return -EINVAL;
 205 }
 206
 207 /* Work around CRU_CLKGATE3_CON bit21~20 bug */
 208 volatile u32 cru_clkgate3_con_mirror;
 209
 210 static int gate_mode(struct clk *clk, int on)
 211 {
 212         u32 reg;
 213         int idx = clk->gate_idx;
 214         u32 v;
 215
 216         if (idx >= CLK_GATE_MAX)
 217                 return -EINVAL;
 218
 219         reg = CRU_CLKGATE0_CON;
 220         reg += (idx >> 5) << 2;
 221         idx &= 0x1F;
 222
 223         if (reg == CRU_CLKGATE3_CON)
 224                 v = cru_clkgate3_con_mirror;
 225         else
 226                 v = cru_readl(reg);
 227
 228         if (on)
 229                 v &= ~(1 << idx);       // clear bit
 230         else
 231                 v |= (1 << idx);        // set bit
 232
 233         if (reg == CRU_CLKGATE3_CON)
 234                 cru_clkgate3_con_mirror = v;
 235         cru_writel(v, reg);
 236
 237         return 0;
 238 }
 239
 240 /* Work around CRU_SOFTRST0_CON bit29~27 bug */
 241 static volatile u32 cru_softrst0_con_mirror;
 242
 243 void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 244 {
 245         unsigned long flags;
 246         u32 reg = CRU_SOFTRST0_CON + ((idx >> 5) << 2);
 247         u32 mask = 1 << (idx & 31);
 248         u32 v;
 249
 250         if (idx >= SOFT_RST_MAX)
 251                 return;
 252
 253         local_irq_save(flags);
 254
 255         if (reg == CRU_SOFTRST0_CON)
 256                 v = cru_softrst0_con_mirror;
 257         else
 258                 v = cru_readl(reg);
 259
 260         if (on)
 261                 v |= mask;
 262         else
 263                 v &= ~mask;
 264
 265         if (reg == CRU_SOFTRST0_CON)
 266                 cru_softrst0_con_mirror = v;
 267         cru_writel(v, reg);
 268
 269         local_irq_restore(flags);
 270 }
 271
 272 static struct clk xin24m = {
 273         .name           = "xin24m",
 274         .rate           = 24 * MHZ,
 275         .flags          = RATE_FIXED,
 276 };
 277
 278 static struct clk clk_12m = {
 279         .name           = "clk_12m",
 280         .rate           = 12 * MHZ,
 281         .parent         = &xin24m,
 282         .flags          = RATE_FIXED,
 283 };
 284
 285 static struct clk xin27m = {
 286         .name           = "xin27m",
 287         .rate           = 27 * MHZ,
 288         .flags          = RATE_FIXED,
 289 };
 290
 291 static struct clk otgphy0_clkin = {
 292         .name           = "otgphy0_clkin",
 293         .rate           = 480 * MHZ,
 294         .flags          = RATE_FIXED,
 295 };
 296
 297 static struct clk otgphy1_clkin = {
 298         .name           = "otgphy1_clkin",
 299         .rate           = 480 * MHZ,
 300         .flags          = RATE_FIXED,
 301 };
 302
 303
 304 static noinline void delay_500ns(void)
 305 {
 306         if (system_state == SYSTEM_BOOTING) {
 307                 LOOP(LOOPS_PER_USEC * 1200 / 24);
 308         } else {
 309                 udelay(1);
 310         }
 311 }
 312
 313 static noinline void delay_300us(void)
 314 {
 315         if (system_state == SYSTEM_BOOTING) {
 316                 LOOP(LOOPS_PER_MSEC * 1200 / 24);
 317         } else {
 318                 mdelay(1);
 319         }
 320 }
 321
 322 static noinline void arm_delay_500ns(void)
 323 {
 324         static unsigned long loops = 0;
 325         if (!loops) {
 326                 loops = general_pll_clk.rate / MHZ;
 327                 loops = loops * LOOPS_PER_USEC / 24;
 328         }
 329         LOOP(loops);
 330 }
 331
 332 static noinline void arm_delay_300us(void)
 333 {
 334         static unsigned long loops = 0;
 335         if (!loops) {
 336                 loops = general_pll_clk.rate / MHZ;
 337                 loops = loops * LOOPS_PER_MSEC / 24;
 338         }
 339         LOOP(loops);
 340 }
 341
 342 #define GENERAL_PLL_IDX     0
 343 #define CODEC_PLL_IDX      1
 344 #define ARM_PLL_IDX        2
 345 #define DDR_PLL_IDX        3
 346
 347 #define GRF_SOC_CON0       0xbc
 348 static void pll_wait_lock(int pll_idx)
 349 {
 350         u32 bit = 0x2000000u << pll_idx;
 351         int delay = 2400000;
 352         while (delay > 0) {
 353                 if (regfile_readl(GRF_SOC_CON0) & bit)
 354                         break;
 355                 delay--;
 356         }
 357         if (delay == 0) {
 358                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 359         }
 360 }
 361
 362 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 363 {
 364         unsigned long rate;
 365
 366         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 367                 u32 v = cru_readl(CRU_APLL_CON);
 368                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 369                 do_div(rate64, PLL_NR(v));
 370                 rate = rate64 >> PLL_NO_SHIFT(v);
 371                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 372         } else {
 373                 rate = clk->parent->rate;
 374                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 375         }
 376
 377         return rate;
 378 }
 379
 380 struct arm_pll_set {
 381         unsigned long rate;
 382         u32 apll_con;
 383         u32 clksel0_con;
 384 };
 385
 386 #define CORE_ACLK_11    (0 << 5)
 387 #define CORE_ACLK_21    (1 << 5)
 388 #define CORE_ACLK_31    (2 << 5)
 389 #define CORE_ACLK_41    (3 << 5)
 390 #define CORE_ACLK_81    (4 << 5)
 391 #define CORE_ACLK_MASK  (7 << 5)
 392
 393 #define ACLK_HCLK_11    (0 << 8)
 394 #define ACLK_HCLK_21    (1 << 8)
 395 #define ACLK_HCLK_41    (2 << 8)
 396 #define ACLK_HCLK_MASK  (3 << 8)
 397
 398 #define ACLK_PCLK_11    (0 << 10)
 399 #define ACLK_PCLK_21    (1 << 10)
 400 #define ACLK_PCLK_41    (2 << 10)
 401 #define ACLK_PCLK_81    (3 << 10)
 402 #define ACLK_PCLK_MASK  (3 << 10)
 403
 404 #define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 405 { \
 406         .rate           = _mhz * MHZ, \
 407         .apll_con       = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 408         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 409 }
 410
 411 static const struct arm_pll_set arm_pll[] = {
 412         // rate = 24 * NF / (NR * NO)
 413         //      rate NR  NF NO adiv hdiv pdiv
 414         ARM_PLL(1200, 1, 50, 1, 31, 21, 81),
 415         ARM_PLL(1104, 1, 46, 1, 31, 21, 81),
 416         ARM_PLL(1008, 1, 42, 1, 31, 21, 81),
 417         ARM_PLL( 912, 1, 38, 1, 31, 21, 81),
 418         ARM_PLL( 888, 2, 74, 1, 31, 21, 81),
 419         ARM_PLL( 816, 1, 34, 1, 31, 21, 81),
 420         ARM_PLL( 696, 1, 58, 2, 31, 21, 81),
 421         ARM_PLL( 624, 1, 52, 2, 31, 21, 81),
 422         ARM_PLL( 600, 1, 50, 2, 21, 21, 81),
 423         ARM_PLL( 504, 1, 42, 2, 21, 21, 81),
 424         ARM_PLL( 408, 1, 34, 2, 21, 21, 81),
 425         ARM_PLL( 300, 1, 50, 4, 21, 21, 41),
 426         ARM_PLL( 204, 1, 34, 4, 21, 21, 41),
 427         ARM_PLL( 102, 1, 34, 8, 21, 21, 41),
 428         // last item, pll power down.
 429         ARM_PLL(  24, 1, 64, 8, 21, 21, 41),
 430 };
 431
 432 #define CORE_PARENT_MASK        (3 << 23)
 433 #define CORE_PARENT_ARM_PLL     (0 << 23)
 434 #define CORE_PARENT_GENERAL_PLL (1 << 23)
 435
 436 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 437 {
 438         const struct arm_pll_set *ps, *pt;
 439
 440         /* find the arm_pll we want. */
 441         ps = pt = &arm_pll[0];
 442         while (1) {
 443                 if (pt->rate == rate) {
 444                         ps = pt;
 445                         break;
 446                 }
 447                 // we are sorted, and ps->rate > pt->rate.
 448                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 449                         ps = pt;
 450                 if (pt->rate < rate || pt->rate == 24 * MHZ)
 451                         break;
 452                 pt++;
 453         }
 454
 455         /* make aclk safe & reparent to general pll */
 456         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_GENERAL_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 457
 458         /* enter slow mode */
 459         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 460
 461         /* power down */
 462         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 463
 464         arm_delay_500ns();
 465
 466         cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
 467
 468         arm_delay_500ns();
 469
 470         /* power up */
 471         cru_writel(ps->apll_con, CRU_APLL_CON);
 472
 473         arm_delay_300us();
 474         pll_wait_lock(ARM_PLL_IDX);
 475
 476         /* reparent to arm pll & set aclk/hclk/pclk */
 477         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | ps->clksel0_con, CRU_CLKSEL0_CON);
 478
 479         /* enter normal mode */
 480         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 481
 482         return 0;
 483 }
 484
 485 static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
 486
 487 static struct clk arm_pll_clk = {
 488         .name           = "arm_pll",
 489         .parent         = &xin24m,
 490         .recalc         = arm_pll_clk_recalc,
 491         .set_rate       = arm_pll_clk_set_rate,
 492         .clksel_con     = CRU_MODE_CON,
 493         .clksel_parent_mask     = 1,
 494         .clksel_parent_shift    = 8,
 495         .parents        = arm_pll_parents,
 496 };
 497
 498 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 499 {
 500         unsigned long rate;
 501
 502         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 503                 u32 v = cru_readl(CRU_DPLL_CON);
 504                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 505                 do_div(rate64, PLL_NR(v));
 506                 rate = rate64 >> PLL_NO_SHIFT(v);
 507                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 508         } else {
 509                 rate = clk->parent->rate;
 510                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 511         }
 512
 513         return rate;
 514 }
 515
 516 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 517 {
 518         /* do nothing here */
 519         return 0;
 520 }
 521
 522 static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &general_pll_clk };
 523
 524 static struct clk ddr_pll_clk = {
 525         .name           = "ddr_pll",
 526         .parent         = &xin24m,
 527         .recalc         = ddr_pll_clk_recalc,
 528         .set_rate       = ddr_pll_clk_set_rate,
 529         .clksel_con     = CRU_MODE_CON,
 530         .clksel_parent_mask     = 3,
 531         .clksel_parent_shift    = 13,
 532         .parents        = ddr_pll_parents,
 533 };
 534
 535
 536 static int codec_pll_clk_mode(struct clk *clk, int on)
 537 {
 538         u32 cpll = cru_readl(CRU_CPLL_CON);
 539         if (on) {
 540                 cru_writel(cpll & ~(PLL_PD | PLL_BYPASS), CRU_CPLL_CON);
 541                 delay_300us();
 542                 pll_wait_lock(CODEC_PLL_IDX);
 543                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
 544         } else {
 545                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 546                 cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 547                 cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 548                 delay_500ns();
 549         }
 550         return 0;
 551 }
 552
 553 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 554 {
 555         unsigned long rate;
 556         u32 v = cru_readl(CRU_CPLL_CON);
 557         u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 558         do_div(rate64, PLL_NR(v));
 559         rate = rate64 >> PLL_NO_SHIFT(v);
 560         pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 561         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) != CRU_CODEC_MODE_NORMAL)
 562                 pr_debug("%s rate is %ld (slow mode) actually\n", clk->name, clk->parent->rate);
 563         return rate;
 564 }
 565
 566 #define CODEC_PLL_PARENT_MASK   (3 << 11)
 567 #define CODEC_PLL_PARENT_XIN24M (0 << 11)
 568 #define CODEC_PLL_PARENT_XIN27M (1 << 11)
 569 #define CODEC_PLL_PARENT_DDR_PLL        (2 << 11)
 570 #define CODEC_PLL_PARENT_GENERAL_PLL    (3 << 11)
 571
 572 struct codec_pll_set {
 573         unsigned long rate;
 574         u32 pll_con;
 575         u32 parent_con;
 576 };
 577
 578 #define CODEC_PLL(_khz, _parent, band, nr, nf, no) \
 579 { \
 580         .rate           = _khz * KHZ, \
 581         .pll_con        = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
 582         .parent_con     = CODEC_PLL_PARENT_XIN##_parent##M, \
 583 }
 584
 585 static const struct codec_pll_set codec_pll[] = {
 586         //        rate parent band NR  NF NO
 587         CODEC_PLL(108000, 24,  LOW, 1, 18, 4),  // for TV
 588         CODEC_PLL(648000, 24, HIGH, 1, 27, 1),
 589         CODEC_PLL(297000, 27,  LOW, 1, 22, 2),  // for HDMI
 590         CODEC_PLL(445500, 27,  LOW, 2, 33, 1),
 591         CODEC_PLL(594000, 27, HIGH, 1, 22, 1),
 592         CODEC_PLL(300000, 24,  LOW, 1, 25, 2),  // for GPU
 593         CODEC_PLL(360000, 24,  LOW, 1, 15, 1),
 594         CODEC_PLL(408000, 24,  LOW, 1, 17, 1),
 595         CODEC_PLL(456000, 24,  LOW, 1, 19, 1),
 596         CODEC_PLL(504000, 24,  LOW, 1, 21, 1),
 597         CODEC_PLL(552000, 24,  LOW, 1, 23, 1),
 598         CODEC_PLL(600000, 24, HIGH, 1, 25, 1),
 599 };
 600
 601 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 602 {
 603         int i;
 604         u32 work_mode;
 605
 606         const struct codec_pll_set *ps = NULL;
 607
 608         for (i = 0; i < ARRAY_SIZE(codec_pll); i++) {
 609                 if (codec_pll[i].rate == rate) {
 610                         ps = &codec_pll[i];
 611                         break;
 612                 }
 613         }
 614         if (!ps)
 615                 return -ENOENT;
 616
 617         if (!has_xin27m && ps->parent_con == CODEC_PLL_PARENT_XIN27M)
 618                 return -ENOENT;
 619
 620         work_mode = cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK;
 621
 622         /* enter slow mode */
 623         cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | ps->parent_con, CRU_MODE_CON);
 624
 625         /* power down */
 626         cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
 627
 628         delay_500ns();
 629
 630         cru_writel(ps->pll_con | PLL_PD, CRU_CPLL_CON);
 631
 632         delay_500ns();
 633
 634         /* power up */
 635         cru_writel(ps->pll_con, CRU_CPLL_CON);
 636
 637         delay_300us();
 638         pll_wait_lock(CODEC_PLL_IDX);
 639
 640         /* enter normal mode */
 641         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | work_mode, CRU_MODE_CON);
 642
 643         clk_set_parent_nolock(clk, ps->parent_con == CODEC_PLL_PARENT_XIN24M ? &xin24m : &xin27m);
 644
 645         return 0;
 646 }
 647
 648 static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &general_pll_clk };
 649
 650 static struct clk codec_pll_clk = {
 651         .name           = "codec_pll",
 652         .parent         = &xin24m,
 653         .mode           = codec_pll_clk_mode,
 654         .recalc         = codec_pll_clk_recalc,
 655         .set_rate       = codec_pll_clk_set_rate,
 656         .clksel_con     = CRU_MODE_CON,
 657         .clksel_parent_mask     = 3,
 658         .clksel_parent_shift    = 11,
 659         .parents        = codec_pll_parents,
 660 };
 661
 662
 663 static unsigned long general_pll_clk_recalc(struct clk *clk)
 664 {
 665         unsigned long rate;
 666
 667         if ((cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) == CRU_GENERAL_MODE_NORMAL) {
 668                 u32 v = cru_readl(CRU_GPLL_CON);
 669                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 670                 do_div(rate64, PLL_NR(v));
 671                 rate = rate64 >> PLL_NO_SHIFT(v);
 672                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 673         } else {
 674                 rate = clk->parent->rate;
 675                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 676         }
 677
 678         return rate;
 679 }
 680
 681 static int general_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 682 {
 683         u32 pll_con;
 684
 685         switch (rate) {
 686         case 96 * MHZ:
 687                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 688                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(16) | PLL_NO_4;
 689         break;
 690         case 144*MHZ:
 691                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 692                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_4;
 693         break;
 694         case 288 * MHZ:
 695                 /* 288M: low-band, NR=1, NF=24, NO=2 */
 696                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_2;
 697                 break;
 698         case 300 * MHZ:
 699                 /* 300M: low-band, NR=1, NF=25, NO=2 */
 700                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(25) | PLL_NO_2;
 701         break;
 702         case 624 * MHZ:
 703                 /* 624M: high-band, NR=1, NF=26, NO=1 */
 704                 pll_con = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 705                 break;
 706         default:
 707                 return -ENOENT;
 708                 break;
 709         }
 710
 711         /* enter slow mode */
 712         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 713
 714         /* power down */
 715         cru_writel(cru_readl(CRU_GPLL_CON) | PLL_PD, CRU_GPLL_CON);
 716
 717         delay_500ns();
 718
 719         cru_writel(pll_con | PLL_PD, CRU_GPLL_CON);
 720
 721         delay_500ns();
 722
 723         /* power up */
 724         cru_writel(pll_con, CRU_GPLL_CON);
 725
 726         delay_300us();
 727         pll_wait_lock(GENERAL_PLL_IDX);
 728
 729         /* enter normal mode */
 730         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_NORMAL, CRU_MODE_CON);
 731
 732         return 0;
 733 }
 734
 735 static struct clk *general_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
 736
 737 static struct clk general_pll_clk = {
 738         .name           = "general_pll",
 739         .parent         = &xin24m,
 740         .recalc         = general_pll_clk_recalc,
 741         .set_rate       = general_pll_clk_set_rate,
 742         .clksel_con     = CRU_MODE_CON,
 743         .clksel_parent_mask     = 3,
 744         .clksel_parent_shift    = 9,
 745         .parents        = general_pll_parents,
 746 };
 747
 748
 749 static struct clk *clk_core_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 750
 751 static struct clk clk_core = {
 752         .name           = "core",
 753         .parent         = &arm_pll_clk,
 754         .recalc         = clksel_recalc_div,
 755         .clksel_con     = CRU_CLKSEL0_CON,
 756         .clksel_mask    = 0x1F,
 757         .clksel_shift   = 0,
 758         .clksel_parent_mask     = 3,
 759         .clksel_parent_shift    = 23,
 760         .parents        = clk_core_parents,
 761 };
 762
 763 static unsigned long aclk_cpu_recalc(struct clk *clk)
 764 {
 765         unsigned long rate;
 766         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 767
 768         BUG_ON(div > 5);
 769         if (div >= 5)
 770                 div = 8;
 771         rate = clk->parent->rate / div;
 772         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 773
 774         return rate;
 775 }
 776
 777 static struct clk aclk_cpu = {
 778         .name           = "aclk_cpu",
 779         .parent         = &clk_core,
 780         .recalc         = aclk_cpu_recalc,
 781 };
 782
 783 static struct clk hclk_cpu = {
 784         .name           = "hclk_cpu",
 785         .parent         = &aclk_cpu,
 786         .recalc         = clksel_recalc_shift,
 787         .set_rate       = clksel_set_rate_shift,
 788         .clksel_con     = CRU_CLKSEL0_CON,
 789         .clksel_mask    = 3,
 790         .clksel_shift   = 8,
 791         .clksel_maxdiv  = 4,
 792 };
 793
 794 static struct clk pclk_cpu = {
 795         .name           = "pclk_cpu",
 796         .parent         = &aclk_cpu,
 797         .recalc         = clksel_recalc_shift,
 798         .set_rate       = clksel_set_rate_shift,
 799         .clksel_con     = CRU_CLKSEL0_CON,
 800         .clksel_mask    = 3,
 801         .clksel_shift   = 10,
 802         .clksel_maxdiv  = 8,
 803 };
 804
 805 static struct clk *aclk_periph_parents[4] = { &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
 806
 807 static struct clk aclk_periph = {
 808         .name           = "aclk_periph",
 809         .mode           = gate_mode,
 810         .gate_idx       = CLK_GATE_ACLK_PEIRPH,
 811         .recalc         = clksel_recalc_div,
 812         .set_rate       = clksel_set_rate_div,
 813         .clksel_con     = CRU_CLKSEL0_CON,
 814         .clksel_mask    = 0x1F,
 815         .clksel_shift   = 14,
 816         .clksel_parent_mask     = 3,
 817         .clksel_parent_shift    = 12,
 818         .parents        = aclk_periph_parents,
 819 };
 820
 821 static struct clk pclk_periph = {
 822         .name           = "pclk_periph",
 823         .mode           = gate_mode,
 824         .gate_idx       = CLK_GATE_PCLK_PEIRPH,
 825         .parent         = &aclk_periph,
 826         .recalc         = clksel_recalc_shift,
 827         .set_rate       = clksel_set_rate_shift,
 828         .clksel_con     = CRU_CLKSEL0_CON,
 829         .clksel_mask    = 3,
 830         .clksel_shift   = 19,
 831         .clksel_maxdiv  = 8,
 832 };
 833
 834 static struct clk hclk_periph = {
 835         .name           = "hclk_periph",
 836         .mode           = gate_mode,
 837         .gate_idx       = CLK_GATE_HCLK_PEIRPH,
 838         .parent         = &aclk_periph,
 839         .recalc         = clksel_recalc_shift,
 840         .set_rate       = clksel_set_rate_shift,
 841         .clksel_con     = CRU_CLKSEL0_CON,
 842         .clksel_mask    = 3,
 843         .clksel_shift   = 21,
 844         .clksel_maxdiv  = 4,
 845 };
 846
 847
 848 static unsigned long uhost_recalc(struct clk *clk)
 849 {
 850         unsigned long rate = clksel_recalc_div(clk);
 851         if (rate != 48 * MHZ) {
 852                 clksel_set_rate_div(clk, 48 * MHZ);
 853                 rate = clksel_recalc_div(clk);
 854         }
 855         return rate;
 856 }
 857
 858 static struct clk *clk_uhost_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 859
 860 static struct clk clk_uhost = {
 861         .name           = "uhost",
 862         .mode           = gate_mode,
 863         .recalc         = uhost_recalc,
 864         .set_rate       = clksel_set_rate_div,
 865         .gate_idx       = CLK_GATE_UHOST,
 866         .clksel_con     = CRU_CLKSEL1_CON,
 867         .clksel_mask    = 0x1F,
 868         .clksel_shift   = 16,
 869         .clksel_parent_mask     = 7,
 870         .clksel_parent_shift    = 13,
 871         .parents        = clk_uhost_parents,
 872 };
 873
 874 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 875
 876 static struct clk clk_otgphy0 = {
 877         .name           = "otgphy0",
 878         .mode           = gate_mode,
 879         .gate_idx       = CLK_GATE_USBPHY0,
 880         .clksel_con     = CRU_CLKSEL1_CON,
 881         .clksel_parent_mask     = 3,
 882         .clksel_parent_shift    = 9,
 883         .parents        = clk_otgphy_parents,
 884 };
 885
 886 static struct clk clk_otgphy1 = {
 887         .name           = "otgphy1",
 888         .mode           = gate_mode,
 889         .gate_idx       = CLK_GATE_USBPHY1,
 890         .clksel_con     = CRU_CLKSEL1_CON,
 891         .clksel_parent_mask     = 3,
 892         .clksel_parent_shift    = 11,
 893         .parents        = clk_otgphy_parents,
 894 };
 895
 896
 897 static struct clk rmii_clkin = {
 898         .name           = "rmii_clkin",
 899 };
 900
 901 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 902
 903 static struct clk clk_mac_ref_div = {
 904         .name           = "mac_ref_div",
 905         .recalc         = clksel_recalc_div,
 906         .set_rate       = clksel_set_rate_div,
 907         .clksel_con     = CRU_CLKSEL1_CON,
 908         .clksel_mask    = 0x1F,
 909         .clksel_shift   = 23,
 910         .clksel_parent_mask     = 3,
 911         .clksel_parent_shift    = 21,
 912         .parents        = clk_mac_ref_div_parents,
 913 };
 914
 915 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 916
 917 static struct clk clk_mac_ref = {
 918         .name           = "mac_ref",
 919         .mode           = gate_mode,
 920         .gate_idx       = CLK_GATE_MAC_REF,
 921         .clksel_con     = CRU_CLKSEL1_CON,
 922         .clksel_parent_mask     = 1,
 923         .clksel_parent_shift    = 28,
 924         .parents        = clk_mac_ref_parents,
 925 };
 926
 927
 928 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 929
 930 static struct clk clk_i2s0_div = {
 931         .name           = "i2s0_div",
 932         .recalc         = clksel_recalc_div,
 933         .set_rate       = clksel_set_rate_div,
 934         .clksel_con     = CRU_CLKSEL2_CON,
 935         .clksel_mask    = 0x1F,
 936         .clksel_shift   = 3,
 937         .clksel_parent_mask     = 7,
 938         .clksel_parent_shift    = 0,
 939         .parents        = clk_i2s_div_parents,
 940 };
 941
 942 static struct clk clk_i2s1_div = {
 943         .name           = "i2s1_div",
 944         .recalc         = clksel_recalc_div,
 945         .set_rate       = clksel_set_rate_div,
 946         .clksel_con     = CRU_CLKSEL2_CON,
 947         .clksel_mask    = 0x1F,
 948         .clksel_shift   = 13,
 949         .clksel_parent_mask     = 7,
 950         .clksel_parent_shift    = 10,
 951         .parents        = clk_i2s_div_parents,
 952 };
 953
 954 static struct clk clk_spdif_div = {
 955         .name           = "spdif_div",
 956         .recalc         = clksel_recalc_div,
 957         .set_rate       = clksel_set_rate_div,
 958         .clksel_con     = CRU_CLKSEL2_CON,
 959         .clksel_mask    = 0x1F,
 960         .clksel_shift   = 23,
 961         .clksel_parent_mask     = 7,
 962         .clksel_parent_shift    = 20,
 963         .parents        = clk_i2s_div_parents,
 964 };
 965
 966 static u32 clk_gcd(u32 numerator, u32 denominator)
 967 {
 968         u32 a, b;
 969
 970         if (!numerator || !denominator)
 971                 return 0;
 972         if (numerator > denominator) {
 973                 a = numerator;
 974                 b = denominator;
 975         } else {
 976                 a = denominator;
 977                 b = numerator;
 978         }
 979         while (b != 0) {
 980                 int r = b;
 981                 b = a % b;
 982                 a = r;
 983         }
 984
 985         return a;
 986 }
 987
 988 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 989 {
 990         u32 numerator, denominator;
 991         u32 gcd;
 992
 993         gcd = clk_gcd(rate, clk->parent->rate);
 994         pr_debug("i2s rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
 995         if (!gcd) {
 996                 pr_err("gcd=0, i2s frac div is not be supported\n");
 997                 return -ENOENT;
 998         }
 999
1000         numerator = rate / gcd;
1001         denominator = clk->parent->rate / gcd;
1002         pr_debug("i2s numerator=%d,denominator=%d,times=%d\n",
1003                 numerator, denominator, denominator / numerator);
1004         if (numerator > 0xffff || denominator > 0xffff) {
1005                 pr_err("i2s can't get a available nume and deno\n");
1006                 return -ENOENT;
1007         }
1008
1009         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1010         cru_writel(numerator << 16 | denominator, clk->clksel_con);
1011
1012         return 0;
1013 }
1014
1015 static struct clk clk_i2s0_frac_div = {
1016         .name           = "i2s0_frac_div",
1017         .parent         = &clk_i2s0_div,
1018         .recalc         = clksel_recalc_frac,
1019         .set_rate       = clk_i2s_frac_div_set_rate,
1020         .clksel_con     = CRU_CLKSEL3_CON,
1021 };
1022
1023 static struct clk clk_i2s1_frac_div = {
1024         .name           = "i2s1_frac_div",
1025         .parent         = &clk_i2s1_div,
1026         .recalc         = clksel_recalc_frac,
1027         .set_rate       = clk_i2s_frac_div_set_rate,
1028         .clksel_con     = CRU_CLKSEL4_CON,
1029 };
1030
1031 static struct clk clk_spdif_frac_div = {
1032         .name           = "spdif_frac_div",
1033         .parent         = &clk_spdif_div,
1034         .recalc         = clksel_recalc_frac,
1035         .set_rate       = clk_i2s_frac_div_set_rate,
1036         .clksel_con     = CRU_CLKSEL5_CON,
1037 };
1038
1039 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1040 {
1041         int ret = 0;
1042         struct clk *parent;
1043
1044         if (rate == 12 * MHZ) {
1045                 parent = &clk_12m;
1046         } else {
1047                 parent = clk->parents[1]; /* frac div */
1048                 ret = clk_set_rate_nolock(parent, rate);
1049                 if (ret)
1050                         return ret;
1051         }
1052         if (clk->parent != parent)
1053                 ret = clk_set_parent_nolock(clk, parent);
1054
1055         return ret;
1056 }
1057
1058 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
1059
1060 static struct clk clk_i2s0 = {
1061         .name           = "i2s0",
1062         .mode           = gate_mode,
1063         .gate_idx       = CLK_GATE_I2S0,
1064         .set_rate       = i2s_set_rate,
1065         .clksel_con     = CRU_CLKSEL2_CON,
1066         .clksel_parent_mask     = 3,
1067         .clksel_parent_shift    = 8,
1068         .parents        = clk_i2s0_parents,
1069 };
1070
1071 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
1072
1073 static struct clk clk_i2s1 = {
1074         .name           = "i2s1",
1075         .mode           = gate_mode,
1076         .gate_idx       = CLK_GATE_I2S1,
1077         .set_rate       = i2s_set_rate,
1078         .clksel_con     = CRU_CLKSEL2_CON,
1079         .clksel_parent_mask     = 3,
1080         .clksel_parent_shift    = 18,
1081         .parents        = clk_i2s1_parents,
1082 };
1083
1084 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
1085
1086 static struct clk clk_spdif = {
1087         .name           = "spdif",
1088         .mode           = gate_mode,
1089         .gate_idx       = CLK_GATE_SPDIF,
1090         .set_rate       = i2s_set_rate,
1091         .clksel_con     = CRU_CLKSEL2_CON,
1092         .clksel_parent_mask     = 3,
1093         .clksel_parent_shift    = 28,
1094         .parents        = clk_spdif_parents,
1095 };
1096
1097
1098 static struct clk *clk_spi_src_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1099
1100 static struct clk clk_spi_src = {
1101         .name           = "spi_src",
1102         .clksel_con     = CRU_CLKSEL6_CON,
1103         .clksel_parent_mask     = 3,
1104         .clksel_parent_shift    = 0,
1105         .parents        = clk_spi_src_parents,
1106 };
1107
1108 static struct clk clk_spi0 = {
1109         .name           = "spi0",
1110         .parent         = &clk_spi_src,
1111         .mode           = gate_mode,
1112         .recalc         = clksel_recalc_div,
1113         .set_rate       = clksel_set_rate_div,
1114         .gate_idx       = CLK_GATE_SPI0,
1115         .clksel_con     = CRU_CLKSEL6_CON,
1116         .clksel_mask    = 0x7F,
1117         .clksel_shift   = 2,
1118 };
1119
1120 static struct clk clk_spi1 = {
1121         .name           = "spi1",
1122         .parent         = &clk_spi_src,
1123         .mode           = gate_mode,
1124         .recalc         = clksel_recalc_div,
1125         .set_rate       = clksel_set_rate_div,
1126         .gate_idx       = CLK_GATE_SPI1,
1127         .clksel_con     = CRU_CLKSEL6_CON,
1128         .clksel_mask    = 0x7F,
1129         .clksel_shift   = 11,
1130 };
1131
1132
1133 static struct clk clk_saradc = {
1134         .name           = "saradc",
1135         .parent         = &pclk_periph,
1136         .mode           = gate_mode,
1137         .recalc         = clksel_recalc_div,
1138         .set_rate       = clksel_set_rate_div,
1139         .gate_idx       = CLK_GATE_SARADC,
1140         .clksel_con     = CRU_CLKSEL6_CON,
1141         .clksel_mask    = 0xFF,
1142         .clksel_shift   = 18,
1143 };
1144
1145
1146 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
1147
1148 static struct clk clk_timer0 = {
1149         .name           = "timer0",
1150         .mode           = gate_mode,
1151         .gate_idx       = CLK_GATE_TIMER0,
1152         .clksel_con     = CRU_CLKSEL6_CON,
1153         .clksel_parent_mask     = 1,
1154         .clksel_parent_shift    = 26,
1155         .parents        = clk_cpu_timer_parents,
1156 };
1157
1158 static struct clk clk_timer1 = {
1159         .name           = "timer1",
1160         .mode           = gate_mode,
1161         .gate_idx       = CLK_GATE_TIMER1,
1162         .clksel_con     = CRU_CLKSEL6_CON,
1163         .clksel_parent_mask     = 1,
1164         .clksel_parent_shift    = 27,
1165         .parents        = clk_cpu_timer_parents,
1166 };
1167
1168 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
1169
1170 static struct clk clk_timer2 = {
1171         .name           = "timer2",
1172         .mode           = gate_mode,
1173         .gate_idx       = CLK_GATE_TIMER2,
1174         .clksel_con     = CRU_CLKSEL6_CON,
1175         .clksel_parent_mask     = 1,
1176         .clksel_parent_shift    = 28,
1177         .parents        = clk_periph_timer_parents,
1178 };
1179
1180 static struct clk clk_timer3 = {
1181         .name           = "timer3",
1182         .mode           = gate_mode,
1183         .gate_idx       = CLK_GATE_TIMER3,
1184         .clksel_con     = CRU_CLKSEL6_CON,
1185         .clksel_parent_mask     = 1,
1186         .clksel_parent_shift    = 29,
1187         .parents        = clk_periph_timer_parents,
1188 };
1189
1190
1191 static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1192
1193 static struct clk clk_mmc_src = {
1194         .name           = "mmc_src",
1195         .clksel_con     = CRU_CLKSEL7_CON,
1196         .clksel_parent_mask     = 3,
1197         .clksel_parent_shift    = 0,
1198         .parents        = clk_mmc_src_parents,
1199 };
1200
1201 static struct clk clk_mmc0 = {
1202         .name           = "mmc0",
1203         .parent         = &clk_mmc_src,
1204         .mode           = gate_mode,
1205         .recalc         = clksel_recalc_div,
1206         .set_rate       = clksel_set_rate_div,
1207         .gate_idx       = CLK_GATE_MMC0,
1208         .clksel_con     = CRU_CLKSEL7_CON,
1209         .clksel_mask    = 0x3F,
1210         .clksel_shift   = 2,
1211 };
1212
1213 static struct clk clk_mmc1 = {
1214         .name           = "mmc1",
1215         .parent         = &clk_mmc_src,
1216         .mode           = gate_mode,
1217         .recalc         = clksel_recalc_div,
1218         .set_rate       = clksel_set_rate_div,
1219         .gate_idx       = CLK_GATE_MMC1,
1220         .clksel_con     = CRU_CLKSEL7_CON,
1221         .clksel_mask    = 0x3F,
1222         .clksel_shift   = 10,
1223 };
1224
1225 static struct clk clk_emmc = {
1226         .name           = "emmc",
1227         .parent         = &clk_mmc_src,
1228         .mode           = gate_mode,
1229         .recalc         = clksel_recalc_div,
1230         .set_rate       = clksel_set_rate_div,
1231         .gate_idx       = CLK_GATE_EMMC,
1232         .clksel_con     = CRU_CLKSEL7_CON,
1233         .clksel_mask    = 0x3F,
1234         .clksel_shift   = 18,
1235 };
1236
1237
1238 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &general_pll_clk, &codec_pll_clk, &arm_pll_clk };
1239
1240 static struct clk clk_ddr = {
1241         .name           = "ddr",
1242         .recalc         = clksel_recalc_shift,
1243         .clksel_con     = CRU_CLKSEL7_CON,
1244         .clksel_mask    = 7,
1245         .clksel_shift   = 26,
1246         .clksel_maxdiv  = 32,
1247         .clksel_parent_mask     = 3,
1248         .clksel_parent_shift    = 24,
1249         .parents        = clk_ddr_parents,
1250 };
1251
1252
1253 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1254 {
1255         int ret = 0;
1256         struct clk *parent;
1257         struct clk *clk_div = clk->parents[0];
1258
1259         switch (rate) {
1260         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
1261                 parent = clk->parents[2]; /* xin24m */
1262                 break;
1263         case 19200*16:
1264         case 38400*16:
1265         case 57600*16:
1266         case 115200*16:
1267         case 230400*16:
1268         case 460800*16:
1269         case 576000*16:
1270                 parent = clk->parents[1]; /* frac div */
1271                 /* reset div to 1 */
1272                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1273                 if (ret)
1274                         return ret;
1275                 break;
1276         default:
1277                 parent = clk_div;
1278                 break;
1279         }
1280
1281         if (parent->set_rate) {
1282                 ret = clk_set_rate_nolock(parent, rate);
1283                 if (ret)
1284                         return ret;
1285         }
1286
1287         if (clk->parent != parent)
1288                 ret = clk_set_parent_nolock(clk, parent);
1289
1290         return ret;
1291 }
1292
1293 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1294 {
1295         u32 numerator, denominator;
1296         u32 gcd;
1297
1298         gcd = clk_gcd(rate, clk->parent->rate);
1299         pr_debug("uart rate=%ld,parent=%ld,gcd=%d\n", rate, clk->parent->rate, gcd);
1300         if (!gcd) {
1301                 pr_err("gcd=0, uart frac div is not be supported\n");
1302                 return -ENOENT;
1303         }
1304
1305         numerator = rate / gcd;
1306         denominator = clk->parent->rate / gcd;
1307         pr_debug("uart numerator=%d,denominator=%d,times=%d\n",
1308                 numerator, denominator, denominator / numerator);
1309         if (numerator > 0xffff || denominator > 0xffff) {
1310                 pr_err("uart_frac can't get a available nume and deno\n");
1311                 return -ENOENT;
1312         }
1313
1314         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1315         cru_writel(numerator << 16 | denominator, clk->clksel_con);
1316
1317         return 0;
1318 }
1319
1320 static struct clk *clk_uart_src_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1321
1322 static struct clk clk_uart01_src = {
1323         .name           = "uart01_src",
1324         .clksel_con     = CRU_CLKSEL8_CON,
1325         .clksel_parent_mask     = 7,
1326         .clksel_parent_shift    = 0,
1327         .parents        = clk_uart_src_parents,
1328 };
1329
1330 static struct clk clk_uart0_div = {
1331         .name           = "uart0_div",
1332         .parent         = &clk_uart01_src,
1333         .recalc         = clksel_recalc_div,
1334         .set_rate       = clksel_set_rate_div,
1335         .clksel_con     = CRU_CLKSEL8_CON,
1336         .clksel_mask    = 0x3F,
1337         .clksel_shift   = 3,
1338 };
1339
1340 static struct clk clk_uart0_frac_div = {
1341         .name           = "uart0_frac_div",
1342         .parent         = &clk_uart0_div,
1343         .recalc         = clksel_recalc_frac,
1344         .set_rate       = clk_uart_frac_div_set_rate,
1345         .clksel_con     = CRU_CLKSEL10_CON,
1346 };
1347
1348 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1349
1350 static struct clk clk_uart0 = {
1351         .name           = "uart0",
1352         .mode           = gate_mode,
1353         .set_rate       = clk_uart_set_rate,
1354         .gate_idx       = CLK_GATE_UART0,
1355         .clksel_con     = CRU_CLKSEL8_CON,
1356         .clksel_parent_mask     = 3,
1357         .clksel_parent_shift    = 9,
1358         .parents        = clk_uart0_parents,
1359 };
1360
1361 static struct clk clk_uart1_div = {
1362         .name           = "uart1_div",
1363         .parent         = &clk_uart01_src,
1364         .recalc         = clksel_recalc_div,
1365         .set_rate       = clksel_set_rate_div,
1366         .clksel_con     = CRU_CLKSEL8_CON,
1367         .clksel_mask    = 0x3F,
1368         .clksel_shift   = 14,
1369 };
1370
1371 static struct clk clk_uart1_frac_div = {
1372         .name           = "uart1_frac_div",
1373         .parent         = &clk_uart1_div,
1374         .recalc         = clksel_recalc_frac,
1375         .set_rate       = clk_uart_frac_div_set_rate,
1376         .clksel_con     = CRU_CLKSEL11_CON,
1377 };
1378
1379 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1380
1381 static struct clk clk_uart1 = {
1382         .name           = "uart1",
1383         .mode           = gate_mode,
1384         .set_rate       = clk_uart_set_rate,
1385         .gate_idx       = CLK_GATE_UART1,
1386         .clksel_con     = CRU_CLKSEL8_CON,
1387         .clksel_parent_mask     = 3,
1388         .clksel_parent_shift    = 20,
1389         .parents        = clk_uart1_parents,
1390 };
1391
1392 static struct clk clk_uart23_src = {
1393         .name           = "uart23_src",
1394         .clksel_con     = CRU_CLKSEL9_CON,
1395         .clksel_parent_mask     = 7,
1396         .clksel_parent_shift    = 0,
1397         .parents        = clk_uart_src_parents,
1398 };
1399
1400 static struct clk clk_uart2_div = {
1401         .name           = "uart2_div",
1402         .parent         = &clk_uart23_src,
1403         .recalc         = clksel_recalc_div,
1404         .set_rate       = clksel_set_rate_div,
1405         .clksel_con     = CRU_CLKSEL9_CON,
1406         .clksel_mask    = 0x3F,
1407         .clksel_shift   = 3,
1408 };
1409
1410 static struct clk clk_uart2_frac_div = {
1411         .name           = "uart2_frac_div",
1412         .parent         = &clk_uart2_div,
1413         .recalc         = clksel_recalc_frac,
1414         .set_rate       = clk_uart_frac_div_set_rate,
1415         .clksel_con     = CRU_CLKSEL12_CON,
1416 };
1417
1418 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1419
1420 static struct clk clk_uart2 = {
1421         .name           = "uart2",
1422         .mode           = gate_mode,
1423         .set_rate       = clk_uart_set_rate,
1424         .gate_idx       = CLK_GATE_UART2,
1425         .clksel_con     = CRU_CLKSEL9_CON,
1426         .clksel_parent_mask     = 3,
1427         .clksel_parent_shift    = 9,
1428         .parents        = clk_uart2_parents,
1429 };
1430
1431 static struct clk clk_uart3_div = {
1432         .name           = "uart3_div",
1433         .parent         = &clk_uart23_src,
1434         .recalc         = clksel_recalc_div,
1435         .set_rate       = clksel_set_rate_div,
1436         .clksel_con     = CRU_CLKSEL9_CON,
1437         .clksel_mask    = 0x3F,
1438         .clksel_shift   = 14,
1439 };
1440
1441 static struct clk clk_uart3_frac_div = {
1442         .name           = "uart3_frac_div",
1443         .parent         = &clk_uart3_div,
1444         .recalc         = clksel_recalc_frac,
1445         .set_rate       = clk_uart_frac_div_set_rate,
1446         .clksel_con     = CRU_CLKSEL13_CON,
1447 };
1448
1449 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1450
1451 static struct clk clk_uart3 = {
1452         .name           = "uart3",
1453         .mode           = gate_mode,
1454         .set_rate       = clk_uart_set_rate,
1455         .gate_idx       = CLK_GATE_UART3,
1456         .clksel_con     = CRU_CLKSEL9_CON,
1457         .clksel_parent_mask     = 3,
1458         .clksel_parent_shift    = 20,
1459         .parents        = clk_uart3_parents,
1460 };
1461
1462
1463 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1464
1465 static struct clk clk_hsadc_div = {
1466         .name           = "hsadc_div",
1467         .recalc         = clksel_recalc_div,
1468         .set_rate       = clksel_set_rate_div,
1469         .clksel_con     = CRU_CLKSEL14_CON,
1470         .clksel_mask    = 0xFF,
1471         .clksel_shift   = 10,
1472         .clksel_parent_mask     = 7,
1473         .clksel_parent_shift    = 7,
1474         .parents        = clk_hsadc_div_parents,
1475 };
1476
1477 static struct clk clk_hsadc_frac_div = {
1478         .name           = "hsadc_frac_div",
1479         .parent         = &clk_hsadc_div,
1480         .recalc         = clksel_recalc_frac,
1481         .clksel_con     = CRU_CLKSEL15_CON,
1482 };
1483
1484 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
1485
1486 static struct clk clk_demod = {
1487         .name           = "demod",
1488         .clksel_con     = CRU_CLKSEL14_CON,
1489         .clksel_parent_mask     = 3,
1490         .clksel_parent_shift    = 18,
1491         .parents        = clk_demod_parents,
1492 };
1493
1494 static struct clk gpsclk = {
1495         .name           = "gpsclk",
1496 };
1497
1498 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1499
1500 static struct clk clk_hsadc = {
1501         .name           = "hsadc",
1502         .mode           = gate_mode,
1503         .gate_idx       = CLK_GATE_HSADC,
1504         .clksel_con     = CRU_CLKSEL14_CON,
1505         .clksel_parent_mask     = 1,
1506         .clksel_parent_shift    = 21,
1507         .parents        = clk_hsadc_parents,
1508 };
1509
1510 static unsigned long div2_recalc(struct clk *clk)
1511 {
1512         return clk->parent->rate >> 1;
1513 }
1514
1515 static struct clk clk_hsadc_div2 = {
1516         .name           = "hsadc_div2",
1517         .parent         = &clk_demod,
1518         .recalc         = div2_recalc,
1519 };
1520
1521 static struct clk clk_hsadc_div2_inv = {
1522         .name           = "hsadc_div2_inv",
1523         .parent         = &clk_demod,
1524         .recalc         = div2_recalc,
1525 };
1526
1527 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1528
1529 static struct clk clk_hsadc_out = {
1530         .name           = "hsadc_out",
1531         .clksel_con     = CRU_CLKSEL14_CON,
1532         .clksel_parent_mask     = 1,
1533         .clksel_parent_shift    = 20,
1534         .parents        = clk_hsadc_out_parents,
1535 };
1536
1537
1538 static int dclk_lcdc_div_set_rate(struct clk *clk, unsigned long rate)
1539 {
1540         struct clk *parent;
1541
1542         switch (rate) {
1543         case 27000 * KHZ:
1544         case 74250 * KHZ:
1545         case 148500 * KHZ:
1546         case 297 * MHZ:
1547         case 594 * MHZ:
1548                 parent = &codec_pll_clk;
1549                 break;
1550         default:
1551                 parent = &general_pll_clk;
1552                 break;
1553         }
1554         if (clk->parent != parent)
1555                 clk_set_parent_nolock(clk, parent);
1556
1557         return clksel_set_rate_div(clk, rate);
1558 }
1559
1560 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
1561
1562 static struct clk dclk_lcdc_div = {
1563         .name           = "dclk_lcdc_div",
1564         .recalc         = clksel_recalc_div,
1565         .set_rate       = dclk_lcdc_div_set_rate,
1566         .clksel_con     = CRU_CLKSEL16_CON,
1567         .clksel_mask    = 0xFF,
1568         .clksel_shift   = 2,
1569         .clksel_parent_mask     = 3,
1570         .clksel_parent_shift    = 0,
1571         .parents        = dclk_lcdc_div_parents,
1572 };
1573
1574 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1575 {
1576         int ret = 0;
1577         struct clk *parent;
1578
1579         if (rate == 27 * MHZ && has_xin27m) {
1580                 parent = &xin27m;
1581         } else {
1582                 parent = &dclk_lcdc_div;
1583                 ret = clk_set_rate_nolock(parent, rate);
1584                 if (ret)
1585                         return ret;
1586         }
1587         if (clk->parent != parent)
1588                 ret = clk_set_parent_nolock(clk, parent);
1589
1590         return ret;
1591 }
1592
1593 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
1594
1595 static struct clk dclk_lcdc = {
1596         .name           = "dclk_lcdc",
1597         .mode           = gate_mode,
1598         .set_rate       = dclk_lcdc_set_rate,
1599         .gate_idx       = CLK_GATE_DCLK_LCDC,
1600         .clksel_con     = CRU_CLKSEL16_CON,
1601         .clksel_parent_mask     = 1,
1602         .clksel_parent_shift    = 10,
1603         .parents        = dclk_lcdc_parents,
1604 };
1605
1606 static struct clk dclk_ebook = {
1607         .name           = "dclk_ebook",
1608         .mode           = gate_mode,
1609         .gate_idx       = CLK_GATE_DCLK_EBOOK,
1610         .recalc         = clksel_recalc_div,
1611         .set_rate       = clksel_set_rate_div,
1612         .clksel_con     = CRU_CLKSEL16_CON,
1613         .clksel_mask    = 0x1F,
1614         .clksel_shift   = 13,
1615         .clksel_parent_mask     = 3,
1616         .clksel_parent_shift    = 11,
1617         .parents        = dclk_lcdc_div_parents,
1618 };
1619
1620 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &general_pll_clk, &arm_pll_clk };
1621
1622 static struct clk aclk_lcdc = {
1623         .name           = "aclk_lcdc",
1624         .mode           = gate_mode,
1625         .gate_idx       = CLK_GATE_ACLK_LCDC,
1626         .recalc         = clksel_recalc_div,
1627         .set_rate       = clksel_set_rate_div,
1628         .clksel_con     = CRU_CLKSEL16_CON,
1629         .clksel_mask    = 0x1F,
1630         .clksel_shift   = 20,
1631         .clksel_parent_mask     = 3,
1632         .clksel_parent_shift    = 18,
1633         .parents        = aclk_lcdc_parents,
1634 };
1635
1636 static struct clk hclk_lcdc = {
1637         .name           = "hclk_lcdc",
1638         .mode           = gate_mode,
1639         .gate_idx       = CLK_GATE_HCLK_LCDC,
1640         .parent         = &aclk_lcdc,
1641         .clksel_con     = CRU_CLKSEL16_CON,
1642         .recalc         = clksel_recalc_shift,
1643         .set_rate       = clksel_set_rate_shift,
1644         .clksel_mask    = 3,
1645         .clksel_shift   = 25,
1646         .clksel_maxdiv  = 4,
1647 };
1648
1649 static struct clk *xpu_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1650
1651 static struct clk aclk_vepu = {
1652         .name           = "aclk_vepu",
1653         .mode           = gate_mode,
1654         .recalc         = clksel_recalc_div,
1655         .set_rate       = clksel_set_rate_div,
1656         .gate_idx       = CLK_GATE_ACLK_VEPU,
1657         .clksel_con     = CRU_CLKSEL17_CON,
1658         .clksel_mask    = 0x1F,
1659         .clksel_shift   = 2,
1660         .clksel_parent_mask     = 3,
1661         .clksel_parent_shift    = 0,
1662         .parents        = xpu_parents,
1663 };
1664
1665 static struct clk hclk_vepu = {
1666         .name           = "hclk_vepu",
1667         .parent         = &aclk_vepu,
1668         .mode           = gate_mode,
1669         .recalc         = clksel_recalc_shift,
1670         .set_rate       = clksel_set_rate_shift,
1671         .gate_idx       = CLK_GATE_HCLK_VEPU,
1672         .clksel_con     = CRU_CLKSEL17_CON,
1673         .clksel_mask    = 3,
1674         .clksel_shift   = 28,
1675         .clksel_maxdiv  = 4,
1676 };
1677
1678 static struct clk aclk_vdpu = {
1679         .name           = "aclk_vdpu",
1680         .parent         = &general_pll_clk,
1681         .mode           = gate_mode,
1682         .recalc         = clksel_recalc_div,
1683         .set_rate       = clksel_set_rate_div,
1684         .gate_idx       = CLK_GATE_ACLK_VDPU,
1685         .clksel_con     = CRU_CLKSEL17_CON,
1686         .clksel_mask    = 0x1F,
1687         .clksel_shift   = 9,
1688         .clksel_parent_mask     = 3,
1689         .clksel_parent_shift    = 7,
1690         .parents        = xpu_parents,
1691 };
1692
1693 static struct clk hclk_vdpu = {
1694         .name           = "hclk_vdpu",
1695         .parent         = &aclk_vdpu,
1696         .mode           = gate_mode,
1697         .recalc         = clksel_recalc_shift,
1698         .set_rate       = clksel_set_rate_shift,
1699         .gate_idx       = CLK_GATE_HCLK_VDPU,
1700         .clksel_con     = CRU_CLKSEL17_CON,
1701         .clksel_mask    = 3,
1702         .clksel_shift   = 30,
1703         .clksel_maxdiv  = 4,
1704 };
1705
1706 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1707 {
1708         if (clk->parent == &codec_pll_clk && rate != codec_pll_clk.rate && rate == general_pll_clk.rate) {
1709                 clk_set_parent_nolock(clk, &general_pll_clk);
1710         } else if (clk->parent == &general_pll_clk && rate != general_pll_clk.rate) {
1711                 clk_set_parent_nolock(clk, &codec_pll_clk);
1712         }
1713         return clksel_set_rate_div(clk, clksel_round_rate_div(clk, rate));
1714 }
1715
1716 static struct clk clk_gpu = {
1717         .name           = "gpu",
1718         .mode           = gate_mode,
1719         .gate_idx       = CLK_GATE_GPU,
1720         .recalc         = clksel_recalc_div,
1721         .set_rate       = clk_gpu_set_rate,
1722         .clksel_con     = CRU_CLKSEL17_CON,
1723         .clksel_mask    = 0x1F,
1724         .clksel_shift   = 16,
1725         .clksel_parent_mask     = 3,
1726         .clksel_parent_shift    = 14,
1727         .parents        = xpu_parents,
1728 };
1729
1730 static struct clk aclk_gpu = {
1731         .name           = "aclk_gpu",
1732         .mode           = gate_mode,
1733         .gate_idx       = CLK_GATE_ACLK_GPU,
1734         .recalc         = clksel_recalc_div,
1735         .set_rate       = clksel_set_rate_div,
1736         .clksel_con     = CRU_CLKSEL17_CON,
1737         .clksel_mask    = 0x1F,
1738         .clksel_shift   = 23,
1739         .clksel_parent_mask     = 3,
1740         .clksel_parent_shift    = 21,
1741         .parents        = xpu_parents,
1742 };
1743
1744
1745 static struct clk vip_clkin = {
1746         .name           = "vip_clkin",
1747 };
1748
1749 static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
1750
1751 static struct clk clk_vip_out = {
1752         .name           = "vip_out",
1753         .mode           = gate_mode,
1754         .gate_idx       = CLK_GATE_VIP_OUT,
1755         .clksel_con     = CRU_CLKSEL1_CON,
1756         .clksel_parent_mask     = 3,
1757         .clksel_parent_shift    = 7,
1758         .parents        = clk_vip_parents,
1759 };
1760
1761
1762 #define GATE_CLK(NAME,PARENT,ID) \
1763 static struct clk clk_##NAME = { \
1764         .name           = #NAME, \
1765         .parent         = &PARENT, \
1766         .mode           = gate_mode, \
1767         .gate_idx       = CLK_GATE_##ID, \
1768 }
1769
1770 GATE_CLK(i2c0, pclk_cpu, I2C0);
1771 GATE_CLK(i2c1, pclk_periph, I2C1);
1772 GATE_CLK(i2c2, pclk_periph, I2C2);
1773 GATE_CLK(i2c3, pclk_periph, I2C3);
1774
1775 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1776 GATE_CLK(gpio1, pclk_periph, GPIO1);
1777 GATE_CLK(gpio2, pclk_periph, GPIO2);
1778 GATE_CLK(gpio3, pclk_periph, GPIO3);
1779 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1780 GATE_CLK(gpio5, pclk_periph, GPIO5);
1781 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1782
1783 GATE_CLK(dma1, aclk_cpu, DMA1);
1784 GATE_CLK(dma2, aclk_periph, DMA2);
1785
1786 GATE_CLK(gic, aclk_cpu, GIC);
1787 GATE_CLK(intmem, aclk_cpu, INTMEM);
1788 GATE_CLK(rom, hclk_cpu, ROM);
1789 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1790 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1791 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1792 GATE_CLK(efuse, pclk_cpu, EFUSE);
1793 GATE_CLK(tzpc, pclk_cpu, TZPC);
1794 GATE_CLK(debug, pclk_cpu, DEBUG);
1795 GATE_CLK(tpiu, pclk_cpu, TPIU);
1796 GATE_CLK(rtc, pclk_cpu, RTC);
1797 GATE_CLK(pmu, pclk_cpu, PMU);
1798 GATE_CLK(grf, pclk_cpu, GRF);
1799
1800 GATE_CLK(emem, hclk_periph, EMEM);
1801 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
1802 GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
1803 GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
1804 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
1805 GATE_CLK(smc, pclk_periph, SMC);
1806 GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
1807 GATE_CLK(mii_tx, hclk_periph, MII_TX);
1808 GATE_CLK(mii_rx, hclk_periph, MII_RX);
1809 GATE_CLK(hif, hclk_periph, HIF);
1810 GATE_CLK(nandc, hclk_periph, NANDC);
1811 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
1812 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1813 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1814 GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
1815 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1816
1817 GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
1818 GATE_CLK(wdt, pclk_periph, WDT);
1819 GATE_CLK(pwm, pclk_periph, PWM);
1820 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1821 GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
1822 GATE_CLK(vip_input, vip_clkin, VIP_INPUT);
1823 GATE_CLK(jtag, aclk_cpu, JTAG);
1824
1825 GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
1826 GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
1827 GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
1828 GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
1829 GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
1830 GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
1831 GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
1832 GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
1833 GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
1834 GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
1835 GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
1836 GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
1837
1838 GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
1839 GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
1840 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
1841
1842
1843 static void __sramfunc pmu_set_power_domain_sram(enum pmu_power_domain pd, bool on)
1844 {
1845         if (on)
1846                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1847         else
1848                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) |  (1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1849         dsb();
1850
1851         while (pmu_power_domain_is_on(pd) != on)
1852                 ;
1853 }
1854
1855 static noinline void do_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1856 {
1857         static unsigned long save_sp;
1858
1859         DDR_SAVE_SP(save_sp);
1860         pmu_set_power_domain_sram(pd, on);
1861         DDR_RESTORE_SP(save_sp);
1862 }
1863
1864 void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1865 {
1866         unsigned long flags;
1867
1868         mdelay(10);
1869         local_irq_save(flags);
1870         do_pmu_set_power_domain(pd, on);
1871         local_irq_restore(flags);
1872         mdelay(10);
1873 }
1874
1875 static int pd_vcodec_mode(struct clk *clk, int on)
1876 {
1877         if (on) {
1878                 u32 gate;
1879
1880                 gate = cru_clkgate3_con_mirror;
1881                 gate |= (1 << CLK_GATE_ACLK_DDR_VEPU % 32);
1882                 gate &= ~((1 << CLK_GATE_ACLK_VEPU % 32)
1883                         | (1 << CLK_GATE_HCLK_VEPU % 32)
1884                         | (1 << CLK_GATE_HCLK_CPU_VCODEC % 32));
1885                 cru_writel(gate, CRU_CLKGATE3_CON);
1886
1887                 pmu_set_power_domain(PD_VCODEC, true);
1888
1889                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1890         } else {
1891                 pmu_set_power_domain(PD_VCODEC, false);
1892         }
1893
1894         return 0;
1895 }
1896
1897 static struct clk pd_vcodec = {
1898         .name   = "pd_vcodec",
1899         .flags  = IS_PD,
1900         .mode   = pd_vcodec_mode,
1901         .gate_idx       = PD_VCODEC,
1902 };
1903
1904 static int pd_display_mode(struct clk *clk, int on)
1905 {
1906 #if 0   /* display power domain is buggy, always keep it on.  */
1907         if (on) {
1908                 u32 gate, gate2;
1909
1910                 gate = cru_clkgate3_con_mirror;
1911                 gate |= (1 << CLK_GATE_ACLK_DDR_LCDC % 32);
1912                 gate &= ~((1 << CLK_GATE_HCLK_CPU_DISPLAY % 32)
1913                         | (1 << CLK_GATE_HCLK_DISP_MATRIX % 32)
1914                         | (1 << CLK_GATE_ACLK_DISP_MATRIX % 32)
1915                         | (1 << CLK_GATE_DCLK_EBOOK % 32)
1916                         | (1 << CLK_GATE_HCLK_EBOOK % 32)
1917                         | (1 << CLK_GATE_HCLK_IPP % 32)
1918                         | (1 << CLK_GATE_ACLK_IPP % 32)
1919                         | (1 << CLK_GATE_DCLK_LCDC % 32)
1920                         | (1 << CLK_GATE_HCLK_LCDC % 32)
1921                         | (1 << CLK_GATE_ACLK_LCDC % 32));
1922                 cru_writel(gate, CRU_CLKGATE3_CON);
1923
1924                 gate2 = cru_readl(CRU_CLKGATE2_CON);
1925                 gate = gate2;
1926                 gate &= ~((1 << CLK_GATE_VIP_OUT % 32)
1927                         | (1 << CLK_GATE_VIP_SLAVE % 32)
1928                         | (1 << CLK_GATE_VIP_MATRIX % 32)
1929                         | (1 << CLK_GATE_VIP_BUS % 32));
1930                 cru_writel(gate, CRU_CLKGATE2_CON);
1931
1932                 pmu_set_power_domain(PD_DISPLAY, true);
1933
1934                 cru_writel(gate2, CRU_CLKGATE2_CON);
1935                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1936         } else {
1937                 pmu_set_power_domain(PD_DISPLAY, false);
1938         }
1939 #endif
1940
1941         return 0;
1942 }
1943
1944 static struct clk pd_display = {
1945         .name   = "pd_display",
1946         .flags  = IS_PD,
1947         .mode   = pd_display_mode,
1948         .gate_idx       = PD_DISPLAY,
1949 };
1950
1951 static int pd_gpu_mode(struct clk *clk, int on)
1952 {
1953         if (on) {
1954                 pmu_set_power_domain(PD_GPU, true);
1955         } else {
1956                 pmu_set_power_domain(PD_GPU, false);
1957         }
1958
1959         return 0;
1960 }
1961
1962 static struct clk pd_gpu = {
1963         .name   = "pd_gpu",
1964         .flags  = IS_PD,
1965         .mode   = pd_gpu_mode,
1966         .gate_idx       = PD_GPU,
1967 };
1968
1969
1970 #define CLK(dev, con, ck) \
1971         { \
1972                 .dev_id = dev, \
1973                 .con_id = con, \
1974                 .clk = ck, \
1975         }
1976
1977 #define CLK1(name) \
1978         { \
1979                 .dev_id = NULL, \
1980                 .con_id = #name, \
1981                 .clk = &clk_##name, \
1982         }
1983
1984 static struct clk_lookup clks[] = {
1985         CLK(NULL, "xin24m", &xin24m),
1986         CLK(NULL, "xin27m", &xin27m),
1987         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1988         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1989         CLK(NULL, "gpsclk", &gpsclk),
1990         CLK(NULL, "vip_clkin", &vip_clkin),
1991
1992         CLK1(12m),
1993         CLK(NULL, "arm_pll", &arm_pll_clk),
1994         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1995         CLK(NULL, "codec_pll", &codec_pll_clk),
1996         CLK(NULL, "general_pll", &general_pll_clk),
1997
1998         CLK1(core),
1999         CLK(NULL, "aclk_cpu", &aclk_cpu),
2000         CLK(NULL, "hclk_cpu", &hclk_cpu),
2001         CLK(NULL, "pclk_cpu", &pclk_cpu),
2002
2003         CLK(NULL, "aclk_periph", &aclk_periph),
2004         CLK(NULL, "hclk_periph", &hclk_periph),
2005         CLK(NULL, "pclk_periph", &pclk_periph),
2006
2007         CLK1(vip_out),
2008         CLK1(otgphy0),
2009         CLK1(otgphy1),
2010         CLK1(uhost),
2011         CLK1(mac_ref_div),
2012         CLK1(mac_ref),
2013
2014         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2015         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2016         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2017         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
2018         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
2019         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
2020         CLK(NULL, "spdif_div", &clk_spdif_div),
2021         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
2022         CLK(NULL, "spdif", &clk_spdif),
2023
2024         CLK1(spi_src),
2025         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2026         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2027
2028         CLK1(saradc),
2029         CLK1(timer0),
2030         CLK1(timer1),
2031         CLK1(timer2),
2032         CLK1(timer3),
2033
2034         CLK1(mmc_src),
2035         CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
2036         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
2037         CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
2038         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
2039         CLK1(emmc),
2040         CLK1(hclk_emmc),
2041         CLK1(ddr),
2042
2043         CLK1(uart01_src),
2044         CLK("rk29_serial.0", "uart", &clk_uart0),
2045         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
2046         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2047         CLK("rk29_serial.1", "uart", &clk_uart1),
2048         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
2049         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2050
2051         CLK1(uart23_src),
2052         CLK("rk29_serial.2", "uart", &clk_uart2),
2053         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
2054         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2055         CLK("rk29_serial.3", "uart", &clk_uart3),
2056         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
2057         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2058
2059         CLK1(hsadc_div),
2060         CLK1(hsadc_frac_div),
2061         CLK1(demod),
2062         CLK1(hsadc),
2063         CLK1(hsadc_div2),
2064         CLK1(hsadc_div2_inv),
2065         CLK1(hsadc_out),
2066
2067         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
2068         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
2069         CLK(NULL, "dclk_ebook", &dclk_ebook),
2070         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
2071         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
2072
2073         CLK(NULL, "aclk_vepu", &aclk_vepu),
2074         CLK(NULL, "hclk_vepu", &hclk_vepu),
2075         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
2076         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
2077         CLK1(gpu),
2078         CLK(NULL, "aclk_gpu", &aclk_gpu),
2079
2080         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
2081         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
2082         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
2083         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
2084
2085         CLK1(gpio0),
2086         CLK1(gpio1),
2087         CLK1(gpio2),
2088         CLK1(gpio3),
2089         CLK1(gpio4),
2090         CLK1(gpio5),
2091         CLK1(gpio6),
2092
2093         CLK1(dma1),
2094         CLK1(dma2),
2095
2096         CLK1(gic),
2097         CLK1(intmem),
2098         CLK1(rom),
2099         CLK1(ddr_phy),
2100         CLK1(ddr_reg),
2101         CLK1(ddr_cpu),
2102         CLK1(efuse),
2103         CLK1(tzpc),
2104         CLK1(debug),
2105         CLK1(tpiu),
2106         CLK1(rtc),
2107         CLK1(pmu),
2108         CLK1(grf),
2109
2110         CLK1(emem),
2111         CLK1(hclk_usb_peri),
2112         CLK1(aclk_ddr_peri),
2113         CLK1(aclk_cpu_peri),
2114         CLK1(aclk_smc),
2115         CLK1(smc),
2116         CLK1(hclk_mac),
2117         CLK1(mii_tx),
2118         CLK1(mii_rx),
2119         CLK1(hif),
2120         CLK1(nandc),
2121         CLK1(hclk_hsadc),
2122         CLK1(usbotg0),
2123         CLK1(usbotg1),
2124         CLK1(hclk_uhost),
2125         CLK1(pid_filter),
2126
2127         CLK1(vip_slave),
2128         CLK1(wdt),
2129         CLK1(pwm),
2130         CLK1(vip_bus),
2131         CLK1(vip_matrix),
2132         CLK1(vip_input),
2133         CLK1(jtag),
2134
2135         CLK1(aclk_ddr_lcdc),
2136         CLK1(aclk_ipp),
2137         CLK1(hclk_ipp),
2138         CLK1(hclk_ebook),
2139         CLK1(aclk_disp_matrix),
2140         CLK1(hclk_disp_matrix),
2141         CLK1(aclk_ddr_vepu),
2142         CLK1(aclk_ddr_vdpu),
2143         CLK1(aclk_ddr_gpu),
2144         CLK1(hclk_gpu),
2145         CLK1(hclk_cpu_vcodec),
2146         CLK1(hclk_cpu_display),
2147
2148         CLK(NULL, "pd_vcodec", &pd_vcodec),
2149         CLK(NULL, "pd_display", &pd_display),
2150         CLK(NULL, "pd_gpu", &pd_gpu),
2151 };
2152
2153 static LIST_HEAD(clocks);
2154 static DEFINE_MUTEX(clocks_mutex);
2155 static DEFINE_SPINLOCK(clockfw_lock);
2156 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
2157 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
2158
2159 static int clk_enable_nolock(struct clk *clk)
2160 {
2161         int ret = 0;
2162
2163         if (clk->usecount == 0) {
2164                 if (clk->parent) {
2165                         ret = clk_enable_nolock(clk->parent);
2166                         if (ret)
2167                                 return ret;
2168                 }
2169
2170                 if (clk->mode) {
2171                         ret = clk->mode(clk, 1);
2172                         if (ret) {
2173                                 if (clk->parent)
2174                                         clk_disable_nolock(clk->parent);
2175                                 return ret;
2176                         }
2177                 }
2178                 pr_debug("%s enabled\n", clk->name);
2179         }
2180         clk->usecount++;
2181
2182         return ret;
2183 }
2184
2185 int clk_enable(struct clk *clk)
2186 {
2187         int ret = 0;
2188
2189         if (clk == NULL || IS_ERR(clk))
2190                 return -EINVAL;
2191
2192         LOCK();
2193         ret = clk_enable_nolock(clk);
2194         UNLOCK();
2195
2196         return ret;
2197 }
2198 EXPORT_SYMBOL(clk_enable);
2199
2200 static void clk_disable_nolock(struct clk *clk)
2201 {
2202         if (clk->usecount == 0) {
2203                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
2204                 WARN_ON(1);
2205                 return;
2206         }
2207
2208         if (--clk->usecount == 0) {
2209                 if (clk->mode)
2210                         clk->mode(clk, 0);
2211                 pr_debug("%s disabled\n", clk->name);
2212                 if (clk->parent)
2213                         clk_disable_nolock(clk->parent);
2214         }
2215 }
2216
2217 void clk_disable(struct clk *clk)
2218 {
2219         if (clk == NULL || IS_ERR(clk))
2220                 return;
2221
2222         LOCK();
2223         clk_disable_nolock(clk);
2224         UNLOCK();
2225 }
2226 EXPORT_SYMBOL(clk_disable);
2227
2228 unsigned long clk_get_rate(struct clk *clk)
2229 {
2230         if (clk == NULL || IS_ERR(clk))
2231                 return 0;
2232
2233         return clk->rate;
2234 }
2235 EXPORT_SYMBOL(clk_get_rate);
2236
2237 /*-------------------------------------------------------------------------
2238  * Optional clock functions defined in include/linux/clk.h
2239  *-------------------------------------------------------------------------*/
2240
2241 /* Given a clock and a rate apply a clock specific rounding function */
2242 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
2243 {
2244         if (clk->round_rate)
2245                 return clk->round_rate(clk, rate);
2246
2247         if (clk->flags & RATE_FIXED)
2248                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
2249
2250         return clk->rate;
2251 }
2252
2253 long clk_round_rate(struct clk *clk, unsigned long rate)
2254 {
2255         long ret = 0;
2256
2257         if (clk == NULL || IS_ERR(clk))
2258                 return ret;
2259
2260         LOCK();
2261         ret = clk_round_rate_nolock(clk, rate);
2262         UNLOCK();
2263
2264         return ret;
2265 }
2266 EXPORT_SYMBOL(clk_round_rate);
2267
2268 static void __clk_recalc(struct clk *clk)
2269 {
2270         if (unlikely(clk->flags & RATE_FIXED))
2271                 return;
2272         if (clk->recalc)
2273                 clk->rate = clk->recalc(clk);
2274         else if (clk->parent)
2275                 clk->rate = clk->parent->rate;
2276         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
2277 }
2278
2279 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
2280 {
2281         int ret;
2282
2283         if (rate == clk->rate)
2284                 return 0;
2285
2286         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
2287
2288         if (clk->flags & CONFIG_PARTICIPANT)
2289                 return -EINVAL;
2290
2291         if (!clk->set_rate)
2292                 return -EINVAL;
2293
2294         ret = clk->set_rate(clk, rate);
2295
2296         if (ret == 0) {
2297                 __clk_recalc(clk);
2298                 __propagate_rate(clk);
2299         }
2300
2301         return ret;
2302 }
2303
2304 /* Set the clock rate for a clock source */
2305 int clk_set_rate(struct clk *clk, unsigned long rate)
2306 {
2307         int ret = -EINVAL;
2308
2309         if (clk == NULL || IS_ERR(clk))
2310                 return ret;
2311
2312         LOCK();
2313         ret = clk_set_rate_nolock(clk, rate);
2314         UNLOCK();
2315
2316         return ret;
2317 }
2318 EXPORT_SYMBOL(clk_set_rate);
2319
2320 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
2321 {
2322         int ret;
2323         int enabled = clk->usecount > 0;
2324         struct clk *old_parent = clk->parent;
2325
2326         if (clk->parent == parent)
2327                 return 0;
2328
2329         /* if clk is already enabled, enable new parent first and disable old parent later. */
2330         if (enabled)
2331                 clk_enable_nolock(parent);
2332
2333         if (clk->set_parent)
2334                 ret = clk->set_parent(clk, parent);
2335         else
2336                 ret = clksel_set_parent(clk, parent);
2337
2338         if (ret == 0) {
2339                 /* OK */
2340                 __clk_reparent(clk, parent);
2341                 __clk_recalc(clk);
2342                 __propagate_rate(clk);
2343                 if (enabled)
2344                         clk_disable_nolock(old_parent);
2345         } else {
2346                 if (enabled)
2347                         clk_disable_nolock(parent);
2348         }
2349
2350         return ret;
2351 }
2352
2353 int clk_set_parent(struct clk *clk, struct clk *parent)
2354 {
2355         int ret = -EINVAL;
2356
2357         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
2358                 return ret;
2359
2360         if (clk->set_parent == NULL && clk->parents == NULL)
2361                 return ret;
2362
2363         LOCK();
2364         if (clk->usecount == 0)
2365                 ret = clk_set_parent_nolock(clk, parent);
2366         else
2367                 ret = -EBUSY;
2368         UNLOCK();
2369
2370         return ret;
2371 }
2372 EXPORT_SYMBOL(clk_set_parent);
2373
2374 struct clk *clk_get_parent(struct clk *clk)
2375 {
2376         return clk->parent;
2377 }
2378 EXPORT_SYMBOL(clk_get_parent);
2379
2380 static void __clk_reparent(struct clk *child, struct clk *parent)
2381 {
2382         if (child->parent == parent)
2383                 return;
2384         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
2385
2386         list_del_init(&child->sibling);
2387         if (parent)
2388                 list_add(&child->sibling, &parent->children);
2389         child->parent = parent;
2390 }
2391
2392 /* Propagate rate to children */
2393 static void __propagate_rate(struct clk *tclk)
2394 {
2395         struct clk *clkp;
2396
2397         list_for_each_entry(clkp, &tclk->children, sibling) {
2398                 __clk_recalc(clkp);
2399                 __propagate_rate(clkp);
2400         }
2401 }
2402
2403 static LIST_HEAD(root_clks);
2404
2405 /**
2406  * recalculate_root_clocks - recalculate and propagate all root clocks
2407  *
2408  * Recalculates all root clocks (clocks with no parent), which if the
2409  * clock's .recalc is set correctly, should also propagate their rates.
2410  * Called at init.
2411  */
2412 static void clk_recalculate_root_clocks_nolock(void)
2413 {
2414         struct clk *clkp;
2415
2416         list_for_each_entry(clkp, &root_clks, sibling) {
2417                 __clk_recalc(clkp);
2418                 __propagate_rate(clkp);
2419         }
2420 }
2421
2422 void clk_recalculate_root_clocks(void)
2423 {
2424         LOCK();
2425         clk_recalculate_root_clocks_nolock();
2426         UNLOCK();
2427 }
2428
2429
2430 /**
2431  * clk_preinit - initialize any fields in the struct clk before clk init
2432  * @clk: struct clk * to initialize
2433  *
2434  * Initialize any struct clk fields needed before normal clk initialization
2435  * can run.  No return value.
2436  */
2437 static void clk_preinit(struct clk *clk)
2438 {
2439         INIT_LIST_HEAD(&clk->children);
2440 }
2441
2442 static int clk_register(struct clk *clk)
2443 {
2444         if (clk == NULL || IS_ERR(clk))
2445                 return -EINVAL;
2446
2447         /*
2448          * trap out already registered clocks
2449          */
2450         if (clk->node.next || clk->node.prev)
2451                 return 0;
2452
2453         mutex_lock(&clocks_mutex);
2454
2455         if (clk->get_parent)
2456                 clk->parent = clk->get_parent(clk);
2457         else if (clk->parents)
2458                 clk->parent = clksel_get_parent(clk);
2459
2460         if (clk->parent)
2461                 list_add(&clk->sibling, &clk->parent->children);
2462         else
2463                 list_add(&clk->sibling, &root_clks);
2464
2465         list_add(&clk->node, &clocks);
2466
2467         mutex_unlock(&clocks_mutex);
2468
2469         return 0;
2470 }
2471
2472 static unsigned int __initdata armclk = 300 * MHZ;
2473
2474 /*
2475  * You can override arm_clk rate with armclk= cmdline option.
2476  */
2477 static int __init armclk_setup(char *str)
2478 {
2479         get_option(&str, &armclk);
2480
2481         if (!armclk)
2482                 return 0;
2483
2484         if (armclk < 10000)
2485                 armclk *= MHZ;
2486
2487         clk_set_rate_nolock(&arm_pll_clk, armclk);
2488         return 0;
2489 }
2490 early_param("armclk", armclk_setup);
2491
2492 static void __init rk29_clock_common_init(unsigned long ppll_rate, unsigned long cpll_rate)
2493 {
2494         unsigned long aclk_p, hclk_p, pclk_p;
2495         struct clk *aclk_vepu_parent, *aclk_vdpu_parent, *aclk_gpu_parent;
2496
2497         /* general pll */
2498         switch (ppll_rate) {
2499         case 96 * MHZ:
2500                 aclk_p = 96 * MHZ;
2501                 hclk_p = 48 * MHZ;
2502                 pclk_p = 24 * MHZ;
2503                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
2504                 break;
2505         case 144 * MHZ:
2506                 aclk_p = 144 * MHZ;
2507                 hclk_p = 72 * MHZ;
2508                 pclk_p = 36 * MHZ;
2509                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &codec_pll_clk;
2510                 break;
2511         default:
2512                 ppll_rate = 288 * MHZ;
2513         case 288 * MHZ:
2514         case 300 * MHZ:
2515                 aclk_p = ppll_rate / 2;
2516                 hclk_p = ppll_rate / 2;
2517                 pclk_p = ppll_rate / 8;
2518                 aclk_gpu_parent = aclk_vdpu_parent = aclk_vepu_parent = &general_pll_clk;
2519                 break;
2520         }
2521
2522         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
2523         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2524         clk_set_rate_nolock(&aclk_periph, aclk_p);
2525         clk_set_rate_nolock(&hclk_periph, hclk_p);
2526         clk_set_rate_nolock(&pclk_periph, pclk_p);
2527         clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
2528         clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2529         if (clk_uhost.rate != 48 * MHZ)
2530                 clk_set_parent_nolock(&clk_uhost, &otgphy1_clkin);
2531         clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
2532         clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
2533         clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
2534         clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
2535         clk_set_rate_nolock(&clk_spi0, 40 * MHZ);
2536         clk_set_rate_nolock(&clk_spi1, 40 * MHZ);
2537         clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
2538         clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
2539         clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
2540         clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
2541         clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
2542         clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
2543
2544         /* codec pll */
2545         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
2546         clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
2547
2548         /* ddr pll */
2549         clk_set_parent_nolock(&aclk_lcdc, &ddr_pll_clk);
2550
2551         /* arm pll */
2552         clk_set_rate_nolock(&arm_pll_clk, armclk);
2553
2554         /*you can choose clk parent form codec pll or periph pll for following logic*/
2555         clk_set_parent_nolock(&aclk_vepu, aclk_vepu_parent);
2556         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
2557         clk_set_rate_nolock(&clk_aclk_ddr_vepu, 300 * MHZ);
2558         clk_set_rate_nolock(&hclk_vepu, 150 * MHZ);
2559         clk_set_parent_nolock(&aclk_vdpu, aclk_vdpu_parent);
2560         clk_set_parent_nolock(&aclk_gpu, aclk_gpu_parent);
2561         clk_set_rate_nolock(&aclk_gpu, 300 * MHZ);
2562 }
2563
2564 static void __init clk_enable_init_clocks(void)
2565 {
2566         clk_enable_nolock(&hclk_cpu);
2567         clk_enable_nolock(&pclk_cpu);
2568         clk_enable_nolock(&hclk_periph);
2569         clk_enable_nolock(&pclk_periph);
2570         clk_enable_nolock(&clk_nandc);
2571         clk_enable_nolock(&clk_aclk_cpu_peri);
2572         clk_enable_nolock(&clk_aclk_ddr_peri);
2573         clk_enable_nolock(&clk_grf);
2574         clk_enable_nolock(&clk_pmu);
2575         clk_enable_nolock(&clk_ddr_cpu);
2576         clk_enable_nolock(&clk_ddr_reg);
2577         clk_enable_nolock(&clk_ddr_phy);
2578         clk_enable_nolock(&clk_gic);
2579         clk_enable_nolock(&clk_dma2);
2580         clk_enable_nolock(&clk_dma1);
2581         clk_enable_nolock(&clk_emem);
2582         clk_enable_nolock(&clk_intmem);
2583         clk_enable_nolock(&clk_ddr);
2584         clk_enable_nolock(&clk_debug);
2585         clk_enable_nolock(&clk_tpiu);
2586         clk_enable_nolock(&clk_jtag);
2587         clk_enable_nolock(&clk_uart1);
2588 }
2589
2590 static int __init clk_disable_unused(void)
2591 {
2592         struct clk *ck;
2593
2594         list_for_each_entry(ck, &clocks, node) {
2595                 if (ck->usecount > 0 || ck->mode == NULL || (ck->flags & IS_PD))
2596                         continue;
2597
2598                 LOCK();
2599                 clk_enable_nolock(ck);
2600                 clk_disable_nolock(ck);
2601                 UNLOCK();
2602         }
2603
2604         return 0;
2605 }
2606
2607 void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate, bool _has_xin27m)
2608 {
2609         struct clk_lookup *lk;
2610
2611         has_xin27m = _has_xin27m;
2612
2613         cru_clkgate3_con_mirror = cru_readl(CRU_CLKGATE3_CON);
2614         cru_softrst0_con_mirror = cru_readl(CRU_SOFTRST0_CON);
2615
2616         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2617                 clk_preinit(lk->clk);
2618
2619         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2620                 clkdev_add(lk);
2621                 clk_register(lk->clk);
2622         }
2623
2624         clk_recalculate_root_clocks_nolock();
2625
2626         /*
2627          * Only enable those clocks we will need, let the drivers
2628          * enable other clocks as necessary
2629          */
2630         clk_enable_init_clocks();
2631
2632         /*
2633          * Disable any unused clocks left on by the bootloader
2634          */
2635         clk_disable_unused();
2636
2637         rk29_clock_common_init(ppll_rate, cpll_rate);
2638
2639         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz",
2640                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
2641                aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
2642         printk(KERN_CONT " (20110715)\n");
2643 }
2644
2645 void __init rk29_clock_init(enum periph_pll ppll_rate)
2646 {
2647         rk29_clock_init2(ppll_rate, codec_pll_445mhz, true);
2648 }
2649
2650 #ifdef CONFIG_PROC_FS
2651 #include <linux/proc_fs.h>
2652 #include <linux/seq_file.h>
2653
2654 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2655 {
2656         struct clk* ck;
2657         int i;
2658         unsigned long rate = clk->rate;
2659
2660         for (i = 0; i < deep; i++)
2661                 seq_printf(s, "    ");
2662
2663         seq_printf(s, "%-11s ", clk->name);
2664
2665         if (clk->flags & IS_PD) {
2666                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
2667         }
2668
2669         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
2670                 u32 reg;
2671                 int idx = clk->gate_idx;
2672                 u32 v;
2673
2674                 reg = CRU_CLKGATE0_CON;
2675                 reg += (idx >> 5) << 2;
2676                 idx &= 0x1F;
2677
2678                 if (reg == CRU_CLKGATE3_CON)
2679                         v = cru_clkgate3_con_mirror & (1 << idx);
2680                 else
2681                         v = cru_readl(reg) & (1 << idx);
2682
2683                 seq_printf(s, "%s ", v ? "off" : "on ");
2684         }
2685
2686         if (clk == &arm_pll_clk) {
2687                 switch (cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) {
2688                 case CRU_CPU_MODE_SLOW:   seq_printf(s, "slow   "); break;
2689                 case CRU_CPU_MODE_NORMAL: seq_printf(s, "normal "); break;
2690                 case CRU_CPU_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2691                 }
2692                 if (cru_readl(CRU_APLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2693         } else if (clk == &ddr_pll_clk) {
2694                 switch (cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) {
2695                 case CRU_DDR_MODE_SLOW:   seq_printf(s, "slow   "); break;
2696                 case CRU_DDR_MODE_NORMAL: seq_printf(s, "normal "); break;
2697                 case CRU_DDR_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2698                 }
2699                 if (cru_readl(CRU_DPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2700         } else if (clk == &codec_pll_clk) {
2701                 switch (cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) {
2702                 case CRU_CODEC_MODE_SLOW:   seq_printf(s, "slow   "); break;
2703                 case CRU_CODEC_MODE_NORMAL: seq_printf(s, "normal "); break;
2704                 case CRU_CODEC_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2705                 }
2706                 if (cru_readl(CRU_CPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2707         } else if (clk == &general_pll_clk) {
2708                 switch (cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) {
2709                 case CRU_GENERAL_MODE_SLOW:   seq_printf(s, "slow   "); break;
2710                 case CRU_GENERAL_MODE_NORMAL: seq_printf(s, "normal "); break;
2711                 case CRU_GENERAL_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2712                 }
2713                 if (cru_readl(CRU_GPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2714         }
2715
2716         if (rate >= MHZ) {
2717                 if (rate % MHZ)
2718                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2719                 else
2720                         seq_printf(s, "%ld MHz", rate / MHZ);
2721         } else if (rate >= KHZ) {
2722                 if (rate % KHZ)
2723                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2724                 else
2725                         seq_printf(s, "%ld KHz", rate / KHZ);
2726         } else {
2727                 seq_printf(s, "%ld Hz", rate);
2728         }
2729
2730         seq_printf(s, " usecount = %d", clk->usecount);
2731
2732         if (clk->parent)
2733                 seq_printf(s, " parent = %s", clk->parent->name);
2734
2735         seq_printf(s, "\n");
2736
2737         list_for_each_entry(ck, &clocks, node) {
2738                 if (ck->parent == clk)
2739                         dump_clock(s, ck, deep + 1);
2740         }
2741 }
2742
2743 static int proc_clk_show(struct seq_file *s, void *v)
2744 {
2745         struct clk* clk;
2746
2747         mutex_lock(&clocks_mutex);
2748         list_for_each_entry(clk, &clocks, node) {
2749                 if (!clk->parent)
2750                         dump_clock(s, clk, 0);
2751         }
2752         mutex_unlock(&clocks_mutex);
2753
2754         seq_printf(s, "\nCRU Registers:\n");
2755         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2756         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2757         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2758         seq_printf(s, "GPLL     : 0x%08x\n", cru_readl(CRU_GPLL_CON));
2759         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2760         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2761         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2762         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2763         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2764         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2765         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2766         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2767         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2768         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2769         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2770         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2771         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2772         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2773         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2774         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2775         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2776         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2777         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2778         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2779         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2780         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2781         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2782         seq_printf(s, "CLKGATE3M: 0x%08x\n", cru_clkgate3_con_mirror);
2783         seq_printf(s, "SOFTRST0 : 0x%08x\n", cru_readl(CRU_SOFTRST0_CON));
2784         seq_printf(s, "SOFTRST0M: 0x%08x\n", cru_softrst0_con_mirror);
2785         seq_printf(s, "SOFTRST1 : 0x%08x\n", cru_readl(CRU_SOFTRST1_CON));
2786         seq_printf(s, "SOFTRST2 : 0x%08x\n", cru_readl(CRU_SOFTRST2_CON));
2787
2788         seq_printf(s, "\nPMU Registers:\n");
2789         seq_printf(s, "WAKEUP_EN0 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN0));
2790         seq_printf(s, "WAKEUP_EN1 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN1));
2791         seq_printf(s, "WAKEUP_EN2 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN2));
2792         seq_printf(s, "PD_CON     : 0x%08x\n", pmu_readl(PMU_PD_CON));
2793         seq_printf(s, "MISC_CON   : 0x%08x\n", pmu_readl(PMU_MISC_CON));
2794         seq_printf(s, "PLL_CNT    : 0x%08x\n", pmu_readl(PMU_PLL_CNT));
2795         seq_printf(s, "PD_ST      : 0x%08x\n", pmu_readl(PMU_PD_ST));
2796         seq_printf(s, "INT_ST     : 0x%08x\n", pmu_readl(PMU_INT_ST));
2797
2798         return 0;
2799 }
2800
2801 static int proc_clk_open(struct inode *inode, struct file *file)
2802 {
2803         return single_open(file, proc_clk_show, NULL);
2804 }
2805
2806 static const struct file_operations proc_clk_fops = {
2807         .open           = proc_clk_open,
2808         .read           = seq_read,
2809         .llseek         = seq_lseek,
2810         .release        = single_release,
2811 };
2812
2813 static int __init clk_proc_init(void)
2814 {
2815         proc_create("clocks", 0, NULL, &proc_clk_fops);
2816         return 0;
2817
2818 }
2819 late_initcall(clk_proc_init);
2820 #endif /* CONFIG_PROC_FS */
2821