arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33
  34 /* CRU PLL CON */
  35 #define PLL_HIGH_BAND   (0x01 << 16)
  36 #define PLL_LOW_BAND    (0x00 << 16)
  37 #define PLL_PD          (0x01 << 15)
  38
  39 #define PLL_CLKR(i)     ((((i) - 1) & 0x1f) << 10)
  40 #define PLL_NR(v)       ((((v) >> 10) & 0x1f) + 1)
  41
  42 #define PLL_CLKF(i)     ((((i) - 1) & 0x7f) << 3)
  43 #define PLL_NF(v)       ((((v) >> 3) & 0x7f) + 1)
  44 #define PLL_NF2(v)      (((((v) >> 3) & 0x7f) + 1) << 1)
  45
  46 #define PLL_CLKOD(i)    (((i) & 0x03) << 1)
  47 #define PLL_NO_1        PLL_CLKOD(0)
  48 #define PLL_NO_2        PLL_CLKOD(1)
  49 #define PLL_NO_4        PLL_CLKOD(2)
  50 #define PLL_NO_8        PLL_CLKOD(3)
  51 #define PLL_NO_SHIFT(v) (((v) >> 1) & 0x03)
  52
  53 #define PLL_BYPASS      (0x01)
  54
  55 /* CRU MODE CON */
  56 #define CRU_CPU_MODE_MASK       (0x03u << 0)
  57 #define CRU_CPU_MODE_SLOW       (0x00u << 0)
  58 #define CRU_CPU_MODE_NORMAL     (0x01u << 0)
  59 #define CRU_CPU_MODE_DSLOW      (0x02u << 0)
  60
  61 #define CRU_PERIPH_MODE_MASK    (0x03u << 2)
  62 #define CRU_PERIPH_MODE_SLOW    (0x00u << 2)
  63 #define CRU_PERIPH_MODE_NORMAL  (0x01u << 2)
  64 #define CRU_PERIPH_MODE_DSLOW   (0x02u << 2)
  65
  66 #define CRU_CODEC_MODE_MASK     (0x03u << 4)
  67 #define CRU_CODEC_MODE_SLOW     (0x00u << 4)
  68 #define CRU_CODEC_MODE_NORMAL   (0x01u << 4)
  69 #define CRU_CODEC_MODE_DSLOW    (0x02u << 4)
  70
  71 #define CRU_DDR_MODE_MASK       (0x03u << 6)
  72 #define CRU_DDR_MODE_SLOW       (0x00u << 6)
  73 #define CRU_DDR_MODE_NORMAL     (0x01u << 6)
  74 #define CRU_DDR_MODE_DSLOW      (0x02u << 6)
  75
  76 /* Clock flags */
  77 /* bit 0 is free */
  78 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  79 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  80 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
  81
  82 #define cru_readl(offset)       readl(RK29_CRU_BASE + offset)
  83 #define cru_writel(v, offset)   writel(v, RK29_CRU_BASE + offset)
  84 #define cru_writel_force(v, offset)     do { u32 _v = v; u32 _count = 5; do { cru_writel(_v, offset); } while (cru_readl(offset) != _v && _count--); } while (0)        /* huangtao: when write CRU_xPLL_CON, first time may failed, so try again. unknown why. */
  85
  86 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  87
  88 #define MHZ                     (1000*1000)
  89 #define KHZ                     1000
  90
  91 struct clk {
  92         struct list_head        node;
  93         const char              *name;
  94         struct clk              *parent;
  95         struct list_head        children;
  96         struct list_head        sibling;        /* node for children */
  97         unsigned long           rate;
  98         u32                     flags;
  99         int                     (*mode)(struct clk *clk, int on);
 100         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
 101         int                     (*set_rate)(struct clk *, unsigned long);
 102         long                    (*round_rate)(struct clk *, unsigned long);
 103         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
 104         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
 105         s32                     usecount;
 106         u8                      gate_idx;
 107         u8                      pll_idx;
 108         u8                      clksel_con;
 109         u8                      clksel_mask;
 110         u8                      clksel_shift;
 111         u8                      clksel_maxdiv;
 112         u8                      clksel_parent_mask;
 113         u8                      clksel_parent_shift;
 114         struct clk              **parents;
 115 };
 116
 117 static int clk_enable_nolock(struct clk *clk);
 118 static void clk_disable_nolock(struct clk *clk);
 119 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
 120 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
 121 static void __clk_reparent(struct clk *child, struct clk *parent);
 122 static void __propagate_rate(struct clk *tclk);
 123
 124 static unsigned long clksel_recalc_div(struct clk *clk)
 125 {
 126         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
 127         unsigned long rate = clk->parent->rate / div;
 128         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 129         return rate;
 130 }
 131
 132 static unsigned long clksel_recalc_shift(struct clk *clk)
 133 {
 134         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
 135         unsigned long rate = clk->parent->rate >> shift;
 136         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 137         return rate;
 138 }
 139
 140 static unsigned long clksel_recalc_frac(struct clk *clk)
 141 {
 142         unsigned long rate;
 143         u64 rate64;
 144         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 145         if (r == 0) // FPGA ?
 146                 return clk->parent->rate;
 147         numerator = r >> 16;
 148         denominator = r & 0xFFFF;
 149         rate64 = (u64)clk->parent->rate * numerator;
 150         do_div(rate64, denominator);
 151         rate = rate64;
 152         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 153         return rate;
 154 }
 155
 156 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 157 {
 158         u32 div;
 159
 160         for (div = 0; div <= clk->clksel_mask; div++) {
 161                 u32 new_rate = clk->parent->rate / (div + 1);
 162                 if (new_rate <= rate) {
 163                         u32 v = cru_readl(clk->clksel_con);
 164                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 165                         v |= div << clk->clksel_shift;
 166                         cru_writel(v, clk->clksel_con);
 167                         clk->rate = new_rate;
 168                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 169                         return 0;
 170                 }
 171         }
 172
 173         return -ENOENT;
 174 }
 175
 176 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 177 {
 178         u32 shift;
 179
 180         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 181                 u32 new_rate = clk->parent->rate >> shift;
 182                 if (new_rate <= rate) {
 183                         u32 v = cru_readl(clk->clksel_con);
 184                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 185                         v |= shift << clk->clksel_shift;
 186                         cru_writel(v, clk->clksel_con);
 187                         clk->rate = new_rate;
 188                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 189                         return 0;
 190                 }
 191         }
 192
 193         return -ENOENT;
 194 }
 195
 196 static struct clk* clksel_get_parent(struct clk *clk)
 197 {
 198         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 199 }
 200
 201 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 202 {
 203         struct clk **p = clk->parents;
 204         u32 i;
 205
 206         if (unlikely(!p))
 207                 return -EINVAL;
 208         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 209                 u32 v;
 210                 if (*p != parent)
 211                         continue;
 212                 v = cru_readl(clk->clksel_con);
 213                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 214                 v |= (i << clk->clksel_parent_shift);
 215                 cru_writel(v, clk->clksel_con);
 216                 return 0;
 217         }
 218         return -EINVAL;
 219 }
 220
 221 static int gate_mode(struct clk *clk, int on)
 222 {
 223         u32 reg;
 224         int idx = clk->gate_idx;
 225         u32 v;
 226
 227         if (idx >= CLK_GATE_MAX)
 228                 return -EINVAL;
 229
 230         reg = CRU_CLKGATE0_CON;
 231         reg += (idx >> 5) << 2;
 232         idx &= 0x1F;
 233
 234         v = cru_readl(reg);
 235         if (on) {
 236                 v &= ~(1 << idx);       // clear bit
 237         } else {
 238                 v |= (1 << idx);        // set bit
 239         }
 240         cru_writel(v, reg);
 241
 242         return 0;
 243 }
 244
 245 static struct clk xin24m = {
 246         .name           = "xin24m",
 247         .rate           = 24 * MHZ,
 248         .flags          = RATE_FIXED,
 249 };
 250
 251 static struct clk clk_12m = {
 252         .name           = "clk_12m",
 253         .rate           = 12 * MHZ,
 254         .parent         = &xin24m,
 255         .flags          = RATE_FIXED,
 256 };
 257
 258 static struct clk extclk = {
 259         .name           = "extclk",
 260         .rate           = 27 * MHZ,
 261         .flags          = RATE_FIXED,
 262 };
 263
 264 static struct clk otgphy0_clkin = {
 265         .name           = "otgphy0_clkin",
 266         .rate           = 480 * MHZ,
 267         .flags          = RATE_FIXED,
 268 };
 269
 270 static struct clk otgphy1_clkin = {
 271         .name           = "otgphy1_clkin",
 272         .rate           = 480 * MHZ,
 273         .flags          = RATE_FIXED,
 274 };
 275
 276
 277 static void delay_500ns(void)
 278 {
 279         int delay = 2000;
 280         while (delay--)
 281            barrier();
 282 }
 283
 284
 285 #define PERIPH_PLL_IDX     0
 286 #define CODEC_PLL_IDX      1
 287 #define ARM_PLL_IDX        2
 288 #define DDR_PLL_IDX        3
 289
 290 #define GRF_SOC_CON0       0xbc
 291 static void pll_wait_lock(int pll_idx, int delay)
 292 {
 293         u32 bit = 0x2000000u << pll_idx;
 294         while (delay > 0) {
 295                 if (regfile_readl(GRF_SOC_CON0) & bit)
 296                         break;
 297                 delay--;
 298         }
 299         if (delay == 0) {
 300                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 301         }
 302 }
 303
 304 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 305 {
 306         unsigned long rate;
 307
 308         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 309                 u32 v = cru_readl(CRU_APLL_CON);
 310                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 311                 do_div(rate64, PLL_NR(v));
 312                 rate = rate64 >> PLL_NO_SHIFT(v);
 313                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 314         } else {
 315                 rate = clk->parent->rate;
 316                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 317         }
 318
 319         return rate;
 320 }
 321
 322 struct arm_pll_set {
 323         u32     clk_hz;
 324         u32     pll_con;
 325         u32     clksel0_con;
 326 };
 327
 328 #define CORE_ACLK_11    (0 << 5)
 329 #define CORE_ACLK_21    (1 << 5)
 330 #define CORE_ACLK_31    (2 << 5)
 331 #define CORE_ACLK_41    (3 << 5)
 332 #define CORE_ACLK_81    (4 << 5)
 333 #define CORE_ACLK_MASK  (7 << 5)
 334
 335 #define ACLK_HCLK_11    (0 << 8)
 336 #define ACLK_HCLK_21    (1 << 8)
 337 #define ACLK_HCLK_41    (2 << 8)
 338 #define ACLK_HCLK_MASK  (3 << 8)
 339
 340 #define ACLK_PCLK_11    (0 << 10)
 341 #define ACLK_PCLK_21    (1 << 10)
 342 #define ACLK_PCLK_41    (2 << 10)
 343 #define ACLK_PCLK_81    (3 << 10)
 344 #define ACLK_PCLK_MASK  (3 << 10)
 345
 346 #define ARM_PLL(_clk_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 347 { \
 348         .clk_hz         = _clk_mhz * MHZ, \
 349         .pll_con        = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 350         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 351 }
 352
 353 static const struct arm_pll_set arm_pll[] = {
 354         // clk_mhz = 24 * NF / (NR * NO)
 355         //      mhz  NR NF NO adiv hdiv pdiv
 356 //      ARM_PLL(600, 1, 50, 2, 21, 21, 41),
 357 //      ARM_PLL(624, 1, 52, 2, 21, 21, 41),
 358         ARM_PLL(720, 1, 60, 2, 21, 21, 41),
 359         // last item, pll power down.
 360         ARM_PLL( 24, 1, 64, 8, 21, 21, 41),
 361 };
 362
 363 #define CORE_PARENT_MASK        (3 << 23)
 364 #define CORE_PARENT_ARM_PLL     (0 << 23)
 365 #define CORE_PARENT_PERIPH_PLL  (1 << 23)
 366
 367 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 368 {
 369         u32 v = arm_pll[0].pll_con;
 370
 371         /* make aclk safe & reparent to periph pll */
 372         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_PERIPH_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 373
 374         /* enter slow mode */
 375         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 376
 377         pll_wait_lock(ARM_PLL_IDX, 2400000);
 378
 379         /* power down */
 380         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 381
 382         delay_500ns();
 383
 384         cru_writel(v | PLL_PD, CRU_APLL_CON);
 385
 386         delay_500ns();
 387
 388         /* power up */
 389         cru_writel(v, CRU_APLL_CON);
 390
 391         pll_wait_lock(ARM_PLL_IDX, 2400000);
 392
 393         /* enter normal mode */
 394         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 395
 396         /* reparent to arm pll & set aclk/hclk/pclk */
 397         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | arm_pll[0].clksel0_con, CRU_CLKSEL0_CON);
 398
 399         return 0;
 400 }
 401
 402 static struct clk arm_pll_clk = {
 403         .name           = "arm_pll",
 404         .parent         = &xin24m,
 405         .recalc         = arm_pll_clk_recalc,
 406         .set_rate       = arm_pll_clk_set_rate,
 407 };
 408
 409 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 410 {
 411         unsigned long rate;
 412
 413         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 414                 u32 v = cru_readl(CRU_DPLL_CON);
 415                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 416                 do_div(rate64, PLL_NR(v));
 417                 rate = rate64 >> PLL_NO_SHIFT(v);
 418                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 419         } else {
 420                 rate = clk->parent->rate;
 421                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 422         }
 423
 424         return rate;
 425 }
 426
 427 static struct clk ddr_pll_clk = {
 428         .name           = "ddr_pll",
 429         .parent         = &xin24m,
 430         .recalc         = ddr_pll_clk_recalc,
 431 };
 432
 433
 434 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 435 {
 436         unsigned long rate;
 437
 438         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) == CRU_CODEC_MODE_NORMAL) {
 439                 u32 v = cru_readl(CRU_CPLL_CON);
 440                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 441                 do_div(rate64, PLL_NR(v));
 442                 rate = rate64 >> PLL_NO_SHIFT(v);
 443                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 444         } else {
 445                 rate = clk->parent->rate;
 446                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 447         }
 448
 449         return rate;
 450 }
 451
 452 static struct clk codec_pll_clk = {
 453         .name           = "codec_pll",
 454         .parent         = &xin24m,
 455         .recalc         = codec_pll_clk_recalc,
 456 };
 457
 458
 459 static unsigned long periph_pll_clk_recalc(struct clk *clk)
 460 {
 461         unsigned long rate;
 462
 463         if ((cru_readl(CRU_MODE_CON) & CRU_PERIPH_MODE_MASK) == CRU_PERIPH_MODE_NORMAL) {
 464                 u32 v = cru_readl(CRU_PPLL_CON);
 465                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 466                 do_div(rate64, PLL_NR(v));
 467                 rate = rate64 >> PLL_NO_SHIFT(v);
 468                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 469         } else {
 470                 rate = clk->parent->rate;
 471                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 472         }
 473
 474         return rate;
 475 }
 476
 477 static int periph_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 478 {
 479         /* 624M: high-band, NR=1, NF=26, NO=1 */
 480         u32 v = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 481
 482         /* enter slow mode */
 483         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_PERIPH_MODE_MASK) | CRU_PERIPH_MODE_SLOW, CRU_MODE_CON);
 484
 485         pll_wait_lock(PERIPH_PLL_IDX, 2400000);
 486
 487         /* power down */
 488         cru_writel(cru_readl(CRU_PPLL_CON) | PLL_PD, CRU_PPLL_CON);
 489
 490         delay_500ns();
 491
 492         cru_writel(v | PLL_PD, CRU_PPLL_CON);
 493
 494         delay_500ns();
 495
 496         /* power up */
 497         cru_writel(v, CRU_PPLL_CON);
 498
 499         pll_wait_lock(PERIPH_PLL_IDX, 2400000);
 500
 501         /* enter normal mode */
 502         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_PERIPH_MODE_MASK) | CRU_PERIPH_MODE_NORMAL, CRU_MODE_CON);
 503
 504         return 0;
 505 }
 506
 507 static struct clk periph_pll_clk = {
 508         .name           = "periph_pll",
 509         .parent         = &xin24m,
 510         .recalc         = periph_pll_clk_recalc,
 511         .set_rate       = periph_pll_clk_set_rate,
 512 };
 513
 514
 515 static struct clk clk_core = {
 516         .name           = "core",
 517         .parent         = &arm_pll_clk,
 518         .recalc         = clksel_recalc_div,
 519         .clksel_con     = CRU_CLKSEL0_CON,
 520         .clksel_mask    = 0x1F,
 521         .clksel_shift   = 0,
 522 };
 523
 524 static unsigned long aclk_cpu_recalc(struct clk *clk)
 525 {
 526         unsigned long rate;
 527         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 528
 529         BUG_ON(div > 5);
 530         if (div >= 5)
 531                 div = 8;
 532         rate = clk->parent->rate / div;
 533         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 534
 535         return rate;
 536 }
 537
 538 static struct clk aclk_cpu = {
 539         .name           = "aclk_cpu",
 540         .parent         = &clk_core,
 541         .recalc         = aclk_cpu_recalc,
 542 };
 543
 544 static struct clk hclk_cpu = {
 545         .name           = "hclk_cpu",
 546         .parent         = &aclk_cpu,
 547         .recalc         = clksel_recalc_shift,
 548         .clksel_con     = CRU_CLKSEL0_CON,
 549         .clksel_mask    = 3,
 550         .clksel_shift   = 8,
 551         .clksel_maxdiv  = 4,
 552 };
 553
 554 static struct clk pclk_cpu = {
 555         .name           = "pclk_cpu",
 556         .parent         = &aclk_cpu,
 557         .recalc         = clksel_recalc_shift,
 558         .clksel_con     = CRU_CLKSEL0_CON,
 559         .clksel_mask    = 3,
 560         .clksel_shift   = 10,
 561         .clksel_maxdiv  = 8,
 562 };
 563
 564 static struct clk aclk_periph = {
 565         .name           = "aclk_periph",
 566         .mode           = gate_mode,
 567         .gate_idx       = CLK_GATE_PEIRPH_AXI,
 568         .parent         = &periph_pll_clk,
 569         .recalc         = clksel_recalc_div,
 570         .clksel_con     = CRU_CLKSEL0_CON,
 571         .clksel_mask    = 0x1F,
 572         .clksel_shift   = 14,
 573 };
 574
 575 static struct clk pclk_periph = {
 576         .name           = "pclk_periph",
 577         .mode           = gate_mode,
 578         .gate_idx       = CLK_GATE_PEIRPH_APB,
 579         .parent         = &aclk_periph,
 580         .recalc         = clksel_recalc_shift,
 581         .clksel_con     = CRU_CLKSEL0_CON,
 582         .clksel_mask    = 3,
 583         .clksel_shift   = 19,
 584         .clksel_maxdiv  = 8,
 585 };
 586
 587 static struct clk hclk_periph = {
 588         .name           = "hclk_periph",
 589         .mode           = gate_mode,
 590         .gate_idx       = CLK_GATE_PEIRPH_AHB,
 591         .parent         = &aclk_periph,
 592         .recalc         = clksel_recalc_shift,
 593         .clksel_con     = CRU_CLKSEL0_CON,
 594         .clksel_mask    = 3,
 595         .clksel_shift   = 21,
 596         .clksel_maxdiv  = 4,
 597 };
 598
 599
 600 static struct clk *clk_uhost_parents[8] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 601
 602 static struct clk clk_uhost = {
 603         .name           = "uhost",
 604         .mode           = gate_mode,
 605         .recalc         = clksel_recalc_div,
 606         .set_rate       = clksel_set_rate_div,
 607         .gate_idx       = CLK_GATE_UHOST,
 608         .clksel_con     = CRU_CLKSEL1_CON,
 609         .clksel_mask    = 0x1F,
 610         .clksel_shift   = 16,
 611         .clksel_parent_mask     = 7,
 612         .clksel_parent_shift    = 13,
 613         .parents        = clk_uhost_parents,
 614 };
 615
 616 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 617
 618 static struct clk clk_otgphy0 = {
 619         .name           = "otgphy0",
 620         .mode           = gate_mode,
 621         .gate_idx       = CLK_GATE_USBPHY0,
 622         .clksel_con     = CRU_CLKSEL1_CON,
 623         .clksel_parent_mask     = 3,
 624         .clksel_parent_shift    = 9,
 625         .parents        = clk_otgphy_parents,
 626 };
 627
 628 static struct clk clk_otgphy1 = {
 629         .name           = "otgphy1",
 630         .mode           = gate_mode,
 631         .gate_idx       = CLK_GATE_USBPHY1,
 632         .clksel_con     = CRU_CLKSEL1_CON,
 633         .clksel_parent_mask     = 3,
 634         .clksel_parent_shift    = 11,
 635         .parents        = clk_otgphy_parents,
 636 };
 637
 638
 639 static struct clk rmii_clkin = {
 640         .name           = "rmii_clkin",
 641 };
 642
 643 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 644
 645 static struct clk clk_mac_ref_div = {
 646         .name           = "mac_ref_div",
 647         .recalc         = clksel_recalc_div,
 648         .set_rate       = clksel_set_rate_div,
 649         .clksel_con     = CRU_CLKSEL1_CON,
 650         .clksel_mask    = 0x1F,
 651         .clksel_shift   = 23,
 652         .clksel_parent_mask     = 3,
 653         .clksel_parent_shift    = 21,
 654         .parents        = clk_mac_ref_div_parents,
 655 };
 656
 657 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 658
 659 static struct clk clk_mac_ref = {
 660         .name           = "mac_ref",
 661         .mode           = gate_mode,
 662         .gate_idx       = CLK_GATE_MAC_PHY,
 663         .clksel_con     = CRU_CLKSEL1_CON,
 664         .clksel_parent_mask     = 1,
 665         .clksel_parent_shift    = 28,
 666         .parents        = clk_mac_ref_parents,
 667 };
 668
 669
 670 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &periph_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 671
 672 static struct clk clk_i2s0_div = {
 673         .name           = "i2s0_div",
 674         .recalc         = clksel_recalc_div,
 675         .set_rate       = clksel_set_rate_div,
 676         .clksel_con     = CRU_CLKSEL2_CON,
 677         .clksel_mask    = 0x1F,
 678         .clksel_shift   = 3,
 679         .clksel_parent_mask     = 7,
 680         .clksel_parent_shift    = 0,
 681         .parents        = clk_i2s_div_parents,
 682 };
 683
 684 static struct clk clk_i2s1_div = {
 685         .name           = "i2s1_div",
 686         .recalc         = clksel_recalc_div,
 687         .set_rate       = clksel_set_rate_div,
 688         .clksel_con     = CRU_CLKSEL2_CON,
 689         .clksel_mask    = 0x1F,
 690         .clksel_shift   = 13,
 691         .clksel_parent_mask     = 7,
 692         .clksel_parent_shift    = 10,
 693         .parents        = clk_i2s_div_parents,
 694 };
 695
 696 static struct clk clk_spdif_div = {
 697         .name           = "spdif_div",
 698         .recalc         = clksel_recalc_div,
 699         .set_rate       = clksel_set_rate_div,
 700         .clksel_con     = CRU_CLKSEL2_CON,
 701         .clksel_mask    = 0x1F,
 702         .clksel_shift   = 23,
 703         .clksel_parent_mask     = 7,
 704         .clksel_parent_shift    = 20,
 705         .parents        = clk_i2s_div_parents,
 706 };
 707
 708 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 709 {
 710         u16 numerator, denominator;
 711
 712         switch (rate) {
 713         case 8192000:   /* 624*128/9750 */
 714                 numerator = 128;
 715                 denominator = 9750;
 716                 break;
 717         case 11289600:  /* 624*294/16250 */
 718                 numerator = 294;
 719                 denominator = 16250;
 720                 break;
 721         case 12288000:  /* 624*64/3250 */
 722                 numerator = 64;
 723                 denominator = 3250;
 724                 break;
 725         case 22579200:  /* 624*294/8125 */
 726                 numerator = 294;
 727                 denominator = 8125;
 728                 break;
 729         case 24576000:  /* 624*64/1625 */
 730                 numerator = 64;
 731                 denominator = 1625;
 732                 break;
 733         case 45158400:  /* 624*588/8125 */
 734                 numerator = 588;
 735                 denominator = 8125;
 736                 break;
 737         case 49152000:  /* 624*128/1625 */
 738                 numerator = 128;
 739                 denominator = 1625;
 740                 break;
 741         default:
 742                 return -ENOENT;
 743         }
 744
 745         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 746         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
 747
 748         return 0;
 749 }
 750
 751 static struct clk clk_i2s0_frac_div = {
 752         .name           = "i2s0_frac_div",
 753         .parent         = &clk_i2s0_div,
 754         .recalc         = clksel_recalc_frac,
 755         .set_rate       = clk_i2s_frac_div_set_rate,
 756         .clksel_con     = CRU_CLKSEL3_CON,
 757 };
 758
 759 static struct clk clk_i2s1_frac_div = {
 760         .name           = "i2s1_frac_div",
 761         .parent         = &clk_i2s1_div,
 762         .recalc         = clksel_recalc_frac,
 763         .set_rate       = clk_i2s_frac_div_set_rate,
 764         .clksel_con     = CRU_CLKSEL4_CON,
 765 };
 766
 767 static struct clk clk_spdif_frac_div = {
 768         .name           = "spdif_frac_div",
 769         .parent         = &clk_spdif_div,
 770         .recalc         = clksel_recalc_frac,
 771         .set_rate       = clk_i2s_frac_div_set_rate,
 772         .clksel_con     = CRU_CLKSEL5_CON,
 773 };
 774
 775 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 776 {
 777         int ret;
 778         struct clk *parent;
 779
 780         if (rate == 12 * MHZ) {
 781                 parent = &clk_12m;
 782         } else {
 783                 parent = clk->parents[1]; /* frac div */
 784                 ret = clk_set_rate_nolock(parent, rate);
 785                 if (ret)
 786                         return ret;
 787         }
 788         if (clk->parent != parent)
 789                 clk_set_parent_nolock(clk, parent);
 790
 791         return ret;
 792 }
 793
 794 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
 795
 796 static struct clk clk_i2s0 = {
 797         .name           = "i2s0",
 798         .mode           = gate_mode,
 799         .gate_idx       = CLK_GATE_I2S0,
 800         .set_rate       = i2s_set_rate,
 801         .clksel_con     = CRU_CLKSEL2_CON,
 802         .clksel_parent_mask     = 3,
 803         .clksel_parent_shift    = 8,
 804         .parents        = clk_i2s0_parents,
 805 };
 806
 807 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
 808
 809 static struct clk clk_i2s1 = {
 810         .name           = "i2s1",
 811         .mode           = gate_mode,
 812         .gate_idx       = CLK_GATE_I2S1,
 813         .set_rate       = i2s_set_rate,
 814         .clksel_con     = CRU_CLKSEL2_CON,
 815         .clksel_parent_mask     = 3,
 816         .clksel_parent_shift    = 18,
 817         .parents        = clk_i2s1_parents,
 818 };
 819
 820 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
 821
 822 static struct clk clk_spdif = {
 823         .name           = "spdif",
 824         .mode           = gate_mode,
 825         .gate_idx       = CLK_GATE_SPDIF,
 826         .set_rate       = i2s_set_rate,
 827         .clksel_con     = CRU_CLKSEL2_CON,
 828         .clksel_parent_mask     = 3,
 829         .clksel_parent_shift    = 28,
 830         .parents        = clk_spdif_parents,
 831 };
 832
 833
 834 static struct clk *clk_spi_src_parents[4] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
 835
 836 static struct clk clk_spi_src = {
 837         .name           = "spi_src",
 838         .clksel_con     = CRU_CLKSEL6_CON,
 839         .clksel_parent_mask     = 3,
 840         .clksel_parent_shift    = 0,
 841         .parents        = clk_spi_src_parents,
 842 };
 843
 844 static struct clk clk_spi0 = {
 845         .name           = "spi0",
 846         .parent         = &clk_spi_src,
 847         .mode           = gate_mode,
 848         .recalc         = clksel_recalc_div,
 849         .set_rate       = clksel_set_rate_div,
 850         .gate_idx       = CLK_GATE_SPI0,
 851         .clksel_con     = CRU_CLKSEL6_CON,
 852         .clksel_mask    = 0x7F,
 853         .clksel_shift   = 2,
 854 };
 855
 856 static struct clk clk_spi1 = {
 857         .name           = "spi1",
 858         .parent         = &clk_spi_src,
 859         .mode           = gate_mode,
 860         .recalc         = clksel_recalc_div,
 861         .set_rate       = clksel_set_rate_div,
 862         .gate_idx       = CLK_GATE_SPI1,
 863         .clksel_con     = CRU_CLKSEL6_CON,
 864         .clksel_mask    = 0x7F,
 865         .clksel_shift   = 11,
 866 };
 867
 868
 869 static struct clk clk_saradc = {
 870         .name           = "saradc",
 871         .parent         = &pclk_periph,
 872         .mode           = gate_mode,
 873         .recalc         = clksel_recalc_div,
 874         .set_rate       = clksel_set_rate_div,
 875         .gate_idx       = CLK_GATE_SARADC,
 876         .clksel_con     = CRU_CLKSEL6_CON,
 877         .clksel_mask    = 0xFF,
 878         .clksel_shift   = 18,
 879 };
 880
 881
 882 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
 883
 884 static struct clk clk_timer0 = {
 885         .name           = "timer0",
 886         .mode           = gate_mode,
 887         .gate_idx       = CLK_GATE_TIMER0,
 888         .clksel_con     = CRU_CLKSEL6_CON,
 889         .clksel_parent_mask     = 1,
 890         .clksel_parent_shift    = 26,
 891         .parents        = clk_cpu_timer_parents,
 892 };
 893
 894 static struct clk clk_timer1 = {
 895         .name           = "timer1",
 896         .mode           = gate_mode,
 897         .gate_idx       = CLK_GATE_TIMER1,
 898         .clksel_con     = CRU_CLKSEL6_CON,
 899         .clksel_parent_mask     = 1,
 900         .clksel_parent_shift    = 27,
 901         .parents        = clk_cpu_timer_parents,
 902 };
 903
 904 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
 905
 906 static struct clk clk_timer2 = {
 907         .name           = "timer2",
 908         .mode           = gate_mode,
 909         .gate_idx       = CLK_GATE_TIMER2,
 910         .clksel_con     = CRU_CLKSEL6_CON,
 911         .clksel_parent_mask     = 1,
 912         .clksel_parent_shift    = 28,
 913         .parents        = clk_periph_timer_parents,
 914 };
 915
 916 static struct clk clk_timer3 = {
 917         .name           = "timer3",
 918         .mode           = gate_mode,
 919         .gate_idx       = CLK_GATE_TIMER3,
 920         .clksel_con     = CRU_CLKSEL6_CON,
 921         .clksel_parent_mask     = 1,
 922         .clksel_parent_shift    = 29,
 923         .parents        = clk_periph_timer_parents,
 924 };
 925
 926
 927 static struct clk *clk_sdmmc_src_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 928
 929 static struct clk clk_sdmmc_src = {
 930         .name           = "sdmmc_src",
 931         .clksel_con     = CRU_CLKSEL7_CON,
 932         .clksel_parent_mask     = 3,
 933         .clksel_parent_shift    = 0,
 934         .parents        = clk_sdmmc_src_parents,
 935 };
 936
 937 static struct clk clk_sdmmc0 = {
 938         .name           = "sdmmc0",
 939         .parent         = &clk_sdmmc_src,
 940         .mode           = gate_mode,
 941         .recalc         = clksel_recalc_div,
 942         .set_rate       = clksel_set_rate_div,
 943         .gate_idx       = CLK_GATE_SDMMC0,
 944         .clksel_con     = CRU_CLKSEL7_CON,
 945         .clksel_mask    = 0x3F,
 946         .clksel_shift   = 2,
 947 };
 948
 949 static struct clk clk_sdmmc1 = {
 950         .name           = "sdmmc1",
 951         .parent         = &clk_sdmmc_src,
 952         .mode           = gate_mode,
 953         .recalc         = clksel_recalc_div,
 954         .set_rate       = clksel_set_rate_div,
 955         .gate_idx       = CLK_GATE_SDMMC1,
 956         .clksel_con     = CRU_CLKSEL7_CON,
 957         .clksel_mask    = 0x3F,
 958         .clksel_shift   = 10,
 959 };
 960
 961 static struct clk clk_emmc = {
 962         .name           = "emmc",
 963         .parent         = &clk_sdmmc_src,
 964         .mode           = gate_mode,
 965         .recalc         = clksel_recalc_div,
 966         .set_rate       = clksel_set_rate_div,
 967         .gate_idx       = CLK_GATE_EMMC,
 968         .clksel_con     = CRU_CLKSEL7_CON,
 969         .clksel_mask    = 0x3F,
 970         .clksel_shift   = 18,
 971 };
 972
 973
 974 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &periph_pll_clk, &codec_pll_clk, &arm_pll_clk };
 975
 976 static struct clk clk_ddr = {
 977         .name           = "ddr",
 978         .recalc         = clksel_recalc_shift,
 979         .clksel_con     = CRU_CLKSEL7_CON,
 980         .clksel_mask    = 7,
 981         .clksel_shift   = 26,
 982         .clksel_maxdiv  = 32,
 983         .clksel_parent_mask     = 3,
 984         .clksel_parent_shift    = 24,
 985         .parents        = clk_ddr_parents,
 986 };
 987
 988
 989 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
 990 {
 991         int ret;
 992         struct clk *parent;
 993         struct clk *clk_div = clk->parents[0];
 994
 995         switch (rate) {
 996         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
 997                 parent = clk->parents[2]; /* xin24m */
 998                 break;
 999         case 9600*16:
1000         case 19200*16:
1001         case 38400*16:
1002         case 57600*16:
1003         case 115200*16:
1004         case 230400*16:
1005         case 460800*16:
1006         case 576000*16:
1007         case 921600*16:
1008         case 1152000*16:
1009                 parent = clk->parents[1]; /* frac div */
1010                 /* reset div to 1 */
1011                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1012                 if (ret)
1013                         return ret;
1014                 break;
1015         default:
1016                 parent = clk_div;
1017                 break;
1018         }
1019
1020         if (parent->set_rate) {
1021                 ret = clk_set_rate_nolock(parent, rate);
1022                 if (ret)
1023                         return ret;
1024         }
1025
1026         if (clk->parent != parent)
1027                 clk_set_parent_nolock(clk, parent);
1028
1029         return 0;
1030 }
1031
1032 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1033 {
1034         u16 numerator, denominator;
1035
1036         switch (rate) {
1037         case 9600*16:
1038                 numerator = 2;
1039                 denominator = 8125;
1040                 break;
1041         case 19200*16:
1042                 numerator = 4;
1043                 denominator = 8125;
1044                 break;
1045         case 38400*16:
1046                 numerator = 8;
1047                 denominator = 8125;
1048                 break;
1049         case 57600*16:
1050                 numerator = 12;
1051                 denominator = 8125;
1052                 break;
1053         case 115200*16:
1054                 numerator = 24;
1055                 denominator = 8125;
1056                 break;
1057         case 230400*16:
1058                 numerator = 48;
1059                 denominator = 8125;
1060                 break;
1061         case 460800*16:
1062                 numerator = 96;
1063                 denominator = 8125;
1064                 break;
1065         case 576000*16:
1066                 numerator = 24;
1067                 denominator = 1625;
1068                 break;
1069         case 921600*16:
1070                 numerator = 192;
1071                 denominator = 8125;
1072                 break;
1073         case 1152000*16:
1074                 numerator = 48;
1075                 denominator = 1625;
1076                 break;
1077         default:
1078                 return -ENOENT;
1079         }
1080
1081         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1082         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
1083
1084         return 0;
1085 }
1086 static struct clk *clk_uart_src_parents[8] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1087
1088 static struct clk clk_uart01_src = {
1089         .name           = "uart01_src",
1090         .clksel_con     = CRU_CLKSEL8_CON,
1091         .clksel_parent_mask     = 7,
1092         .clksel_parent_shift    = 0,
1093         .parents        = clk_uart_src_parents,
1094 };
1095
1096 static struct clk clk_uart0_div = {
1097         .name           = "uart0_div",
1098         .parent         = &clk_uart01_src,
1099         .recalc         = clksel_recalc_div,
1100         .set_rate       = clksel_set_rate_div,
1101         .clksel_con     = CRU_CLKSEL8_CON,
1102         .clksel_mask    = 0x3F,
1103         .clksel_shift   = 3,
1104 };
1105
1106 static struct clk clk_uart0_frac_div = {
1107         .name           = "uart0_frac_div",
1108         .parent         = &clk_uart0_div,
1109         .recalc         = clksel_recalc_frac,
1110         .set_rate       = clk_uart_frac_div_set_rate,
1111         .clksel_con     = CRU_CLKSEL10_CON,
1112 };
1113
1114 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1115
1116 static struct clk clk_uart0 = {
1117         .name           = "uart0",
1118         .mode           = gate_mode,
1119         .set_rate       = clk_uart_set_rate,
1120         .gate_idx       = CLK_GATE_UART0,
1121         .clksel_con     = CRU_CLKSEL8_CON,
1122         .clksel_parent_mask     = 3,
1123         .clksel_parent_shift    = 9,
1124         .parents        = clk_uart0_parents,
1125 };
1126
1127 static struct clk clk_uart1_div = {
1128         .name           = "uart1_div",
1129         .parent         = &clk_uart01_src,
1130         .recalc         = clksel_recalc_div,
1131         .set_rate       = clksel_set_rate_div,
1132         .clksel_con     = CRU_CLKSEL8_CON,
1133         .clksel_mask    = 0x3F,
1134         .clksel_shift   = 14,
1135 };
1136
1137 static struct clk clk_uart1_frac_div = {
1138         .name           = "uart1_frac_div",
1139         .parent         = &clk_uart1_div,
1140         .recalc         = clksel_recalc_frac,
1141         .set_rate       = clk_uart_frac_div_set_rate,
1142         .clksel_con     = CRU_CLKSEL11_CON,
1143 };
1144
1145 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1146
1147 static struct clk clk_uart1 = {
1148         .name           = "uart1",
1149         .mode           = gate_mode,
1150         .set_rate       = clk_uart_set_rate,
1151         .gate_idx       = CLK_GATE_UART1,
1152         .clksel_con     = CRU_CLKSEL8_CON,
1153         .clksel_parent_mask     = 3,
1154         .clksel_parent_shift    = 20,
1155         .parents        = clk_uart1_parents,
1156 };
1157
1158 static struct clk clk_uart23_src = {
1159         .name           = "uart23_src",
1160         .clksel_con     = CRU_CLKSEL9_CON,
1161         .clksel_parent_mask     = 7,
1162         .clksel_parent_shift    = 0,
1163         .parents        = clk_uart_src_parents,
1164 };
1165
1166 static struct clk clk_uart2_div = {
1167         .name           = "uart2_div",
1168         .parent         = &clk_uart23_src,
1169         .recalc         = clksel_recalc_div,
1170         .set_rate       = clksel_set_rate_div,
1171         .clksel_con     = CRU_CLKSEL9_CON,
1172         .clksel_mask    = 0x3F,
1173         .clksel_shift   = 3,
1174 };
1175
1176 static struct clk clk_uart2_frac_div = {
1177         .name           = "uart2_frac_div",
1178         .parent         = &clk_uart2_div,
1179         .recalc         = clksel_recalc_frac,
1180         .set_rate       = clk_uart_frac_div_set_rate,
1181         .clksel_con     = CRU_CLKSEL12_CON,
1182 };
1183
1184 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1185
1186 static struct clk clk_uart2 = {
1187         .name           = "uart2",
1188         .mode           = gate_mode,
1189         .set_rate       = clk_uart_set_rate,
1190         .gate_idx       = CLK_GATE_UART2,
1191         .clksel_con     = CRU_CLKSEL9_CON,
1192         .clksel_parent_mask     = 3,
1193         .clksel_parent_shift    = 9,
1194         .parents        = clk_uart2_parents,
1195 };
1196
1197 static struct clk clk_uart3_div = {
1198         .name           = "uart3_div",
1199         .parent         = &clk_uart23_src,
1200         .recalc         = clksel_recalc_div,
1201         .set_rate       = clksel_set_rate_div,
1202         .clksel_con     = CRU_CLKSEL9_CON,
1203         .clksel_mask    = 0x3F,
1204         .clksel_shift   = 14,
1205 };
1206
1207 static struct clk clk_uart3_frac_div = {
1208         .name           = "uart3_frac_div",
1209         .parent         = &clk_uart3_div,
1210         .recalc         = clksel_recalc_frac,
1211         .set_rate       = clk_uart_frac_div_set_rate,
1212         .clksel_con     = CRU_CLKSEL13_CON,
1213 };
1214
1215 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1216
1217 static struct clk clk_uart3 = {
1218         .name           = "uart3",
1219         .mode           = gate_mode,
1220         .set_rate       = clk_uart_set_rate,
1221         .gate_idx       = CLK_GATE_UART3,
1222         .clksel_con     = CRU_CLKSEL9_CON,
1223         .clksel_parent_mask     = 3,
1224         .clksel_parent_shift    = 20,
1225         .parents        = clk_uart3_parents,
1226 };
1227
1228
1229 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &periph_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1230
1231 static struct clk clk_hsadc_div = {
1232         .name           = "hsadc_div",
1233         .recalc         = clksel_recalc_div,
1234         .set_rate       = clksel_set_rate_div,
1235         .clksel_con     = CRU_CLKSEL14_CON,
1236         .clksel_mask    = 0xFF,
1237         .clksel_shift   = 10,
1238         .clksel_parent_mask     = 7,
1239         .clksel_parent_shift    = 7,
1240         .parents        = clk_hsadc_div_parents,
1241 };
1242
1243 static struct clk clk_hsadc_frac_div = {
1244         .name           = "hsadc_frac_div",
1245         .parent         = &clk_hsadc_div,
1246         .recalc         = clksel_recalc_frac,
1247         .clksel_con     = CRU_CLKSEL15_CON,
1248 };
1249
1250 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &extclk };
1251
1252 static struct clk clk_demod = {
1253         .name           = "demod",
1254         .clksel_con     = CRU_CLKSEL14_CON,
1255         .clksel_parent_mask     = 3,
1256         .clksel_parent_shift    = 18,
1257         .parents        = clk_demod_parents,
1258 };
1259
1260 static struct clk gpsclk = {
1261         .name           = "gpsclk",
1262 };
1263
1264 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1265
1266 static struct clk clk_hsadc = {
1267         .name           = "hsadc",
1268         .mode           = gate_mode,
1269         .gate_idx       = CLK_GATE_HSADC,
1270         .clksel_con     = CRU_CLKSEL14_CON,
1271         .clksel_parent_mask     = 1,
1272         .clksel_parent_shift    = 21,
1273         .parents        = clk_hsadc_parents,
1274 };
1275
1276 static unsigned long div2_recalc(struct clk *clk)
1277 {
1278         return clk->parent->rate >> 1;
1279 }
1280
1281 static struct clk clk_hsadc_div2 = {
1282         .name           = "hsadc_div2",
1283         .parent         = &clk_demod,
1284         .recalc         = div2_recalc,
1285 };
1286
1287 static struct clk clk_hsadc_div2_inv = {
1288         .name           = "hsadc_div2_inv",
1289         .parent         = &clk_demod,
1290         .recalc         = div2_recalc,
1291 };
1292
1293 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1294
1295 static struct clk clk_hsadc_out = {
1296         .name           = "hsadc_out",
1297         .clksel_con     = CRU_CLKSEL14_CON,
1298         .clksel_parent_mask     = 1,
1299         .clksel_parent_shift    = 20,
1300         .parents        = clk_hsadc_out_parents,
1301 };
1302
1303
1304 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &periph_pll_clk, &arm_pll_clk };
1305
1306 static struct clk dclk_lcdc_div = {
1307         .name           = "dclk_lcdc_div",
1308         .recalc         = clksel_recalc_div,
1309         .set_rate       = clksel_set_rate_div,
1310         .clksel_con     = CRU_CLKSEL16_CON,
1311         .clksel_mask    = 0xFF,
1312         .clksel_shift   = 2,
1313         .clksel_parent_mask     = 3,
1314         .clksel_parent_shift    = 0,
1315         .parents        = dclk_lcdc_div_parents,
1316 };
1317
1318 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &extclk };
1319
1320 static struct clk dclk_lcdc = {
1321         .name           = "dclk_lcdc",
1322         .mode           = gate_mode,
1323         .gate_idx       = CLK_GATE_LCDC,
1324         .clksel_con     = CRU_CLKSEL16_CON,
1325         .clksel_parent_mask     = 1,
1326         .clksel_parent_shift    = 10,
1327         .parents        = dclk_lcdc_parents,
1328 };
1329
1330 static struct clk dclk_ebook = {
1331         .name           = "dclk_ebook",
1332         .mode           = gate_mode,
1333         .gate_idx       = CLK_GATE_EBOOK,
1334         .recalc         = clksel_recalc_div,
1335         .set_rate       = clksel_set_rate_div,
1336         .clksel_con     = CRU_CLKSEL16_CON,
1337         .clksel_mask    = 0x1F,
1338         .clksel_shift   = 13,
1339         .clksel_parent_mask     = 3,
1340         .clksel_parent_shift    = 11,
1341         .parents        = dclk_lcdc_div_parents,
1342 };
1343
1344 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &periph_pll_clk, &arm_pll_clk };
1345
1346 static struct clk aclk_lcdc = {
1347         .name           = "aclk_lcdc",
1348         .mode           = gate_mode,
1349         .gate_idx       = CLK_GATE_LCDC_AXI,
1350         .recalc         = clksel_recalc_div,
1351         .set_rate       = clksel_set_rate_div,
1352         .clksel_con     = CRU_CLKSEL16_CON,
1353         .clksel_mask    = 0x1F,
1354         .clksel_shift   = 20,
1355         .clksel_parent_mask     = 3,
1356         .clksel_parent_shift    = 18,
1357         .parents        = aclk_lcdc_parents,
1358 };
1359
1360 static struct clk hclk_lcdc = {
1361         .name           = "hclk_lcdc",
1362         .mode           = gate_mode,
1363         .gate_idx       = CLK_GATE_LCDC_AHB,
1364         .parent         = &aclk_lcdc,
1365         .clksel_con     = CRU_CLKSEL16_CON,
1366         .recalc         = clksel_recalc_shift,
1367         .set_rate       = clksel_set_rate_shift,
1368         .clksel_mask    = 3,
1369         .clksel_shift   = 25,
1370         .clksel_maxdiv  = 4,
1371 };
1372
1373 static struct clk *xpu_parents[4] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1374
1375 static struct clk aclk_vepu = {
1376         .name           = "aclk_vepu",
1377         .mode           = gate_mode,
1378         .recalc         = clksel_recalc_div,
1379         .set_rate       = clksel_set_rate_div,
1380         .gate_idx       = CLK_GAET_VEPU_AXI,
1381         .clksel_con     = CRU_CLKSEL17_CON,
1382         .clksel_mask    = 0x1F,
1383         .clksel_shift   = 2,
1384         .clksel_parent_mask     = 3,
1385         .clksel_parent_shift    = 0,
1386         .parents        = xpu_parents,
1387 };
1388
1389 static struct clk hclk_vepu = {
1390         .name           = "hclk_vepu",
1391         .parent         = &aclk_vepu,
1392         .mode           = gate_mode,
1393         .recalc         = clksel_recalc_shift,
1394         .set_rate       = clksel_set_rate_shift,
1395         .gate_idx       = CLK_GATE_VEPU_AHB,
1396         .clksel_con     = CRU_CLKSEL17_CON,
1397         .clksel_mask    = 3,
1398         .clksel_shift   = 28,
1399         .clksel_maxdiv  = 4,
1400 };
1401
1402 static struct clk aclk_vdpu = {
1403         .name           = "aclk_vdpu",
1404         .parent         = &periph_pll_clk,
1405         .mode           = gate_mode,
1406         .recalc         = clksel_recalc_div,
1407         .set_rate       = clksel_set_rate_div,
1408         .gate_idx       = CLK_GATE_VDPU_AXI,
1409         .clksel_con     = CRU_CLKSEL17_CON,
1410         .clksel_mask    = 0x1F,
1411         .clksel_shift   = 9,
1412         .clksel_parent_mask     = 3,
1413         .clksel_parent_shift    = 7,
1414         .parents        = xpu_parents,
1415 };
1416
1417 static struct clk hclk_vdpu = {
1418         .name           = "hclk_vdpu",
1419         .parent         = &aclk_vdpu,
1420         .mode           = gate_mode,
1421         .recalc         = clksel_recalc_shift,
1422         .set_rate       = clksel_set_rate_shift,
1423         .gate_idx       = CLK_GATE_VDPU_AHB,
1424         .clksel_con     = CRU_CLKSEL17_CON,
1425         .clksel_mask    = 3,
1426         .clksel_shift   = 30,
1427         .clksel_maxdiv  = 4,
1428 };
1429
1430 static struct clk clk_gpu = {
1431         .name           = "gpu",
1432         .mode           = gate_mode,
1433         .gate_idx       = CLK_GATE_GPU,
1434         .recalc         = clksel_recalc_div,
1435         .set_rate       = clksel_set_rate_div,
1436         .clksel_con     = CRU_CLKSEL17_CON,
1437         .clksel_mask    = 0x1F,
1438         .clksel_shift   = 16,
1439         .clksel_parent_mask     = 3,
1440         .clksel_parent_shift    = 14,
1441         .parents        = xpu_parents,
1442 };
1443
1444 static struct clk aclk_gpu = {
1445         .name           = "aclk_gpu",
1446         .mode           = gate_mode,
1447         .gate_idx       = CLK_GATE_GPU_AXI,
1448         .recalc         = clksel_recalc_div,
1449         .set_rate       = clksel_set_rate_div,
1450         .clksel_con     = CRU_CLKSEL17_CON,
1451         .clksel_mask    = 0x1F,
1452         .clksel_shift   = 23,
1453         .clksel_parent_mask     = 3,
1454         .clksel_parent_shift    = 21,
1455         .parents        = xpu_parents,
1456 };
1457
1458
1459 static struct clk *clk_vip_parents[4] = { &xin24m, &extclk, &dclk_ebook };
1460
1461 static struct clk clk_vip = {
1462         .name           = "vip",
1463         .mode           = gate_mode,
1464         .gate_idx       = CLK_GATE_VIP,
1465         .clksel_con     = CRU_CLKSEL1_CON,
1466         .clksel_parent_mask     = 3,
1467         .clksel_parent_shift    = 7,
1468         .parents        = clk_vip_parents,
1469 };
1470
1471
1472 #define GATE_CLK(NAME,PARENT,ID) \
1473 static struct clk clk_##NAME = { \
1474         .name           = #NAME, \
1475         .parent         = &PARENT, \
1476         .mode           = gate_mode, \
1477         .gate_idx       = CLK_GATE_##ID, \
1478 }
1479
1480 GATE_CLK(i2c0, pclk_cpu, I2C0);
1481 GATE_CLK(i2c1, pclk_periph, I2C1);
1482 GATE_CLK(i2c2, pclk_periph, I2C2);
1483 GATE_CLK(i2c3, pclk_periph, I2C3);
1484
1485 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1486 GATE_CLK(gpio1, pclk_periph, GPIO1);
1487 GATE_CLK(gpio2, pclk_periph, GPIO2);
1488 GATE_CLK(gpio3, pclk_periph, GPIO3);
1489 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1490 GATE_CLK(gpio5, pclk_periph, GPIO5);
1491 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1492
1493 GATE_CLK(dma0, aclk_cpu, DMA0);
1494 GATE_CLK(dma1, aclk_periph, DMA1);
1495 GATE_CLK(dma2, aclk_periph, DMA2);
1496
1497 GATE_CLK(gic, aclk_cpu, GIC);
1498 GATE_CLK(imem, aclk_cpu, IMEM);
1499 GATE_CLK(ebrom, hclk_cpu, EBROM);
1500 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1501 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1502 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1503 GATE_CLK(efuse, pclk_cpu, EFUSE);
1504 GATE_CLK(tzpc, pclk_cpu, TZPC);
1505 GATE_CLK(debug, pclk_cpu, DEBUG);
1506 GATE_CLK(tpiu, pclk_cpu, TPIU);
1507 GATE_CLK(rtc, pclk_cpu, RTC);
1508 GATE_CLK(pmu, pclk_cpu, PMU);
1509 GATE_CLK(grf, pclk_cpu, GRF);
1510
1511 GATE_CLK(emem, hclk_periph, EMEM);
1512 GATE_CLK(usb, hclk_periph, USB);
1513 GATE_CLK(ddr_periph, aclk_periph, DDR_PERIPH);
1514 GATE_CLK(periph_cpu, aclk_cpu, PERIPH_CPU);
1515 GATE_CLK(smc_axi, aclk_periph, SMC_AXI);
1516 GATE_CLK(smc, pclk_periph, SMC);
1517 GATE_CLK(mac_ahb, hclk_periph, MAC_AHB);
1518 GATE_CLK(mac_tx, hclk_periph, MAC_TX);
1519 GATE_CLK(mac_rx, hclk_periph, MAC_RX);
1520 GATE_CLK(hif, hclk_periph, HIF);
1521 GATE_CLK(nandc, hclk_periph, NANDC);
1522 GATE_CLK(hsadc_ahb, hclk_periph, HSADC_AHB);
1523 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1524 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1525 GATE_CLK(uhost_ahb, hclk_periph, UHOST_AHB);
1526 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1527
1528 GATE_CLK(vip_slave, hclk_cpu, VIP_SLAVE);
1529 GATE_CLK(wdt, pclk_periph, WDT);
1530 GATE_CLK(pwm, pclk_periph, PWM);
1531 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1532 GATE_CLK(vip_matrix, hclk_cpu, VIP_MATRIX);
1533 GATE_CLK(vip_input, hclk_cpu, VIP_INPUT);
1534 GATE_CLK(jtag, aclk_cpu, JTAG);
1535
1536 GATE_CLK(ddr_lcdc_axi, aclk_cpu, DDR_LCDC_AXI);
1537 GATE_CLK(ipp_axi, aclk_cpu, IPP_AXI);
1538 GATE_CLK(ipp_ahb, hclk_cpu, IPP_AHB);
1539 GATE_CLK(ebook_ahb, hclk_cpu, EBOOK_AHB);
1540 GATE_CLK(display_matrix_axi, aclk_cpu, DISPLAY_MATRIX_AXI);
1541 GATE_CLK(display_matrix_ahb, hclk_cpu, DISPLAY_MATRIX_AHB);
1542 GATE_CLK(ddr_vepu_axi, aclk_cpu, DDR_VEPU_AXI);
1543 GATE_CLK(ddr_vdpu_axi, aclk_cpu, DDR_VDPU_AXI);
1544 GATE_CLK(ddr_gpu_axi, aclk_cpu, DDR_GPU_AXI);
1545 GATE_CLK(gpu_ahb, hclk_cpu, GPU_AHB);
1546 GATE_CLK(cpu_vcodec_ahb, hclk_cpu, CPU_VCODEC_AHB);
1547 GATE_CLK(cpu_display_ahb, hclk_cpu, CPU_DISPLAY_AHB);
1548
1549 GATE_CLK(sdmmc0_ahb, hclk_periph, SDMMC0_AHB);
1550 GATE_CLK(sdmmc1_ahb, hclk_periph, SDMMC1_AHB);
1551 GATE_CLK(emmc_ahb, hclk_periph, EMMC_AHB);
1552
1553 #define CLK(dev, con, ck) \
1554         { \
1555                 .dev_id = dev, \
1556                 .con_id = con, \
1557                 .clk = ck, \
1558         }
1559
1560 #define CLK1(name) \
1561         { \
1562                 .dev_id = NULL, \
1563                 .con_id = #name, \
1564                 .clk = &clk_##name, \
1565         }
1566
1567 static struct clk_lookup clks[] = {
1568         CLK(NULL, "xin24m", &xin24m),
1569         CLK(NULL, "extclk", &extclk),
1570         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1571         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1572         CLK(NULL, "gpsclk", &gpsclk),
1573
1574         CLK1(12m),
1575         CLK(NULL, "arm_pll", &arm_pll_clk),
1576         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1577         CLK(NULL, "codec_pll", &codec_pll_clk),
1578         CLK(NULL, "periph_pll", &periph_pll_clk),
1579
1580         CLK1(core),
1581         CLK(NULL, "aclk_cpu", &aclk_cpu),
1582         CLK(NULL, "hclk_cpu", &hclk_cpu),
1583         CLK(NULL, "pclk_cpu", &pclk_cpu),
1584
1585         CLK(NULL, "aclk_periph", &aclk_periph),
1586         CLK(NULL, "hclk_periph", &hclk_periph),
1587         CLK(NULL, "pclk_periph", &pclk_periph),
1588
1589         CLK1(vip),
1590         CLK("rk29_otgphy.0", "otgphy", &clk_otgphy0),
1591         CLK("rk29_otgphy.1", "otgphy", &clk_otgphy1),
1592         CLK(NULL, "uhost", &clk_uhost),
1593         CLK(NULL, "mac_ref_div", &clk_mac_ref_div),
1594         CLK(NULL, "mac_ref", &clk_mac_ref),
1595
1596         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
1597         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
1598         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
1599         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
1600         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
1601         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
1602         CLK(NULL, "spdif_div", &clk_spdif_div),
1603         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
1604         CLK(NULL, "spdif", &clk_spdif),
1605
1606         CLK1(spi_src),
1607         CLK("rk29xx_spim.0", "spi0", &clk_spi0),
1608         CLK("rk29xx_spim.1", "spi1", &clk_spi1),
1609
1610         CLK1(saradc),
1611         CLK1(timer0),
1612         CLK1(timer1),
1613         CLK1(timer2),
1614         CLK1(timer3),
1615
1616         CLK1(sdmmc_src),
1617         CLK("rk29_sdmmc.0", "sdmmc", &clk_sdmmc0),
1618         CLK("rk29_sdmmc.0", "sdmmc_ahb", &clk_sdmmc0_ahb),
1619         CLK("rk29_sdmmc.1", "sdmmc", &clk_sdmmc1),
1620         CLK("rk29_sdmmc.1", "sdmmc_ahb", &clk_sdmmc1_ahb),
1621         CLK1(emmc),
1622         CLK1(emmc_ahb),
1623         CLK1(ddr),
1624
1625         CLK1(uart01_src),
1626         CLK("rk29_serial.0", "uart", &clk_uart0),
1627         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
1628         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
1629         CLK("rk29_serial.1", "uart", &clk_uart1),
1630         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
1631         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
1632
1633         CLK1(uart23_src),
1634         CLK("rk29_serial.2", "uart", &clk_uart2),
1635         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
1636         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
1637         CLK("rk29_serial.3", "uart", &clk_uart3),
1638         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
1639         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
1640
1641         CLK1(hsadc_div),
1642         CLK1(hsadc_frac_div),
1643         CLK1(demod),
1644         CLK1(hsadc),
1645         CLK1(hsadc_div2),
1646         CLK1(hsadc_div2_inv),
1647         CLK1(hsadc_out),
1648
1649         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
1650         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
1651         CLK(NULL, "dclk_ebook", &dclk_ebook),
1652         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
1653         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
1654
1655         CLK(NULL, "aclk_vepu", &aclk_vepu),
1656         CLK(NULL, "hclk_vepu", &hclk_vepu),
1657         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
1658         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
1659         CLK1(gpu),
1660         CLK(NULL, "aclk_gpu", &aclk_gpu),
1661
1662         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
1663         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
1664         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
1665         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
1666
1667         CLK1(gpio0),
1668         CLK1(gpio1),
1669         CLK1(gpio2),
1670         CLK1(gpio3),
1671         CLK1(gpio4),
1672         CLK1(gpio5),
1673         CLK1(gpio6),
1674
1675         CLK1(dma0),
1676         CLK1(dma1),
1677         CLK1(dma2),
1678
1679         CLK1(gic),
1680         CLK1(imem),
1681         CLK1(ebrom),
1682         CLK1(ddr_phy),
1683         CLK1(ddr_reg),
1684         CLK1(ddr_cpu),
1685         CLK1(efuse),
1686         CLK1(tzpc),
1687         CLK1(debug),
1688         CLK1(tpiu),
1689         CLK1(rtc),
1690         CLK1(pmu),
1691         CLK1(grf),
1692
1693         CLK1(emem),
1694         CLK1(usb),
1695         CLK1(ddr_periph),
1696         CLK1(periph_cpu),
1697         CLK1(smc_axi),
1698         CLK1(smc),
1699         CLK1(mac_ahb),
1700         CLK1(mac_tx),
1701         CLK1(mac_rx),
1702         CLK1(hif),
1703         CLK1(nandc),
1704         CLK1(hsadc_ahb),
1705         CLK1(usbotg0),
1706         CLK1(usbotg1),
1707         CLK1(uhost_ahb),
1708         CLK1(pid_filter),
1709
1710         CLK1(vip_slave),
1711         CLK1(wdt),
1712         CLK1(pwm),
1713         CLK1(vip_bus),
1714         CLK1(vip_matrix),
1715         CLK1(vip_input),
1716         CLK1(jtag),
1717
1718         CLK1(ddr_lcdc_axi),
1719         CLK1(ipp_axi),
1720         CLK1(ipp_ahb),
1721         CLK1(ebook_ahb),
1722         CLK1(display_matrix_axi),
1723         CLK1(display_matrix_ahb),
1724         CLK1(ddr_vepu_axi),
1725         CLK1(ddr_vdpu_axi),
1726         CLK1(ddr_gpu_axi),
1727         CLK1(gpu_ahb),
1728         CLK1(cpu_vcodec_ahb),
1729         CLK1(cpu_display_ahb),
1730 };
1731
1732 static LIST_HEAD(clocks);
1733 static DEFINE_MUTEX(clocks_mutex);
1734 static DEFINE_SPINLOCK(clockfw_lock);
1735 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
1736 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
1737
1738 static int clk_enable_nolock(struct clk *clk)
1739 {
1740         int ret = 0;
1741
1742         if (clk->usecount == 0) {
1743                 if (clk->parent) {
1744                         ret = clk_enable_nolock(clk->parent);
1745                         if (ret)
1746                                 return ret;
1747                 }
1748
1749                 if (clk->mode) {
1750                         ret = clk->mode(clk, 1);
1751                         if (ret) {
1752                                 if (clk->parent)
1753                                         clk_disable_nolock(clk->parent);
1754                                 return ret;
1755                         }
1756                 }
1757                 pr_debug("%s enabled\n", clk->name);
1758         }
1759         clk->usecount++;
1760
1761         return ret;
1762 }
1763
1764 int clk_enable(struct clk *clk)
1765 {
1766         int ret = 0;
1767
1768         if (clk == NULL || IS_ERR(clk))
1769                 return -EINVAL;
1770
1771         LOCK();
1772         ret = clk_enable_nolock(clk);
1773         UNLOCK();
1774
1775         return ret;
1776 }
1777 EXPORT_SYMBOL(clk_enable);
1778
1779 static void clk_disable_nolock(struct clk *clk)
1780 {
1781         if (clk->usecount == 0) {
1782                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
1783                 WARN_ON(1);
1784                 return;
1785         }
1786
1787         if (--clk->usecount == 0) {
1788                 if (clk->mode)
1789                         clk->mode(clk, 0);
1790                 pr_debug("%s disabled\n", clk->name);
1791                 if (clk->parent)
1792                         clk_disable_nolock(clk->parent);
1793         }
1794 }
1795
1796 void clk_disable(struct clk *clk)
1797 {
1798         if (clk == NULL || IS_ERR(clk))
1799                 return;
1800
1801         LOCK();
1802         clk_disable_nolock(clk);
1803         UNLOCK();
1804 }
1805 EXPORT_SYMBOL(clk_disable);
1806
1807 unsigned long clk_get_rate(struct clk *clk)
1808 {
1809         if (clk == NULL || IS_ERR(clk))
1810                 return 0;
1811
1812         return clk->rate;
1813 }
1814 EXPORT_SYMBOL(clk_get_rate);
1815
1816 /*-------------------------------------------------------------------------
1817  * Optional clock functions defined in include/linux/clk.h
1818  *-------------------------------------------------------------------------*/
1819
1820 /* Given a clock and a rate apply a clock specific rounding function */
1821 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
1822 {
1823         if (clk->round_rate)
1824                 return clk->round_rate(clk, rate);
1825
1826         if (clk->flags & RATE_FIXED)
1827                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
1828
1829         return clk->rate;
1830 }
1831
1832 long clk_round_rate(struct clk *clk, unsigned long rate)
1833 {
1834         long ret = 0;
1835
1836         if (clk == NULL || IS_ERR(clk))
1837                 return ret;
1838
1839         LOCK();
1840         ret = clk_round_rate_nolock(clk, rate);
1841         UNLOCK();
1842
1843         return ret;
1844 }
1845 EXPORT_SYMBOL(clk_round_rate);
1846
1847 static void __clk_recalc(struct clk *clk)
1848 {
1849         if (unlikely(clk->flags & RATE_FIXED))
1850                 return;
1851         if (clk->recalc)
1852                 clk->rate = clk->recalc(clk);
1853         else if (clk->parent)
1854                 clk->rate = clk->parent->rate;
1855         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
1856 }
1857
1858 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
1859 {
1860         int ret;
1861
1862         if (rate == clk->rate)
1863                 return 0;
1864
1865         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
1866
1867         if (clk->flags & CONFIG_PARTICIPANT)
1868                 return -EINVAL;
1869
1870         if (!clk->set_rate)
1871                 return -EINVAL;
1872
1873         ret = clk->set_rate(clk, rate);
1874
1875         if (ret == 0) {
1876                 __clk_recalc(clk);
1877                 __propagate_rate(clk);
1878         }
1879
1880         return ret;
1881 }
1882
1883 /* Set the clock rate for a clock source */
1884 int clk_set_rate(struct clk *clk, unsigned long rate)
1885 {
1886         int ret = -EINVAL;
1887
1888         if (clk == NULL || IS_ERR(clk))
1889                 return ret;
1890
1891         LOCK();
1892         ret = clk_set_rate_nolock(clk, rate);
1893         UNLOCK();
1894
1895         return ret;
1896 }
1897 EXPORT_SYMBOL(clk_set_rate);
1898
1899 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
1900 {
1901         int ret;
1902         int enabled = clk->usecount > 0;
1903         struct clk *old_parent = clk->parent;
1904
1905         if (clk->parent == parent)
1906                 return 0;
1907
1908         /* if clk is already enabled, enable new parent first and disable old parent later. */
1909         if (enabled)
1910                 clk_enable_nolock(parent);
1911
1912         if (clk->set_parent)
1913                 ret = clk->set_parent(clk, parent);
1914         else
1915                 ret = clksel_set_parent(clk, parent);
1916
1917         if (ret == 0) {
1918                 /* OK */
1919                 __clk_reparent(clk, parent);
1920                 __clk_recalc(clk);
1921                 __propagate_rate(clk);
1922                 if (enabled)
1923                         clk_disable_nolock(old_parent);
1924         } else {
1925                 if (enabled)
1926                         clk_disable_nolock(parent);
1927         }
1928
1929         return ret;
1930 }
1931
1932 int clk_set_parent(struct clk *clk, struct clk *parent)
1933 {
1934         int ret = -EINVAL;
1935
1936         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
1937                 return ret;
1938
1939         if (clk->set_parent == NULL && clk->parents == NULL)
1940                 return ret;
1941
1942         LOCK();
1943         if (clk->usecount == 0)
1944                 ret = clk_set_parent_nolock(clk, parent);
1945         else
1946                 ret = -EBUSY;
1947         UNLOCK();
1948
1949         return ret;
1950 }
1951 EXPORT_SYMBOL(clk_set_parent);
1952
1953 struct clk *clk_get_parent(struct clk *clk)
1954 {
1955         return clk->parent;
1956 }
1957 EXPORT_SYMBOL(clk_get_parent);
1958
1959 static void __clk_reparent(struct clk *child, struct clk *parent)
1960 {
1961         if (child->parent == parent)
1962                 return;
1963         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
1964
1965         list_del_init(&child->sibling);
1966         if (parent)
1967                 list_add(&child->sibling, &parent->children);
1968         child->parent = parent;
1969 }
1970
1971 /* Propagate rate to children */
1972 static void __propagate_rate(struct clk *tclk)
1973 {
1974         struct clk *clkp;
1975
1976         list_for_each_entry(clkp, &tclk->children, sibling) {
1977                 __clk_recalc(clkp);
1978                 __propagate_rate(clkp);
1979         }
1980 }
1981
1982 static LIST_HEAD(root_clks);
1983
1984 /**
1985  * recalculate_root_clocks - recalculate and propagate all root clocks
1986  *
1987  * Recalculates all root clocks (clocks with no parent), which if the
1988  * clock's .recalc is set correctly, should also propagate their rates.
1989  * Called at init.
1990  */
1991 static void clk_recalculate_root_clocks_nolock(void)
1992 {
1993         struct clk *clkp;
1994
1995         list_for_each_entry(clkp, &root_clks, sibling) {
1996                 __clk_recalc(clkp);
1997                 __propagate_rate(clkp);
1998         }
1999 }
2000
2001 void clk_recalculate_root_clocks(void)
2002 {
2003         LOCK();
2004         clk_recalculate_root_clocks_nolock();
2005         UNLOCK();
2006 }
2007
2008
2009 /**
2010  * clk_preinit - initialize any fields in the struct clk before clk init
2011  * @clk: struct clk * to initialize
2012  *
2013  * Initialize any struct clk fields needed before normal clk initialization
2014  * can run.  No return value.
2015  */
2016 static void clk_preinit(struct clk *clk)
2017 {
2018         INIT_LIST_HEAD(&clk->children);
2019 }
2020
2021 static int clk_register(struct clk *clk)
2022 {
2023         if (clk == NULL || IS_ERR(clk))
2024                 return -EINVAL;
2025
2026         /*
2027          * trap out already registered clocks
2028          */
2029         if (clk->node.next || clk->node.prev)
2030                 return 0;
2031
2032         mutex_lock(&clocks_mutex);
2033
2034         if (clk->get_parent)
2035                 clk->parent = clk->get_parent(clk);
2036         else if (clk->parents)
2037                 clk->parent = clksel_get_parent(clk);
2038
2039         if (clk->parent)
2040                 list_add(&clk->sibling, &clk->parent->children);
2041         else
2042                 list_add(&clk->sibling, &root_clks);
2043
2044         list_add(&clk->node, &clocks);
2045
2046         mutex_unlock(&clocks_mutex);
2047
2048         return 0;
2049 }
2050
2051 static void clk_enable_init_clocks(void)
2052 {
2053         struct clk *clkp;
2054
2055         list_for_each_entry(clkp, &clocks, node) {
2056                 if (clkp->flags & ENABLE_ON_INIT)
2057                         clk_enable(clkp);
2058         }
2059 }
2060
2061 static void rk29_clock_common_init(void)
2062 {
2063         /* periph pll */
2064         clk_set_rate_nolock(&periph_pll_clk, 624 * MHZ);
2065         clk_set_parent_nolock(&aclk_periph, &periph_pll_clk);   // default
2066         clk_set_rate_nolock(&aclk_periph, 312 * MHZ);   // default
2067         clk_set_rate_nolock(&hclk_periph, 156 * MHZ);   // default
2068         clk_set_rate_nolock(&pclk_periph, 78 * MHZ);    // default
2069         clk_set_parent_nolock(&clk_uhost, &periph_pll_clk);     // default
2070         clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2071         clk_set_parent_nolock(&clk_i2s0_div, &periph_pll_clk);  // default
2072         clk_set_parent_nolock(&clk_i2s1_div, &periph_pll_clk);  // default
2073         clk_set_parent_nolock(&clk_spdif_div, &periph_pll_clk); // default
2074         clk_set_parent_nolock(&clk_spi_src, &periph_pll_clk);   // default
2075         clk_set_parent_nolock(&clk_sdmmc_src, &periph_pll_clk);
2076         clk_set_parent_nolock(&clk_uart01_src, &periph_pll_clk);        // default
2077         clk_set_parent_nolock(&clk_uart23_src, &periph_pll_clk);        // default
2078         clk_set_parent_nolock(&dclk_lcdc_div, &periph_pll_clk);
2079         clk_set_parent_nolock(&aclk_lcdc, &periph_pll_clk);
2080         clk_set_parent_nolock(&aclk_vepu, &periph_pll_clk);     // default
2081         clk_set_parent_nolock(&aclk_vdpu, &periph_pll_clk);     // default
2082         clk_set_parent_nolock(&clk_gpu, &periph_pll_clk);       // default
2083         clk_set_parent_nolock(&aclk_gpu, &periph_pll_clk);      // default
2084         clk_set_parent_nolock(&clk_mac_ref_div, &periph_pll_clk);
2085         clk_set_parent_nolock(&clk_hsadc_div, &periph_pll_clk);
2086
2087         /* arm pll */
2088         clk_set_rate_nolock(&arm_pll_clk, 600 * MHZ);
2089 }
2090
2091 void __init rk29_clock_init(void)
2092 {
2093         struct clk_lookup *lk;
2094
2095         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2096                 clk_preinit(lk->clk);
2097
2098         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2099                 clkdev_add(lk);
2100                 clk_register(lk->clk);
2101         }
2102
2103         clk_recalculate_root_clocks_nolock();
2104
2105         rk29_clock_common_init();
2106
2107         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/ppll/core/aclk/hclk/pclk): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
2108                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, periph_pll_clk.rate / MHZ,
2109                clk_core.rate / MHZ, aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ);
2110
2111         /*
2112          * Only enable those clocks we will need, let the drivers
2113          * enable other clocks as necessary
2114          */
2115         clk_enable_init_clocks();
2116 }
2117
2118 #ifdef CONFIG_PROC_FS
2119 #include <linux/proc_fs.h>
2120 #include <linux/seq_file.h>
2121
2122 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2123 {
2124         struct clk* ck;
2125         int i;
2126         unsigned long rate = clk->rate;
2127
2128         for (i = 0; i < deep; i++)
2129                 seq_printf(s, "    ");
2130
2131         seq_printf(s, "%-9s ", clk->name);
2132
2133         if (clk->mode && (clk->gate_idx < CLK_GATE_MAX)) {
2134                 u32 reg;
2135                 int idx = clk->gate_idx;
2136                 u32 v;
2137
2138                 reg = CRU_CLKGATE0_CON;
2139                 reg += (idx >> 5) << 2;
2140                 idx &= 0x1F;
2141
2142                 v = cru_readl(reg) & (1 << idx);
2143
2144                 seq_printf(s, "%s ", v ? "off" : "on ");
2145         }
2146
2147         if (rate >= MHZ) {
2148                 if (rate % MHZ)
2149                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2150                 else
2151                         seq_printf(s, "%ld MHz", rate / MHZ);
2152         } else if (rate >= KHZ) {
2153                 if (rate % KHZ)
2154                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2155                 else
2156                         seq_printf(s, "%ld KHz", rate / KHZ);
2157         } else {
2158                 seq_printf(s, "%ld Hz", rate);
2159         }
2160
2161         seq_printf(s, " usecount = %d", clk->usecount);
2162
2163         seq_printf(s, " parent = %s\n", clk->parent ? clk->parent->name : "NULL");
2164
2165         list_for_each_entry(ck, &clocks, node) {
2166                 if (ck->parent == clk)
2167                         dump_clock(s, ck, deep + 1);
2168         }
2169 }
2170
2171 static int proc_clk_show(struct seq_file *s, void *v)
2172 {
2173         struct clk* clk;
2174
2175         mutex_lock(&clocks_mutex);
2176         list_for_each_entry(clk, &clocks, node) {
2177                 if (!clk->parent)
2178                         dump_clock(s, clk, 0);
2179         }
2180         mutex_unlock(&clocks_mutex);
2181
2182         seq_printf(s, "\nRegisters:\n");
2183         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2184         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2185         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2186         seq_printf(s, "PPLL     : 0x%08x\n", cru_readl(CRU_PPLL_CON));
2187         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2188         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2189         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2190         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2191         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2192         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2193         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2194         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2195         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2196         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2197         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2198         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2199         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2200         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2201         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2202         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2203         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2204         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2205         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2206         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2207         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2208         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2209         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2210
2211         return 0;
2212 }
2213
2214 static int proc_clk_open(struct inode *inode, struct file *file)
2215 {
2216         return single_open(file, proc_clk_show, NULL);
2217 }
2218
2219 static const struct file_operations proc_clk_fops = {
2220         .open           = proc_clk_open,
2221         .read           = seq_read,
2222         .llseek         = seq_lseek,
2223         .release        = single_release,
2224 };
2225
2226 static int __init clk_proc_init(void)
2227 {
2228         proc_create("clocks", 0, NULL, &proc_clk_fops);
2229         return 0;
2230
2231 }
2232 late_initcall(clk_proc_init);
2233 #endif /* CONFIG_PROC_FS */
2234