arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33 #include <mach/pmu.h>
  34
  35
  36 /* Clock flags */
  37 /* bit 0 is free */
  38 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  39 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  40
  41 #define cru_readl(offset)       readl(RK29_CRU_BASE + offset)
  42 #define cru_writel(v, offset)   writel(v, RK29_CRU_BASE + offset)
  43
  44 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  45 #define pmu_readl(offset)       readl(RK29_PMU_BASE + offset)
  46
  47 #define MHZ                     (1000*1000)
  48 #define KHZ                     1000
  49
  50 struct clk {
  51         struct list_head        node;
  52         const char              *name;
  53         struct clk              *parent;
  54         struct list_head        children;
  55         struct list_head        sibling;        /* node for children */
  56         unsigned long           rate;
  57         u32                     flags;
  58         int                     (*mode)(struct clk *clk, int on);
  59         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  60         int                     (*set_rate)(struct clk *, unsigned long);
  61         long                    (*round_rate)(struct clk *, unsigned long);
  62         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
  63         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
  64         s32                     usecount;
  65         u8                      gate_idx;
  66         u8                      pll_idx;
  67         u8                      clksel_con;
  68         u8                      clksel_mask;
  69         u8                      clksel_shift;
  70         u8                      clksel_maxdiv;
  71         u8                      clksel_parent_mask;
  72         u8                      clksel_parent_shift;
  73         struct clk              **parents;
  74 };
  75
  76 static int clk_enable_nolock(struct clk *clk);
  77 static void clk_disable_nolock(struct clk *clk);
  78 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
  79 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
  80 static void __clk_reparent(struct clk *child, struct clk *parent);
  81 static void __propagate_rate(struct clk *tclk);
  82 static struct clk codec_pll_clk;
  83 static struct clk general_pll_clk;
  84
  85 static unsigned long clksel_recalc_div(struct clk *clk)
  86 {
  87         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
  88         unsigned long rate = clk->parent->rate / div;
  89         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
  90         return rate;
  91 }
  92
  93 static unsigned long clksel_recalc_shift(struct clk *clk)
  94 {
  95         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
  96         unsigned long rate = clk->parent->rate >> shift;
  97         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
  98         return rate;
  99 }
 100
 101 static unsigned long clksel_recalc_frac(struct clk *clk)
 102 {
 103         unsigned long rate;
 104         u64 rate64;
 105         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 106         if (r == 0) // FPGA ?
 107                 return clk->parent->rate;
 108         numerator = r >> 16;
 109         denominator = r & 0xFFFF;
 110         rate64 = (u64)clk->parent->rate * numerator;
 111         do_div(rate64, denominator);
 112         rate = rate64;
 113         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 114         return rate;
 115 }
 116
 117 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 118 {
 119         u32 div;
 120
 121         for (div = 0; div <= clk->clksel_mask; div++) {
 122                 u32 new_rate = clk->parent->rate / (div + 1);
 123                 if (new_rate <= rate) {
 124                         u32 v = cru_readl(clk->clksel_con);
 125                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 126                         v |= div << clk->clksel_shift;
 127                         cru_writel(v, clk->clksel_con);
 128                         clk->rate = new_rate;
 129                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 130                         return 0;
 131                 }
 132         }
 133
 134         return -ENOENT;
 135 }
 136
 137 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 138 {
 139         u32 shift;
 140
 141         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 142                 u32 new_rate = clk->parent->rate >> shift;
 143                 if (new_rate <= rate) {
 144                         u32 v = cru_readl(clk->clksel_con);
 145                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 146                         v |= shift << clk->clksel_shift;
 147                         cru_writel(v, clk->clksel_con);
 148                         clk->rate = new_rate;
 149                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 150                         return 0;
 151                 }
 152         }
 153
 154         return -ENOENT;
 155 }
 156
 157 static struct clk* clksel_get_parent(struct clk *clk)
 158 {
 159         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 160 }
 161
 162 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 163 {
 164         struct clk **p = clk->parents;
 165         u32 i;
 166
 167         if (unlikely(!p))
 168                 return -EINVAL;
 169         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 170                 u32 v;
 171                 if (*p != parent)
 172                         continue;
 173                 v = cru_readl(clk->clksel_con);
 174                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 175                 v |= (i << clk->clksel_parent_shift);
 176                 cru_writel(v, clk->clksel_con);
 177                 return 0;
 178         }
 179         return -EINVAL;
 180 }
 181
 182 /* Work around CRU_CLKGATE3_CON bit21~20 bug */
 183 volatile u32 cru_clkgate3_con_mirror;
 184
 185 static int gate_mode(struct clk *clk, int on)
 186 {
 187         u32 reg;
 188         int idx = clk->gate_idx;
 189         u32 v;
 190
 191         if (idx >= CLK_GATE_MAX)
 192                 return -EINVAL;
 193
 194         reg = CRU_CLKGATE0_CON;
 195         reg += (idx >> 5) << 2;
 196         idx &= 0x1F;
 197
 198         if (reg == CRU_CLKGATE3_CON)
 199                 v = cru_clkgate3_con_mirror;
 200         else
 201                 v = cru_readl(reg);
 202
 203         if (on)
 204                 v &= ~(1 << idx);       // clear bit
 205         else
 206                 v |= (1 << idx);        // set bit
 207
 208         if (reg == CRU_CLKGATE3_CON)
 209                 cru_clkgate3_con_mirror = v;
 210         cru_writel(v, reg);
 211
 212         return 0;
 213 }
 214
 215 /* Work around CRU_SOFTRST0_CON bit29~27 bug */
 216 static volatile u32 cru_softrst0_con_mirror;
 217
 218 void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 219 {
 220         unsigned long flags;
 221         u32 reg = CRU_SOFTRST0_CON + ((idx >> 5) << 2);
 222         u32 mask = 1 << (idx & 31);
 223         u32 v;
 224
 225         if (idx >= SOFT_RST_MAX)
 226                 return;
 227
 228         local_irq_save(flags);
 229
 230         if (reg == CRU_SOFTRST0_CON)
 231                 v = cru_softrst0_con_mirror;
 232         else
 233                 v = cru_readl(reg);
 234
 235         if (on)
 236                 v |= mask;
 237         else
 238                 v &= ~mask;
 239
 240         if (reg == CRU_SOFTRST0_CON)
 241                 cru_softrst0_con_mirror = v;
 242         cru_writel(v, reg);
 243
 244         local_irq_restore(flags);
 245 }
 246
 247 static struct clk xin24m = {
 248         .name           = "xin24m",
 249         .rate           = 24 * MHZ,
 250         .flags          = RATE_FIXED,
 251 };
 252
 253 static struct clk clk_12m = {
 254         .name           = "clk_12m",
 255         .rate           = 12 * MHZ,
 256         .parent         = &xin24m,
 257         .flags          = RATE_FIXED,
 258 };
 259
 260 static struct clk xin27m = {
 261         .name           = "xin27m",
 262         .rate           = 27 * MHZ,
 263         .flags          = RATE_FIXED,
 264 };
 265
 266 static struct clk otgphy0_clkin = {
 267         .name           = "otgphy0_clkin",
 268         .rate           = 480 * MHZ,
 269         .flags          = RATE_FIXED,
 270 };
 271
 272 static struct clk otgphy1_clkin = {
 273         .name           = "otgphy1_clkin",
 274         .rate           = 480 * MHZ,
 275         .flags          = RATE_FIXED,
 276 };
 277
 278
 279 static void delay_500ns(void)
 280 {
 281         int delay = 2000;
 282         while (delay--)
 283                 barrier();
 284 }
 285
 286 static void delay_300us(void)
 287 {
 288         int i;
 289         for (i = 0; i < 600; i++)
 290                 delay_500ns();
 291 }
 292
 293 #define GENERAL_PLL_IDX     0
 294 #define CODEC_PLL_IDX      1
 295 #define ARM_PLL_IDX        2
 296 #define DDR_PLL_IDX        3
 297
 298 #define GRF_SOC_CON0       0xbc
 299 static void pll_wait_lock(int pll_idx)
 300 {
 301         u32 bit = 0x2000000u << pll_idx;
 302         int delay = 2400000;
 303         while (delay > 0) {
 304                 if (regfile_readl(GRF_SOC_CON0) & bit)
 305                         break;
 306                 delay--;
 307         }
 308         if (delay == 0) {
 309                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 310         }
 311 }
 312
 313 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 314 {
 315         unsigned long rate;
 316
 317         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 318                 u32 v = cru_readl(CRU_APLL_CON);
 319                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 320                 do_div(rate64, PLL_NR(v));
 321                 rate = rate64 >> PLL_NO_SHIFT(v);
 322                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 323         } else {
 324                 rate = clk->parent->rate;
 325                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 326         }
 327
 328         return rate;
 329 }
 330
 331 struct arm_pll_set {
 332         unsigned long rate;
 333         u32 apll_con;
 334         u32 clksel0_con;
 335 };
 336
 337 #define CORE_ACLK_11    (0 << 5)
 338 #define CORE_ACLK_21    (1 << 5)
 339 #define CORE_ACLK_31    (2 << 5)
 340 #define CORE_ACLK_41    (3 << 5)
 341 #define CORE_ACLK_81    (4 << 5)
 342 #define CORE_ACLK_MASK  (7 << 5)
 343
 344 #define ACLK_HCLK_11    (0 << 8)
 345 #define ACLK_HCLK_21    (1 << 8)
 346 #define ACLK_HCLK_41    (2 << 8)
 347 #define ACLK_HCLK_MASK  (3 << 8)
 348
 349 #define ACLK_PCLK_11    (0 << 10)
 350 #define ACLK_PCLK_21    (1 << 10)
 351 #define ACLK_PCLK_41    (2 << 10)
 352 #define ACLK_PCLK_81    (3 << 10)
 353 #define ACLK_PCLK_MASK  (3 << 10)
 354
 355 #define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 356 { \
 357         .rate           = _mhz * MHZ, \
 358         .apll_con       = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 359         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 360 }
 361
 362 static const struct arm_pll_set arm_pll[] = {
 363         // rate = 24 * NF / (NR * NO)
 364         //      rate NR  NF NO adiv hdiv pdiv
 365         ARM_PLL(1200, 1, 50, 1, 41, 21, 81),
 366         ARM_PLL(1104, 1, 46, 1, 41, 21, 81),
 367         ARM_PLL(1008, 1, 42, 1, 41, 21, 81),
 368         ARM_PLL( 912, 1, 38, 1, 31, 21, 81),
 369         ARM_PLL( 888, 2, 74, 1, 31, 21, 81),
 370         ARM_PLL( 816, 1, 34, 1, 31, 21, 81),
 371         ARM_PLL( 696, 1, 58, 2, 31, 21, 81),
 372         ARM_PLL( 624, 1, 52, 2, 31, 21, 81),
 373         ARM_PLL( 600, 1, 50, 2, 21, 21, 81),
 374         ARM_PLL( 504, 1, 42, 2, 21, 21, 81),
 375         ARM_PLL( 408, 1, 34, 2, 21, 21, 81),
 376         ARM_PLL( 300, 1, 50, 4, 21, 21, 41),
 377         ARM_PLL( 204, 1, 34, 4, 21, 21, 41),
 378         ARM_PLL( 102, 1, 34, 8, 21, 21, 41),
 379         // last item, pll power down.
 380         ARM_PLL(  24, 1, 64, 8, 21, 21, 41),
 381 };
 382
 383 #define CORE_PARENT_MASK        (3 << 23)
 384 #define CORE_PARENT_ARM_PLL     (0 << 23)
 385 #define CORE_PARENT_GENERAL_PLL (1 << 23)
 386
 387 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 388 {
 389         const struct arm_pll_set *ps, *pt;
 390
 391         /* find the arm_pll we want. */
 392         ps = pt = &arm_pll[0];
 393         while (1) {
 394                 if (pt->rate == rate) {
 395                         ps = pt;
 396                         break;
 397                 }
 398                 // we are sorted, and ps->rate > pt->rate.
 399                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 400                         ps = pt;
 401                 if (pt->rate < rate || pt->rate == 24 * MHZ)
 402                         break;
 403                 pt++;
 404         }
 405
 406         /* make aclk safe & reparent to general pll */
 407         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_GENERAL_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 408
 409         /* enter slow mode */
 410         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 411
 412         /* power down */
 413         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 414
 415         delay_500ns();
 416
 417         cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
 418
 419         delay_500ns();
 420
 421         /* power up */
 422         cru_writel(ps->apll_con, CRU_APLL_CON);
 423
 424         delay_300us();
 425         pll_wait_lock(ARM_PLL_IDX);
 426
 427         /* reparent to arm pll & set aclk/hclk/pclk */
 428         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | ps->clksel0_con, CRU_CLKSEL0_CON);
 429
 430         /* enter normal mode */
 431         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 432
 433         return 0;
 434 }
 435
 436 static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
 437
 438 static struct clk arm_pll_clk = {
 439         .name           = "arm_pll",
 440         .parent         = &xin24m,
 441         .recalc         = arm_pll_clk_recalc,
 442         .set_rate       = arm_pll_clk_set_rate,
 443         .clksel_con     = CRU_MODE_CON,
 444         .clksel_parent_mask     = 1,
 445         .clksel_parent_shift    = 8,
 446         .parents        = arm_pll_parents,
 447 };
 448
 449 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 450 {
 451         unsigned long rate;
 452
 453         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 454                 u32 v = cru_readl(CRU_DPLL_CON);
 455                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 456                 do_div(rate64, PLL_NR(v));
 457                 rate = rate64 >> PLL_NO_SHIFT(v);
 458                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 459         } else {
 460                 rate = clk->parent->rate;
 461                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 462         }
 463
 464         return rate;
 465 }
 466
 467 static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &general_pll_clk };
 468
 469 static struct clk ddr_pll_clk = {
 470         .name           = "ddr_pll",
 471         .parent         = &xin24m,
 472         .recalc         = ddr_pll_clk_recalc,
 473         .clksel_con     = CRU_MODE_CON,
 474         .clksel_parent_mask     = 3,
 475         .clksel_parent_shift    = 13,
 476         .parents        = ddr_pll_parents,
 477 };
 478
 479
 480 static int codec_pll_clk_mode(struct clk *clk, int on)
 481 {
 482         u32 cpll = cru_readl(CRU_CPLL_CON);
 483         if (on) {
 484                 cru_writel(cpll & ~(PLL_PD | PLL_BYPASS), CRU_CPLL_CON);
 485                 delay_300us();
 486                 pll_wait_lock(CODEC_PLL_IDX);
 487                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
 488         } else {
 489                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 490                 cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 491                 cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 492                 delay_500ns();
 493         }
 494         return 0;
 495 }
 496
 497 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 498 {
 499         unsigned long rate;
 500         u32 v = cru_readl(CRU_CPLL_CON);
 501         u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 502         do_div(rate64, PLL_NR(v));
 503         rate = rate64 >> PLL_NO_SHIFT(v);
 504         pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 505         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) != CRU_CODEC_MODE_NORMAL)
 506                 pr_debug("%s rate is %ld (slow mode) actually\n", clk->name, clk->parent->rate);
 507         return rate;
 508 }
 509
 510 #define CODEC_PLL_PARENT_MASK   (3 << 11)
 511 #define CODEC_PLL_PARENT_XIN24M (0 << 11)
 512 #define CODEC_PLL_PARENT_XIN27M (1 << 11)
 513 #define CODEC_PLL_PARENT_DDR_PLL        (2 << 11)
 514 #define CODEC_PLL_PARENT_GENERAL_PLL    (3 << 11)
 515
 516 struct codec_pll_set {
 517         unsigned long rate;
 518         u32 pll_con;
 519         u32 parent_con;
 520 };
 521
 522 #define CODEC_PLL(_mhz, _parent, band, nr, nf, no) \
 523 { \
 524         .rate           = _mhz * MHZ, \
 525         .pll_con        = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
 526         .parent_con     = CODEC_PLL_PARENT_XIN##_parent##M, \
 527 }
 528
 529 static const struct codec_pll_set codec_pll[] = {
 530         //      rate parent band NR NF NO
 531         CODEC_PLL(108, 24,  LOW, 1, 18, 4),     // for TV
 532         CODEC_PLL(648, 24, HIGH, 1, 27, 1),
 533         CODEC_PLL(297, 27,  LOW, 1, 22, 2),     // for HDMI
 534         CODEC_PLL(594, 27,  LOW, 1, 22, 1),
 535         CODEC_PLL(360, 24,  LOW, 1, 15, 1),     // for GPU
 536         CODEC_PLL(408, 24,  LOW, 1, 17, 1),
 537         CODEC_PLL(456, 24,  LOW, 1, 19, 1),
 538         CODEC_PLL(504, 24,  LOW, 1, 21, 1),
 539         CODEC_PLL(552, 24,  LOW, 1, 23, 1),
 540         CODEC_PLL(600, 24, HIGH, 1, 25, 1),
 541 };
 542
 543 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 544 {
 545         int i;
 546         u32 work_mode;
 547
 548         const struct codec_pll_set *ps = NULL;
 549
 550         for (i = 0; i < ARRAY_SIZE(codec_pll); i++) {
 551                 if (codec_pll[i].rate == rate) {
 552                         ps = &codec_pll[i];
 553                         break;
 554                 }
 555         }
 556         if (!ps)
 557                 return  -ENOENT;
 558
 559         work_mode = cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK;
 560
 561         /* enter slow mode */
 562         cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | ps->parent_con, CRU_MODE_CON);
 563
 564         /* power down */
 565         cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
 566
 567         delay_500ns();
 568
 569         cru_writel(ps->pll_con | PLL_PD, CRU_CPLL_CON);
 570
 571         delay_500ns();
 572
 573         /* power up */
 574         cru_writel(ps->pll_con, CRU_CPLL_CON);
 575
 576         delay_300us();
 577         pll_wait_lock(CODEC_PLL_IDX);
 578
 579         /* enter normal mode */
 580         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | work_mode, CRU_MODE_CON);
 581
 582         clk_set_parent_nolock(clk, ps->parent_con == CODEC_PLL_PARENT_XIN24M ? &xin24m : &xin27m);
 583
 584         return 0;
 585 }
 586
 587 static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &general_pll_clk };
 588
 589 static struct clk codec_pll_clk = {
 590         .name           = "codec_pll",
 591         .parent         = &xin24m,
 592         .mode           = codec_pll_clk_mode,
 593         .recalc         = codec_pll_clk_recalc,
 594         .set_rate       = codec_pll_clk_set_rate,
 595         .clksel_con     = CRU_MODE_CON,
 596         .clksel_parent_mask     = 3,
 597         .clksel_parent_shift    = 11,
 598         .parents        = codec_pll_parents,
 599 };
 600
 601
 602 static unsigned long general_pll_clk_recalc(struct clk *clk)
 603 {
 604         unsigned long rate;
 605
 606         if ((cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) == CRU_GENERAL_MODE_NORMAL) {
 607                 u32 v = cru_readl(CRU_GPLL_CON);
 608                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 609                 do_div(rate64, PLL_NR(v));
 610                 rate = rate64 >> PLL_NO_SHIFT(v);
 611                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 612         } else {
 613                 rate = clk->parent->rate;
 614                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 615         }
 616
 617         return rate;
 618 }
 619
 620 static int general_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 621 {
 622         u32 pll_con;
 623
 624         switch (rate) {
 625         case 288 * MHZ:
 626                 /* 288M: low-band, NR=1, NF=24, NO=2 */
 627                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_2;
 628                 break;
 629         case 624 * MHZ:
 630                 /* 624M: high-band, NR=1, NF=26, NO=1 */
 631                 pll_con = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 632                 break;
 633         default:
 634                 return -ENOENT;
 635                 break;
 636         }
 637
 638         /* enter slow mode */
 639         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 640
 641         /* power down */
 642         cru_writel(cru_readl(CRU_GPLL_CON) | PLL_PD, CRU_GPLL_CON);
 643
 644         delay_500ns();
 645
 646         cru_writel(pll_con | PLL_PD, CRU_GPLL_CON);
 647
 648         delay_500ns();
 649
 650         /* power up */
 651         cru_writel(pll_con, CRU_GPLL_CON);
 652
 653         delay_300us();
 654         pll_wait_lock(GENERAL_PLL_IDX);
 655
 656         /* enter normal mode */
 657         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_NORMAL, CRU_MODE_CON);
 658
 659         return 0;
 660 }
 661
 662 static struct clk *general_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
 663
 664 static struct clk general_pll_clk = {
 665         .name           = "general_pll",
 666         .parent         = &xin24m,
 667         .recalc         = general_pll_clk_recalc,
 668         .set_rate       = general_pll_clk_set_rate,
 669         .clksel_con     = CRU_MODE_CON,
 670         .clksel_parent_mask     = 3,
 671         .clksel_parent_shift    = 9,
 672         .parents        = general_pll_parents,
 673 };
 674
 675
 676 static struct clk *clk_core_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 677
 678 static struct clk clk_core = {
 679         .name           = "core",
 680         .parent         = &arm_pll_clk,
 681         .recalc         = clksel_recalc_div,
 682         .clksel_con     = CRU_CLKSEL0_CON,
 683         .clksel_mask    = 0x1F,
 684         .clksel_shift   = 0,
 685         .clksel_parent_mask     = 3,
 686         .clksel_parent_shift    = 23,
 687         .parents        = clk_core_parents,
 688 };
 689
 690 static unsigned long aclk_cpu_recalc(struct clk *clk)
 691 {
 692         unsigned long rate;
 693         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 694
 695         BUG_ON(div > 5);
 696         if (div >= 5)
 697                 div = 8;
 698         rate = clk->parent->rate / div;
 699         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 700
 701         return rate;
 702 }
 703
 704 static struct clk aclk_cpu = {
 705         .name           = "aclk_cpu",
 706         .parent         = &clk_core,
 707         .recalc         = aclk_cpu_recalc,
 708 };
 709
 710 static struct clk hclk_cpu = {
 711         .name           = "hclk_cpu",
 712         .parent         = &aclk_cpu,
 713         .recalc         = clksel_recalc_shift,
 714         .set_rate       = clksel_set_rate_shift,
 715         .clksel_con     = CRU_CLKSEL0_CON,
 716         .clksel_mask    = 3,
 717         .clksel_shift   = 8,
 718         .clksel_maxdiv  = 4,
 719 };
 720
 721 static struct clk pclk_cpu = {
 722         .name           = "pclk_cpu",
 723         .parent         = &aclk_cpu,
 724         .recalc         = clksel_recalc_shift,
 725         .set_rate       = clksel_set_rate_shift,
 726         .clksel_con     = CRU_CLKSEL0_CON,
 727         .clksel_mask    = 3,
 728         .clksel_shift   = 10,
 729         .clksel_maxdiv  = 8,
 730 };
 731
 732 static struct clk *aclk_periph_parents[4] = { &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
 733
 734 static struct clk aclk_periph = {
 735         .name           = "aclk_periph",
 736         .mode           = gate_mode,
 737         .gate_idx       = CLK_GATE_ACLK_PEIRPH,
 738         .recalc         = clksel_recalc_div,
 739         .set_rate       = clksel_set_rate_div,
 740         .clksel_con     = CRU_CLKSEL0_CON,
 741         .clksel_mask    = 0x1F,
 742         .clksel_shift   = 14,
 743         .clksel_parent_mask     = 3,
 744         .clksel_parent_shift    = 12,
 745         .parents        = aclk_periph_parents,
 746 };
 747
 748 static struct clk pclk_periph = {
 749         .name           = "pclk_periph",
 750         .mode           = gate_mode,
 751         .gate_idx       = CLK_GATE_PCLK_PEIRPH,
 752         .parent         = &aclk_periph,
 753         .recalc         = clksel_recalc_shift,
 754         .set_rate       = clksel_set_rate_shift,
 755         .clksel_con     = CRU_CLKSEL0_CON,
 756         .clksel_mask    = 3,
 757         .clksel_shift   = 19,
 758         .clksel_maxdiv  = 8,
 759 };
 760
 761 static struct clk hclk_periph = {
 762         .name           = "hclk_periph",
 763         .mode           = gate_mode,
 764         .gate_idx       = CLK_GATE_HCLK_PEIRPH,
 765         .parent         = &aclk_periph,
 766         .recalc         = clksel_recalc_shift,
 767         .set_rate       = clksel_set_rate_shift,
 768         .clksel_con     = CRU_CLKSEL0_CON,
 769         .clksel_mask    = 3,
 770         .clksel_shift   = 21,
 771         .clksel_maxdiv  = 4,
 772 };
 773
 774
 775 static struct clk *clk_uhost_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 776
 777 static struct clk clk_uhost = {
 778         .name           = "uhost",
 779         .mode           = gate_mode,
 780         .recalc         = clksel_recalc_div,
 781         .set_rate       = clksel_set_rate_div,
 782         .gate_idx       = CLK_GATE_UHOST,
 783         .clksel_con     = CRU_CLKSEL1_CON,
 784         .clksel_mask    = 0x1F,
 785         .clksel_shift   = 16,
 786         .clksel_parent_mask     = 7,
 787         .clksel_parent_shift    = 13,
 788         .parents        = clk_uhost_parents,
 789 };
 790
 791 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 792
 793 static struct clk clk_otgphy0 = {
 794         .name           = "otgphy0",
 795         .mode           = gate_mode,
 796         .gate_idx       = CLK_GATE_USBPHY0,
 797         .clksel_con     = CRU_CLKSEL1_CON,
 798         .clksel_parent_mask     = 3,
 799         .clksel_parent_shift    = 9,
 800         .parents        = clk_otgphy_parents,
 801 };
 802
 803 static struct clk clk_otgphy1 = {
 804         .name           = "otgphy1",
 805         .mode           = gate_mode,
 806         .gate_idx       = CLK_GATE_USBPHY1,
 807         .clksel_con     = CRU_CLKSEL1_CON,
 808         .clksel_parent_mask     = 3,
 809         .clksel_parent_shift    = 11,
 810         .parents        = clk_otgphy_parents,
 811 };
 812
 813
 814 static struct clk rmii_clkin = {
 815         .name           = "rmii_clkin",
 816 };
 817
 818 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 819
 820 static struct clk clk_mac_ref_div = {
 821         .name           = "mac_ref_div",
 822         .recalc         = clksel_recalc_div,
 823         .set_rate       = clksel_set_rate_div,
 824         .clksel_con     = CRU_CLKSEL1_CON,
 825         .clksel_mask    = 0x1F,
 826         .clksel_shift   = 23,
 827         .clksel_parent_mask     = 3,
 828         .clksel_parent_shift    = 21,
 829         .parents        = clk_mac_ref_div_parents,
 830 };
 831
 832 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 833
 834 static struct clk clk_mac_ref = {
 835         .name           = "mac_ref",
 836         .mode           = gate_mode,
 837         .gate_idx       = CLK_GATE_MAC_REF,
 838         .clksel_con     = CRU_CLKSEL1_CON,
 839         .clksel_parent_mask     = 1,
 840         .clksel_parent_shift    = 28,
 841         .parents        = clk_mac_ref_parents,
 842 };
 843
 844
 845 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 846
 847 static struct clk clk_i2s0_div = {
 848         .name           = "i2s0_div",
 849         .recalc         = clksel_recalc_div,
 850         .set_rate       = clksel_set_rate_div,
 851         .clksel_con     = CRU_CLKSEL2_CON,
 852         .clksel_mask    = 0x1F,
 853         .clksel_shift   = 3,
 854         .clksel_parent_mask     = 7,
 855         .clksel_parent_shift    = 0,
 856         .parents        = clk_i2s_div_parents,
 857 };
 858
 859 static struct clk clk_i2s1_div = {
 860         .name           = "i2s1_div",
 861         .recalc         = clksel_recalc_div,
 862         .set_rate       = clksel_set_rate_div,
 863         .clksel_con     = CRU_CLKSEL2_CON,
 864         .clksel_mask    = 0x1F,
 865         .clksel_shift   = 13,
 866         .clksel_parent_mask     = 7,
 867         .clksel_parent_shift    = 10,
 868         .parents        = clk_i2s_div_parents,
 869 };
 870
 871 static struct clk clk_spdif_div = {
 872         .name           = "spdif_div",
 873         .recalc         = clksel_recalc_div,
 874         .set_rate       = clksel_set_rate_div,
 875         .clksel_con     = CRU_CLKSEL2_CON,
 876         .clksel_mask    = 0x1F,
 877         .clksel_shift   = 23,
 878         .clksel_parent_mask     = 7,
 879         .clksel_parent_shift    = 20,
 880         .parents        = clk_i2s_div_parents,
 881 };
 882
 883 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 884 {
 885         u16 numerator, denominator;
 886
 887         switch (rate) {
 888         case 8192000:   /* 288*32/1125 */
 889                 numerator = 32;
 890                 denominator = 1125;
 891                 break;
 892         case 11289600:  /* 288*49/1250 */
 893                 numerator = 49;
 894                 denominator = 1250;
 895                 break;
 896         case 12288000:  /* 288*16/375 */
 897                 numerator = 16;
 898                 denominator = 375;
 899                 break;
 900         default:
 901                 return -ENOENT;
 902         }
 903
 904         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 905         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
 906
 907         return 0;
 908 }
 909
 910 static struct clk clk_i2s0_frac_div = {
 911         .name           = "i2s0_frac_div",
 912         .parent         = &clk_i2s0_div,
 913         .recalc         = clksel_recalc_frac,
 914         .set_rate       = clk_i2s_frac_div_set_rate,
 915         .clksel_con     = CRU_CLKSEL3_CON,
 916 };
 917
 918 static struct clk clk_i2s1_frac_div = {
 919         .name           = "i2s1_frac_div",
 920         .parent         = &clk_i2s1_div,
 921         .recalc         = clksel_recalc_frac,
 922         .set_rate       = clk_i2s_frac_div_set_rate,
 923         .clksel_con     = CRU_CLKSEL4_CON,
 924 };
 925
 926 static struct clk clk_spdif_frac_div = {
 927         .name           = "spdif_frac_div",
 928         .parent         = &clk_spdif_div,
 929         .recalc         = clksel_recalc_frac,
 930         .set_rate       = clk_i2s_frac_div_set_rate,
 931         .clksel_con     = CRU_CLKSEL5_CON,
 932 };
 933
 934 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 935 {
 936         int ret;
 937         struct clk *parent;
 938
 939         if (rate == 12 * MHZ) {
 940                 parent = &clk_12m;
 941         } else {
 942                 parent = clk->parents[1]; /* frac div */
 943                 ret = clk_set_rate_nolock(parent, rate);
 944                 if (ret)
 945                         return ret;
 946         }
 947         if (clk->parent != parent)
 948                 clk_set_parent_nolock(clk, parent);
 949
 950         return ret;
 951 }
 952
 953 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
 954
 955 static struct clk clk_i2s0 = {
 956         .name           = "i2s0",
 957         .mode           = gate_mode,
 958         .gate_idx       = CLK_GATE_I2S0,
 959         .set_rate       = i2s_set_rate,
 960         .clksel_con     = CRU_CLKSEL2_CON,
 961         .clksel_parent_mask     = 3,
 962         .clksel_parent_shift    = 8,
 963         .parents        = clk_i2s0_parents,
 964 };
 965
 966 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
 967
 968 static struct clk clk_i2s1 = {
 969         .name           = "i2s1",
 970         .mode           = gate_mode,
 971         .gate_idx       = CLK_GATE_I2S1,
 972         .set_rate       = i2s_set_rate,
 973         .clksel_con     = CRU_CLKSEL2_CON,
 974         .clksel_parent_mask     = 3,
 975         .clksel_parent_shift    = 18,
 976         .parents        = clk_i2s1_parents,
 977 };
 978
 979 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
 980
 981 static struct clk clk_spdif = {
 982         .name           = "spdif",
 983         .mode           = gate_mode,
 984         .gate_idx       = CLK_GATE_SPDIF,
 985         .set_rate       = i2s_set_rate,
 986         .clksel_con     = CRU_CLKSEL2_CON,
 987         .clksel_parent_mask     = 3,
 988         .clksel_parent_shift    = 28,
 989         .parents        = clk_spdif_parents,
 990 };
 991
 992
 993 static struct clk *clk_spi_src_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
 994
 995 static struct clk clk_spi_src = {
 996         .name           = "spi_src",
 997         .clksel_con     = CRU_CLKSEL6_CON,
 998         .clksel_parent_mask     = 3,
 999         .clksel_parent_shift    = 0,
1000         .parents        = clk_spi_src_parents,
1001 };
1002
1003 static struct clk clk_spi0 = {
1004         .name           = "spi0",
1005         .parent         = &clk_spi_src,
1006         .mode           = gate_mode,
1007         .recalc         = clksel_recalc_div,
1008         .set_rate       = clksel_set_rate_div,
1009         .gate_idx       = CLK_GATE_SPI0,
1010         .clksel_con     = CRU_CLKSEL6_CON,
1011         .clksel_mask    = 0x7F,
1012         .clksel_shift   = 2,
1013 };
1014
1015 static struct clk clk_spi1 = {
1016         .name           = "spi1",
1017         .parent         = &clk_spi_src,
1018         .mode           = gate_mode,
1019         .recalc         = clksel_recalc_div,
1020         .set_rate       = clksel_set_rate_div,
1021         .gate_idx       = CLK_GATE_SPI1,
1022         .clksel_con     = CRU_CLKSEL6_CON,
1023         .clksel_mask    = 0x7F,
1024         .clksel_shift   = 11,
1025 };
1026
1027
1028 static struct clk clk_saradc = {
1029         .name           = "saradc",
1030         .parent         = &pclk_periph,
1031         .mode           = gate_mode,
1032         .recalc         = clksel_recalc_div,
1033         .set_rate       = clksel_set_rate_div,
1034         .gate_idx       = CLK_GATE_SARADC,
1035         .clksel_con     = CRU_CLKSEL6_CON,
1036         .clksel_mask    = 0xFF,
1037         .clksel_shift   = 18,
1038 };
1039
1040
1041 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
1042
1043 static struct clk clk_timer0 = {
1044         .name           = "timer0",
1045         .mode           = gate_mode,
1046         .gate_idx       = CLK_GATE_TIMER0,
1047         .clksel_con     = CRU_CLKSEL6_CON,
1048         .clksel_parent_mask     = 1,
1049         .clksel_parent_shift    = 26,
1050         .parents        = clk_cpu_timer_parents,
1051 };
1052
1053 static struct clk clk_timer1 = {
1054         .name           = "timer1",
1055         .mode           = gate_mode,
1056         .gate_idx       = CLK_GATE_TIMER1,
1057         .clksel_con     = CRU_CLKSEL6_CON,
1058         .clksel_parent_mask     = 1,
1059         .clksel_parent_shift    = 27,
1060         .parents        = clk_cpu_timer_parents,
1061 };
1062
1063 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
1064
1065 static struct clk clk_timer2 = {
1066         .name           = "timer2",
1067         .mode           = gate_mode,
1068         .gate_idx       = CLK_GATE_TIMER2,
1069         .clksel_con     = CRU_CLKSEL6_CON,
1070         .clksel_parent_mask     = 1,
1071         .clksel_parent_shift    = 28,
1072         .parents        = clk_periph_timer_parents,
1073 };
1074
1075 static struct clk clk_timer3 = {
1076         .name           = "timer3",
1077         .mode           = gate_mode,
1078         .gate_idx       = CLK_GATE_TIMER3,
1079         .clksel_con     = CRU_CLKSEL6_CON,
1080         .clksel_parent_mask     = 1,
1081         .clksel_parent_shift    = 29,
1082         .parents        = clk_periph_timer_parents,
1083 };
1084
1085
1086 static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1087
1088 static struct clk clk_mmc_src = {
1089         .name           = "mmc_src",
1090         .clksel_con     = CRU_CLKSEL7_CON,
1091         .clksel_parent_mask     = 3,
1092         .clksel_parent_shift    = 0,
1093         .parents        = clk_mmc_src_parents,
1094 };
1095
1096 static struct clk clk_mmc0 = {
1097         .name           = "mmc0",
1098         .parent         = &clk_mmc_src,
1099         .mode           = gate_mode,
1100         .recalc         = clksel_recalc_div,
1101         .set_rate       = clksel_set_rate_div,
1102         .gate_idx       = CLK_GATE_MMC0,
1103         .clksel_con     = CRU_CLKSEL7_CON,
1104         .clksel_mask    = 0x3F,
1105         .clksel_shift   = 2,
1106 };
1107
1108 static struct clk clk_mmc1 = {
1109         .name           = "mmc1",
1110         .parent         = &clk_mmc_src,
1111         .mode           = gate_mode,
1112         .recalc         = clksel_recalc_div,
1113         .set_rate       = clksel_set_rate_div,
1114         .gate_idx       = CLK_GATE_MMC1,
1115         .clksel_con     = CRU_CLKSEL7_CON,
1116         .clksel_mask    = 0x3F,
1117         .clksel_shift   = 10,
1118 };
1119
1120 static struct clk clk_emmc = {
1121         .name           = "emmc",
1122         .parent         = &clk_mmc_src,
1123         .mode           = gate_mode,
1124         .recalc         = clksel_recalc_div,
1125         .set_rate       = clksel_set_rate_div,
1126         .gate_idx       = CLK_GATE_EMMC,
1127         .clksel_con     = CRU_CLKSEL7_CON,
1128         .clksel_mask    = 0x3F,
1129         .clksel_shift   = 18,
1130 };
1131
1132
1133 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &general_pll_clk, &codec_pll_clk, &arm_pll_clk };
1134
1135 static struct clk clk_ddr = {
1136         .name           = "ddr",
1137         .recalc         = clksel_recalc_shift,
1138         .clksel_con     = CRU_CLKSEL7_CON,
1139         .clksel_mask    = 7,
1140         .clksel_shift   = 26,
1141         .clksel_maxdiv  = 32,
1142         .clksel_parent_mask     = 3,
1143         .clksel_parent_shift    = 24,
1144         .parents        = clk_ddr_parents,
1145 };
1146
1147
1148 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1149 {
1150         int ret;
1151         struct clk *parent;
1152         struct clk *clk_div = clk->parents[0];
1153
1154         switch (rate) {
1155         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
1156                 parent = clk->parents[2]; /* xin24m */
1157                 break;
1158         case 19200*16:
1159         case 38400*16:
1160         case 57600*16:
1161         case 115200*16:
1162         case 230400*16:
1163         case 460800*16:
1164         case 576000*16:
1165                 parent = clk->parents[1]; /* frac div */
1166                 /* reset div to 1 */
1167                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1168                 if (ret)
1169                         return ret;
1170                 break;
1171         default:
1172                 parent = clk_div;
1173                 break;
1174         }
1175
1176         if (parent->set_rate) {
1177                 ret = clk_set_rate_nolock(parent, rate);
1178                 if (ret)
1179                         return ret;
1180         }
1181
1182         if (clk->parent != parent)
1183                 clk_set_parent_nolock(clk, parent);
1184
1185         return 0;
1186 }
1187
1188 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1189 {
1190         u16 numerator, denominator;
1191
1192         switch (rate) {
1193         case 19200*16:  /* 288*2/1875 */
1194                 numerator = 2;
1195                 denominator = 1875;
1196                 break;
1197         case 38400*16:  /* 288*4/1875 */
1198                 numerator = 4;
1199                 denominator = 1875;
1200                 break;
1201         case 57600*16:  /* 288*2/625 */
1202                 numerator = 2;
1203                 denominator = 625;
1204                 break;
1205         case 115200*16: /* 288*8/1250 */
1206                 numerator = 8;
1207                 denominator = 1250;
1208                 break;
1209         case 230400*16: /* 288*8/625 */
1210                 numerator = 8;
1211                 denominator = 625;
1212                 break;
1213         case 460800*16: /* 288*16/25 */
1214                 numerator = 16;
1215                 denominator = 625;
1216                 break;
1217         case 576000*16: /* 288*20/625 */
1218                 numerator = 20;
1219                 denominator = 625;
1220                 break;
1221         default:
1222                 return -ENOENT;
1223         }
1224
1225         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1226         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
1227
1228         return 0;
1229 }
1230 static struct clk *clk_uart_src_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1231
1232 static struct clk clk_uart01_src = {
1233         .name           = "uart01_src",
1234         .clksel_con     = CRU_CLKSEL8_CON,
1235         .clksel_parent_mask     = 7,
1236         .clksel_parent_shift    = 0,
1237         .parents        = clk_uart_src_parents,
1238 };
1239
1240 static struct clk clk_uart0_div = {
1241         .name           = "uart0_div",
1242         .parent         = &clk_uart01_src,
1243         .recalc         = clksel_recalc_div,
1244         .set_rate       = clksel_set_rate_div,
1245         .clksel_con     = CRU_CLKSEL8_CON,
1246         .clksel_mask    = 0x3F,
1247         .clksel_shift   = 3,
1248 };
1249
1250 static struct clk clk_uart0_frac_div = {
1251         .name           = "uart0_frac_div",
1252         .parent         = &clk_uart0_div,
1253         .recalc         = clksel_recalc_frac,
1254         .set_rate       = clk_uart_frac_div_set_rate,
1255         .clksel_con     = CRU_CLKSEL10_CON,
1256 };
1257
1258 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1259
1260 static struct clk clk_uart0 = {
1261         .name           = "uart0",
1262         .mode           = gate_mode,
1263         .set_rate       = clk_uart_set_rate,
1264         .gate_idx       = CLK_GATE_UART0,
1265         .clksel_con     = CRU_CLKSEL8_CON,
1266         .clksel_parent_mask     = 3,
1267         .clksel_parent_shift    = 9,
1268         .parents        = clk_uart0_parents,
1269 };
1270
1271 static struct clk clk_uart1_div = {
1272         .name           = "uart1_div",
1273         .parent         = &clk_uart01_src,
1274         .recalc         = clksel_recalc_div,
1275         .set_rate       = clksel_set_rate_div,
1276         .clksel_con     = CRU_CLKSEL8_CON,
1277         .clksel_mask    = 0x3F,
1278         .clksel_shift   = 14,
1279 };
1280
1281 static struct clk clk_uart1_frac_div = {
1282         .name           = "uart1_frac_div",
1283         .parent         = &clk_uart1_div,
1284         .recalc         = clksel_recalc_frac,
1285         .set_rate       = clk_uart_frac_div_set_rate,
1286         .clksel_con     = CRU_CLKSEL11_CON,
1287 };
1288
1289 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1290
1291 static struct clk clk_uart1 = {
1292         .name           = "uart1",
1293         .mode           = gate_mode,
1294         .set_rate       = clk_uart_set_rate,
1295         .gate_idx       = CLK_GATE_UART1,
1296         .clksel_con     = CRU_CLKSEL8_CON,
1297         .clksel_parent_mask     = 3,
1298         .clksel_parent_shift    = 20,
1299         .parents        = clk_uart1_parents,
1300 };
1301
1302 static struct clk clk_uart23_src = {
1303         .name           = "uart23_src",
1304         .clksel_con     = CRU_CLKSEL9_CON,
1305         .clksel_parent_mask     = 7,
1306         .clksel_parent_shift    = 0,
1307         .parents        = clk_uart_src_parents,
1308 };
1309
1310 static struct clk clk_uart2_div = {
1311         .name           = "uart2_div",
1312         .parent         = &clk_uart23_src,
1313         .recalc         = clksel_recalc_div,
1314         .set_rate       = clksel_set_rate_div,
1315         .clksel_con     = CRU_CLKSEL9_CON,
1316         .clksel_mask    = 0x3F,
1317         .clksel_shift   = 3,
1318 };
1319
1320 static struct clk clk_uart2_frac_div = {
1321         .name           = "uart2_frac_div",
1322         .parent         = &clk_uart2_div,
1323         .recalc         = clksel_recalc_frac,
1324         .set_rate       = clk_uart_frac_div_set_rate,
1325         .clksel_con     = CRU_CLKSEL12_CON,
1326 };
1327
1328 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1329
1330 static struct clk clk_uart2 = {
1331         .name           = "uart2",
1332         .mode           = gate_mode,
1333         .set_rate       = clk_uart_set_rate,
1334         .gate_idx       = CLK_GATE_UART2,
1335         .clksel_con     = CRU_CLKSEL9_CON,
1336         .clksel_parent_mask     = 3,
1337         .clksel_parent_shift    = 9,
1338         .parents        = clk_uart2_parents,
1339 };
1340
1341 static struct clk clk_uart3_div = {
1342         .name           = "uart3_div",
1343         .parent         = &clk_uart23_src,
1344         .recalc         = clksel_recalc_div,
1345         .set_rate       = clksel_set_rate_div,
1346         .clksel_con     = CRU_CLKSEL9_CON,
1347         .clksel_mask    = 0x3F,
1348         .clksel_shift   = 14,
1349 };
1350
1351 static struct clk clk_uart3_frac_div = {
1352         .name           = "uart3_frac_div",
1353         .parent         = &clk_uart3_div,
1354         .recalc         = clksel_recalc_frac,
1355         .set_rate       = clk_uart_frac_div_set_rate,
1356         .clksel_con     = CRU_CLKSEL13_CON,
1357 };
1358
1359 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1360
1361 static struct clk clk_uart3 = {
1362         .name           = "uart3",
1363         .mode           = gate_mode,
1364         .set_rate       = clk_uart_set_rate,
1365         .gate_idx       = CLK_GATE_UART3,
1366         .clksel_con     = CRU_CLKSEL9_CON,
1367         .clksel_parent_mask     = 3,
1368         .clksel_parent_shift    = 20,
1369         .parents        = clk_uart3_parents,
1370 };
1371
1372
1373 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1374
1375 static struct clk clk_hsadc_div = {
1376         .name           = "hsadc_div",
1377         .recalc         = clksel_recalc_div,
1378         .set_rate       = clksel_set_rate_div,
1379         .clksel_con     = CRU_CLKSEL14_CON,
1380         .clksel_mask    = 0xFF,
1381         .clksel_shift   = 10,
1382         .clksel_parent_mask     = 7,
1383         .clksel_parent_shift    = 7,
1384         .parents        = clk_hsadc_div_parents,
1385 };
1386
1387 static struct clk clk_hsadc_frac_div = {
1388         .name           = "hsadc_frac_div",
1389         .parent         = &clk_hsadc_div,
1390         .recalc         = clksel_recalc_frac,
1391         .clksel_con     = CRU_CLKSEL15_CON,
1392 };
1393
1394 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
1395
1396 static struct clk clk_demod = {
1397         .name           = "demod",
1398         .clksel_con     = CRU_CLKSEL14_CON,
1399         .clksel_parent_mask     = 3,
1400         .clksel_parent_shift    = 18,
1401         .parents        = clk_demod_parents,
1402 };
1403
1404 static struct clk gpsclk = {
1405         .name           = "gpsclk",
1406 };
1407
1408 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1409
1410 static struct clk clk_hsadc = {
1411         .name           = "hsadc",
1412         .mode           = gate_mode,
1413         .gate_idx       = CLK_GATE_HSADC,
1414         .clksel_con     = CRU_CLKSEL14_CON,
1415         .clksel_parent_mask     = 1,
1416         .clksel_parent_shift    = 21,
1417         .parents        = clk_hsadc_parents,
1418 };
1419
1420 static unsigned long div2_recalc(struct clk *clk)
1421 {
1422         return clk->parent->rate >> 1;
1423 }
1424
1425 static struct clk clk_hsadc_div2 = {
1426         .name           = "hsadc_div2",
1427         .parent         = &clk_demod,
1428         .recalc         = div2_recalc,
1429 };
1430
1431 static struct clk clk_hsadc_div2_inv = {
1432         .name           = "hsadc_div2_inv",
1433         .parent         = &clk_demod,
1434         .recalc         = div2_recalc,
1435 };
1436
1437 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1438
1439 static struct clk clk_hsadc_out = {
1440         .name           = "hsadc_out",
1441         .clksel_con     = CRU_CLKSEL14_CON,
1442         .clksel_parent_mask     = 1,
1443         .clksel_parent_shift    = 20,
1444         .parents        = clk_hsadc_out_parents,
1445 };
1446
1447
1448 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
1449
1450 static struct clk dclk_lcdc_div = {
1451         .name           = "dclk_lcdc_div",
1452         .recalc         = clksel_recalc_div,
1453         .set_rate       = clksel_set_rate_div,
1454         .clksel_con     = CRU_CLKSEL16_CON,
1455         .clksel_mask    = 0xFF,
1456         .clksel_shift   = 2,
1457         .clksel_parent_mask     = 3,
1458         .clksel_parent_shift    = 0,
1459         .parents        = dclk_lcdc_div_parents,
1460 };
1461
1462 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
1463
1464 static struct clk dclk_lcdc = {
1465         .name           = "dclk_lcdc",
1466         .mode           = gate_mode,
1467         .gate_idx       = CLK_GATE_DCLK_LCDC,
1468         .clksel_con     = CRU_CLKSEL16_CON,
1469         .clksel_parent_mask     = 1,
1470         .clksel_parent_shift    = 10,
1471         .parents        = dclk_lcdc_parents,
1472 };
1473
1474 static struct clk dclk_ebook = {
1475         .name           = "dclk_ebook",
1476         .mode           = gate_mode,
1477         .gate_idx       = CLK_GATE_DCLK_EBOOK,
1478         .recalc         = clksel_recalc_div,
1479         .set_rate       = clksel_set_rate_div,
1480         .clksel_con     = CRU_CLKSEL16_CON,
1481         .clksel_mask    = 0x1F,
1482         .clksel_shift   = 13,
1483         .clksel_parent_mask     = 3,
1484         .clksel_parent_shift    = 11,
1485         .parents        = dclk_lcdc_div_parents,
1486 };
1487
1488 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &general_pll_clk, &arm_pll_clk };
1489
1490 static struct clk aclk_lcdc = {
1491         .name           = "aclk_lcdc",
1492         .mode           = gate_mode,
1493         .gate_idx       = CLK_GATE_ACLK_LCDC,
1494         .recalc         = clksel_recalc_div,
1495         .set_rate       = clksel_set_rate_div,
1496         .clksel_con     = CRU_CLKSEL16_CON,
1497         .clksel_mask    = 0x1F,
1498         .clksel_shift   = 20,
1499         .clksel_parent_mask     = 3,
1500         .clksel_parent_shift    = 18,
1501         .parents        = aclk_lcdc_parents,
1502 };
1503
1504 static struct clk hclk_lcdc = {
1505         .name           = "hclk_lcdc",
1506         .mode           = gate_mode,
1507         .gate_idx       = CLK_GATE_HCLK_LCDC,
1508         .parent         = &aclk_lcdc,
1509         .clksel_con     = CRU_CLKSEL16_CON,
1510         .recalc         = clksel_recalc_shift,
1511         .set_rate       = clksel_set_rate_shift,
1512         .clksel_mask    = 3,
1513         .clksel_shift   = 25,
1514         .clksel_maxdiv  = 4,
1515 };
1516
1517 static struct clk *xpu_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1518
1519 static struct clk aclk_vepu = {
1520         .name           = "aclk_vepu",
1521         .mode           = gate_mode,
1522         .recalc         = clksel_recalc_div,
1523         .set_rate       = clksel_set_rate_div,
1524         .gate_idx       = CLK_GATE_ACLK_VEPU,
1525         .clksel_con     = CRU_CLKSEL17_CON,
1526         .clksel_mask    = 0x1F,
1527         .clksel_shift   = 2,
1528         .clksel_parent_mask     = 3,
1529         .clksel_parent_shift    = 0,
1530         .parents        = xpu_parents,
1531 };
1532
1533 static struct clk hclk_vepu = {
1534         .name           = "hclk_vepu",
1535         .parent         = &aclk_vepu,
1536         .mode           = gate_mode,
1537         .recalc         = clksel_recalc_shift,
1538         .set_rate       = clksel_set_rate_shift,
1539         .gate_idx       = CLK_GATE_HCLK_VEPU,
1540         .clksel_con     = CRU_CLKSEL17_CON,
1541         .clksel_mask    = 3,
1542         .clksel_shift   = 28,
1543         .clksel_maxdiv  = 4,
1544 };
1545
1546 static struct clk aclk_vdpu = {
1547         .name           = "aclk_vdpu",
1548         .parent         = &general_pll_clk,
1549         .mode           = gate_mode,
1550         .recalc         = clksel_recalc_div,
1551         .set_rate       = clksel_set_rate_div,
1552         .gate_idx       = CLK_GATE_ACLK_VDPU,
1553         .clksel_con     = CRU_CLKSEL17_CON,
1554         .clksel_mask    = 0x1F,
1555         .clksel_shift   = 9,
1556         .clksel_parent_mask     = 3,
1557         .clksel_parent_shift    = 7,
1558         .parents        = xpu_parents,
1559 };
1560
1561 static struct clk hclk_vdpu = {
1562         .name           = "hclk_vdpu",
1563         .parent         = &aclk_vdpu,
1564         .mode           = gate_mode,
1565         .recalc         = clksel_recalc_shift,
1566         .set_rate       = clksel_set_rate_shift,
1567         .gate_idx       = CLK_GATE_HCLK_VDPU,
1568         .clksel_con     = CRU_CLKSEL17_CON,
1569         .clksel_mask    = 3,
1570         .clksel_shift   = 30,
1571         .clksel_maxdiv  = 4,
1572 };
1573
1574 static struct clk clk_gpu = {
1575         .name           = "gpu",
1576         .mode           = gate_mode,
1577         .gate_idx       = CLK_GATE_GPU,
1578         .recalc         = clksel_recalc_div,
1579         .set_rate       = clksel_set_rate_div,
1580         .clksel_con     = CRU_CLKSEL17_CON,
1581         .clksel_mask    = 0x1F,
1582         .clksel_shift   = 16,
1583         .clksel_parent_mask     = 3,
1584         .clksel_parent_shift    = 14,
1585         .parents        = xpu_parents,
1586 };
1587
1588 static struct clk aclk_gpu = {
1589         .name           = "aclk_gpu",
1590         .mode           = gate_mode,
1591         .gate_idx       = CLK_GATE_ACLK_GPU,
1592         .recalc         = clksel_recalc_div,
1593         .set_rate       = clksel_set_rate_div,
1594         .clksel_con     = CRU_CLKSEL17_CON,
1595         .clksel_mask    = 0x1F,
1596         .clksel_shift   = 23,
1597         .clksel_parent_mask     = 3,
1598         .clksel_parent_shift    = 21,
1599         .parents        = xpu_parents,
1600 };
1601
1602
1603 static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
1604
1605 static struct clk clk_vip = {
1606         .name           = "vip",
1607         .mode           = gate_mode,
1608         .gate_idx       = CLK_GATE_VIP,
1609         .clksel_con     = CRU_CLKSEL1_CON,
1610         .clksel_parent_mask     = 3,
1611         .clksel_parent_shift    = 7,
1612         .parents        = clk_vip_parents,
1613 };
1614
1615
1616 #define GATE_CLK(NAME,PARENT,ID) \
1617 static struct clk clk_##NAME = { \
1618         .name           = #NAME, \
1619         .parent         = &PARENT, \
1620         .mode           = gate_mode, \
1621         .gate_idx       = CLK_GATE_##ID, \
1622 }
1623
1624 GATE_CLK(i2c0, pclk_cpu, I2C0);
1625 GATE_CLK(i2c1, pclk_periph, I2C1);
1626 GATE_CLK(i2c2, pclk_periph, I2C2);
1627 GATE_CLK(i2c3, pclk_periph, I2C3);
1628
1629 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1630 GATE_CLK(gpio1, pclk_periph, GPIO1);
1631 GATE_CLK(gpio2, pclk_periph, GPIO2);
1632 GATE_CLK(gpio3, pclk_periph, GPIO3);
1633 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1634 GATE_CLK(gpio5, pclk_periph, GPIO5);
1635 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1636
1637 GATE_CLK(dma1, aclk_cpu, DMA1);
1638 GATE_CLK(dma2, aclk_periph, DMA2);
1639
1640 GATE_CLK(gic, aclk_cpu, GIC);
1641 GATE_CLK(intmem, aclk_cpu, INTMEM);
1642 GATE_CLK(rom, hclk_cpu, ROM);
1643 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1644 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1645 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1646 GATE_CLK(efuse, pclk_cpu, EFUSE);
1647 GATE_CLK(tzpc, pclk_cpu, TZPC);
1648 GATE_CLK(debug, pclk_cpu, DEBUG);
1649 GATE_CLK(tpiu, pclk_cpu, TPIU);
1650 GATE_CLK(rtc, pclk_cpu, RTC);
1651 GATE_CLK(pmu, pclk_cpu, PMU);
1652 GATE_CLK(grf, pclk_cpu, GRF);
1653
1654 GATE_CLK(emem, hclk_periph, EMEM);
1655 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
1656 GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
1657 GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
1658 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
1659 GATE_CLK(smc, pclk_periph, SMC);
1660 GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
1661 GATE_CLK(mii_tx, hclk_periph, MII_TX);
1662 GATE_CLK(mii_rx, hclk_periph, MII_RX);
1663 GATE_CLK(hif, hclk_periph, HIF);
1664 GATE_CLK(nandc, hclk_periph, NANDC);
1665 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
1666 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1667 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1668 GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
1669 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1670
1671 GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
1672 GATE_CLK(wdt, pclk_periph, WDT);
1673 GATE_CLK(pwm, pclk_periph, PWM);
1674 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1675 GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
1676 GATE_CLK(vip_input, hclk_cpu, VIP_INPUT);
1677 GATE_CLK(jtag, aclk_cpu, JTAG);
1678
1679 GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
1680 GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
1681 GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
1682 GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
1683 GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
1684 GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
1685 GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
1686 GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
1687 GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
1688 GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
1689 GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
1690 GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
1691
1692 GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
1693 GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
1694 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
1695
1696 #define CLK(dev, con, ck) \
1697         { \
1698                 .dev_id = dev, \
1699                 .con_id = con, \
1700                 .clk = ck, \
1701         }
1702
1703 #define CLK1(name) \
1704         { \
1705                 .dev_id = NULL, \
1706                 .con_id = #name, \
1707                 .clk = &clk_##name, \
1708         }
1709
1710 static struct clk_lookup clks[] = {
1711         CLK(NULL, "xin24m", &xin24m),
1712         CLK(NULL, "xin27m", &xin27m),
1713         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1714         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1715         CLK(NULL, "gpsclk", &gpsclk),
1716
1717         CLK1(12m),
1718         CLK(NULL, "arm_pll", &arm_pll_clk),
1719         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1720         CLK(NULL, "codec_pll", &codec_pll_clk),
1721         CLK(NULL, "general_pll", &general_pll_clk),
1722
1723         CLK1(core),
1724         CLK(NULL, "aclk_cpu", &aclk_cpu),
1725         CLK(NULL, "hclk_cpu", &hclk_cpu),
1726         CLK(NULL, "pclk_cpu", &pclk_cpu),
1727
1728         CLK(NULL, "aclk_periph", &aclk_periph),
1729         CLK(NULL, "hclk_periph", &hclk_periph),
1730         CLK(NULL, "pclk_periph", &pclk_periph),
1731
1732         CLK1(vip),
1733         CLK1(otgphy0),
1734         CLK1(otgphy1),
1735         CLK1(uhost),
1736         CLK1(mac_ref_div),
1737         CLK1(mac_ref),
1738
1739         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
1740         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
1741         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
1742         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
1743         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
1744         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
1745         CLK(NULL, "spdif_div", &clk_spdif_div),
1746         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
1747         CLK(NULL, "spdif", &clk_spdif),
1748
1749         CLK1(spi_src),
1750         CLK("rk29xx_spim.0", "spi", &clk_spi0),
1751         CLK("rk29xx_spim.1", "spi", &clk_spi1),
1752
1753         CLK1(saradc),
1754         CLK1(timer0),
1755         CLK1(timer1),
1756         CLK1(timer2),
1757         CLK1(timer3),
1758
1759         CLK1(mmc_src),
1760         CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
1761         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
1762         CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
1763         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
1764         CLK1(emmc),
1765         CLK1(hclk_emmc),
1766         CLK1(ddr),
1767
1768         CLK1(uart01_src),
1769         CLK("rk29_serial.0", "uart", &clk_uart0),
1770         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
1771         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
1772         CLK("rk29_serial.1", "uart", &clk_uart1),
1773         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
1774         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
1775
1776         CLK1(uart23_src),
1777         CLK("rk29_serial.2", "uart", &clk_uart2),
1778         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
1779         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
1780         CLK("rk29_serial.3", "uart", &clk_uart3),
1781         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
1782         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
1783
1784         CLK1(hsadc_div),
1785         CLK1(hsadc_frac_div),
1786         CLK1(demod),
1787         CLK1(hsadc),
1788         CLK1(hsadc_div2),
1789         CLK1(hsadc_div2_inv),
1790         CLK1(hsadc_out),
1791
1792         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
1793         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
1794         CLK(NULL, "dclk_ebook", &dclk_ebook),
1795         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
1796         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
1797
1798         CLK(NULL, "aclk_vepu", &aclk_vepu),
1799         CLK(NULL, "hclk_vepu", &hclk_vepu),
1800         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
1801         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
1802         CLK1(gpu),
1803         CLK(NULL, "aclk_gpu", &aclk_gpu),
1804
1805         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
1806         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
1807         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
1808         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
1809
1810         CLK1(gpio0),
1811         CLK1(gpio1),
1812         CLK1(gpio2),
1813         CLK1(gpio3),
1814         CLK1(gpio4),
1815         CLK1(gpio5),
1816         CLK1(gpio6),
1817
1818         CLK1(dma1),
1819         CLK1(dma2),
1820
1821         CLK1(gic),
1822         CLK1(intmem),
1823         CLK1(rom),
1824         CLK1(ddr_phy),
1825         CLK1(ddr_reg),
1826         CLK1(ddr_cpu),
1827         CLK1(efuse),
1828         CLK1(tzpc),
1829         CLK1(debug),
1830         CLK1(tpiu),
1831         CLK1(rtc),
1832         CLK1(pmu),
1833         CLK1(grf),
1834
1835         CLK1(emem),
1836         CLK1(hclk_usb_peri),
1837         CLK1(aclk_ddr_peri),
1838         CLK1(aclk_cpu_peri),
1839         CLK1(aclk_smc),
1840         CLK1(smc),
1841         CLK1(hclk_mac),
1842         CLK1(mii_tx),
1843         CLK1(mii_rx),
1844         CLK1(hif),
1845         CLK1(nandc),
1846         CLK1(hclk_hsadc),
1847         CLK1(usbotg0),
1848         CLK1(usbotg1),
1849         CLK1(hclk_uhost),
1850         CLK1(pid_filter),
1851
1852         CLK1(vip_slave),
1853         CLK1(wdt),
1854         CLK1(pwm),
1855         CLK1(vip_bus),
1856         CLK1(vip_matrix),
1857         CLK1(vip_input),
1858         CLK1(jtag),
1859
1860         CLK1(aclk_ddr_lcdc),
1861         CLK1(aclk_ipp),
1862         CLK1(hclk_ipp),
1863         CLK1(hclk_ebook),
1864         CLK1(aclk_disp_matrix),
1865         CLK1(hclk_disp_matrix),
1866         CLK1(aclk_ddr_vepu),
1867         CLK1(aclk_ddr_vdpu),
1868         CLK1(aclk_ddr_gpu),
1869         CLK1(hclk_gpu),
1870         CLK1(hclk_cpu_vcodec),
1871         CLK1(hclk_cpu_display),
1872 };
1873
1874 static LIST_HEAD(clocks);
1875 static DEFINE_MUTEX(clocks_mutex);
1876 static DEFINE_SPINLOCK(clockfw_lock);
1877 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
1878 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
1879
1880 static int clk_enable_nolock(struct clk *clk)
1881 {
1882         int ret = 0;
1883
1884         if (clk->usecount == 0) {
1885                 if (clk->parent) {
1886                         ret = clk_enable_nolock(clk->parent);
1887                         if (ret)
1888                                 return ret;
1889                 }
1890
1891                 if (clk->mode) {
1892                         ret = clk->mode(clk, 1);
1893                         if (ret) {
1894                                 if (clk->parent)
1895                                         clk_disable_nolock(clk->parent);
1896                                 return ret;
1897                         }
1898                 }
1899                 pr_debug("%s enabled\n", clk->name);
1900         }
1901         clk->usecount++;
1902
1903         return ret;
1904 }
1905
1906 int clk_enable(struct clk *clk)
1907 {
1908         int ret = 0;
1909
1910         if (clk == NULL || IS_ERR(clk))
1911                 return -EINVAL;
1912
1913         LOCK();
1914         ret = clk_enable_nolock(clk);
1915         UNLOCK();
1916
1917         return ret;
1918 }
1919 EXPORT_SYMBOL(clk_enable);
1920
1921 static void clk_disable_nolock(struct clk *clk)
1922 {
1923         if (clk->usecount == 0) {
1924                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
1925                 WARN_ON(1);
1926                 return;
1927         }
1928
1929         if (--clk->usecount == 0) {
1930                 if (clk->mode)
1931                         clk->mode(clk, 0);
1932                 pr_debug("%s disabled\n", clk->name);
1933                 if (clk->parent)
1934                         clk_disable_nolock(clk->parent);
1935         }
1936 }
1937
1938 void clk_disable(struct clk *clk)
1939 {
1940         if (clk == NULL || IS_ERR(clk))
1941                 return;
1942
1943         LOCK();
1944         clk_disable_nolock(clk);
1945         UNLOCK();
1946 }
1947 EXPORT_SYMBOL(clk_disable);
1948
1949 unsigned long clk_get_rate(struct clk *clk)
1950 {
1951         if (clk == NULL || IS_ERR(clk))
1952                 return 0;
1953
1954         return clk->rate;
1955 }
1956 EXPORT_SYMBOL(clk_get_rate);
1957
1958 /*-------------------------------------------------------------------------
1959  * Optional clock functions defined in include/linux/clk.h
1960  *-------------------------------------------------------------------------*/
1961
1962 /* Given a clock and a rate apply a clock specific rounding function */
1963 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
1964 {
1965         if (clk->round_rate)
1966                 return clk->round_rate(clk, rate);
1967
1968         if (clk->flags & RATE_FIXED)
1969                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
1970
1971         return clk->rate;
1972 }
1973
1974 long clk_round_rate(struct clk *clk, unsigned long rate)
1975 {
1976         long ret = 0;
1977
1978         if (clk == NULL || IS_ERR(clk))
1979                 return ret;
1980
1981         LOCK();
1982         ret = clk_round_rate_nolock(clk, rate);
1983         UNLOCK();
1984
1985         return ret;
1986 }
1987 EXPORT_SYMBOL(clk_round_rate);
1988
1989 static void __clk_recalc(struct clk *clk)
1990 {
1991         if (unlikely(clk->flags & RATE_FIXED))
1992                 return;
1993         if (clk->recalc)
1994                 clk->rate = clk->recalc(clk);
1995         else if (clk->parent)
1996                 clk->rate = clk->parent->rate;
1997         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
1998 }
1999
2000 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
2001 {
2002         int ret;
2003
2004         if (rate == clk->rate)
2005                 return 0;
2006
2007         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
2008
2009         if (clk->flags & CONFIG_PARTICIPANT)
2010                 return -EINVAL;
2011
2012         if (!clk->set_rate)
2013                 return -EINVAL;
2014
2015         ret = clk->set_rate(clk, rate);
2016
2017         if (ret == 0) {
2018                 __clk_recalc(clk);
2019                 __propagate_rate(clk);
2020         }
2021
2022         return ret;
2023 }
2024
2025 /* Set the clock rate for a clock source */
2026 int clk_set_rate(struct clk *clk, unsigned long rate)
2027 {
2028         int ret = -EINVAL;
2029
2030         if (clk == NULL || IS_ERR(clk))
2031                 return ret;
2032
2033         LOCK();
2034         ret = clk_set_rate_nolock(clk, rate);
2035         UNLOCK();
2036
2037         return ret;
2038 }
2039 EXPORT_SYMBOL(clk_set_rate);
2040
2041 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
2042 {
2043         int ret;
2044         int enabled = clk->usecount > 0;
2045         struct clk *old_parent = clk->parent;
2046
2047         if (clk->parent == parent)
2048                 return 0;
2049
2050         /* if clk is already enabled, enable new parent first and disable old parent later. */
2051         if (enabled)
2052                 clk_enable_nolock(parent);
2053
2054         if (clk->set_parent)
2055                 ret = clk->set_parent(clk, parent);
2056         else
2057                 ret = clksel_set_parent(clk, parent);
2058
2059         if (ret == 0) {
2060                 /* OK */
2061                 __clk_reparent(clk, parent);
2062                 __clk_recalc(clk);
2063                 __propagate_rate(clk);
2064                 if (enabled)
2065                         clk_disable_nolock(old_parent);
2066         } else {
2067                 if (enabled)
2068                         clk_disable_nolock(parent);
2069         }
2070
2071         return ret;
2072 }
2073
2074 int clk_set_parent(struct clk *clk, struct clk *parent)
2075 {
2076         int ret = -EINVAL;
2077
2078         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
2079                 return ret;
2080
2081         if (clk->set_parent == NULL && clk->parents == NULL)
2082                 return ret;
2083
2084         LOCK();
2085         if (clk->usecount == 0)
2086                 ret = clk_set_parent_nolock(clk, parent);
2087         else
2088                 ret = -EBUSY;
2089         UNLOCK();
2090
2091         return ret;
2092 }
2093 EXPORT_SYMBOL(clk_set_parent);
2094
2095 struct clk *clk_get_parent(struct clk *clk)
2096 {
2097         return clk->parent;
2098 }
2099 EXPORT_SYMBOL(clk_get_parent);
2100
2101 static void __clk_reparent(struct clk *child, struct clk *parent)
2102 {
2103         if (child->parent == parent)
2104                 return;
2105         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
2106
2107         list_del_init(&child->sibling);
2108         if (parent)
2109                 list_add(&child->sibling, &parent->children);
2110         child->parent = parent;
2111 }
2112
2113 /* Propagate rate to children */
2114 static void __propagate_rate(struct clk *tclk)
2115 {
2116         struct clk *clkp;
2117
2118         list_for_each_entry(clkp, &tclk->children, sibling) {
2119                 __clk_recalc(clkp);
2120                 __propagate_rate(clkp);
2121         }
2122 }
2123
2124 static LIST_HEAD(root_clks);
2125
2126 /**
2127  * recalculate_root_clocks - recalculate and propagate all root clocks
2128  *
2129  * Recalculates all root clocks (clocks with no parent), which if the
2130  * clock's .recalc is set correctly, should also propagate their rates.
2131  * Called at init.
2132  */
2133 static void clk_recalculate_root_clocks_nolock(void)
2134 {
2135         struct clk *clkp;
2136
2137         list_for_each_entry(clkp, &root_clks, sibling) {
2138                 __clk_recalc(clkp);
2139                 __propagate_rate(clkp);
2140         }
2141 }
2142
2143 void clk_recalculate_root_clocks(void)
2144 {
2145         LOCK();
2146         clk_recalculate_root_clocks_nolock();
2147         UNLOCK();
2148 }
2149
2150
2151 /**
2152  * clk_preinit - initialize any fields in the struct clk before clk init
2153  * @clk: struct clk * to initialize
2154  *
2155  * Initialize any struct clk fields needed before normal clk initialization
2156  * can run.  No return value.
2157  */
2158 static void clk_preinit(struct clk *clk)
2159 {
2160         INIT_LIST_HEAD(&clk->children);
2161 }
2162
2163 static int clk_register(struct clk *clk)
2164 {
2165         if (clk == NULL || IS_ERR(clk))
2166                 return -EINVAL;
2167
2168         /*
2169          * trap out already registered clocks
2170          */
2171         if (clk->node.next || clk->node.prev)
2172                 return 0;
2173
2174         mutex_lock(&clocks_mutex);
2175
2176         if (clk->get_parent)
2177                 clk->parent = clk->get_parent(clk);
2178         else if (clk->parents)
2179                 clk->parent = clksel_get_parent(clk);
2180
2181         if (clk->parent)
2182                 list_add(&clk->sibling, &clk->parent->children);
2183         else
2184                 list_add(&clk->sibling, &root_clks);
2185
2186         list_add(&clk->node, &clocks);
2187
2188         mutex_unlock(&clocks_mutex);
2189
2190         return 0;
2191 }
2192
2193 static unsigned int __initdata armclk = 600 * MHZ;
2194
2195 /*
2196  * You can override arm_clk rate with armclk= cmdline option.
2197  */
2198 static int __init armclk_setup(char *str)
2199 {
2200         get_option(&str, &armclk);
2201
2202         if (!armclk)
2203                 return 0;
2204
2205         if (armclk < 10000)
2206                 armclk *= MHZ;
2207
2208         clk_set_rate_nolock(&arm_pll_clk, armclk);
2209         return 0;
2210 }
2211 early_param("armclk", armclk_setup);
2212
2213 static void __init rk29_clock_common_init(void)
2214 {
2215         /* general pll */
2216         clk_set_rate_nolock(&general_pll_clk, 288 * MHZ);
2217         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2218         clk_set_rate_nolock(&aclk_periph, 144 * MHZ);
2219         clk_set_rate_nolock(&hclk_periph, 144 * MHZ);
2220         clk_set_rate_nolock(&pclk_periph, 36 * MHZ);
2221         clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
2222         clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2223         clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
2224         clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
2225         clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
2226         clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
2227         clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
2228         clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
2229         clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
2230         clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
2231         clk_set_parent_nolock(&aclk_lcdc, &general_pll_clk);
2232         clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
2233         clk_set_rate_nolock(&aclk_vepu, 288 * MHZ);
2234         clk_set_rate_nolock(&clk_aclk_ddr_vepu, 288 * MHZ);
2235         clk_set_rate_nolock(&hclk_vepu, 144 * MHZ);
2236         clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
2237         clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
2238         clk_set_rate_nolock(&aclk_gpu, 288 * MHZ);
2239         clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
2240         clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
2241
2242         /* codec pll */
2243         clk_set_rate_nolock(&codec_pll_clk, 552 * MHZ);
2244         clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
2245
2246         /* arm pll */
2247         clk_set_rate_nolock(&arm_pll_clk, armclk);
2248         clk_set_parent_nolock(&clk_mac_ref_div, &arm_pll_clk);
2249 }
2250
2251 static void __init clk_enable_init_clocks(void)
2252 {
2253         clk_enable_nolock(&hclk_cpu);
2254         clk_enable_nolock(&pclk_cpu);
2255         clk_enable_nolock(&hclk_periph);
2256         clk_enable_nolock(&pclk_periph);
2257         clk_enable_nolock(&clk_nandc);
2258         clk_enable_nolock(&clk_aclk_cpu_peri);
2259         clk_enable_nolock(&clk_aclk_ddr_peri);
2260         clk_enable_nolock(&clk_grf);
2261         clk_enable_nolock(&clk_pmu);
2262         clk_enable_nolock(&clk_ddr_cpu);
2263         clk_enable_nolock(&clk_ddr_reg);
2264         clk_enable_nolock(&clk_ddr_phy);
2265         clk_enable_nolock(&clk_gic);
2266         clk_enable_nolock(&clk_dma2);
2267         clk_enable_nolock(&clk_dma1);
2268         clk_enable_nolock(&clk_emem);
2269         clk_enable_nolock(&clk_intmem);
2270         clk_enable_nolock(&clk_ddr);
2271         clk_enable_nolock(&clk_debug);
2272         clk_enable_nolock(&clk_jtag);
2273         clk_enable_nolock(&clk_uart1);
2274 }
2275
2276 static int __init clk_disable_unused(void)
2277 {
2278         struct clk *ck;
2279
2280         list_for_each_entry(ck, &clocks, node) {
2281                 if (ck->usecount > 0 || ck->mode == NULL)
2282                         continue;
2283
2284                 LOCK();
2285                 clk_enable_nolock(ck);
2286                 clk_disable_nolock(ck);
2287                 UNLOCK();
2288         }
2289
2290         return 0;
2291 }
2292
2293 void __init rk29_clock_init(void)
2294 {
2295         struct clk_lookup *lk;
2296
2297         cru_clkgate3_con_mirror = cru_readl(CRU_CLKGATE3_CON);
2298         cru_softrst0_con_mirror = cru_readl(CRU_SOFTRST0_CON);
2299
2300         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2301                 clk_preinit(lk->clk);
2302
2303         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2304                 clkdev_add(lk);
2305                 clk_register(lk->clk);
2306         }
2307
2308         clk_recalculate_root_clocks_nolock();
2309
2310         /*
2311          * Only enable those clocks we will need, let the drivers
2312          * enable other clocks as necessary
2313          */
2314         clk_enable_init_clocks();
2315
2316         /*
2317          * Disable any unused clocks left on by the bootloader
2318          */
2319         clk_disable_unused();
2320
2321         rk29_clock_common_init();
2322
2323         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
2324                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
2325                aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
2326 }
2327
2328 #ifdef CONFIG_PROC_FS
2329 #include <linux/proc_fs.h>
2330 #include <linux/seq_file.h>
2331
2332 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2333 {
2334         struct clk* ck;
2335         int i;
2336         unsigned long rate = clk->rate;
2337
2338         for (i = 0; i < deep; i++)
2339                 seq_printf(s, "    ");
2340
2341         seq_printf(s, "%-9s ", clk->name);
2342
2343         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
2344                 u32 reg;
2345                 int idx = clk->gate_idx;
2346                 u32 v;
2347
2348                 reg = CRU_CLKGATE0_CON;
2349                 reg += (idx >> 5) << 2;
2350                 idx &= 0x1F;
2351
2352                 if (reg == CRU_CLKGATE3_CON)
2353                         v = cru_clkgate3_con_mirror & (1 << idx);
2354                 else
2355                         v = cru_readl(reg) & (1 << idx);
2356
2357                 seq_printf(s, "%s ", v ? "off" : "on ");
2358         }
2359
2360         if (clk == &arm_pll_clk) {
2361                 switch (cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) {
2362                 case CRU_CPU_MODE_SLOW:   seq_printf(s, "slow   "); break;
2363                 case CRU_CPU_MODE_NORMAL: seq_printf(s, "normal "); break;
2364                 case CRU_CPU_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2365                 }
2366                 if (cru_readl(CRU_APLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2367         } else if (clk == &ddr_pll_clk) {
2368                 switch (cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) {
2369                 case CRU_DDR_MODE_SLOW:   seq_printf(s, "slow   "); break;
2370                 case CRU_DDR_MODE_NORMAL: seq_printf(s, "normal "); break;
2371                 case CRU_DDR_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2372                 }
2373                 if (cru_readl(CRU_DPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2374         } else if (clk == &codec_pll_clk) {
2375                 switch (cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) {
2376                 case CRU_CODEC_MODE_SLOW:   seq_printf(s, "slow   "); break;
2377                 case CRU_CODEC_MODE_NORMAL: seq_printf(s, "normal "); break;
2378                 case CRU_CODEC_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2379                 }
2380                 if (cru_readl(CRU_CPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2381         } else if (clk == &general_pll_clk) {
2382                 switch (cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) {
2383                 case CRU_GENERAL_MODE_SLOW:   seq_printf(s, "slow   "); break;
2384                 case CRU_GENERAL_MODE_NORMAL: seq_printf(s, "normal "); break;
2385                 case CRU_GENERAL_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2386                 }
2387                 if (cru_readl(CRU_GPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2388         }
2389
2390         if (rate >= MHZ) {
2391                 if (rate % MHZ)
2392                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2393                 else
2394                         seq_printf(s, "%ld MHz", rate / MHZ);
2395         } else if (rate >= KHZ) {
2396                 if (rate % KHZ)
2397                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2398                 else
2399                         seq_printf(s, "%ld KHz", rate / KHZ);
2400         } else {
2401                 seq_printf(s, "%ld Hz", rate);
2402         }
2403
2404         seq_printf(s, " usecount = %d", clk->usecount);
2405
2406         seq_printf(s, " parent = %s\n", clk->parent ? clk->parent->name : "NULL");
2407
2408         list_for_each_entry(ck, &clocks, node) {
2409                 if (ck->parent == clk)
2410                         dump_clock(s, ck, deep + 1);
2411         }
2412 }
2413
2414 static int proc_clk_show(struct seq_file *s, void *v)
2415 {
2416         struct clk* clk;
2417
2418         mutex_lock(&clocks_mutex);
2419         list_for_each_entry(clk, &clocks, node) {
2420                 if (!clk->parent)
2421                         dump_clock(s, clk, 0);
2422         }
2423         mutex_unlock(&clocks_mutex);
2424
2425         seq_printf(s, "\nCRU Registers:\n");
2426         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2427         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2428         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2429         seq_printf(s, "GPLL     : 0x%08x\n", cru_readl(CRU_GPLL_CON));
2430         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2431         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2432         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2433         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2434         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2435         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2436         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2437         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2438         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2439         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2440         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2441         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2442         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2443         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2444         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2445         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2446         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2447         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2448         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2449         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2450         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2451         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2452         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2453         seq_printf(s, "CLKGATE3M: 0x%08x\n", cru_clkgate3_con_mirror);
2454         seq_printf(s, "SOFTRST0 : 0x%08x\n", cru_readl(CRU_SOFTRST0_CON));
2455         seq_printf(s, "SOFTRST0M: 0x%08x\n", cru_softrst0_con_mirror);
2456         seq_printf(s, "SOFTRST1 : 0x%08x\n", cru_readl(CRU_SOFTRST1_CON));
2457         seq_printf(s, "SOFTRST2 : 0x%08x\n", cru_readl(CRU_SOFTRST2_CON));
2458
2459         seq_printf(s, "\nPMU Registers:\n");
2460         seq_printf(s, "WAKEUP_EN0 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN0));
2461         seq_printf(s, "WAKEUP_EN1 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN1));
2462         seq_printf(s, "WAKEUP_EN2 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN2));
2463         seq_printf(s, "PD_CON     : 0x%08x\n", pmu_readl(PMU_PD_CON));
2464         seq_printf(s, "MISC_CON   : 0x%08x\n", pmu_readl(PMU_MISC_CON));
2465         seq_printf(s, "PLL_CNT    : 0x%08x\n", pmu_readl(PMU_PLL_CNT));
2466         seq_printf(s, "PD_ST      : 0x%08x\n", pmu_readl(PMU_PD_ST));
2467         seq_printf(s, "INT_ST     : 0x%08x\n", pmu_readl(PMU_INT_ST));
2468
2469         return 0;
2470 }
2471
2472 static int proc_clk_open(struct inode *inode, struct file *file)
2473 {
2474         return single_open(file, proc_clk_show, NULL);
2475 }
2476
2477 static const struct file_operations proc_clk_fops = {
2478         .open           = proc_clk_open,
2479         .read           = seq_read,
2480         .llseek         = seq_lseek,
2481         .release        = single_release,
2482 };
2483
2484 static int __init clk_proc_init(void)
2485 {
2486         proc_create("clocks", 0, NULL, &proc_clk_fops);
2487         return 0;
2488
2489 }
2490 late_initcall(clk_proc_init);
2491 #endif /* CONFIG_PROC_FS */
2492