arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33 #include <mach/pmu.h>
  34 #include <mach/sram.h>
  35
  36
  37 /* Clock flags */
  38 /* bit 0 is free */
  39 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  40 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  41 #define IS_PD                   (1 << 2)        /* Power Domain */
  42
  43 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  44 #define pmu_readl(offset)       readl(RK29_PMU_BASE + offset)
  45
  46 #define MHZ                     (1000*1000)
  47 #define KHZ                     1000
  48
  49 struct clk {
  50         struct list_head        node;
  51         const char              *name;
  52         struct clk              *parent;
  53         struct list_head        children;
  54         struct list_head        sibling;        /* node for children */
  55         unsigned long           rate;
  56         u32                     flags;
  57         int                     (*mode)(struct clk *clk, int on);
  58         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  59         int                     (*set_rate)(struct clk *, unsigned long);
  60         long                    (*round_rate)(struct clk *, unsigned long);
  61         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
  62         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
  63         s32                     usecount;
  64         u8                      gate_idx;
  65         u8                      pll_idx;
  66         u8                      clksel_con;
  67         u8                      clksel_mask;
  68         u8                      clksel_shift;
  69         u8                      clksel_maxdiv;
  70         u8                      clksel_parent_mask;
  71         u8                      clksel_parent_shift;
  72         struct clk              **parents;
  73 };
  74
  75 static int clk_enable_nolock(struct clk *clk);
  76 static void clk_disable_nolock(struct clk *clk);
  77 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
  78 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
  79 static void __clk_reparent(struct clk *child, struct clk *parent);
  80 static void __propagate_rate(struct clk *tclk);
  81 static struct clk codec_pll_clk;
  82 static struct clk general_pll_clk;
  83
  84 static unsigned long clksel_recalc_div(struct clk *clk)
  85 {
  86         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
  87         unsigned long rate = clk->parent->rate / div;
  88         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
  89         return rate;
  90 }
  91
  92 static unsigned long clksel_recalc_shift(struct clk *clk)
  93 {
  94         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
  95         unsigned long rate = clk->parent->rate >> shift;
  96         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
  97         return rate;
  98 }
  99
 100 static unsigned long clksel_recalc_frac(struct clk *clk)
 101 {
 102         unsigned long rate;
 103         u64 rate64;
 104         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 105         if (r == 0) // FPGA ?
 106                 return clk->parent->rate;
 107         numerator = r >> 16;
 108         denominator = r & 0xFFFF;
 109         rate64 = (u64)clk->parent->rate * numerator;
 110         do_div(rate64, denominator);
 111         rate = rate64;
 112         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 113         return rate;
 114 }
 115
 116 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 117 {
 118         u32 div;
 119
 120         for (div = 0; div <= clk->clksel_mask; div++) {
 121                 u32 new_rate = clk->parent->rate / (div + 1);
 122                 if (new_rate <= rate) {
 123                         u32 v = cru_readl(clk->clksel_con);
 124                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 125                         v |= div << clk->clksel_shift;
 126                         cru_writel(v, clk->clksel_con);
 127                         clk->rate = new_rate;
 128                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 129                         return 0;
 130                 }
 131         }
 132
 133         return -ENOENT;
 134 }
 135
 136 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 137 {
 138         u32 shift;
 139
 140         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 141                 u32 new_rate = clk->parent->rate >> shift;
 142                 if (new_rate <= rate) {
 143                         u32 v = cru_readl(clk->clksel_con);
 144                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 145                         v |= shift << clk->clksel_shift;
 146                         cru_writel(v, clk->clksel_con);
 147                         clk->rate = new_rate;
 148                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 149                         return 0;
 150                 }
 151         }
 152
 153         return -ENOENT;
 154 }
 155
 156 static struct clk* clksel_get_parent(struct clk *clk)
 157 {
 158         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 159 }
 160
 161 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 162 {
 163         struct clk **p = clk->parents;
 164         u32 i;
 165
 166         if (unlikely(!p))
 167                 return -EINVAL;
 168         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 169                 u32 v;
 170                 if (*p != parent)
 171                         continue;
 172                 v = cru_readl(clk->clksel_con);
 173                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 174                 v |= (i << clk->clksel_parent_shift);
 175                 cru_writel(v, clk->clksel_con);
 176                 return 0;
 177         }
 178         return -EINVAL;
 179 }
 180
 181 /* Work around CRU_CLKGATE3_CON bit21~20 bug */
 182 volatile u32 cru_clkgate3_con_mirror;
 183
 184 static int gate_mode(struct clk *clk, int on)
 185 {
 186         u32 reg;
 187         int idx = clk->gate_idx;
 188         u32 v;
 189
 190         if (idx >= CLK_GATE_MAX)
 191                 return -EINVAL;
 192
 193         reg = CRU_CLKGATE0_CON;
 194         reg += (idx >> 5) << 2;
 195         idx &= 0x1F;
 196
 197         if (reg == CRU_CLKGATE3_CON)
 198                 v = cru_clkgate3_con_mirror;
 199         else
 200                 v = cru_readl(reg);
 201
 202         if (on)
 203                 v &= ~(1 << idx);       // clear bit
 204         else
 205                 v |= (1 << idx);        // set bit
 206
 207         if (reg == CRU_CLKGATE3_CON)
 208                 cru_clkgate3_con_mirror = v;
 209         cru_writel(v, reg);
 210
 211         return 0;
 212 }
 213
 214 /* Work around CRU_SOFTRST0_CON bit29~27 bug */
 215 static volatile u32 cru_softrst0_con_mirror;
 216
 217 void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 218 {
 219         unsigned long flags;
 220         u32 reg = CRU_SOFTRST0_CON + ((idx >> 5) << 2);
 221         u32 mask = 1 << (idx & 31);
 222         u32 v;
 223
 224         if (idx >= SOFT_RST_MAX)
 225                 return;
 226
 227         local_irq_save(flags);
 228
 229         if (reg == CRU_SOFTRST0_CON)
 230                 v = cru_softrst0_con_mirror;
 231         else
 232                 v = cru_readl(reg);
 233
 234         if (on)
 235                 v |= mask;
 236         else
 237                 v &= ~mask;
 238
 239         if (reg == CRU_SOFTRST0_CON)
 240                 cru_softrst0_con_mirror = v;
 241         cru_writel(v, reg);
 242
 243         local_irq_restore(flags);
 244 }
 245
 246 static struct clk xin24m = {
 247         .name           = "xin24m",
 248         .rate           = 24 * MHZ,
 249         .flags          = RATE_FIXED,
 250 };
 251
 252 static struct clk clk_12m = {
 253         .name           = "clk_12m",
 254         .rate           = 12 * MHZ,
 255         .parent         = &xin24m,
 256         .flags          = RATE_FIXED,
 257 };
 258
 259 static struct clk xin27m = {
 260         .name           = "xin27m",
 261         .rate           = 27 * MHZ,
 262         .flags          = RATE_FIXED,
 263 };
 264
 265 static struct clk otgphy0_clkin = {
 266         .name           = "otgphy0_clkin",
 267         .rate           = 480 * MHZ,
 268         .flags          = RATE_FIXED,
 269 };
 270
 271 static struct clk otgphy1_clkin = {
 272         .name           = "otgphy1_clkin",
 273         .rate           = 480 * MHZ,
 274         .flags          = RATE_FIXED,
 275 };
 276
 277
 278 static void delay_500ns(void)
 279 {
 280         int delay = 2000;
 281         while (delay--)
 282                 barrier();
 283 }
 284
 285 static void delay_300us(void)
 286 {
 287         int i;
 288         for (i = 0; i < 600; i++)
 289                 delay_500ns();
 290 }
 291
 292 #define GENERAL_PLL_IDX     0
 293 #define CODEC_PLL_IDX      1
 294 #define ARM_PLL_IDX        2
 295 #define DDR_PLL_IDX        3
 296
 297 #define GRF_SOC_CON0       0xbc
 298 static void pll_wait_lock(int pll_idx)
 299 {
 300         u32 bit = 0x2000000u << pll_idx;
 301         int delay = 2400000;
 302         while (delay > 0) {
 303                 if (regfile_readl(GRF_SOC_CON0) & bit)
 304                         break;
 305                 delay--;
 306         }
 307         if (delay == 0) {
 308                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 309         }
 310 }
 311
 312 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 313 {
 314         unsigned long rate;
 315
 316         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 317                 u32 v = cru_readl(CRU_APLL_CON);
 318                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 319                 do_div(rate64, PLL_NR(v));
 320                 rate = rate64 >> PLL_NO_SHIFT(v);
 321                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 322         } else {
 323                 rate = clk->parent->rate;
 324                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 325         }
 326
 327         return rate;
 328 }
 329
 330 struct arm_pll_set {
 331         unsigned long rate;
 332         u32 apll_con;
 333         u32 clksel0_con;
 334 };
 335
 336 #define CORE_ACLK_11    (0 << 5)
 337 #define CORE_ACLK_21    (1 << 5)
 338 #define CORE_ACLK_31    (2 << 5)
 339 #define CORE_ACLK_41    (3 << 5)
 340 #define CORE_ACLK_81    (4 << 5)
 341 #define CORE_ACLK_MASK  (7 << 5)
 342
 343 #define ACLK_HCLK_11    (0 << 8)
 344 #define ACLK_HCLK_21    (1 << 8)
 345 #define ACLK_HCLK_41    (2 << 8)
 346 #define ACLK_HCLK_MASK  (3 << 8)
 347
 348 #define ACLK_PCLK_11    (0 << 10)
 349 #define ACLK_PCLK_21    (1 << 10)
 350 #define ACLK_PCLK_41    (2 << 10)
 351 #define ACLK_PCLK_81    (3 << 10)
 352 #define ACLK_PCLK_MASK  (3 << 10)
 353
 354 #define ARM_PLL(_mhz, nr, nf, no, _axi_div, _ahb_div, _apb_div) \
 355 { \
 356         .rate           = _mhz * MHZ, \
 357         .apll_con       = PLL_CLKR(nr) | PLL_CLKF(nf >> 1) | PLL_NO_##no, \
 358         .clksel0_con    = CORE_ACLK_##_axi_div | ACLK_HCLK_##_ahb_div | ACLK_PCLK_##_apb_div, \
 359 }
 360
 361 static const struct arm_pll_set arm_pll[] = {
 362         // rate = 24 * NF / (NR * NO)
 363         //      rate NR  NF NO adiv hdiv pdiv
 364         ARM_PLL(1200, 1, 50, 1, 41, 21, 81),
 365         ARM_PLL(1104, 1, 46, 1, 41, 21, 81),
 366         ARM_PLL(1008, 1, 42, 1, 41, 21, 81),
 367         ARM_PLL( 912, 1, 38, 1, 31, 21, 81),
 368         ARM_PLL( 888, 2, 74, 1, 31, 21, 81),
 369         ARM_PLL( 816, 1, 34, 1, 31, 21, 81),
 370         ARM_PLL( 696, 1, 58, 2, 31, 21, 81),
 371         ARM_PLL( 624, 1, 52, 2, 31, 21, 81),
 372         ARM_PLL( 600, 1, 50, 2, 21, 21, 81),
 373         ARM_PLL( 504, 1, 42, 2, 21, 21, 81),
 374         ARM_PLL( 408, 1, 34, 2, 21, 21, 81),
 375         ARM_PLL( 300, 1, 50, 4, 21, 21, 41),
 376         ARM_PLL( 204, 1, 34, 4, 21, 21, 41),
 377         ARM_PLL( 102, 1, 34, 8, 21, 21, 41),
 378         // last item, pll power down.
 379         ARM_PLL(  24, 1, 64, 8, 21, 21, 41),
 380 };
 381
 382 #define CORE_PARENT_MASK        (3 << 23)
 383 #define CORE_PARENT_ARM_PLL     (0 << 23)
 384 #define CORE_PARENT_GENERAL_PLL (1 << 23)
 385
 386 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 387 {
 388         const struct arm_pll_set *ps, *pt;
 389
 390         /* find the arm_pll we want. */
 391         ps = pt = &arm_pll[0];
 392         while (1) {
 393                 if (pt->rate == rate) {
 394                         ps = pt;
 395                         break;
 396                 }
 397                 // we are sorted, and ps->rate > pt->rate.
 398                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 399                         ps = pt;
 400                 if (pt->rate < rate || pt->rate == 24 * MHZ)
 401                         break;
 402                 pt++;
 403         }
 404
 405         /* make aclk safe & reparent to general pll */
 406         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK)) | CORE_PARENT_GENERAL_PLL | CORE_ACLK_21, CRU_CLKSEL0_CON);
 407
 408         /* enter slow mode */
 409         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 410
 411         /* power down */
 412         cru_writel(cru_readl(CRU_APLL_CON) | PLL_PD, CRU_APLL_CON);
 413
 414         delay_500ns();
 415
 416         cru_writel(ps->apll_con | PLL_PD, CRU_APLL_CON);
 417
 418         delay_500ns();
 419
 420         /* power up */
 421         cru_writel(ps->apll_con, CRU_APLL_CON);
 422
 423         delay_300us();
 424         pll_wait_lock(ARM_PLL_IDX);
 425
 426         /* reparent to arm pll & set aclk/hclk/pclk */
 427         cru_writel((cru_readl(CRU_CLKSEL0_CON) & ~(CORE_PARENT_MASK | CORE_ACLK_MASK | ACLK_HCLK_MASK | ACLK_PCLK_MASK)) | CORE_PARENT_ARM_PLL | ps->clksel0_con, CRU_CLKSEL0_CON);
 428
 429         /* enter normal mode */
 430         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_NORMAL, CRU_MODE_CON);
 431
 432         return 0;
 433 }
 434
 435 static struct clk *arm_pll_parents[2] = { &xin24m, &xin27m };
 436
 437 static struct clk arm_pll_clk = {
 438         .name           = "arm_pll",
 439         .parent         = &xin24m,
 440         .recalc         = arm_pll_clk_recalc,
 441         .set_rate       = arm_pll_clk_set_rate,
 442         .clksel_con     = CRU_MODE_CON,
 443         .clksel_parent_mask     = 1,
 444         .clksel_parent_shift    = 8,
 445         .parents        = arm_pll_parents,
 446 };
 447
 448 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 449 {
 450         unsigned long rate;
 451
 452         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 453                 u32 v = cru_readl(CRU_DPLL_CON);
 454                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 455                 do_div(rate64, PLL_NR(v));
 456                 rate = rate64 >> PLL_NO_SHIFT(v);
 457                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 458         } else {
 459                 rate = clk->parent->rate;
 460                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 461         }
 462
 463         return rate;
 464 }
 465
 466 static struct clk *ddr_pll_parents[4] = { &xin24m, &xin27m, &codec_pll_clk, &general_pll_clk };
 467
 468 static struct clk ddr_pll_clk = {
 469         .name           = "ddr_pll",
 470         .parent         = &xin24m,
 471         .recalc         = ddr_pll_clk_recalc,
 472         .clksel_con     = CRU_MODE_CON,
 473         .clksel_parent_mask     = 3,
 474         .clksel_parent_shift    = 13,
 475         .parents        = ddr_pll_parents,
 476 };
 477
 478
 479 static int codec_pll_clk_mode(struct clk *clk, int on)
 480 {
 481         u32 cpll = cru_readl(CRU_CPLL_CON);
 482         if (on) {
 483                 cru_writel(cpll & ~(PLL_PD | PLL_BYPASS), CRU_CPLL_CON);
 484                 delay_300us();
 485                 pll_wait_lock(CODEC_PLL_IDX);
 486                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_NORMAL, CRU_MODE_CON);
 487         } else {
 488                 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 489                 cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 490                 cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 491                 delay_500ns();
 492         }
 493         return 0;
 494 }
 495
 496 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 497 {
 498         unsigned long rate;
 499         u32 v = cru_readl(CRU_CPLL_CON);
 500         u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 501         do_div(rate64, PLL_NR(v));
 502         rate = rate64 >> PLL_NO_SHIFT(v);
 503         pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 504         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) != CRU_CODEC_MODE_NORMAL)
 505                 pr_debug("%s rate is %ld (slow mode) actually\n", clk->name, clk->parent->rate);
 506         return rate;
 507 }
 508
 509 #define CODEC_PLL_PARENT_MASK   (3 << 11)
 510 #define CODEC_PLL_PARENT_XIN24M (0 << 11)
 511 #define CODEC_PLL_PARENT_XIN27M (1 << 11)
 512 #define CODEC_PLL_PARENT_DDR_PLL        (2 << 11)
 513 #define CODEC_PLL_PARENT_GENERAL_PLL    (3 << 11)
 514
 515 struct codec_pll_set {
 516         unsigned long rate;
 517         u32 pll_con;
 518         u32 parent_con;
 519 };
 520
 521 #define CODEC_PLL(_mhz, _parent, band, nr, nf, no) \
 522 { \
 523         .rate           = _mhz * MHZ, \
 524         .pll_con        = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
 525         .parent_con     = CODEC_PLL_PARENT_XIN##_parent##M, \
 526 }
 527
 528 static const struct codec_pll_set codec_pll[] = {
 529         //      rate parent band NR NF NO
 530         CODEC_PLL(108, 24,  LOW, 1, 18, 4),     // for TV
 531         CODEC_PLL(648, 24, HIGH, 1, 27, 1),
 532         CODEC_PLL(297, 27,  LOW, 1, 22, 2),     // for HDMI
 533         CODEC_PLL(594, 27,  LOW, 1, 22, 1),
 534         CODEC_PLL(360, 24,  LOW, 1, 15, 1),     // for GPU
 535         CODEC_PLL(408, 24,  LOW, 1, 17, 1),
 536         CODEC_PLL(456, 24,  LOW, 1, 19, 1),
 537         CODEC_PLL(504, 24,  LOW, 1, 21, 1),
 538         CODEC_PLL(552, 24,  LOW, 1, 23, 1),
 539         CODEC_PLL(600, 24, HIGH, 1, 25, 1),
 540 };
 541
 542 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 543 {
 544         int i;
 545         u32 work_mode;
 546
 547         const struct codec_pll_set *ps = NULL;
 548
 549         for (i = 0; i < ARRAY_SIZE(codec_pll); i++) {
 550                 if (codec_pll[i].rate == rate) {
 551                         ps = &codec_pll[i];
 552                         break;
 553                 }
 554         }
 555         if (!ps)
 556                 return  -ENOENT;
 557
 558         work_mode = cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK;
 559
 560         /* enter slow mode */
 561         cru_writel((cru_readl(CRU_MODE_CON) & ~(CRU_CODEC_MODE_MASK | CODEC_PLL_PARENT_MASK)) | CRU_CODEC_MODE_SLOW | ps->parent_con, CRU_MODE_CON);
 562
 563         /* power down */
 564         cru_writel(cru_readl(CRU_CPLL_CON) | PLL_PD, CRU_CPLL_CON);
 565
 566         delay_500ns();
 567
 568         cru_writel(ps->pll_con | PLL_PD, CRU_CPLL_CON);
 569
 570         delay_500ns();
 571
 572         /* power up */
 573         cru_writel(ps->pll_con, CRU_CPLL_CON);
 574
 575         delay_300us();
 576         pll_wait_lock(CODEC_PLL_IDX);
 577
 578         /* enter normal mode */
 579         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | work_mode, CRU_MODE_CON);
 580
 581         clk_set_parent_nolock(clk, ps->parent_con == CODEC_PLL_PARENT_XIN24M ? &xin24m : &xin27m);
 582
 583         return 0;
 584 }
 585
 586 static struct clk *codec_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &general_pll_clk };
 587
 588 static struct clk codec_pll_clk = {
 589         .name           = "codec_pll",
 590         .parent         = &xin24m,
 591         .mode           = codec_pll_clk_mode,
 592         .recalc         = codec_pll_clk_recalc,
 593         .set_rate       = codec_pll_clk_set_rate,
 594         .clksel_con     = CRU_MODE_CON,
 595         .clksel_parent_mask     = 3,
 596         .clksel_parent_shift    = 11,
 597         .parents        = codec_pll_parents,
 598 };
 599
 600
 601 static unsigned long general_pll_clk_recalc(struct clk *clk)
 602 {
 603         unsigned long rate;
 604
 605         if ((cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) == CRU_GENERAL_MODE_NORMAL) {
 606                 u32 v = cru_readl(CRU_GPLL_CON);
 607                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 608                 do_div(rate64, PLL_NR(v));
 609                 rate = rate64 >> PLL_NO_SHIFT(v);
 610                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 611         } else {
 612                 rate = clk->parent->rate;
 613                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 614         }
 615
 616         return rate;
 617 }
 618
 619 static int general_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 620 {
 621         u32 pll_con;
 622
 623         switch (rate) {
 624         case 96 * MHZ:
 625                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 626                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(16) | PLL_NO_4;
 627         break;
 628         case 144*MHZ:
 629                 /* 96M: low-band, NR=1, NF=16, NO=4 */
 630                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_4;
 631         break;
 632         case 288 * MHZ:
 633                 /* 288M: low-band, NR=1, NF=24, NO=2 */
 634                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(24) | PLL_NO_2;
 635                 break;
 636         case 300 * MHZ:
 637                 /* 300M: low-band, NR=1, NF=25, NO=2 */
 638                 pll_con = PLL_LOW_BAND | PLL_CLKR(1) | PLL_CLKF(25) | PLL_NO_2;
 639         break;
 640         case 624 * MHZ:
 641                 /* 624M: high-band, NR=1, NF=26, NO=1 */
 642                 pll_con = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 643                 break;
 644         default:
 645                 return -ENOENT;
 646                 break;
 647         }
 648
 649         /* enter slow mode */
 650         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 651
 652         /* power down */
 653         cru_writel(cru_readl(CRU_GPLL_CON) | PLL_PD, CRU_GPLL_CON);
 654
 655         delay_500ns();
 656
 657         cru_writel(pll_con | PLL_PD, CRU_GPLL_CON);
 658
 659         delay_500ns();
 660
 661         /* power up */
 662         cru_writel(pll_con, CRU_GPLL_CON);
 663
 664         delay_300us();
 665         pll_wait_lock(GENERAL_PLL_IDX);
 666
 667         /* enter normal mode */
 668         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_NORMAL, CRU_MODE_CON);
 669
 670         return 0;
 671 }
 672
 673 static struct clk *general_pll_parents[4] = { &xin24m, &xin27m, &ddr_pll_clk, &codec_pll_clk };
 674
 675 static struct clk general_pll_clk = {
 676         .name           = "general_pll",
 677         .parent         = &xin24m,
 678         .recalc         = general_pll_clk_recalc,
 679         .set_rate       = general_pll_clk_set_rate,
 680         .clksel_con     = CRU_MODE_CON,
 681         .clksel_parent_mask     = 3,
 682         .clksel_parent_shift    = 9,
 683         .parents        = general_pll_parents,
 684 };
 685
 686
 687 static struct clk *clk_core_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 688
 689 static struct clk clk_core = {
 690         .name           = "core",
 691         .parent         = &arm_pll_clk,
 692         .recalc         = clksel_recalc_div,
 693         .clksel_con     = CRU_CLKSEL0_CON,
 694         .clksel_mask    = 0x1F,
 695         .clksel_shift   = 0,
 696         .clksel_parent_mask     = 3,
 697         .clksel_parent_shift    = 23,
 698         .parents        = clk_core_parents,
 699 };
 700
 701 static unsigned long aclk_cpu_recalc(struct clk *clk)
 702 {
 703         unsigned long rate;
 704         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 705
 706         BUG_ON(div > 5);
 707         if (div >= 5)
 708                 div = 8;
 709         rate = clk->parent->rate / div;
 710         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 711
 712         return rate;
 713 }
 714
 715 static struct clk aclk_cpu = {
 716         .name           = "aclk_cpu",
 717         .parent         = &clk_core,
 718         .recalc         = aclk_cpu_recalc,
 719 };
 720
 721 static struct clk hclk_cpu = {
 722         .name           = "hclk_cpu",
 723         .parent         = &aclk_cpu,
 724         .recalc         = clksel_recalc_shift,
 725         .set_rate       = clksel_set_rate_shift,
 726         .clksel_con     = CRU_CLKSEL0_CON,
 727         .clksel_mask    = 3,
 728         .clksel_shift   = 8,
 729         .clksel_maxdiv  = 4,
 730 };
 731
 732 static struct clk pclk_cpu = {
 733         .name           = "pclk_cpu",
 734         .parent         = &aclk_cpu,
 735         .recalc         = clksel_recalc_shift,
 736         .set_rate       = clksel_set_rate_shift,
 737         .clksel_con     = CRU_CLKSEL0_CON,
 738         .clksel_mask    = 3,
 739         .clksel_shift   = 10,
 740         .clksel_maxdiv  = 8,
 741 };
 742
 743 static struct clk *aclk_periph_parents[4] = { &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &codec_pll_clk };
 744
 745 static struct clk aclk_periph = {
 746         .name           = "aclk_periph",
 747         .mode           = gate_mode,
 748         .gate_idx       = CLK_GATE_ACLK_PEIRPH,
 749         .recalc         = clksel_recalc_div,
 750         .set_rate       = clksel_set_rate_div,
 751         .clksel_con     = CRU_CLKSEL0_CON,
 752         .clksel_mask    = 0x1F,
 753         .clksel_shift   = 14,
 754         .clksel_parent_mask     = 3,
 755         .clksel_parent_shift    = 12,
 756         .parents        = aclk_periph_parents,
 757 };
 758
 759 static struct clk pclk_periph = {
 760         .name           = "pclk_periph",
 761         .mode           = gate_mode,
 762         .gate_idx       = CLK_GATE_PCLK_PEIRPH,
 763         .parent         = &aclk_periph,
 764         .recalc         = clksel_recalc_shift,
 765         .set_rate       = clksel_set_rate_shift,
 766         .clksel_con     = CRU_CLKSEL0_CON,
 767         .clksel_mask    = 3,
 768         .clksel_shift   = 19,
 769         .clksel_maxdiv  = 8,
 770 };
 771
 772 static struct clk hclk_periph = {
 773         .name           = "hclk_periph",
 774         .mode           = gate_mode,
 775         .gate_idx       = CLK_GATE_HCLK_PEIRPH,
 776         .parent         = &aclk_periph,
 777         .recalc         = clksel_recalc_shift,
 778         .set_rate       = clksel_set_rate_shift,
 779         .clksel_con     = CRU_CLKSEL0_CON,
 780         .clksel_mask    = 3,
 781         .clksel_shift   = 21,
 782         .clksel_maxdiv  = 4,
 783 };
 784
 785
 786 static struct clk *clk_uhost_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 787
 788 static struct clk clk_uhost = {
 789         .name           = "uhost",
 790         .mode           = gate_mode,
 791         .recalc         = clksel_recalc_div,
 792         .set_rate       = clksel_set_rate_div,
 793         .gate_idx       = CLK_GATE_UHOST,
 794         .clksel_con     = CRU_CLKSEL1_CON,
 795         .clksel_mask    = 0x1F,
 796         .clksel_shift   = 16,
 797         .clksel_parent_mask     = 7,
 798         .clksel_parent_shift    = 13,
 799         .parents        = clk_uhost_parents,
 800 };
 801
 802 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 803
 804 static struct clk clk_otgphy0 = {
 805         .name           = "otgphy0",
 806         .mode           = gate_mode,
 807         .gate_idx       = CLK_GATE_USBPHY0,
 808         .clksel_con     = CRU_CLKSEL1_CON,
 809         .clksel_parent_mask     = 3,
 810         .clksel_parent_shift    = 9,
 811         .parents        = clk_otgphy_parents,
 812 };
 813
 814 static struct clk clk_otgphy1 = {
 815         .name           = "otgphy1",
 816         .mode           = gate_mode,
 817         .gate_idx       = CLK_GATE_USBPHY1,
 818         .clksel_con     = CRU_CLKSEL1_CON,
 819         .clksel_parent_mask     = 3,
 820         .clksel_parent_shift    = 11,
 821         .parents        = clk_otgphy_parents,
 822 };
 823
 824
 825 static struct clk rmii_clkin = {
 826         .name           = "rmii_clkin",
 827 };
 828
 829 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 830
 831 static struct clk clk_mac_ref_div = {
 832         .name           = "mac_ref_div",
 833         .recalc         = clksel_recalc_div,
 834         .set_rate       = clksel_set_rate_div,
 835         .clksel_con     = CRU_CLKSEL1_CON,
 836         .clksel_mask    = 0x1F,
 837         .clksel_shift   = 23,
 838         .clksel_parent_mask     = 3,
 839         .clksel_parent_shift    = 21,
 840         .parents        = clk_mac_ref_div_parents,
 841 };
 842
 843 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 844
 845 static struct clk clk_mac_ref = {
 846         .name           = "mac_ref",
 847         .mode           = gate_mode,
 848         .gate_idx       = CLK_GATE_MAC_REF,
 849         .clksel_con     = CRU_CLKSEL1_CON,
 850         .clksel_parent_mask     = 1,
 851         .clksel_parent_shift    = 28,
 852         .parents        = clk_mac_ref_parents,
 853 };
 854
 855
 856 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &general_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 857
 858 static struct clk clk_i2s0_div = {
 859         .name           = "i2s0_div",
 860         .recalc         = clksel_recalc_div,
 861         .set_rate       = clksel_set_rate_div,
 862         .clksel_con     = CRU_CLKSEL2_CON,
 863         .clksel_mask    = 0x1F,
 864         .clksel_shift   = 3,
 865         .clksel_parent_mask     = 7,
 866         .clksel_parent_shift    = 0,
 867         .parents        = clk_i2s_div_parents,
 868 };
 869
 870 static struct clk clk_i2s1_div = {
 871         .name           = "i2s1_div",
 872         .recalc         = clksel_recalc_div,
 873         .set_rate       = clksel_set_rate_div,
 874         .clksel_con     = CRU_CLKSEL2_CON,
 875         .clksel_mask    = 0x1F,
 876         .clksel_shift   = 13,
 877         .clksel_parent_mask     = 7,
 878         .clksel_parent_shift    = 10,
 879         .parents        = clk_i2s_div_parents,
 880 };
 881
 882 static struct clk clk_spdif_div = {
 883         .name           = "spdif_div",
 884         .recalc         = clksel_recalc_div,
 885         .set_rate       = clksel_set_rate_div,
 886         .clksel_con     = CRU_CLKSEL2_CON,
 887         .clksel_mask    = 0x1F,
 888         .clksel_shift   = 23,
 889         .clksel_parent_mask     = 7,
 890         .clksel_parent_shift    = 20,
 891         .parents        = clk_i2s_div_parents,
 892 };
 893 u32 clk_gcd(u32 numerator,u32 denominator)
 894 {
 895
 896         u32 a,b,r;
 897
 898         if(!numerator||!denominator)
 899                 return 0;
 900         if(numerator > denominator){
 901                 a = numerator;
 902                 b = denominator;
 903         }else{
 904                 a = denominator;
 905                 b = numerator;
 906         }
 907         while(b != 0){
 908         int r = b;
 909         b = a % b;
 910         a = r;
 911     }
 912
 913         return a;
 914 }
 915 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 916 {
 917         u16 numerator, denominator;
 918         u32 gcd=0;
 919         gcd=clk_gcd(rate,clk->parent->rate);
 920         pr_debug("%s i2s rate=%d,parent=%d,gcd=%d\n",__FUNCTION__,
 921                 rate,clk->parent->rate,gcd);
 922         if(!gcd)
 923         {
 924                 printk("gcd=0,i2s frac div is not be supported\n");
 925                 return -ENOENT;
 926         }
 927         numerator=rate/gcd;
 928         denominator=clk->parent->rate/gcd;
 929         pr_debug("%s i2s numerator=%d,denominator=%d,times=%d\n",
 930                 __FUNCTION__,numerator,denominator,denominator/numerator);
 931         if(numerator>0xffff||denominator>0xffff)
 932         {
 933                 printk("i2s can't get a available nume and deno\n");
 934                 return -ENOENT;
 935         }
 936 #if 0
 937         switch (rate) {
 938         case 8192000:   /* 288*32/1125 */
 939                 numerator = 32;
 940                 denominator = 1125;
 941                 break;
 942         case 11289600:  /* 288*49/1250 */
 943                 numerator = 49;
 944                 denominator = 1250;
 945                 break;
 946         case 12288000:  /* 288*16/375 */
 947                 numerator = 16;
 948                 denominator = 375;
 949                 break;
 950         default:
 951                 return -ENOENT;
 952         }
 953 #endif
 954         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 955         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
 956
 957         return 0;
 958 }
 959
 960 static struct clk clk_i2s0_frac_div = {
 961         .name           = "i2s0_frac_div",
 962         .parent         = &clk_i2s0_div,
 963         .recalc         = clksel_recalc_frac,
 964         .set_rate       = clk_i2s_frac_div_set_rate,
 965         .clksel_con     = CRU_CLKSEL3_CON,
 966 };
 967
 968 static struct clk clk_i2s1_frac_div = {
 969         .name           = "i2s1_frac_div",
 970         .parent         = &clk_i2s1_div,
 971         .recalc         = clksel_recalc_frac,
 972         .set_rate       = clk_i2s_frac_div_set_rate,
 973         .clksel_con     = CRU_CLKSEL4_CON,
 974 };
 975
 976 static struct clk clk_spdif_frac_div = {
 977         .name           = "spdif_frac_div",
 978         .parent         = &clk_spdif_div,
 979         .recalc         = clksel_recalc_frac,
 980         .set_rate       = clk_i2s_frac_div_set_rate,
 981         .clksel_con     = CRU_CLKSEL5_CON,
 982 };
 983
 984 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 985 {
 986         int ret;
 987         struct clk *parent;
 988
 989         if (rate == 12 * MHZ) {
 990                 parent = &clk_12m;
 991         } else {
 992                 parent = clk->parents[1]; /* frac div */
 993                 ret = clk_set_rate_nolock(parent, rate);
 994                 if (ret)
 995                         return ret;
 996         }
 997         if (clk->parent != parent)
 998                 clk_set_parent_nolock(clk, parent);
 999
1000         return ret;
1001 }
1002
1003 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
1004
1005 static struct clk clk_i2s0 = {
1006         .name           = "i2s0",
1007         .mode           = gate_mode,
1008         .gate_idx       = CLK_GATE_I2S0,
1009         .set_rate       = i2s_set_rate,
1010         .clksel_con     = CRU_CLKSEL2_CON,
1011         .clksel_parent_mask     = 3,
1012         .clksel_parent_shift    = 8,
1013         .parents        = clk_i2s0_parents,
1014 };
1015
1016 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
1017
1018 static struct clk clk_i2s1 = {
1019         .name           = "i2s1",
1020         .mode           = gate_mode,
1021         .gate_idx       = CLK_GATE_I2S1,
1022         .set_rate       = i2s_set_rate,
1023         .clksel_con     = CRU_CLKSEL2_CON,
1024         .clksel_parent_mask     = 3,
1025         .clksel_parent_shift    = 18,
1026         .parents        = clk_i2s1_parents,
1027 };
1028
1029 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
1030
1031 static struct clk clk_spdif = {
1032         .name           = "spdif",
1033         .mode           = gate_mode,
1034         .gate_idx       = CLK_GATE_SPDIF,
1035         .set_rate       = i2s_set_rate,
1036         .clksel_con     = CRU_CLKSEL2_CON,
1037         .clksel_parent_mask     = 3,
1038         .clksel_parent_shift    = 28,
1039         .parents        = clk_spdif_parents,
1040 };
1041
1042
1043 static struct clk *clk_spi_src_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1044
1045 static struct clk clk_spi_src = {
1046         .name           = "spi_src",
1047         .clksel_con     = CRU_CLKSEL6_CON,
1048         .clksel_parent_mask     = 3,
1049         .clksel_parent_shift    = 0,
1050         .parents        = clk_spi_src_parents,
1051 };
1052
1053 static struct clk clk_spi0 = {
1054         .name           = "spi0",
1055         .parent         = &clk_spi_src,
1056         .mode           = gate_mode,
1057         .recalc         = clksel_recalc_div,
1058         .set_rate       = clksel_set_rate_div,
1059         .gate_idx       = CLK_GATE_SPI0,
1060         .clksel_con     = CRU_CLKSEL6_CON,
1061         .clksel_mask    = 0x7F,
1062         .clksel_shift   = 2,
1063 };
1064
1065 static struct clk clk_spi1 = {
1066         .name           = "spi1",
1067         .parent         = &clk_spi_src,
1068         .mode           = gate_mode,
1069         .recalc         = clksel_recalc_div,
1070         .set_rate       = clksel_set_rate_div,
1071         .gate_idx       = CLK_GATE_SPI1,
1072         .clksel_con     = CRU_CLKSEL6_CON,
1073         .clksel_mask    = 0x7F,
1074         .clksel_shift   = 11,
1075 };
1076
1077
1078 static struct clk clk_saradc = {
1079         .name           = "saradc",
1080         .parent         = &pclk_periph,
1081         .mode           = gate_mode,
1082         .recalc         = clksel_recalc_div,
1083         .set_rate       = clksel_set_rate_div,
1084         .gate_idx       = CLK_GATE_SARADC,
1085         .clksel_con     = CRU_CLKSEL6_CON,
1086         .clksel_mask    = 0xFF,
1087         .clksel_shift   = 18,
1088 };
1089
1090
1091 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
1092
1093 static struct clk clk_timer0 = {
1094         .name           = "timer0",
1095         .mode           = gate_mode,
1096         .gate_idx       = CLK_GATE_TIMER0,
1097         .clksel_con     = CRU_CLKSEL6_CON,
1098         .clksel_parent_mask     = 1,
1099         .clksel_parent_shift    = 26,
1100         .parents        = clk_cpu_timer_parents,
1101 };
1102
1103 static struct clk clk_timer1 = {
1104         .name           = "timer1",
1105         .mode           = gate_mode,
1106         .gate_idx       = CLK_GATE_TIMER1,
1107         .clksel_con     = CRU_CLKSEL6_CON,
1108         .clksel_parent_mask     = 1,
1109         .clksel_parent_shift    = 27,
1110         .parents        = clk_cpu_timer_parents,
1111 };
1112
1113 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
1114
1115 static struct clk clk_timer2 = {
1116         .name           = "timer2",
1117         .mode           = gate_mode,
1118         .gate_idx       = CLK_GATE_TIMER2,
1119         .clksel_con     = CRU_CLKSEL6_CON,
1120         .clksel_parent_mask     = 1,
1121         .clksel_parent_shift    = 28,
1122         .parents        = clk_periph_timer_parents,
1123 };
1124
1125 static struct clk clk_timer3 = {
1126         .name           = "timer3",
1127         .mode           = gate_mode,
1128         .gate_idx       = CLK_GATE_TIMER3,
1129         .clksel_con     = CRU_CLKSEL6_CON,
1130         .clksel_parent_mask     = 1,
1131         .clksel_parent_shift    = 29,
1132         .parents        = clk_periph_timer_parents,
1133 };
1134
1135
1136 static struct clk *clk_mmc_src_parents[4] = { &arm_pll_clk, &general_pll_clk, &codec_pll_clk, &ddr_pll_clk };
1137
1138 static struct clk clk_mmc_src = {
1139         .name           = "mmc_src",
1140         .clksel_con     = CRU_CLKSEL7_CON,
1141         .clksel_parent_mask     = 3,
1142         .clksel_parent_shift    = 0,
1143         .parents        = clk_mmc_src_parents,
1144 };
1145
1146 static struct clk clk_mmc0 = {
1147         .name           = "mmc0",
1148         .parent         = &clk_mmc_src,
1149         .mode           = gate_mode,
1150         .recalc         = clksel_recalc_div,
1151         .set_rate       = clksel_set_rate_div,
1152         .gate_idx       = CLK_GATE_MMC0,
1153         .clksel_con     = CRU_CLKSEL7_CON,
1154         .clksel_mask    = 0x3F,
1155         .clksel_shift   = 2,
1156 };
1157
1158 static struct clk clk_mmc1 = {
1159         .name           = "mmc1",
1160         .parent         = &clk_mmc_src,
1161         .mode           = gate_mode,
1162         .recalc         = clksel_recalc_div,
1163         .set_rate       = clksel_set_rate_div,
1164         .gate_idx       = CLK_GATE_MMC1,
1165         .clksel_con     = CRU_CLKSEL7_CON,
1166         .clksel_mask    = 0x3F,
1167         .clksel_shift   = 10,
1168 };
1169
1170 static struct clk clk_emmc = {
1171         .name           = "emmc",
1172         .parent         = &clk_mmc_src,
1173         .mode           = gate_mode,
1174         .recalc         = clksel_recalc_div,
1175         .set_rate       = clksel_set_rate_div,
1176         .gate_idx       = CLK_GATE_EMMC,
1177         .clksel_con     = CRU_CLKSEL7_CON,
1178         .clksel_mask    = 0x3F,
1179         .clksel_shift   = 18,
1180 };
1181
1182
1183 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &general_pll_clk, &codec_pll_clk, &arm_pll_clk };
1184
1185 static struct clk clk_ddr = {
1186         .name           = "ddr",
1187         .recalc         = clksel_recalc_shift,
1188         .clksel_con     = CRU_CLKSEL7_CON,
1189         .clksel_mask    = 7,
1190         .clksel_shift   = 26,
1191         .clksel_maxdiv  = 32,
1192         .clksel_parent_mask     = 3,
1193         .clksel_parent_shift    = 24,
1194         .parents        = clk_ddr_parents,
1195 };
1196
1197
1198 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1199 {
1200         int ret;
1201         struct clk *parent;
1202         struct clk *clk_div = clk->parents[0];
1203
1204         switch (rate) {
1205         case 24*MHZ: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
1206                 parent = clk->parents[2]; /* xin24m */
1207                 break;
1208         case 19200*16:
1209         case 38400*16:
1210         case 57600*16:
1211         case 115200*16:
1212         case 230400*16:
1213         case 460800*16:
1214         case 576000*16:
1215                 parent = clk->parents[1]; /* frac div */
1216                 /* reset div to 1 */
1217                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
1218                 if (ret)
1219                         return ret;
1220                 break;
1221         default:
1222                 parent = clk_div;
1223                 break;
1224         }
1225
1226         if (parent->set_rate) {
1227                 ret = clk_set_rate_nolock(parent, rate);
1228                 if (ret)
1229                         return ret;
1230         }
1231
1232         if (clk->parent != parent)
1233                 clk_set_parent_nolock(clk, parent);
1234
1235         return 0;
1236 }
1237
1238 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
1239 {
1240         u16 numerator, denominator;
1241         u32 gcd=0;
1242         gcd=clk_gcd(rate,clk->parent->rate);
1243         pr_debug("%s uart rate=%d,parent=%d,gcd=%d\n",__FUNCTION__,rate,clk->parent->rate,gcd);
1244         if(!gcd)
1245         {
1246                 printk("gcd=0,uart frac div is not be supported\n");
1247                 return -ENOENT;
1248         }
1249         numerator=rate/gcd;
1250         denominator=clk->parent->rate/gcd;
1251         pr_debug("%s uart numerator=%d,denominator=%d,times=%d\n",__FUNCTION__,
1252                 numerator,denominator,denominator/numerator);
1253         if(numerator>0xffff||denominator>0xffff)
1254         {
1255                 printk("uart_frac can't get a available nume and deno\n");
1256                 return -ENOENT;
1257         }
1258 #if 0
1259         switch (rate) {
1260         case 19200*16:  /* 288*2/1875 */
1261                 numerator = 2;
1262                 denominator = 1875;
1263                 break;
1264         case 38400*16:  /* 288*4/1875 */
1265                 numerator = 4;
1266                 denominator = 1875;
1267                 break;
1268         case 57600*16:  /* 288*2/625 */
1269                 numerator = 2;
1270                 denominator = 625;
1271                 break;
1272         case 115200*16: /* 288*8/1250 */
1273                 numerator = 8;
1274                 denominator = 1250;
1275                 break;
1276         case 230400*16: /* 288*8/625 */
1277                 numerator = 8;
1278                 denominator = 625;
1279                 break;
1280         case 460800*16: /* 288*16/25 */
1281                 numerator = 16;
1282                 denominator = 625;
1283                 break;
1284         case 576000*16: /* 288*20/625 */
1285                 numerator = 20;
1286                 denominator = 625;
1287                 break;
1288         default:
1289                 return -ENOENT;
1290         }
1291 #endif
1292         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
1293         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
1294
1295         return 0;
1296 }
1297 static struct clk *clk_uart_src_parents[8] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1298
1299 static struct clk clk_uart01_src = {
1300         .name           = "uart01_src",
1301         .clksel_con     = CRU_CLKSEL8_CON,
1302         .clksel_parent_mask     = 7,
1303         .clksel_parent_shift    = 0,
1304         .parents        = clk_uart_src_parents,
1305 };
1306
1307 static struct clk clk_uart0_div = {
1308         .name           = "uart0_div",
1309         .parent         = &clk_uart01_src,
1310         .recalc         = clksel_recalc_div,
1311         .set_rate       = clksel_set_rate_div,
1312         .clksel_con     = CRU_CLKSEL8_CON,
1313         .clksel_mask    = 0x3F,
1314         .clksel_shift   = 3,
1315 };
1316
1317 static struct clk clk_uart0_frac_div = {
1318         .name           = "uart0_frac_div",
1319         .parent         = &clk_uart0_div,
1320         .recalc         = clksel_recalc_frac,
1321         .set_rate       = clk_uart_frac_div_set_rate,
1322         .clksel_con     = CRU_CLKSEL10_CON,
1323 };
1324
1325 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1326
1327 static struct clk clk_uart0 = {
1328         .name           = "uart0",
1329         .mode           = gate_mode,
1330         .set_rate       = clk_uart_set_rate,
1331         .gate_idx       = CLK_GATE_UART0,
1332         .clksel_con     = CRU_CLKSEL8_CON,
1333         .clksel_parent_mask     = 3,
1334         .clksel_parent_shift    = 9,
1335         .parents        = clk_uart0_parents,
1336 };
1337
1338 static struct clk clk_uart1_div = {
1339         .name           = "uart1_div",
1340         .parent         = &clk_uart01_src,
1341         .recalc         = clksel_recalc_div,
1342         .set_rate       = clksel_set_rate_div,
1343         .clksel_con     = CRU_CLKSEL8_CON,
1344         .clksel_mask    = 0x3F,
1345         .clksel_shift   = 14,
1346 };
1347
1348 static struct clk clk_uart1_frac_div = {
1349         .name           = "uart1_frac_div",
1350         .parent         = &clk_uart1_div,
1351         .recalc         = clksel_recalc_frac,
1352         .set_rate       = clk_uart_frac_div_set_rate,
1353         .clksel_con     = CRU_CLKSEL11_CON,
1354 };
1355
1356 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1357
1358 static struct clk clk_uart1 = {
1359         .name           = "uart1",
1360         .mode           = gate_mode,
1361         .set_rate       = clk_uart_set_rate,
1362         .gate_idx       = CLK_GATE_UART1,
1363         .clksel_con     = CRU_CLKSEL8_CON,
1364         .clksel_parent_mask     = 3,
1365         .clksel_parent_shift    = 20,
1366         .parents        = clk_uart1_parents,
1367 };
1368
1369 static struct clk clk_uart23_src = {
1370         .name           = "uart23_src",
1371         .clksel_con     = CRU_CLKSEL9_CON,
1372         .clksel_parent_mask     = 7,
1373         .clksel_parent_shift    = 0,
1374         .parents        = clk_uart_src_parents,
1375 };
1376
1377 static struct clk clk_uart2_div = {
1378         .name           = "uart2_div",
1379         .parent         = &clk_uart23_src,
1380         .recalc         = clksel_recalc_div,
1381         .set_rate       = clksel_set_rate_div,
1382         .clksel_con     = CRU_CLKSEL9_CON,
1383         .clksel_mask    = 0x3F,
1384         .clksel_shift   = 3,
1385 };
1386
1387 static struct clk clk_uart2_frac_div = {
1388         .name           = "uart2_frac_div",
1389         .parent         = &clk_uart2_div,
1390         .recalc         = clksel_recalc_frac,
1391         .set_rate       = clk_uart_frac_div_set_rate,
1392         .clksel_con     = CRU_CLKSEL12_CON,
1393 };
1394
1395 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1396
1397 static struct clk clk_uart2 = {
1398         .name           = "uart2",
1399         .mode           = gate_mode,
1400         .set_rate       = clk_uart_set_rate,
1401         .gate_idx       = CLK_GATE_UART2,
1402         .clksel_con     = CRU_CLKSEL9_CON,
1403         .clksel_parent_mask     = 3,
1404         .clksel_parent_shift    = 9,
1405         .parents        = clk_uart2_parents,
1406 };
1407
1408 static struct clk clk_uart3_div = {
1409         .name           = "uart3_div",
1410         .parent         = &clk_uart23_src,
1411         .recalc         = clksel_recalc_div,
1412         .set_rate       = clksel_set_rate_div,
1413         .clksel_con     = CRU_CLKSEL9_CON,
1414         .clksel_mask    = 0x3F,
1415         .clksel_shift   = 14,
1416 };
1417
1418 static struct clk clk_uart3_frac_div = {
1419         .name           = "uart3_frac_div",
1420         .parent         = &clk_uart3_div,
1421         .recalc         = clksel_recalc_frac,
1422         .set_rate       = clk_uart_frac_div_set_rate,
1423         .clksel_con     = CRU_CLKSEL13_CON,
1424 };
1425
1426 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1427
1428 static struct clk clk_uart3 = {
1429         .name           = "uart3",
1430         .mode           = gate_mode,
1431         .set_rate       = clk_uart_set_rate,
1432         .gate_idx       = CLK_GATE_UART3,
1433         .clksel_con     = CRU_CLKSEL9_CON,
1434         .clksel_parent_mask     = 3,
1435         .clksel_parent_shift    = 20,
1436         .parents        = clk_uart3_parents,
1437 };
1438
1439
1440 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1441
1442 static struct clk clk_hsadc_div = {
1443         .name           = "hsadc_div",
1444         .recalc         = clksel_recalc_div,
1445         .set_rate       = clksel_set_rate_div,
1446         .clksel_con     = CRU_CLKSEL14_CON,
1447         .clksel_mask    = 0xFF,
1448         .clksel_shift   = 10,
1449         .clksel_parent_mask     = 7,
1450         .clksel_parent_shift    = 7,
1451         .parents        = clk_hsadc_div_parents,
1452 };
1453
1454 static struct clk clk_hsadc_frac_div = {
1455         .name           = "hsadc_frac_div",
1456         .parent         = &clk_hsadc_div,
1457         .recalc         = clksel_recalc_frac,
1458         .clksel_con     = CRU_CLKSEL15_CON,
1459 };
1460
1461 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &xin27m };
1462
1463 static struct clk clk_demod = {
1464         .name           = "demod",
1465         .clksel_con     = CRU_CLKSEL14_CON,
1466         .clksel_parent_mask     = 3,
1467         .clksel_parent_shift    = 18,
1468         .parents        = clk_demod_parents,
1469 };
1470
1471 static struct clk gpsclk = {
1472         .name           = "gpsclk",
1473 };
1474
1475 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1476
1477 static struct clk clk_hsadc = {
1478         .name           = "hsadc",
1479         .mode           = gate_mode,
1480         .gate_idx       = CLK_GATE_HSADC,
1481         .clksel_con     = CRU_CLKSEL14_CON,
1482         .clksel_parent_mask     = 1,
1483         .clksel_parent_shift    = 21,
1484         .parents        = clk_hsadc_parents,
1485 };
1486
1487 static unsigned long div2_recalc(struct clk *clk)
1488 {
1489         return clk->parent->rate >> 1;
1490 }
1491
1492 static struct clk clk_hsadc_div2 = {
1493         .name           = "hsadc_div2",
1494         .parent         = &clk_demod,
1495         .recalc         = div2_recalc,
1496 };
1497
1498 static struct clk clk_hsadc_div2_inv = {
1499         .name           = "hsadc_div2_inv",
1500         .parent         = &clk_demod,
1501         .recalc         = div2_recalc,
1502 };
1503
1504 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1505
1506 static struct clk clk_hsadc_out = {
1507         .name           = "hsadc_out",
1508         .clksel_con     = CRU_CLKSEL14_CON,
1509         .clksel_parent_mask     = 1,
1510         .clksel_parent_shift    = 20,
1511         .parents        = clk_hsadc_out_parents,
1512 };
1513
1514
1515 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
1516
1517 static struct clk dclk_lcdc_div = {
1518         .name           = "dclk_lcdc_div",
1519         .recalc         = clksel_recalc_div,
1520         .set_rate       = clksel_set_rate_div,
1521         .clksel_con     = CRU_CLKSEL16_CON,
1522         .clksel_mask    = 0xFF,
1523         .clksel_shift   = 2,
1524         .clksel_parent_mask     = 3,
1525         .clksel_parent_shift    = 0,
1526         .parents        = dclk_lcdc_div_parents,
1527 };
1528
1529 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
1530
1531 static struct clk dclk_lcdc = {
1532         .name           = "dclk_lcdc",
1533         .mode           = gate_mode,
1534         .gate_idx       = CLK_GATE_DCLK_LCDC,
1535         .clksel_con     = CRU_CLKSEL16_CON,
1536         .clksel_parent_mask     = 1,
1537         .clksel_parent_shift    = 10,
1538         .parents        = dclk_lcdc_parents,
1539 };
1540
1541 static struct clk dclk_ebook = {
1542         .name           = "dclk_ebook",
1543         .mode           = gate_mode,
1544         .gate_idx       = CLK_GATE_DCLK_EBOOK,
1545         .recalc         = clksel_recalc_div,
1546         .set_rate       = clksel_set_rate_div,
1547         .clksel_con     = CRU_CLKSEL16_CON,
1548         .clksel_mask    = 0x1F,
1549         .clksel_shift   = 13,
1550         .clksel_parent_mask     = 3,
1551         .clksel_parent_shift    = 11,
1552         .parents        = dclk_lcdc_div_parents,
1553 };
1554
1555 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &general_pll_clk, &arm_pll_clk };
1556
1557 static struct clk aclk_lcdc = {
1558         .name           = "aclk_lcdc",
1559         .mode           = gate_mode,
1560         .gate_idx       = CLK_GATE_ACLK_LCDC,
1561         .recalc         = clksel_recalc_div,
1562         .set_rate       = clksel_set_rate_div,
1563         .clksel_con     = CRU_CLKSEL16_CON,
1564         .clksel_mask    = 0x1F,
1565         .clksel_shift   = 20,
1566         .clksel_parent_mask     = 3,
1567         .clksel_parent_shift    = 18,
1568         .parents        = aclk_lcdc_parents,
1569 };
1570
1571 static struct clk hclk_lcdc = {
1572         .name           = "hclk_lcdc",
1573         .mode           = gate_mode,
1574         .gate_idx       = CLK_GATE_HCLK_LCDC,
1575         .parent         = &aclk_lcdc,
1576         .clksel_con     = CRU_CLKSEL16_CON,
1577         .recalc         = clksel_recalc_shift,
1578         .set_rate       = clksel_set_rate_shift,
1579         .clksel_mask    = 3,
1580         .clksel_shift   = 25,
1581         .clksel_maxdiv  = 4,
1582 };
1583
1584 static struct clk *xpu_parents[4] = { &general_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1585
1586 static struct clk aclk_vepu = {
1587         .name           = "aclk_vepu",
1588         .mode           = gate_mode,
1589         .recalc         = clksel_recalc_div,
1590         .set_rate       = clksel_set_rate_div,
1591         .gate_idx       = CLK_GATE_ACLK_VEPU,
1592         .clksel_con     = CRU_CLKSEL17_CON,
1593         .clksel_mask    = 0x1F,
1594         .clksel_shift   = 2,
1595         .clksel_parent_mask     = 3,
1596         .clksel_parent_shift    = 0,
1597         .parents        = xpu_parents,
1598 };
1599
1600 static struct clk hclk_vepu = {
1601         .name           = "hclk_vepu",
1602         .parent         = &aclk_vepu,
1603         .mode           = gate_mode,
1604         .recalc         = clksel_recalc_shift,
1605         .set_rate       = clksel_set_rate_shift,
1606         .gate_idx       = CLK_GATE_HCLK_VEPU,
1607         .clksel_con     = CRU_CLKSEL17_CON,
1608         .clksel_mask    = 3,
1609         .clksel_shift   = 28,
1610         .clksel_maxdiv  = 4,
1611 };
1612
1613 static struct clk aclk_vdpu = {
1614         .name           = "aclk_vdpu",
1615         .parent         = &general_pll_clk,
1616         .mode           = gate_mode,
1617         .recalc         = clksel_recalc_div,
1618         .set_rate       = clksel_set_rate_div,
1619         .gate_idx       = CLK_GATE_ACLK_VDPU,
1620         .clksel_con     = CRU_CLKSEL17_CON,
1621         .clksel_mask    = 0x1F,
1622         .clksel_shift   = 9,
1623         .clksel_parent_mask     = 3,
1624         .clksel_parent_shift    = 7,
1625         .parents        = xpu_parents,
1626 };
1627
1628 static struct clk hclk_vdpu = {
1629         .name           = "hclk_vdpu",
1630         .parent         = &aclk_vdpu,
1631         .mode           = gate_mode,
1632         .recalc         = clksel_recalc_shift,
1633         .set_rate       = clksel_set_rate_shift,
1634         .gate_idx       = CLK_GATE_HCLK_VDPU,
1635         .clksel_con     = CRU_CLKSEL17_CON,
1636         .clksel_mask    = 3,
1637         .clksel_shift   = 30,
1638         .clksel_maxdiv  = 4,
1639 };
1640
1641 static struct clk clk_gpu = {
1642         .name           = "gpu",
1643         .mode           = gate_mode,
1644         .gate_idx       = CLK_GATE_GPU,
1645         .recalc         = clksel_recalc_div,
1646         .set_rate       = clksel_set_rate_div,
1647         .clksel_con     = CRU_CLKSEL17_CON,
1648         .clksel_mask    = 0x1F,
1649         .clksel_shift   = 16,
1650         .clksel_parent_mask     = 3,
1651         .clksel_parent_shift    = 14,
1652         .parents        = xpu_parents,
1653 };
1654
1655 static struct clk aclk_gpu = {
1656         .name           = "aclk_gpu",
1657         .mode           = gate_mode,
1658         .gate_idx       = CLK_GATE_ACLK_GPU,
1659         .recalc         = clksel_recalc_div,
1660         .set_rate       = clksel_set_rate_div,
1661         .clksel_con     = CRU_CLKSEL17_CON,
1662         .clksel_mask    = 0x1F,
1663         .clksel_shift   = 23,
1664         .clksel_parent_mask     = 3,
1665         .clksel_parent_shift    = 21,
1666         .parents        = xpu_parents,
1667 };
1668
1669
1670 static struct clk vip_clkin = {
1671         .name           = "vip_clkin",
1672 };
1673
1674 static struct clk *clk_vip_parents[4] = { &xin24m, &xin27m, &dclk_ebook };
1675
1676 static struct clk clk_vip_out = {
1677         .name           = "vip_out",
1678         .mode           = gate_mode,
1679         .gate_idx       = CLK_GATE_VIP_OUT,
1680         .clksel_con     = CRU_CLKSEL1_CON,
1681         .clksel_parent_mask     = 3,
1682         .clksel_parent_shift    = 7,
1683         .parents        = clk_vip_parents,
1684 };
1685
1686
1687 #define GATE_CLK(NAME,PARENT,ID) \
1688 static struct clk clk_##NAME = { \
1689         .name           = #NAME, \
1690         .parent         = &PARENT, \
1691         .mode           = gate_mode, \
1692         .gate_idx       = CLK_GATE_##ID, \
1693 }
1694
1695 GATE_CLK(i2c0, pclk_cpu, I2C0);
1696 GATE_CLK(i2c1, pclk_periph, I2C1);
1697 GATE_CLK(i2c2, pclk_periph, I2C2);
1698 GATE_CLK(i2c3, pclk_periph, I2C3);
1699
1700 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1701 GATE_CLK(gpio1, pclk_periph, GPIO1);
1702 GATE_CLK(gpio2, pclk_periph, GPIO2);
1703 GATE_CLK(gpio3, pclk_periph, GPIO3);
1704 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1705 GATE_CLK(gpio5, pclk_periph, GPIO5);
1706 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1707
1708 GATE_CLK(dma1, aclk_cpu, DMA1);
1709 GATE_CLK(dma2, aclk_periph, DMA2);
1710
1711 GATE_CLK(gic, aclk_cpu, GIC);
1712 GATE_CLK(intmem, aclk_cpu, INTMEM);
1713 GATE_CLK(rom, hclk_cpu, ROM);
1714 GATE_CLK(ddr_phy, aclk_cpu, DDR_PHY);
1715 GATE_CLK(ddr_reg, aclk_cpu, DDR_REG);
1716 GATE_CLK(ddr_cpu, aclk_cpu, DDR_CPU);
1717 GATE_CLK(efuse, pclk_cpu, EFUSE);
1718 GATE_CLK(tzpc, pclk_cpu, TZPC);
1719 GATE_CLK(debug, pclk_cpu, DEBUG);
1720 GATE_CLK(tpiu, pclk_cpu, TPIU);
1721 GATE_CLK(rtc, pclk_cpu, RTC);
1722 GATE_CLK(pmu, pclk_cpu, PMU);
1723 GATE_CLK(grf, pclk_cpu, GRF);
1724
1725 GATE_CLK(emem, hclk_periph, EMEM);
1726 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
1727 GATE_CLK(aclk_ddr_peri, aclk_periph, ACLK_DDR_PERI);
1728 GATE_CLK(aclk_cpu_peri, aclk_cpu, ACLK_CPU_PERI);
1729 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
1730 GATE_CLK(smc, pclk_periph, SMC);
1731 GATE_CLK(hclk_mac, hclk_periph, HCLK_MAC);
1732 GATE_CLK(mii_tx, hclk_periph, MII_TX);
1733 GATE_CLK(mii_rx, hclk_periph, MII_RX);
1734 GATE_CLK(hif, hclk_periph, HIF);
1735 GATE_CLK(nandc, hclk_periph, NANDC);
1736 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
1737 GATE_CLK(usbotg0, hclk_periph, USBOTG0);
1738 GATE_CLK(usbotg1, hclk_periph, USBOTG1);
1739 GATE_CLK(hclk_uhost, hclk_periph, HCLK_UHOST);
1740 GATE_CLK(pid_filter, hclk_periph, PID_FILTER);
1741
1742 GATE_CLK(vip_slave, hclk_lcdc, VIP_SLAVE);
1743 GATE_CLK(wdt, pclk_periph, WDT);
1744 GATE_CLK(pwm, pclk_periph, PWM);
1745 GATE_CLK(vip_bus, aclk_cpu, VIP_BUS);
1746 GATE_CLK(vip_matrix, clk_vip_bus, VIP_MATRIX);
1747 GATE_CLK(vip_input, vip_clkin, VIP_INPUT);
1748 GATE_CLK(jtag, aclk_cpu, JTAG);
1749
1750 GATE_CLK(aclk_ddr_lcdc, aclk_lcdc, ACLK_DDR_LCDC);
1751 GATE_CLK(aclk_ipp, aclk_lcdc, ACLK_IPP);
1752 GATE_CLK(hclk_ipp, hclk_lcdc, HCLK_IPP);
1753 GATE_CLK(hclk_ebook, hclk_lcdc, HCLK_EBOOK);
1754 GATE_CLK(aclk_disp_matrix, aclk_lcdc, ACLK_DISP_MATRIX);
1755 GATE_CLK(hclk_disp_matrix, hclk_lcdc, HCLK_DISP_MATRIX);
1756 GATE_CLK(aclk_ddr_vepu, aclk_vepu, ACLK_DDR_VEPU);
1757 GATE_CLK(aclk_ddr_vdpu, aclk_vdpu, ACLK_DDR_VDPU);
1758 GATE_CLK(aclk_ddr_gpu, aclk_gpu, ACLK_DDR_GPU);
1759 GATE_CLK(hclk_gpu, hclk_cpu, HCLK_GPU);
1760 GATE_CLK(hclk_cpu_vcodec, hclk_cpu, HCLK_CPU_VCODEC);
1761 GATE_CLK(hclk_cpu_display, hclk_cpu, HCLK_CPU_DISPLAY);
1762
1763 GATE_CLK(hclk_mmc0, hclk_periph, HCLK_MMC0);
1764 GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
1765 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
1766
1767
1768 static void __sramfunc pmu_set_power_domain_sram(enum pmu_power_domain pd, bool on)
1769 {
1770         if (on)
1771                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1772         else
1773                 writel(readl(RK29_PMU_BASE + PMU_PD_CON) |  (1 << pd), RK29_PMU_BASE + PMU_PD_CON);
1774         dsb();
1775
1776         while (pmu_power_domain_is_on(pd) != on)
1777                 ;
1778 }
1779
1780 static noinline void do_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1781 {
1782         static unsigned long save_sp;
1783
1784         DDR_SAVE_SP(save_sp);
1785         pmu_set_power_domain_sram(pd, on);
1786         DDR_RESTORE_SP(save_sp);
1787 }
1788
1789 void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
1790 {
1791         unsigned long flags;
1792
1793         mdelay(10);
1794         local_irq_save(flags);
1795         do_pmu_set_power_domain(pd, on);
1796         local_irq_restore(flags);
1797         mdelay(10);
1798 }
1799
1800 static int pd_vcodec_mode(struct clk *clk, int on)
1801 {
1802         if (on) {
1803                 u32 gate;
1804
1805                 gate = cru_clkgate3_con_mirror;
1806                 gate |= (1 << CLK_GATE_ACLK_DDR_VEPU % 32);
1807                 gate &= ~((1 << CLK_GATE_ACLK_VEPU % 32)
1808                         | (1 << CLK_GATE_HCLK_VEPU % 32)
1809                         | (1 << CLK_GATE_HCLK_CPU_VCODEC % 32));
1810                 cru_writel(gate, CRU_CLKGATE3_CON);
1811
1812                 pmu_set_power_domain(PD_VCODEC, true);
1813
1814                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1815         } else {
1816                 pmu_set_power_domain(PD_VCODEC, false);
1817         }
1818
1819         return 0;
1820 }
1821
1822 static struct clk pd_vcodec = {
1823         .name   = "pd_vcodec",
1824         .flags  = IS_PD,
1825         .mode   = pd_vcodec_mode,
1826 };
1827
1828 static int pd_display_mode(struct clk *clk, int on)
1829 {
1830         if (on) {
1831                 u32 gate, gate2;
1832
1833                 gate = cru_clkgate3_con_mirror;
1834                 gate |= (1 << CLK_GATE_ACLK_DDR_LCDC % 32);
1835                 gate &= ~((1 << CLK_GATE_HCLK_CPU_DISPLAY % 32)
1836                         | (1 << CLK_GATE_HCLK_DISP_MATRIX % 32)
1837                         | (1 << CLK_GATE_ACLK_DISP_MATRIX % 32)
1838                         | (1 << CLK_GATE_DCLK_EBOOK % 32)
1839                         | (1 << CLK_GATE_HCLK_EBOOK % 32)
1840                         | (1 << CLK_GATE_HCLK_IPP % 32)
1841                         | (1 << CLK_GATE_ACLK_IPP % 32)
1842                         | (1 << CLK_GATE_DCLK_LCDC % 32)
1843                         | (1 << CLK_GATE_HCLK_LCDC % 32)
1844                         | (1 << CLK_GATE_ACLK_LCDC % 32));
1845                 cru_writel(gate, CRU_CLKGATE3_CON);
1846
1847                 gate2 = cru_readl(CRU_CLKGATE2_CON);
1848                 gate = gate2;
1849                 gate &= ~((1 << CLK_GATE_VIP_OUT % 32)
1850                         | (1 << CLK_GATE_VIP_SLAVE % 32)
1851                         | (1 << CLK_GATE_VIP_MATRIX % 32)
1852                         | (1 << CLK_GATE_VIP_BUS % 32));
1853                 cru_writel(gate, CRU_CLKGATE2_CON);
1854
1855                 pmu_set_power_domain(PD_DISPLAY, true);
1856
1857                 cru_writel(gate2, CRU_CLKGATE2_CON);
1858                 cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
1859         } else {
1860                 pmu_set_power_domain(PD_DISPLAY, false);
1861         }
1862
1863         return 0;
1864 }
1865
1866 static struct clk pd_display = {
1867         .name   = "pd_display",
1868         .flags  = IS_PD,
1869         .mode   = pd_display_mode,
1870 };
1871
1872 static int pd_gpu_mode(struct clk *clk, int on)
1873 {
1874         if (on) {
1875                 pmu_set_power_domain(PD_GPU, true);
1876         } else {
1877                 pmu_set_power_domain(PD_GPU, false);
1878         }
1879
1880         return 0;
1881 }
1882
1883 static struct clk pd_gpu = {
1884         .name   = "pd_gpu",
1885         .flags  = IS_PD,
1886         .mode   = pd_gpu_mode,
1887 };
1888
1889
1890 #define CLK(dev, con, ck) \
1891         { \
1892                 .dev_id = dev, \
1893                 .con_id = con, \
1894                 .clk = ck, \
1895         }
1896
1897 #define CLK1(name) \
1898         { \
1899                 .dev_id = NULL, \
1900                 .con_id = #name, \
1901                 .clk = &clk_##name, \
1902         }
1903
1904 static struct clk_lookup clks[] = {
1905         CLK(NULL, "xin24m", &xin24m),
1906         CLK(NULL, "xin27m", &xin27m),
1907         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1908         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1909         CLK(NULL, "gpsclk", &gpsclk),
1910         CLK(NULL, "vip_clkin", &vip_clkin),
1911
1912         CLK1(12m),
1913         CLK(NULL, "arm_pll", &arm_pll_clk),
1914         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1915         CLK(NULL, "codec_pll", &codec_pll_clk),
1916         CLK(NULL, "general_pll", &general_pll_clk),
1917
1918         CLK1(core),
1919         CLK(NULL, "aclk_cpu", &aclk_cpu),
1920         CLK(NULL, "hclk_cpu", &hclk_cpu),
1921         CLK(NULL, "pclk_cpu", &pclk_cpu),
1922
1923         CLK(NULL, "aclk_periph", &aclk_periph),
1924         CLK(NULL, "hclk_periph", &hclk_periph),
1925         CLK(NULL, "pclk_periph", &pclk_periph),
1926
1927         CLK1(vip_out),
1928         CLK1(otgphy0),
1929         CLK1(otgphy1),
1930         CLK1(uhost),
1931         CLK1(mac_ref_div),
1932         CLK1(mac_ref),
1933
1934         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
1935         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
1936         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
1937         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
1938         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
1939         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
1940         CLK(NULL, "spdif_div", &clk_spdif_div),
1941         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
1942         CLK(NULL, "spdif", &clk_spdif),
1943
1944         CLK1(spi_src),
1945         CLK("rk29xx_spim.0", "spi", &clk_spi0),
1946         CLK("rk29xx_spim.1", "spi", &clk_spi1),
1947
1948         CLK1(saradc),
1949         CLK1(timer0),
1950         CLK1(timer1),
1951         CLK1(timer2),
1952         CLK1(timer3),
1953
1954         CLK1(mmc_src),
1955         CLK("rk29_sdmmc.0", "mmc", &clk_mmc0),
1956         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_mmc0),
1957         CLK("rk29_sdmmc.1", "mmc", &clk_mmc1),
1958         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_mmc1),
1959         CLK1(emmc),
1960         CLK1(hclk_emmc),
1961         CLK1(ddr),
1962
1963         CLK1(uart01_src),
1964         CLK("rk29_serial.0", "uart", &clk_uart0),
1965         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
1966         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
1967         CLK("rk29_serial.1", "uart", &clk_uart1),
1968         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
1969         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
1970
1971         CLK1(uart23_src),
1972         CLK("rk29_serial.2", "uart", &clk_uart2),
1973         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
1974         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
1975         CLK("rk29_serial.3", "uart", &clk_uart3),
1976         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
1977         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
1978
1979         CLK1(hsadc_div),
1980         CLK1(hsadc_frac_div),
1981         CLK1(demod),
1982         CLK1(hsadc),
1983         CLK1(hsadc_div2),
1984         CLK1(hsadc_div2_inv),
1985         CLK1(hsadc_out),
1986
1987         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
1988         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
1989         CLK(NULL, "dclk_ebook", &dclk_ebook),
1990         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
1991         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
1992
1993         CLK(NULL, "aclk_vepu", &aclk_vepu),
1994         CLK(NULL, "hclk_vepu", &hclk_vepu),
1995         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
1996         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
1997         CLK1(gpu),
1998         CLK(NULL, "aclk_gpu", &aclk_gpu),
1999
2000         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
2001         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
2002         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
2003         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
2004
2005         CLK1(gpio0),
2006         CLK1(gpio1),
2007         CLK1(gpio2),
2008         CLK1(gpio3),
2009         CLK1(gpio4),
2010         CLK1(gpio5),
2011         CLK1(gpio6),
2012
2013         CLK1(dma1),
2014         CLK1(dma2),
2015
2016         CLK1(gic),
2017         CLK1(intmem),
2018         CLK1(rom),
2019         CLK1(ddr_phy),
2020         CLK1(ddr_reg),
2021         CLK1(ddr_cpu),
2022         CLK1(efuse),
2023         CLK1(tzpc),
2024         CLK1(debug),
2025         CLK1(tpiu),
2026         CLK1(rtc),
2027         CLK1(pmu),
2028         CLK1(grf),
2029
2030         CLK1(emem),
2031         CLK1(hclk_usb_peri),
2032         CLK1(aclk_ddr_peri),
2033         CLK1(aclk_cpu_peri),
2034         CLK1(aclk_smc),
2035         CLK1(smc),
2036         CLK1(hclk_mac),
2037         CLK1(mii_tx),
2038         CLK1(mii_rx),
2039         CLK1(hif),
2040         CLK1(nandc),
2041         CLK1(hclk_hsadc),
2042         CLK1(usbotg0),
2043         CLK1(usbotg1),
2044         CLK1(hclk_uhost),
2045         CLK1(pid_filter),
2046
2047         CLK1(vip_slave),
2048         CLK1(wdt),
2049         CLK1(pwm),
2050         CLK1(vip_bus),
2051         CLK1(vip_matrix),
2052         CLK1(vip_input),
2053         CLK1(jtag),
2054
2055         CLK1(aclk_ddr_lcdc),
2056         CLK1(aclk_ipp),
2057         CLK1(hclk_ipp),
2058         CLK1(hclk_ebook),
2059         CLK1(aclk_disp_matrix),
2060         CLK1(hclk_disp_matrix),
2061         CLK1(aclk_ddr_vepu),
2062         CLK1(aclk_ddr_vdpu),
2063         CLK1(aclk_ddr_gpu),
2064         CLK1(hclk_gpu),
2065         CLK1(hclk_cpu_vcodec),
2066         CLK1(hclk_cpu_display),
2067
2068         CLK(NULL, "pd_vcodec", &pd_vcodec),
2069         CLK(NULL, "pd_display", &pd_display),
2070         CLK(NULL, "pd_gpu", &pd_gpu),
2071 };
2072
2073 static LIST_HEAD(clocks);
2074 static DEFINE_MUTEX(clocks_mutex);
2075 static DEFINE_SPINLOCK(clockfw_lock);
2076 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
2077 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
2078
2079 static int clk_enable_nolock(struct clk *clk)
2080 {
2081         int ret = 0;
2082
2083         if (clk->usecount == 0) {
2084                 if (clk->parent) {
2085                         ret = clk_enable_nolock(clk->parent);
2086                         if (ret)
2087                                 return ret;
2088                 }
2089
2090                 if (clk->mode) {
2091                         ret = clk->mode(clk, 1);
2092                         if (ret) {
2093                                 if (clk->parent)
2094                                         clk_disable_nolock(clk->parent);
2095                                 return ret;
2096                         }
2097                 }
2098                 pr_debug("%s enabled\n", clk->name);
2099         }
2100         clk->usecount++;
2101
2102         return ret;
2103 }
2104
2105 int clk_enable(struct clk *clk)
2106 {
2107         int ret = 0;
2108
2109         if (clk == NULL || IS_ERR(clk))
2110                 return -EINVAL;
2111
2112         LOCK();
2113         ret = clk_enable_nolock(clk);
2114         UNLOCK();
2115
2116         return ret;
2117 }
2118 EXPORT_SYMBOL(clk_enable);
2119
2120 static void clk_disable_nolock(struct clk *clk)
2121 {
2122         if (clk->usecount == 0) {
2123                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
2124                 WARN_ON(1);
2125                 return;
2126         }
2127
2128         if (--clk->usecount == 0) {
2129                 if (clk->mode)
2130                         clk->mode(clk, 0);
2131                 pr_debug("%s disabled\n", clk->name);
2132                 if (clk->parent)
2133                         clk_disable_nolock(clk->parent);
2134         }
2135 }
2136
2137 void clk_disable(struct clk *clk)
2138 {
2139         if (clk == NULL || IS_ERR(clk))
2140                 return;
2141
2142         LOCK();
2143         clk_disable_nolock(clk);
2144         UNLOCK();
2145 }
2146 EXPORT_SYMBOL(clk_disable);
2147
2148 unsigned long clk_get_rate(struct clk *clk)
2149 {
2150         if (clk == NULL || IS_ERR(clk))
2151                 return 0;
2152
2153         return clk->rate;
2154 }
2155 EXPORT_SYMBOL(clk_get_rate);
2156
2157 /*-------------------------------------------------------------------------
2158  * Optional clock functions defined in include/linux/clk.h
2159  *-------------------------------------------------------------------------*/
2160
2161 /* Given a clock and a rate apply a clock specific rounding function */
2162 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
2163 {
2164         if (clk->round_rate)
2165                 return clk->round_rate(clk, rate);
2166
2167         if (clk->flags & RATE_FIXED)
2168                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
2169
2170         return clk->rate;
2171 }
2172
2173 long clk_round_rate(struct clk *clk, unsigned long rate)
2174 {
2175         long ret = 0;
2176
2177         if (clk == NULL || IS_ERR(clk))
2178                 return ret;
2179
2180         LOCK();
2181         ret = clk_round_rate_nolock(clk, rate);
2182         UNLOCK();
2183
2184         return ret;
2185 }
2186 EXPORT_SYMBOL(clk_round_rate);
2187
2188 static void __clk_recalc(struct clk *clk)
2189 {
2190         if (unlikely(clk->flags & RATE_FIXED))
2191                 return;
2192         if (clk->recalc)
2193                 clk->rate = clk->recalc(clk);
2194         else if (clk->parent)
2195                 clk->rate = clk->parent->rate;
2196         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
2197 }
2198
2199 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
2200 {
2201         int ret;
2202
2203         if (rate == clk->rate)
2204                 return 0;
2205
2206         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
2207
2208         if (clk->flags & CONFIG_PARTICIPANT)
2209                 return -EINVAL;
2210
2211         if (!clk->set_rate)
2212                 return -EINVAL;
2213
2214         ret = clk->set_rate(clk, rate);
2215
2216         if (ret == 0) {
2217                 __clk_recalc(clk);
2218                 __propagate_rate(clk);
2219         }
2220
2221         return ret;
2222 }
2223
2224 /* Set the clock rate for a clock source */
2225 int clk_set_rate(struct clk *clk, unsigned long rate)
2226 {
2227         int ret = -EINVAL;
2228
2229         if (clk == NULL || IS_ERR(clk))
2230                 return ret;
2231
2232         LOCK();
2233         ret = clk_set_rate_nolock(clk, rate);
2234         UNLOCK();
2235
2236         return ret;
2237 }
2238 EXPORT_SYMBOL(clk_set_rate);
2239
2240 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
2241 {
2242         int ret;
2243         int enabled = clk->usecount > 0;
2244         struct clk *old_parent = clk->parent;
2245
2246         if (clk->parent == parent)
2247                 return 0;
2248
2249         /* if clk is already enabled, enable new parent first and disable old parent later. */
2250         if (enabled)
2251                 clk_enable_nolock(parent);
2252
2253         if (clk->set_parent)
2254                 ret = clk->set_parent(clk, parent);
2255         else
2256                 ret = clksel_set_parent(clk, parent);
2257
2258         if (ret == 0) {
2259                 /* OK */
2260                 __clk_reparent(clk, parent);
2261                 __clk_recalc(clk);
2262                 __propagate_rate(clk);
2263                 if (enabled)
2264                         clk_disable_nolock(old_parent);
2265         } else {
2266                 if (enabled)
2267                         clk_disable_nolock(parent);
2268         }
2269
2270         return ret;
2271 }
2272
2273 int clk_set_parent(struct clk *clk, struct clk *parent)
2274 {
2275         int ret = -EINVAL;
2276
2277         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
2278                 return ret;
2279
2280         if (clk->set_parent == NULL && clk->parents == NULL)
2281                 return ret;
2282
2283         LOCK();
2284         if (clk->usecount == 0)
2285                 ret = clk_set_parent_nolock(clk, parent);
2286         else
2287                 ret = -EBUSY;
2288         UNLOCK();
2289
2290         return ret;
2291 }
2292 EXPORT_SYMBOL(clk_set_parent);
2293
2294 struct clk *clk_get_parent(struct clk *clk)
2295 {
2296         return clk->parent;
2297 }
2298 EXPORT_SYMBOL(clk_get_parent);
2299
2300 static void __clk_reparent(struct clk *child, struct clk *parent)
2301 {
2302         if (child->parent == parent)
2303                 return;
2304         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
2305
2306         list_del_init(&child->sibling);
2307         if (parent)
2308                 list_add(&child->sibling, &parent->children);
2309         child->parent = parent;
2310 }
2311
2312 /* Propagate rate to children */
2313 static void __propagate_rate(struct clk *tclk)
2314 {
2315         struct clk *clkp;
2316
2317         list_for_each_entry(clkp, &tclk->children, sibling) {
2318                 __clk_recalc(clkp);
2319                 __propagate_rate(clkp);
2320         }
2321 }
2322
2323 static LIST_HEAD(root_clks);
2324
2325 /**
2326  * recalculate_root_clocks - recalculate and propagate all root clocks
2327  *
2328  * Recalculates all root clocks (clocks with no parent), which if the
2329  * clock's .recalc is set correctly, should also propagate their rates.
2330  * Called at init.
2331  */
2332 static void clk_recalculate_root_clocks_nolock(void)
2333 {
2334         struct clk *clkp;
2335
2336         list_for_each_entry(clkp, &root_clks, sibling) {
2337                 __clk_recalc(clkp);
2338                 __propagate_rate(clkp);
2339         }
2340 }
2341
2342 void clk_recalculate_root_clocks(void)
2343 {
2344         LOCK();
2345         clk_recalculate_root_clocks_nolock();
2346         UNLOCK();
2347 }
2348
2349
2350 /**
2351  * clk_preinit - initialize any fields in the struct clk before clk init
2352  * @clk: struct clk * to initialize
2353  *
2354  * Initialize any struct clk fields needed before normal clk initialization
2355  * can run.  No return value.
2356  */
2357 static void clk_preinit(struct clk *clk)
2358 {
2359         INIT_LIST_HEAD(&clk->children);
2360 }
2361
2362 static int clk_register(struct clk *clk)
2363 {
2364         if (clk == NULL || IS_ERR(clk))
2365                 return -EINVAL;
2366
2367         /*
2368          * trap out already registered clocks
2369          */
2370         if (clk->node.next || clk->node.prev)
2371                 return 0;
2372
2373         mutex_lock(&clocks_mutex);
2374
2375         if (clk->get_parent)
2376                 clk->parent = clk->get_parent(clk);
2377         else if (clk->parents)
2378                 clk->parent = clksel_get_parent(clk);
2379
2380         if (clk->parent)
2381                 list_add(&clk->sibling, &clk->parent->children);
2382         else
2383                 list_add(&clk->sibling, &root_clks);
2384
2385         list_add(&clk->node, &clocks);
2386
2387         mutex_unlock(&clocks_mutex);
2388
2389         return 0;
2390 }
2391
2392 static unsigned int __initdata armclk = 300 * MHZ;
2393
2394 /*
2395  * You can override arm_clk rate with armclk= cmdline option.
2396  */
2397 static int __init armclk_setup(char *str)
2398 {
2399         get_option(&str, &armclk);
2400
2401         if (!armclk)
2402                 return 0;
2403
2404         if (armclk < 10000)
2405                 armclk *= MHZ;
2406
2407         clk_set_rate_nolock(&arm_pll_clk, armclk);
2408         return 0;
2409 }
2410 early_param("armclk", armclk_setup);
2411
2412 static void __init rk29_clock_common_init(unsigned long ppll_rate)
2413 {
2414                 unsigned long aclk_p,hclk_p,pclk_p;
2415                 struct clk *aclk_vepu_parent,*aclk_vdpu_parent,*aclk_gpu_parent;
2416                 unsigned long aclk_vepu_rate,hclk_vepu_rate,aclk_ddr_vepu_rate,aclk_gpu_rate;
2417                 unsigned long codec_pll=552 * MHZ;
2418                 /* general pll */
2419                 switch(ppll_rate)
2420                 {
2421                         case 96* MHZ:
2422                                 aclk_p=96*MHZ;
2423                                 hclk_p=48*MHZ;
2424                                 pclk_p=24*MHZ;
2425                                 aclk_gpu_parent=aclk_vdpu_parent=aclk_vepu_parent=&codec_pll_clk;
2426                                 aclk_gpu_rate=aclk_ddr_vepu_rate=aclk_vepu_rate=codec_pll/2;
2427                                 hclk_vepu_rate=codec_pll/4;
2428                                 break;
2429                         case 144* MHZ:
2430                                 aclk_p=144*MHZ;
2431                                 hclk_p=72*MHZ;
2432                                 pclk_p=36*MHZ;
2433                                 aclk_gpu_parent=aclk_vdpu_parent=aclk_vepu_parent=&codec_pll_clk;
2434                                 aclk_gpu_rate=aclk_ddr_vepu_rate=aclk_vepu_rate=codec_pll/2;
2435                                 hclk_vepu_rate=codec_pll/4;
2436                                 break;
2437                         case 288* MHZ:
2438                         case 300* MHZ:
2439                                 aclk_p=ppll_rate/2;
2440                                 hclk_p=ppll_rate/2;
2441                                 pclk_p=ppll_rate/8;
2442                                 aclk_gpu_parent=aclk_vdpu_parent=aclk_vepu_parent=&general_pll_clk;
2443                                 aclk_gpu_rate=aclk_ddr_vepu_rate=aclk_vepu_rate=ppll_rate;
2444                                 hclk_vepu_rate=ppll_rate/2;
2445                                 break;
2446                         default:
2447                                 ppll_rate=288* MHZ;
2448                                 aclk_p=ppll_rate/2;
2449                                 hclk_p=ppll_rate/2;
2450                                 pclk_p=ppll_rate/8;
2451                                 aclk_gpu_parent=aclk_vdpu_parent=aclk_vepu_parent=&general_pll_clk;
2452                                 aclk_gpu_rate=aclk_ddr_vepu_rate=aclk_vepu_rate=ppll_rate;
2453                                 hclk_vepu_rate=ppll_rate/2;
2454                                 break;
2455                 }
2456                 clk_set_rate_nolock(&general_pll_clk,ppll_rate);// 288
2457                 clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2458                 clk_set_rate_nolock(&aclk_periph, aclk_p);//144
2459                 clk_set_rate_nolock(&hclk_periph, hclk_p);// 144
2460                 clk_set_rate_nolock(&pclk_periph, pclk_p);// 36
2461                 clk_set_parent_nolock(&clk_uhost, &general_pll_clk);
2462                 clk_set_rate_nolock(&clk_uhost, 48 * MHZ);
2463                 clk_set_parent_nolock(&clk_i2s0_div, &general_pll_clk);
2464                 clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
2465                 clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
2466                 clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
2467                 clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
2468                 clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
2469                 clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
2470                 clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
2471                 clk_set_parent_nolock(&aclk_lcdc, &general_pll_clk);
2472                 clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
2473                 clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
2474                 /* codec pll */
2475                 clk_set_rate_nolock(&codec_pll_clk, codec_pll);
2476                 clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
2477                 /* arm pll */
2478                 clk_set_rate_nolock(&arm_pll_clk, armclk);
2479                 clk_set_parent_nolock(&clk_mac_ref_div, &arm_pll_clk);
2480                 /*you can choose clk parent form codec pll or periph pll for following logic*/
2481                 clk_set_parent_nolock(&aclk_vepu, aclk_vepu_parent);
2482                 clk_set_rate_nolock(&aclk_vepu, aclk_vepu_rate);
2483                 clk_set_rate_nolock(&clk_aclk_ddr_vepu,aclk_ddr_vepu_rate);
2484                 clk_set_rate_nolock(&hclk_vepu, hclk_vepu_rate);
2485                 clk_set_parent_nolock(&aclk_vdpu, aclk_vdpu_parent);
2486                 clk_set_parent_nolock(&aclk_gpu, aclk_gpu_parent);
2487                 clk_set_rate_nolock(&aclk_gpu,aclk_gpu_rate);
2488 }
2489 static void __init clk_enable_init_clocks(void)
2490 {
2491         clk_enable_nolock(&hclk_cpu);
2492         clk_enable_nolock(&pclk_cpu);
2493         clk_enable_nolock(&hclk_periph);
2494         clk_enable_nolock(&pclk_periph);
2495         clk_enable_nolock(&clk_nandc);
2496         clk_enable_nolock(&clk_aclk_cpu_peri);
2497         clk_enable_nolock(&clk_aclk_ddr_peri);
2498         clk_enable_nolock(&clk_grf);
2499         clk_enable_nolock(&clk_pmu);
2500         clk_enable_nolock(&clk_ddr_cpu);
2501         clk_enable_nolock(&clk_ddr_reg);
2502         clk_enable_nolock(&clk_ddr_phy);
2503         clk_enable_nolock(&clk_gic);
2504         clk_enable_nolock(&clk_dma2);
2505         clk_enable_nolock(&clk_dma1);
2506         clk_enable_nolock(&clk_emem);
2507         clk_enable_nolock(&clk_intmem);
2508         clk_enable_nolock(&clk_ddr);
2509         clk_enable_nolock(&clk_debug);
2510         clk_enable_nolock(&clk_jtag);
2511         clk_enable_nolock(&clk_uart1);
2512 }
2513
2514 static int __init clk_disable_unused(void)
2515 {
2516         struct clk *ck;
2517
2518         list_for_each_entry(ck, &clocks, node) {
2519                 if (ck->usecount > 0 || ck->mode == NULL || (ck->flags & IS_PD))
2520                         continue;
2521
2522                 LOCK();
2523                 clk_enable_nolock(ck);
2524                 clk_disable_nolock(ck);
2525                 UNLOCK();
2526         }
2527
2528         return 0;
2529 }
2530
2531 void __init rk29_clock_init(unsigned long ppll_rate)
2532 {
2533         struct clk_lookup *lk;
2534
2535         cru_clkgate3_con_mirror = cru_readl(CRU_CLKGATE3_CON);
2536         cru_softrst0_con_mirror = cru_readl(CRU_SOFTRST0_CON);
2537
2538         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
2539                 clk_preinit(lk->clk);
2540
2541         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
2542                 clkdev_add(lk);
2543                 clk_register(lk->clk);
2544         }
2545
2546         clk_recalculate_root_clocks_nolock();
2547
2548         /*
2549          * Only enable those clocks we will need, let the drivers
2550          * enable other clocks as necessary
2551          */
2552         clk_enable_init_clocks();
2553
2554         /*
2555          * Disable any unused clocks left on by the bootloader
2556          */
2557         clk_disable_unused();
2558
2559         rk29_clock_common_init(ppll_rate);
2560
2561         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
2562                arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
2563                aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
2564 }
2565
2566 #ifdef CONFIG_PROC_FS
2567 #include <linux/proc_fs.h>
2568 #include <linux/seq_file.h>
2569
2570 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
2571 {
2572         struct clk* ck;
2573         int i;
2574         unsigned long rate = clk->rate;
2575
2576         for (i = 0; i < deep; i++)
2577                 seq_printf(s, "    ");
2578
2579         seq_printf(s, "%-9s ", clk->name);
2580
2581         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
2582                 u32 reg;
2583                 int idx = clk->gate_idx;
2584                 u32 v;
2585
2586                 reg = CRU_CLKGATE0_CON;
2587                 reg += (idx >> 5) << 2;
2588                 idx &= 0x1F;
2589
2590                 if (reg == CRU_CLKGATE3_CON)
2591                         v = cru_clkgate3_con_mirror & (1 << idx);
2592                 else
2593                         v = cru_readl(reg) & (1 << idx);
2594
2595                 seq_printf(s, "%s ", v ? "off" : "on ");
2596         }
2597
2598         if (clk == &arm_pll_clk) {
2599                 switch (cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) {
2600                 case CRU_CPU_MODE_SLOW:   seq_printf(s, "slow   "); break;
2601                 case CRU_CPU_MODE_NORMAL: seq_printf(s, "normal "); break;
2602                 case CRU_CPU_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2603                 }
2604                 if (cru_readl(CRU_APLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2605         } else if (clk == &ddr_pll_clk) {
2606                 switch (cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) {
2607                 case CRU_DDR_MODE_SLOW:   seq_printf(s, "slow   "); break;
2608                 case CRU_DDR_MODE_NORMAL: seq_printf(s, "normal "); break;
2609                 case CRU_DDR_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2610                 }
2611                 if (cru_readl(CRU_DPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2612         } else if (clk == &codec_pll_clk) {
2613                 switch (cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) {
2614                 case CRU_CODEC_MODE_SLOW:   seq_printf(s, "slow   "); break;
2615                 case CRU_CODEC_MODE_NORMAL: seq_printf(s, "normal "); break;
2616                 case CRU_CODEC_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2617                 }
2618                 if (cru_readl(CRU_CPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2619         } else if (clk == &general_pll_clk) {
2620                 switch (cru_readl(CRU_MODE_CON) & CRU_GENERAL_MODE_MASK) {
2621                 case CRU_GENERAL_MODE_SLOW:   seq_printf(s, "slow   "); break;
2622                 case CRU_GENERAL_MODE_NORMAL: seq_printf(s, "normal "); break;
2623                 case CRU_GENERAL_MODE_SLOW27: seq_printf(s, "slow27 "); break;
2624                 }
2625                 if (cru_readl(CRU_GPLL_CON) & PLL_BYPASS) seq_printf(s, "bypass ");
2626         }
2627
2628         if (rate >= MHZ) {
2629                 if (rate % MHZ)
2630                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
2631                 else
2632                         seq_printf(s, "%ld MHz", rate / MHZ);
2633         } else if (rate >= KHZ) {
2634                 if (rate % KHZ)
2635                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
2636                 else
2637                         seq_printf(s, "%ld KHz", rate / KHZ);
2638         } else {
2639                 seq_printf(s, "%ld Hz", rate);
2640         }
2641
2642         seq_printf(s, " usecount = %d", clk->usecount);
2643
2644         seq_printf(s, " parent = %s\n", clk->parent ? clk->parent->name : "NULL");
2645
2646         list_for_each_entry(ck, &clocks, node) {
2647                 if (ck->parent == clk)
2648                         dump_clock(s, ck, deep + 1);
2649         }
2650 }
2651
2652 static int proc_clk_show(struct seq_file *s, void *v)
2653 {
2654         struct clk* clk;
2655
2656         mutex_lock(&clocks_mutex);
2657         list_for_each_entry(clk, &clocks, node) {
2658                 if (!clk->parent)
2659                         dump_clock(s, clk, 0);
2660         }
2661         mutex_unlock(&clocks_mutex);
2662
2663         seq_printf(s, "\nCRU Registers:\n");
2664         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
2665         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
2666         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
2667         seq_printf(s, "GPLL     : 0x%08x\n", cru_readl(CRU_GPLL_CON));
2668         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
2669         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
2670         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
2671         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
2672         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
2673         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
2674         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
2675         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
2676         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
2677         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
2678         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
2679         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
2680         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
2681         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
2682         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
2683         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
2684         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
2685         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
2686         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
2687         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
2688         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
2689         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
2690         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
2691         seq_printf(s, "CLKGATE3M: 0x%08x\n", cru_clkgate3_con_mirror);
2692         seq_printf(s, "SOFTRST0 : 0x%08x\n", cru_readl(CRU_SOFTRST0_CON));
2693         seq_printf(s, "SOFTRST0M: 0x%08x\n", cru_softrst0_con_mirror);
2694         seq_printf(s, "SOFTRST1 : 0x%08x\n", cru_readl(CRU_SOFTRST1_CON));
2695         seq_printf(s, "SOFTRST2 : 0x%08x\n", cru_readl(CRU_SOFTRST2_CON));
2696
2697         seq_printf(s, "\nPMU Registers:\n");
2698         seq_printf(s, "WAKEUP_EN0 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN0));
2699         seq_printf(s, "WAKEUP_EN1 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN1));
2700         seq_printf(s, "WAKEUP_EN2 : 0x%08x\n", pmu_readl(PMU_WAKEUP_EN2));
2701         seq_printf(s, "PD_CON     : 0x%08x\n", pmu_readl(PMU_PD_CON));
2702         seq_printf(s, "MISC_CON   : 0x%08x\n", pmu_readl(PMU_MISC_CON));
2703         seq_printf(s, "PLL_CNT    : 0x%08x\n", pmu_readl(PMU_PLL_CNT));
2704         seq_printf(s, "PD_ST      : 0x%08x\n", pmu_readl(PMU_PD_ST));
2705         seq_printf(s, "INT_ST     : 0x%08x\n", pmu_readl(PMU_INT_ST));
2706
2707         return 0;
2708 }
2709
2710 static int proc_clk_open(struct inode *inode, struct file *file)
2711 {
2712         return single_open(file, proc_clk_show, NULL);
2713 }
2714
2715 static const struct file_operations proc_clk_fops = {
2716         .open           = proc_clk_open,
2717         .read           = seq_read,
2718         .llseek         = seq_lseek,
2719         .release        = single_release,
2720 };
2721
2722 static int __init clk_proc_init(void)
2723 {
2724         proc_create("clocks", 0, NULL, &proc_clk_fops);
2725         return 0;
2726
2727 }
2728 late_initcall(clk_proc_init);
2729 #endif /* CONFIG_PROC_FS */
2730