arch/arm/mach-rk29/clock.c

   1 /* arch/arm/mach-rk29/clock.c
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 //#define DEBUG
  17 #define pr_fmt(fmt) "clock: %s: " fmt, __func__
  18
  19 #include <linux/clk.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <asm/clkdev.h>
  31 #include <mach/rk29_iomap.h>
  32 #include <mach/cru.h>
  33
  34 /* CRU PLL CON */
  35 #define PLL_HIGH_BAND   (0x01 << 16)
  36 #define PLL_LOW_BAND    (0x00 << 16)
  37 #define PLL_PD          (0x01 << 15)
  38
  39 #define PLL_CLKR(i)     ((((i) - 1) & 0x1f) << 10)
  40 #define PLL_NR(v)       ((((v) >> 10) & 0x1f) + 1)
  41
  42 #define PLL_CLKF(i)     ((((i) - 1) & 0x7f) << 3)
  43 #define PLL_NF(v)       ((((v) >> 3) & 0x7f) + 1)
  44 #define PLL_NF2(v)      (((((v) >> 3) & 0x7f) + 1) << 1)
  45
  46 #define PLL_CLKOD(i)    (((i) & 0x03) << 1)
  47 #define PLL_NO_1        PLL_CLKOD(0)
  48 #define PLL_NO_2        PLL_CLKOD(1)
  49 #define PLL_NO_4        PLL_CLKOD(2)
  50 #define PLL_NO_8        PLL_CLKOD(3)
  51 #define PLL_NO_SHIFT(v) (((v) >> 1) & 0x03)
  52
  53 #define PLL_BYPASS      (0x01)
  54
  55 /* CRU MODE CON */
  56 #define CRU_CPU_MODE_MASK       (0x03u << 0)
  57 #define CRU_CPU_MODE_SLOW       (0x00u << 0)
  58 #define CRU_CPU_MODE_NORMAL     (0x01u << 0)
  59 #define CRU_CPU_MODE_DSLOW      (0x02u << 0)
  60
  61 #define CRU_PERIPH_MODE_MASK    (0x03u << 2)
  62 #define CRU_PERIPH_MODE_SLOW    (0x00u << 2)
  63 #define CRU_PERIPH_MODE_NORMAL  (0x01u << 2)
  64 #define CRU_PERIPH_MODE_DSLOW   (0x02u << 2)
  65
  66 #define CRU_CODEC_MODE_MASK     (0x03u << 4)
  67 #define CRU_CODEC_MODE_SLOW     (0x00u << 4)
  68 #define CRU_CODEC_MODE_NORMAL   (0x01u << 4)
  69 #define CRU_CODEC_MODE_DSLOW    (0x02u << 4)
  70
  71 #define CRU_DDR_MODE_MASK       (0x03u << 6)
  72 #define CRU_DDR_MODE_SLOW       (0x00u << 6)
  73 #define CRU_DDR_MODE_NORMAL     (0x01u << 6)
  74 #define CRU_DDR_MODE_DSLOW      (0x02u << 6)
  75
  76 /* Clock flags */
  77 /* bit 0 is free */
  78 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
  79 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
  80 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
  81
  82 #define cru_readl(offset)       readl(RK29_CRU_BASE + offset)
  83 #define cru_writel(v, offset)   writel(v, RK29_CRU_BASE + offset)
  84 #define cru_writel_force(v, offset)     do { u32 _v = v; u32 _count = 5; do { cru_writel(_v, offset); } while (cru_readl(offset) != _v && _count--); } while (0)        /* huangtao: when write CRU_xPLL_CON, first time may failed, so try again. unknown why. */
  85
  86 #define regfile_readl(offset)   readl(RK29_GRF_BASE + offset)
  87
  88 struct clk {
  89         struct list_head        node;
  90         const char              *name;
  91         struct clk              *parent;
  92         struct list_head        children;
  93         struct list_head        sibling;        /* node for children */
  94         unsigned long           rate;
  95         u32                     flags;
  96         int                     (*mode)(struct clk *clk, int on);
  97         unsigned long           (*recalc)(struct clk *);        /* if null, follow parent */
  98         int                     (*set_rate)(struct clk *, unsigned long);
  99         long                    (*round_rate)(struct clk *, unsigned long);
 100         struct clk*             (*get_parent)(struct clk *);    /* get clk's parent from the hardware. default is clksel_get_parent if parents present */
 101         int                     (*set_parent)(struct clk *, struct clk *);      /* default is clksel_set_parent if parents present */
 102         s32                     usecount;
 103         u8                      gate_idx;
 104         u8                      pll_idx;
 105         u8                      clksel_con;
 106         u8                      clksel_mask;
 107         u8                      clksel_shift;
 108         u8                      clksel_maxdiv;
 109         u8                      clksel_parent_mask;
 110         u8                      clksel_parent_shift;
 111         struct clk              **parents;
 112 };
 113
 114 static int clk_enable_nolock(struct clk *clk);
 115 static void clk_disable_nolock(struct clk *clk);
 116 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate);
 117 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent);
 118 static void __clk_reparent(struct clk *child, struct clk *parent);
 119 static void __propagate_rate(struct clk *tclk);
 120
 121 static unsigned long clksel_recalc_div(struct clk *clk)
 122 {
 123         u32 div = ((cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask) + 1;
 124         unsigned long rate = clk->parent->rate / div;
 125         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 126         return rate;
 127 }
 128
 129 static unsigned long clksel_recalc_shift(struct clk *clk)
 130 {
 131         u32 shift = (cru_readl(clk->clksel_con) >> clk->clksel_shift) & clk->clksel_mask;
 132         unsigned long rate = clk->parent->rate >> shift;
 133         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 134         return rate;
 135 }
 136
 137 static unsigned long clksel_recalc_frac(struct clk *clk)
 138 {
 139         unsigned long rate;
 140         u64 rate64;
 141         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 142         if (r == 0) // FPGA ?
 143                 return clk->parent->rate;
 144         numerator = r >> 16;
 145         denominator = r & 0xFFFF;
 146         rate64 = (u64)clk->parent->rate * numerator;
 147         do_div(rate64, denominator);
 148         rate = rate64;
 149         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 150         return rate;
 151 }
 152
 153 static int clksel_set_rate_div(struct clk *clk, unsigned long rate)
 154 {
 155         u32 div;
 156
 157         for (div = 0; div <= clk->clksel_mask; div++) {
 158                 u32 new_rate = clk->parent->rate / (div + 1);
 159                 if (new_rate <= rate) {
 160                         u32 v = cru_readl(clk->clksel_con);
 161                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 162                         v |= div << clk->clksel_shift;
 163                         cru_writel(v, clk->clksel_con);
 164                         clk->rate = new_rate;
 165                         pr_debug("clksel_set_rate_div for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 166                         return 0;
 167                 }
 168         }
 169
 170         return -ENOENT;
 171 }
 172
 173 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 174 {
 175         u32 shift;
 176
 177         for (shift = 0; (1 << shift) <= clk->clksel_maxdiv; shift++) {
 178                 u32 new_rate = clk->parent->rate >> shift;
 179                 if (new_rate <= rate) {
 180                         u32 v = cru_readl(clk->clksel_con);
 181                         v &= ~((u32) clk->clksel_mask << clk->clksel_shift);
 182                         v |= shift << clk->clksel_shift;
 183                         cru_writel(v, clk->clksel_con);
 184                         clk->rate = new_rate;
 185                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 186                         return 0;
 187                 }
 188         }
 189
 190         return -ENOENT;
 191 }
 192
 193 static struct clk* clksel_get_parent(struct clk *clk)
 194 {
 195         return clk->parents[(cru_readl(clk->clksel_con) >> clk->clksel_parent_shift) & clk->clksel_parent_mask];
 196 }
 197
 198 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 199 {
 200         struct clk **p = clk->parents;
 201         u32 i;
 202
 203         if (unlikely(!p))
 204                 return -EINVAL;
 205         for (i = 0; (i <= clk->clksel_parent_mask) && *p; i++, p++) {
 206                 u32 v;
 207                 if (*p != parent)
 208                         continue;
 209                 v = cru_readl(clk->clksel_con);
 210                 v &= ~((u32) clk->clksel_parent_mask << clk->clksel_parent_shift);
 211                 v |= (i << clk->clksel_parent_shift);
 212                 cru_writel(v, clk->clksel_con);
 213                 return 0;
 214         }
 215         return -EINVAL;
 216 }
 217
 218 static int gate_mode(struct clk *clk, int on)
 219 {
 220         u32 reg;
 221         int idx = clk->gate_idx;
 222         u32 v;
 223
 224         if (idx >= CLK_GATE_MAX)
 225                 return -EINVAL;
 226
 227         reg = CRU_CLKGATE0_CON;
 228         reg += (idx >> 5) << 2;
 229         idx &= 0x1F;
 230
 231         v = cru_readl(reg);
 232         if (on) {
 233                 v &= ~(1 << idx);       // clear bit
 234         } else {
 235                 v |= (1 << idx);        // set bit
 236         }
 237         cru_writel(v, reg);
 238
 239         return 0;
 240 }
 241
 242 static struct clk xin24m = {
 243         .name           = "xin24m",
 244         .rate           = 24000000,
 245         .flags          = RATE_FIXED,
 246 };
 247
 248 static struct clk clk_12m = {
 249         .name           = "clk_12m",
 250         .rate           = 12000000,
 251         .parent         = &xin24m,
 252         .flags          = RATE_FIXED,
 253 };
 254
 255 static struct clk extclk = {
 256         .name           = "extclk",
 257         .rate           = 27000000,
 258         .flags          = RATE_FIXED,
 259 };
 260
 261 static struct clk otgphy0_clkin = {
 262         .name           = "otgphy0_clkin",
 263         .rate           = 480000000,
 264         .flags          = RATE_FIXED,
 265 };
 266
 267 static struct clk otgphy1_clkin = {
 268         .name           = "otgphy1_clkin",
 269         .rate           = 480000000,
 270         .flags          = RATE_FIXED,
 271 };
 272
 273
 274 static void delay_500ns(void)
 275 {
 276         int delay = 2000;
 277         while (delay--)
 278            barrier();
 279 }
 280
 281
 282 #define PERIPH_PLL_IDX     0
 283 #define CODEC_PLL_IDX      1
 284 #define ARM_PLL_IDX        2
 285 #define DDR_PLL_IDX        3
 286
 287 #define GRF_SOC_CON0       0xbc
 288 static void pll_wait_lock(int pll_idx, int delay)
 289 {
 290         u32 bit = 0x2000000u << pll_idx;
 291         while (delay > 0) {
 292                 if (regfile_readl(GRF_SOC_CON0) & bit)
 293                         break;
 294                 delay--;
 295         }
 296         if (delay == 0) {
 297                 pr_warning("wait pll bit 0x%x time out!\n", bit);
 298         }
 299 }
 300
 301
 302 static unsigned long arm_pll_clk_recalc(struct clk *clk)
 303 {
 304         unsigned long rate;
 305
 306         if ((cru_readl(CRU_MODE_CON) & CRU_CPU_MODE_MASK) == CRU_CPU_MODE_NORMAL) {
 307                 u32 v = cru_readl(CRU_APLL_CON);
 308                 u64 rate64 = (u64) clk->parent->rate * PLL_NF2(v);
 309                 do_div(rate64, PLL_NR(v));
 310                 rate = rate64 >> PLL_NO_SHIFT(v);
 311                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF2(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 312         } else {
 313                 rate = clk->parent->rate;
 314                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 315         }
 316
 317         return rate;
 318 }
 319
 320 static struct clk arm_pll_clk = {
 321         .name           = "arm_pll",
 322         .parent         = &xin24m,
 323         .recalc         = arm_pll_clk_recalc,
 324 };
 325
 326 static unsigned long ddr_pll_clk_recalc(struct clk *clk)
 327 {
 328         unsigned long rate;
 329
 330         if ((cru_readl(CRU_MODE_CON) & CRU_DDR_MODE_MASK) == CRU_DDR_MODE_NORMAL) {
 331                 u32 v = cru_readl(CRU_DPLL_CON);
 332                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 333                 do_div(rate64, PLL_NR(v));
 334                 rate = rate64 >> PLL_NO_SHIFT(v);
 335                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 336         } else {
 337                 rate = clk->parent->rate;
 338                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 339         }
 340
 341         return rate;
 342 }
 343
 344 static struct clk ddr_pll_clk = {
 345         .name           = "ddr_pll",
 346         .parent         = &xin24m,
 347         .recalc         = ddr_pll_clk_recalc,
 348 };
 349
 350
 351 static unsigned long codec_pll_clk_recalc(struct clk *clk)
 352 {
 353         unsigned long rate;
 354
 355         if ((cru_readl(CRU_MODE_CON) & CRU_CODEC_MODE_MASK) == CRU_CODEC_MODE_NORMAL) {
 356                 u32 v = cru_readl(CRU_CPLL_CON);
 357                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 358                 do_div(rate64, PLL_NR(v));
 359                 rate = rate64 >> PLL_NO_SHIFT(v);
 360                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 361         } else {
 362                 rate = clk->parent->rate;
 363                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 364         }
 365
 366         return rate;
 367 }
 368
 369 static struct clk codec_pll_clk = {
 370         .name           = "codec_pll",
 371         .parent         = &xin24m,
 372         .recalc         = codec_pll_clk_recalc,
 373 };
 374
 375
 376 static unsigned long periph_pll_clk_recalc(struct clk *clk)
 377 {
 378         unsigned long rate;
 379
 380         if ((cru_readl(CRU_MODE_CON) & CRU_PERIPH_MODE_MASK) == CRU_PERIPH_MODE_NORMAL) {
 381                 u32 v = cru_readl(CRU_PPLL_CON);
 382                 u64 rate64 = (u64) clk->parent->rate * PLL_NF(v);
 383                 do_div(rate64, PLL_NR(v));
 384                 rate = rate64 >> PLL_NO_SHIFT(v);
 385                 pr_debug("%s new clock rate is %ld (NF %d NR %d NO %d)\n", clk->name, rate, PLL_NF(v), PLL_NR(v), 1 << PLL_NO_SHIFT(v));
 386         } else {
 387                 rate = clk->parent->rate;
 388                 pr_debug("%s new clock rate is %ld (slow mode)\n", clk->name, rate);
 389         }
 390
 391         return rate;
 392 }
 393
 394 static int periph_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 395 {
 396         /* 624M: high-band, NR=1, NF=26, NO=1 */
 397         u32 v = PLL_HIGH_BAND | PLL_CLKR(1) | PLL_CLKF(26) | PLL_NO_1;
 398
 399         /* enter slow mode */
 400         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_PERIPH_MODE_MASK) | CRU_PERIPH_MODE_SLOW, CRU_MODE_CON);
 401
 402         pll_wait_lock(PERIPH_PLL_IDX, 2400000);
 403
 404         /* power down */
 405         cru_writel(cru_readl(CRU_PPLL_CON) | PLL_PD, CRU_PPLL_CON);
 406
 407         delay_500ns();
 408
 409         cru_writel(v | PLL_PD, CRU_PPLL_CON);
 410
 411         delay_500ns();
 412
 413         /* power up */
 414         cru_writel(v, CRU_PPLL_CON);
 415
 416         pll_wait_lock(PERIPH_PLL_IDX, 2400000);
 417
 418         /* enter normal mode */
 419         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_PERIPH_MODE_MASK) | CRU_PERIPH_MODE_NORMAL, CRU_MODE_CON);
 420
 421         return 0;
 422 }
 423
 424 static struct clk periph_pll_clk = {
 425         .name           = "periph_pll",
 426         .parent         = &xin24m,
 427         .recalc         = periph_pll_clk_recalc,
 428         .set_rate       = periph_pll_clk_set_rate,
 429 };
 430
 431
 432 static struct clk clk_core = {
 433         .name           = "core",
 434         .parent         = &arm_pll_clk,
 435         .recalc         = clksel_recalc_div,
 436         .clksel_con     = CRU_CLKSEL0_CON,
 437         .clksel_mask    = 0x1F,
 438         .clksel_shift   = 0,
 439 };
 440
 441 static unsigned long aclk_cpu_recalc(struct clk *clk)
 442 {
 443         unsigned long rate;
 444         u32 div = ((cru_readl(CRU_CLKSEL0_CON) >> 5) & 0x7) + 1;
 445
 446         BUG_ON(div > 5);
 447         if (div >= 5)
 448                 div = 8;
 449         rate = clk->parent->rate / div;
 450         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
 451
 452         return rate;
 453 }
 454
 455 static struct clk aclk_cpu = {
 456         .name           = "aclk_cpu",
 457         .parent         = &clk_core,
 458         .recalc         = aclk_cpu_recalc,
 459 };
 460
 461 static struct clk hclk_cpu = {
 462         .name           = "hclk_cpu",
 463         .parent         = &aclk_cpu,
 464         .recalc         = clksel_recalc_shift,
 465         .clksel_con     = CRU_CLKSEL0_CON,
 466         .clksel_mask    = 3,
 467         .clksel_shift   = 8,
 468         .clksel_maxdiv  = 4,
 469 };
 470
 471 static struct clk pclk_cpu = {
 472         .name           = "pclk_cpu",
 473         .parent         = &aclk_cpu,
 474         .recalc         = clksel_recalc_shift,
 475         .clksel_con     = CRU_CLKSEL0_CON,
 476         .clksel_mask    = 3,
 477         .clksel_shift   = 10,
 478         .clksel_maxdiv  = 8,
 479 };
 480
 481 static struct clk aclk_periph = {
 482         .name           = "aclk_periph",
 483         .parent         = &periph_pll_clk,
 484         .recalc         = clksel_recalc_div,
 485         .clksel_con     = CRU_CLKSEL0_CON,
 486         .clksel_mask    = 0x1F,
 487         .clksel_shift   = 14,
 488 };
 489
 490 static struct clk pclk_periph = {
 491         .name           = "pclk_periph",
 492         .parent         = &aclk_periph,
 493         .recalc         = clksel_recalc_shift,
 494         .clksel_con     = CRU_CLKSEL0_CON,
 495         .clksel_mask    = 3,
 496         .clksel_shift   = 19,
 497         .clksel_maxdiv  = 8,
 498 };
 499
 500 static struct clk hclk_periph = {
 501         .name           = "hclk_periph",
 502         .parent         = &aclk_periph,
 503         .recalc         = clksel_recalc_shift,
 504         .clksel_con     = CRU_CLKSEL0_CON,
 505         .clksel_mask    = 3,
 506         .clksel_shift   = 21,
 507         .clksel_maxdiv  = 4,
 508 };
 509
 510
 511 static struct clk *clk_uhost_parents[8] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 512
 513 static struct clk clk_uhost = {
 514         .name           = "uhost",
 515         .mode           = gate_mode,
 516         .recalc         = clksel_recalc_div,
 517         .set_rate       = clksel_set_rate_div,
 518         .gate_idx       = CLK_GATE_UHOST,
 519         .clksel_con     = CRU_CLKSEL1_CON,
 520         .clksel_mask    = 0x1F,
 521         .clksel_shift   = 16,
 522         .clksel_parent_mask     = 7,
 523         .clksel_parent_shift    = 13,
 524         .parents        = clk_uhost_parents,
 525 };
 526
 527 static struct clk *clk_otgphy_parents[4] = { &xin24m, &clk_12m, &clk_uhost };
 528
 529 static struct clk clk_otgphy0 = {
 530         .name           = "otgphy0",
 531         .clksel_con     = CRU_CLKSEL1_CON,
 532         .clksel_parent_mask     = 3,
 533         .clksel_parent_shift    = 9,
 534         .parents        = clk_otgphy_parents,
 535 };
 536
 537 static struct clk clk_otgphy1 = {
 538         .name           = "otgphy1",
 539         .clksel_con     = CRU_CLKSEL1_CON,
 540         .clksel_parent_mask     = 3,
 541         .clksel_parent_shift    = 11,
 542         .parents        = clk_otgphy_parents,
 543 };
 544
 545
 546 static struct clk rmii_clkin = {
 547         .name           = "rmii_clkin",
 548 };
 549
 550 static struct clk *clk_mac_ref_div_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 551
 552 static struct clk clk_mac_ref_div = {
 553         .name           = "mac_ref_div",
 554         .recalc         = clksel_recalc_div,
 555         .set_rate       = clksel_set_rate_div,
 556         .clksel_con     = CRU_CLKSEL1_CON,
 557         .clksel_mask    = 0x1F,
 558         .clksel_shift   = 23,
 559         .clksel_parent_mask     = 3,
 560         .clksel_parent_shift    = 21,
 561         .parents        = clk_mac_ref_div_parents,
 562 };
 563
 564 static struct clk *clk_mac_ref_parents[2] = { &clk_mac_ref_div, &rmii_clkin };
 565
 566 static struct clk clk_mac_ref = {
 567         .name           = "mac_ref",
 568         .clksel_con     = CRU_CLKSEL1_CON,
 569         .clksel_parent_mask     = 1,
 570         .clksel_parent_shift    = 28,
 571         .parents        = clk_mac_ref_parents,
 572 };
 573
 574
 575 static struct clk *clk_i2s_div_parents[8] = { &codec_pll_clk, &periph_pll_clk, &arm_pll_clk, &ddr_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 576
 577 static struct clk clk_i2s0_div = {
 578         .name           = "i2s0_div",
 579         .recalc         = clksel_recalc_div,
 580         .set_rate       = clksel_set_rate_div,
 581         .clksel_con     = CRU_CLKSEL2_CON,
 582         .clksel_mask    = 0x1F,
 583         .clksel_shift   = 3,
 584         .clksel_parent_mask     = 7,
 585         .clksel_parent_shift    = 0,
 586         .parents        = clk_i2s_div_parents,
 587 };
 588
 589 static struct clk clk_i2s1_div = {
 590         .name           = "i2s1_div",
 591         .recalc         = clksel_recalc_div,
 592         .set_rate       = clksel_set_rate_div,
 593         .clksel_con     = CRU_CLKSEL2_CON,
 594         .clksel_mask    = 0x1F,
 595         .clksel_shift   = 13,
 596         .clksel_parent_mask     = 7,
 597         .clksel_parent_shift    = 10,
 598         .parents        = clk_i2s_div_parents,
 599 };
 600
 601 static struct clk clk_spdif_div = {
 602         .name           = "spdif_div",
 603         .recalc         = clksel_recalc_div,
 604         .set_rate       = clksel_set_rate_div,
 605         .clksel_con     = CRU_CLKSEL2_CON,
 606         .clksel_mask    = 0x1F,
 607         .clksel_shift   = 23,
 608         .clksel_parent_mask     = 7,
 609         .clksel_parent_shift    = 20,
 610         .parents        = clk_i2s_div_parents,
 611 };
 612
 613 static int clk_i2s_frac_div_set_rate(struct clk *clk, unsigned long rate)
 614 {
 615         u16 numerator, denominator;
 616
 617         switch (rate) {
 618         case 8192000:   /* 624*128/9750 */
 619                 numerator = 128;
 620                 denominator = 9750;
 621                 break;
 622         case 11289600:  /* 624*294/16250 */
 623                 numerator = 294;
 624                 denominator = 16250;
 625                 break;
 626         case 12288000:  /* 624*64/3250 */
 627                 numerator = 64;
 628                 denominator = 3250;
 629                 break;
 630         case 22579200:  /* 624*294/8125 */
 631                 numerator = 294;
 632                 denominator = 8125;
 633                 break;
 634         case 24576000:  /* 624*64/1625 */
 635                 numerator = 64;
 636                 denominator = 1625;
 637                 break;
 638         case 45158400:  /* 624*588/8125 */
 639                 numerator = 588;
 640                 denominator = 8125;
 641                 break;
 642         case 49152000:  /* 624*128/1625 */
 643                 numerator = 128;
 644                 denominator = 1625;
 645                 break;
 646         default:
 647                 return -ENOENT;
 648         }
 649
 650         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 651         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
 652
 653         return 0;
 654 }
 655
 656 static struct clk clk_i2s0_frac_div = {
 657         .name           = "i2s0_frac_div",
 658         .parent         = &clk_i2s0_div,
 659         .recalc         = clksel_recalc_frac,
 660         .set_rate       = clk_i2s_frac_div_set_rate,
 661         .clksel_con     = CRU_CLKSEL3_CON,
 662 };
 663
 664 static struct clk clk_i2s1_frac_div = {
 665         .name           = "i2s1_frac_div",
 666         .parent         = &clk_i2s1_div,
 667         .recalc         = clksel_recalc_frac,
 668         .set_rate       = clk_i2s_frac_div_set_rate,
 669         .clksel_con     = CRU_CLKSEL4_CON,
 670 };
 671
 672 static struct clk clk_spdif_frac_div = {
 673         .name           = "spdif_frac_div",
 674         .parent         = &clk_spdif_div,
 675         .recalc         = clksel_recalc_frac,
 676         .set_rate       = clk_i2s_frac_div_set_rate,
 677         .clksel_con     = CRU_CLKSEL5_CON,
 678 };
 679
 680 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 681 {
 682         int ret;
 683         struct clk *parent;
 684
 685         if (rate == 12000000) {
 686                 parent = &clk_12m;
 687         } else {
 688                 parent = clk->parents[1]; /* frac div */
 689                 ret = clk_set_rate_nolock(parent, rate);
 690                 if (ret)
 691                         return ret;
 692         }
 693         if (clk->parent != parent)
 694                 clk_set_parent_nolock(clk, parent);
 695
 696         return ret;
 697 }
 698
 699 static struct clk *clk_i2s0_parents[4] = { &clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m, &xin24m };
 700
 701 static struct clk clk_i2s0 = {
 702         .name           = "i2s0",
 703         .set_rate       = i2s_set_rate,
 704         .clksel_con     = CRU_CLKSEL2_CON,
 705         .clksel_parent_mask     = 3,
 706         .clksel_parent_shift    = 8,
 707         .parents        = clk_i2s0_parents,
 708 };
 709
 710 static struct clk *clk_i2s1_parents[4] = { &clk_i2s1_div, &clk_i2s1_frac_div, &clk_12m, &xin24m };
 711
 712 static struct clk clk_i2s1 = {
 713         .name           = "i2s1",
 714         .set_rate       = i2s_set_rate,
 715         .clksel_con     = CRU_CLKSEL2_CON,
 716         .clksel_parent_mask     = 3,
 717         .clksel_parent_shift    = 18,
 718         .parents        = clk_i2s1_parents,
 719 };
 720
 721 static struct clk *clk_spdif_parents[4] = { &clk_spdif_div, &clk_spdif_frac_div, &clk_12m, &xin24m };
 722
 723 static struct clk clk_spdif = {
 724         .name           = "spdif",
 725         .set_rate       = i2s_set_rate,
 726         .clksel_con     = CRU_CLKSEL2_CON,
 727         .clksel_parent_mask     = 3,
 728         .clksel_parent_shift    = 28,
 729         .parents        = clk_spdif_parents,
 730 };
 731
 732
 733 static struct clk *clk_spi_src_parents[4] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
 734
 735 static struct clk clk_spi_src = {
 736         .name           = "spi_src",
 737         .clksel_con     = CRU_CLKSEL6_CON,
 738         .clksel_parent_mask     = 3,
 739         .clksel_parent_shift    = 0,
 740         .parents        = clk_spi_src_parents,
 741 };
 742
 743 static struct clk clk_spi0 = {
 744         .name           = "spi0",
 745         .parent         = &clk_spi_src,
 746         .mode           = gate_mode,
 747         .recalc         = clksel_recalc_div,
 748         .set_rate       = clksel_set_rate_div,
 749         .gate_idx       = CLK_GATE_SPI0,
 750         .clksel_con     = CRU_CLKSEL6_CON,
 751         .clksel_mask    = 0x7F,
 752         .clksel_shift   = 2,
 753 };
 754
 755 static struct clk clk_spi1 = {
 756         .name           = "spi1",
 757         .parent         = &clk_spi_src,
 758         .mode           = gate_mode,
 759         .recalc         = clksel_recalc_div,
 760         .set_rate       = clksel_set_rate_div,
 761         .gate_idx       = CLK_GATE_SPI1,
 762         .clksel_con     = CRU_CLKSEL6_CON,
 763         .clksel_mask    = 0x7F,
 764         .clksel_shift   = 11,
 765 };
 766
 767
 768 static struct clk clk_saradc = {
 769         .name           = "saradc",
 770         .parent         = &pclk_periph,
 771         .mode           = gate_mode,
 772         .recalc         = clksel_recalc_div,
 773         .set_rate       = clksel_set_rate_div,
 774         .gate_idx       = CLK_GATE_SARADC,
 775         .clksel_con     = CRU_CLKSEL6_CON,
 776         .clksel_mask    = 0xFF,
 777         .clksel_shift   = 18,
 778 };
 779
 780
 781 static struct clk *clk_cpu_timer_parents[2] = { &pclk_cpu, &xin24m };
 782
 783 static struct clk clk_timer0 = {
 784         .name           = "timer0",
 785         .mode           = gate_mode,
 786         .gate_idx       = CLK_GATE_TIMER0,
 787         .clksel_con     = CRU_CLKSEL6_CON,
 788         .clksel_parent_mask     = 1,
 789         .clksel_parent_shift    = 26,
 790         .parents        = clk_cpu_timer_parents,
 791 };
 792
 793 static struct clk clk_timer1 = {
 794         .name           = "timer1",
 795         .mode           = gate_mode,
 796         .gate_idx       = CLK_GATE_TIMER1,
 797         .clksel_con     = CRU_CLKSEL6_CON,
 798         .clksel_parent_mask     = 1,
 799         .clksel_parent_shift    = 27,
 800         .parents        = clk_cpu_timer_parents,
 801 };
 802
 803 static struct clk *clk_periph_timer_parents[2] = { &pclk_periph, &xin24m };
 804
 805 static struct clk clk_timer2 = {
 806         .name           = "timer2",
 807         .mode           = gate_mode,
 808         .gate_idx       = CLK_GATE_TIMER2,
 809         .clksel_con     = CRU_CLKSEL6_CON,
 810         .clksel_parent_mask     = 1,
 811         .clksel_parent_shift    = 28,
 812         .parents        = clk_periph_timer_parents,
 813 };
 814
 815 static struct clk clk_timer3 = {
 816         .name           = "timer3",
 817         .mode           = gate_mode,
 818         .gate_idx       = CLK_GATE_TIMER3,
 819         .clksel_con     = CRU_CLKSEL6_CON,
 820         .clksel_parent_mask     = 1,
 821         .clksel_parent_shift    = 29,
 822         .parents        = clk_periph_timer_parents,
 823 };
 824
 825
 826 static struct clk *clk_sdmmc_src_parents[4] = { &arm_pll_clk, &periph_pll_clk, &codec_pll_clk, &ddr_pll_clk };
 827
 828 static struct clk clk_sdmmc_src = {
 829         .name           = "sdmmc_src",
 830         .clksel_con     = CRU_CLKSEL7_CON,
 831         .clksel_parent_mask     = 3,
 832         .clksel_parent_shift    = 0,
 833         .parents        = clk_sdmmc_src_parents,
 834 };
 835
 836 static struct clk clk_sdmmc0 = {
 837         .name           = "sdmmc0",
 838         .parent         = &clk_sdmmc_src,
 839         .mode           = gate_mode,
 840         .recalc         = clksel_recalc_div,
 841         .set_rate       = clksel_set_rate_div,
 842         .gate_idx       = CLK_GATE_SDMMC0,
 843         .clksel_con     = CRU_CLKSEL7_CON,
 844         .clksel_mask    = 0x3F,
 845         .clksel_shift   = 2,
 846 };
 847
 848 static struct clk clk_sdmmc1 = {
 849         .name           = "sdmmc1",
 850         .parent         = &clk_sdmmc_src,
 851         .mode           = gate_mode,
 852         .recalc         = clksel_recalc_div,
 853         .set_rate       = clksel_set_rate_div,
 854         .gate_idx       = CLK_GATE_SDMMC1,
 855         .clksel_con     = CRU_CLKSEL7_CON,
 856         .clksel_mask    = 0x3F,
 857         .clksel_shift   = 10,
 858 };
 859
 860 static struct clk clk_emmc = {
 861         .name           = "emmc",
 862         .parent         = &clk_sdmmc_src,
 863         .mode           = gate_mode,
 864         .recalc         = clksel_recalc_div,
 865         .set_rate       = clksel_set_rate_div,
 866         .gate_idx       = CLK_GATE_EMMC,
 867         .clksel_con     = CRU_CLKSEL7_CON,
 868         .clksel_mask    = 0x3F,
 869         .clksel_shift   = 18,
 870 };
 871
 872
 873 static struct clk *clk_ddr_parents[8] = { &ddr_pll_clk, &periph_pll_clk, &codec_pll_clk, &arm_pll_clk };
 874
 875 static struct clk clk_ddr = {
 876         .name           = "ddr",
 877         .recalc         = clksel_recalc_shift,
 878         .clksel_con     = CRU_CLKSEL7_CON,
 879         .clksel_mask    = 7,
 880         .clksel_shift   = 26,
 881         .clksel_maxdiv  = 32,
 882         .clksel_parent_mask     = 3,
 883         .clksel_parent_shift    = 24,
 884         .parents        = clk_ddr_parents,
 885 };
 886
 887
 888 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
 889 {
 890         int ret;
 891         struct clk *parent;
 892         struct clk *clk_div = clk->parents[0];
 893
 894         switch (rate) {
 895         case 24000000: /* 1.5M/0.5M/50/75/150/200/300/600/1200/2400 */
 896                 parent = clk->parents[2]; /* xin24m */
 897                 break;
 898         case 48000000: /* 3M */
 899         case 16000000: /* 1M */
 900         case 8125*16: /* 4800 */
 901                 parent = clk_div;
 902                 break;
 903         default:
 904                 parent = clk->parents[1]; /* frac div */
 905                 /* reset div to 1 */
 906                 ret = clk_set_rate_nolock(clk_div, clk_div->parent->rate);
 907                 if (ret)
 908                         return ret;
 909                 break;
 910         }
 911
 912         if (parent->set_rate) {
 913                 ret = clk_set_rate_nolock(parent, rate);
 914                 if (ret)
 915                         return ret;
 916         }
 917
 918         if (clk->parent != parent)
 919                 clk_set_parent_nolock(clk, parent);
 920
 921         return 0;
 922 }
 923
 924 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
 925 {
 926         u16 numerator, denominator;
 927
 928         switch (rate) {
 929         case 9600*16:
 930                 numerator = 2;
 931                 denominator = 8125;
 932                 break;
 933         case 19200*16:
 934                 numerator = 4;
 935                 denominator = 8125;
 936                 break;
 937         case 38400*16:
 938                 numerator = 8;
 939                 denominator = 8125;
 940                 break;
 941         case 57600*16:
 942                 numerator = 12;
 943                 denominator = 8125;
 944                 break;
 945         case 115200*16:
 946                 numerator = 24;
 947                 denominator = 8125;
 948                 break;
 949         case 230400*16:
 950                 numerator = 48;
 951                 denominator = 8125;
 952                 break;
 953         case 460800*16:
 954                 numerator = 96;
 955                 denominator = 8125;
 956                 break;
 957         case 576000*16:
 958                 numerator = 24;
 959                 denominator = 1625;
 960                 break;
 961         case 921600*16:
 962                 numerator = 192;
 963                 denominator = 8125;
 964                 break;
 965         case 1152000*16:
 966                 numerator = 48;
 967                 denominator = 1625;
 968                 break;
 969         default:
 970                 return -ENOENT;
 971         }
 972
 973         pr_debug("set clock %s to rate %ld (%d/%d)\n", clk->name, rate, numerator, denominator);
 974         cru_writel((u32)numerator << 16 | denominator, clk->clksel_con);
 975
 976         return 0;
 977 }
 978 static struct clk *clk_uart_src_parents[8] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
 979
 980 static struct clk clk_uart01_src = {
 981         .name           = "uart01_src",
 982         .clksel_con     = CRU_CLKSEL8_CON,
 983         .clksel_parent_mask     = 7,
 984         .clksel_parent_shift    = 0,
 985         .parents        = clk_uart_src_parents,
 986 };
 987
 988 static struct clk clk_uart0_div = {
 989         .name           = "uart0_div",
 990         .parent         = &clk_uart01_src,
 991         .recalc         = clksel_recalc_div,
 992         .set_rate       = clksel_set_rate_div,
 993         .clksel_con     = CRU_CLKSEL8_CON,
 994         .clksel_mask    = 0x3F,
 995         .clksel_shift   = 3,
 996 };
 997
 998 static struct clk clk_uart0_frac_div = {
 999         .name           = "uart0_frac_div",
1000         .parent         = &clk_uart0_div,
1001         .recalc         = clksel_recalc_frac,
1002         .set_rate       = clk_uart_frac_div_set_rate,
1003         .clksel_con     = CRU_CLKSEL10_CON,
1004 };
1005
1006 static struct clk *clk_uart0_parents[4] = { &clk_uart0_div, &clk_uart0_frac_div, &xin24m };
1007
1008 static struct clk clk_uart0 = {
1009         .name           = "uart0",
1010         .mode           = gate_mode,
1011         .set_rate       = clk_uart_set_rate,
1012         .gate_idx       = CLK_GATE_UART0,
1013         .clksel_con     = CRU_CLKSEL8_CON,
1014         .clksel_parent_mask     = 3,
1015         .clksel_parent_shift    = 9,
1016         .parents        = clk_uart0_parents,
1017 };
1018
1019 static struct clk clk_uart1_div = {
1020         .name           = "uart1_div",
1021         .parent         = &clk_uart01_src,
1022         .recalc         = clksel_recalc_div,
1023         .set_rate       = clksel_set_rate_div,
1024         .clksel_con     = CRU_CLKSEL8_CON,
1025         .clksel_mask    = 0x3F,
1026         .clksel_shift   = 14,
1027 };
1028
1029 static struct clk clk_uart1_frac_div = {
1030         .name           = "uart1_frac_div",
1031         .parent         = &clk_uart1_div,
1032         .recalc         = clksel_recalc_frac,
1033         .set_rate       = clk_uart_frac_div_set_rate,
1034         .clksel_con     = CRU_CLKSEL11_CON,
1035 };
1036
1037 static struct clk *clk_uart1_parents[4] = { &clk_uart1_div, &clk_uart1_frac_div, &xin24m };
1038
1039 static struct clk clk_uart1 = {
1040         .name           = "uart1",
1041         .mode           = gate_mode,
1042         .set_rate       = clk_uart_set_rate,
1043         .gate_idx       = CLK_GATE_UART1,
1044         .clksel_con     = CRU_CLKSEL8_CON,
1045         .clksel_parent_mask     = 3,
1046         .clksel_parent_shift    = 20,
1047         .parents        = clk_uart1_parents,
1048 };
1049
1050 static struct clk clk_uart23_src = {
1051         .name           = "uart23_src",
1052         .clksel_con     = CRU_CLKSEL9_CON,
1053         .clksel_parent_mask     = 7,
1054         .clksel_parent_shift    = 0,
1055         .parents        = clk_uart_src_parents,
1056 };
1057
1058 static struct clk clk_uart2_div = {
1059         .name           = "uart2_div",
1060         .parent         = &clk_uart23_src,
1061         .recalc         = clksel_recalc_div,
1062         .set_rate       = clksel_set_rate_div,
1063         .clksel_con     = CRU_CLKSEL9_CON,
1064         .clksel_mask    = 0x3F,
1065         .clksel_shift   = 3,
1066 };
1067
1068 static struct clk clk_uart2_frac_div = {
1069         .name           = "uart2_frac_div",
1070         .parent         = &clk_uart2_div,
1071         .recalc         = clksel_recalc_frac,
1072         .set_rate       = clk_uart_frac_div_set_rate,
1073         .clksel_con     = CRU_CLKSEL12_CON,
1074 };
1075
1076 static struct clk *clk_uart2_parents[4] = { &clk_uart2_div, &clk_uart2_frac_div, &xin24m };
1077
1078 static struct clk clk_uart2 = {
1079         .name           = "uart2",
1080         .mode           = gate_mode,
1081         .set_rate       = clk_uart_set_rate,
1082         .gate_idx       = CLK_GATE_UART2,
1083         .clksel_con     = CRU_CLKSEL9_CON,
1084         .clksel_parent_mask     = 3,
1085         .clksel_parent_shift    = 9,
1086         .parents        = clk_uart2_parents,
1087 };
1088
1089 static struct clk clk_uart3_div = {
1090         .name           = "uart3_div",
1091         .parent         = &clk_uart23_src,
1092         .recalc         = clksel_recalc_div,
1093         .set_rate       = clksel_set_rate_div,
1094         .clksel_con     = CRU_CLKSEL9_CON,
1095         .clksel_mask    = 0x3F,
1096         .clksel_shift   = 14,
1097 };
1098
1099 static struct clk clk_uart3_frac_div = {
1100         .name           = "uart3_frac_div",
1101         .parent         = &clk_uart3_div,
1102         .recalc         = clksel_recalc_frac,
1103         .set_rate       = clk_uart_frac_div_set_rate,
1104         .clksel_con     = CRU_CLKSEL13_CON,
1105 };
1106
1107 static struct clk *clk_uart3_parents[4] = { &clk_uart3_div, &clk_uart3_frac_div, &xin24m };
1108
1109 static struct clk clk_uart3 = {
1110         .name           = "uart3",
1111         .mode           = gate_mode,
1112         .set_rate       = clk_uart_set_rate,
1113         .gate_idx       = CLK_GATE_UART3,
1114         .clksel_con     = CRU_CLKSEL9_CON,
1115         .clksel_parent_mask     = 3,
1116         .clksel_parent_shift    = 20,
1117         .parents        = clk_uart3_parents,
1118 };
1119
1120
1121 static struct clk *clk_hsadc_div_parents[8] = { &codec_pll_clk, &ddr_pll_clk, &periph_pll_clk, &arm_pll_clk, &otgphy0_clkin, &otgphy1_clkin };
1122
1123 static struct clk clk_hsadc_div = {
1124         .name           = "hsadc_div",
1125         .recalc         = clksel_recalc_div,
1126         .set_rate       = clksel_set_rate_div,
1127         .clksel_con     = CRU_CLKSEL14_CON,
1128         .clksel_mask    = 0xFF,
1129         .clksel_shift   = 10,
1130         .clksel_parent_mask     = 7,
1131         .clksel_parent_shift    = 7,
1132         .parents        = clk_hsadc_div_parents,
1133 };
1134
1135 static struct clk clk_hsadc_frac_div = {
1136         .name           = "hsadc_frac_div",
1137         .parent         = &clk_hsadc_div,
1138         .recalc         = clksel_recalc_frac,
1139         .clksel_con     = CRU_CLKSEL15_CON,
1140 };
1141
1142 static struct clk *clk_demod_parents[4] = { &clk_hsadc_div, &clk_hsadc_frac_div, &extclk };
1143
1144 static struct clk clk_demod = {
1145         .name           = "demod",
1146         .clksel_con     = CRU_CLKSEL14_CON,
1147         .clksel_parent_mask     = 3,
1148         .clksel_parent_shift    = 18,
1149         .parents        = clk_demod_parents,
1150 };
1151
1152 static struct clk gpsclk = {
1153         .name           = "gpsclk",
1154 };
1155
1156 static struct clk *clk_hsadc_parents[2] = { &clk_demod, &gpsclk };
1157
1158 static struct clk clk_hsadc = {
1159         .name           = "hsadc",
1160         .clksel_con     = CRU_CLKSEL14_CON,
1161         .clksel_parent_mask     = 1,
1162         .clksel_parent_shift    = 21,
1163         .parents        = clk_hsadc_parents,
1164 };
1165
1166 static unsigned long div2_recalc(struct clk *clk)
1167 {
1168         return clk->parent->rate >> 1;
1169 }
1170
1171 static struct clk clk_hsadc_div2 = {
1172         .name           = "hsadc_div2",
1173         .parent         = &clk_demod,
1174         .recalc         = div2_recalc,
1175 };
1176
1177 static struct clk clk_hsadc_div2_inv = {
1178         .name           = "hsadc_div2_inv",
1179         .parent         = &clk_demod,
1180         .recalc         = div2_recalc,
1181 };
1182
1183 static struct clk *clk_hsadc_out_parents[2] = { &clk_hsadc_div2, &clk_hsadc_div2_inv };
1184
1185 static struct clk clk_hsadc_out = {
1186         .name           = "hsadc_out",
1187         .clksel_con     = CRU_CLKSEL14_CON,
1188         .clksel_parent_mask     = 1,
1189         .clksel_parent_shift    = 20,
1190         .parents        = clk_hsadc_out_parents,
1191 };
1192
1193
1194 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &periph_pll_clk, &arm_pll_clk };
1195
1196 static struct clk dclk_lcdc_div = {
1197         .name           = "dclk_lcdc_div",
1198         .recalc         = clksel_recalc_div,
1199         .set_rate       = clksel_set_rate_div,
1200         .clksel_con     = CRU_CLKSEL16_CON,
1201         .clksel_mask    = 0xFF,
1202         .clksel_shift   = 2,
1203         .clksel_parent_mask     = 3,
1204         .clksel_parent_shift    = 0,
1205         .parents        = dclk_lcdc_div_parents,
1206 };
1207
1208 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &extclk };
1209
1210 static struct clk dclk_lcdc = {
1211         .name           = "dclk_lcdc",
1212         .mode           = gate_mode,
1213         .gate_idx       = CLK_GATE_LCDC,
1214         .clksel_con     = CRU_CLKSEL16_CON,
1215         .clksel_parent_mask     = 1,
1216         .clksel_parent_shift    = 10,
1217         .parents        = dclk_lcdc_parents,
1218 };
1219
1220 static struct clk dclk_ebook = {
1221         .name           = "dclk_ebook",
1222         .recalc         = clksel_recalc_div,
1223         .set_rate       = clksel_set_rate_div,
1224         .clksel_con     = CRU_CLKSEL16_CON,
1225         .clksel_mask    = 0x1F,
1226         .clksel_shift   = 13,
1227         .clksel_parent_mask     = 3,
1228         .clksel_parent_shift    = 11,
1229         .parents        = dclk_lcdc_div_parents,
1230 };
1231
1232 static struct clk *aclk_lcdc_parents[4] = { &ddr_pll_clk, &codec_pll_clk, &periph_pll_clk, &arm_pll_clk };
1233
1234 static struct clk aclk_lcdc = {
1235         .name           = "aclk_lcdc",
1236         .mode           = gate_mode,
1237         .gate_idx       = CLK_GATE_LCDC_AXI,
1238         .recalc         = clksel_recalc_div,
1239         .set_rate       = clksel_set_rate_div,
1240         .clksel_con     = CRU_CLKSEL16_CON,
1241         .clksel_mask    = 0x1F,
1242         .clksel_shift   = 20,
1243         .clksel_parent_mask     = 3,
1244         .clksel_parent_shift    = 18,
1245         .parents        = aclk_lcdc_parents,
1246 };
1247
1248 static struct clk hclk_lcdc = {
1249         .name           = "hclk_lcdc",
1250         .mode           = gate_mode,
1251         .gate_idx       = CLK_GATE_LCDC_AHB,
1252         .parent         = &aclk_lcdc,
1253         .clksel_con     = CRU_CLKSEL16_CON,
1254         .recalc         = clksel_recalc_shift,
1255         .set_rate       = clksel_set_rate_shift,
1256         .clksel_mask    = 3,
1257         .clksel_shift   = 25,
1258         .clksel_maxdiv  = 4,
1259 };
1260
1261 static struct clk *xpu_parents[4] = { &periph_pll_clk, &ddr_pll_clk, &codec_pll_clk, &arm_pll_clk };
1262
1263 static struct clk aclk_vepu = {
1264         .name           = "aclk_vepu",
1265         .mode           = gate_mode,
1266         .recalc         = clksel_recalc_div,
1267         .set_rate       = clksel_set_rate_div,
1268         .gate_idx       = CLK_GAET_VEPU_AXI,
1269         .clksel_con     = CRU_CLKSEL17_CON,
1270         .clksel_mask    = 0x1F,
1271         .clksel_shift   = 2,
1272         .clksel_parent_mask     = 3,
1273         .clksel_parent_shift    = 0,
1274         .parents        = xpu_parents,
1275 };
1276
1277 static struct clk hclk_vepu = {
1278         .name           = "hclk_vepu",
1279         .parent         = &aclk_vepu,
1280         .mode           = gate_mode,
1281         .recalc         = clksel_recalc_shift,
1282         .set_rate       = clksel_set_rate_shift,
1283         .gate_idx       = CLK_GATE_VEPU_AHB,
1284         .clksel_con     = CRU_CLKSEL17_CON,
1285         .clksel_mask    = 3,
1286         .clksel_shift   = 28,
1287         .clksel_maxdiv  = 4,
1288 };
1289
1290 static struct clk aclk_vdpu = {
1291         .name           = "aclk_vdpu",
1292         .parent         = &periph_pll_clk,
1293         .mode           = gate_mode,
1294         .recalc         = clksel_recalc_div,
1295         .set_rate       = clksel_set_rate_div,
1296         .gate_idx       = CLK_GATE_VDPU_AXI,
1297         .clksel_con     = CRU_CLKSEL17_CON,
1298         .clksel_mask    = 0x1F,
1299         .clksel_shift   = 9,
1300         .clksel_parent_mask     = 3,
1301         .clksel_parent_shift    = 7,
1302         .parents        = xpu_parents,
1303 };
1304
1305 static struct clk hclk_vdpu = {
1306         .name           = "hclk_vdpu",
1307         .parent         = &aclk_vdpu,
1308         .mode           = gate_mode,
1309         .recalc         = clksel_recalc_shift,
1310         .set_rate       = clksel_set_rate_shift,
1311         .gate_idx       = CLK_GATE_VDPU_AHB,
1312         .clksel_con     = CRU_CLKSEL17_CON,
1313         .clksel_mask    = 3,
1314         .clksel_shift   = 30,
1315         .clksel_maxdiv  = 4,
1316 };
1317
1318 static struct clk clk_gpu = {
1319         .name           = "gpu",
1320         .recalc         = clksel_recalc_div,
1321         .set_rate       = clksel_set_rate_div,
1322         .clksel_con     = CRU_CLKSEL17_CON,
1323         .clksel_mask    = 0x1F,
1324         .clksel_shift   = 16,
1325         .clksel_parent_mask     = 3,
1326         .clksel_parent_shift    = 14,
1327         .parents        = xpu_parents,
1328 };
1329
1330 static struct clk aclk_gpu = {
1331         .name           = "aclk_gpu",
1332         .recalc         = clksel_recalc_div,
1333         .set_rate       = clksel_set_rate_div,
1334         .clksel_con     = CRU_CLKSEL17_CON,
1335         .clksel_mask    = 0x1F,
1336         .clksel_shift   = 23,
1337         .clksel_parent_mask     = 3,
1338         .clksel_parent_shift    = 21,
1339         .parents        = xpu_parents,
1340 };
1341
1342
1343 static struct clk *clk_vip_parents[4] = { &xin24m, &extclk, &dclk_ebook };
1344
1345 static struct clk clk_vip = {
1346         .name           = "vip",
1347         .mode           = gate_mode,
1348         .gate_idx       = CLK_GATE_VIP,
1349         .clksel_con     = CRU_CLKSEL1_CON,
1350         .clksel_parent_mask     = 3,
1351         .clksel_parent_shift    = 7,
1352         .parents        = clk_vip_parents,
1353 };
1354
1355
1356 #define GATE_CLK(NAME,PARENT,ID) \
1357 static struct clk clk_##NAME = { \
1358         .name           = #NAME, \
1359         .parent         = &PARENT, \
1360         .mode           = gate_mode, \
1361         .gate_idx       = CLK_GATE_##ID, \
1362 }
1363
1364 GATE_CLK(i2c0, pclk_cpu, I2C0);
1365 GATE_CLK(i2c1, pclk_periph, I2C1);
1366 GATE_CLK(i2c2, pclk_periph, I2C2);
1367 GATE_CLK(i2c3, pclk_periph, I2C3);
1368
1369 GATE_CLK(gpio0, pclk_cpu, GPIO0);
1370 GATE_CLK(gpio1, pclk_periph, GPIO1);
1371 GATE_CLK(gpio2, pclk_periph, GPIO2);
1372 GATE_CLK(gpio3, pclk_periph, GPIO3);
1373 GATE_CLK(gpio4, pclk_cpu, GPIO4);
1374 GATE_CLK(gpio5, pclk_periph, GPIO5);
1375 GATE_CLK(gpio6, pclk_cpu, GPIO6);
1376
1377 #define CLK(dev, con, ck) \
1378         { \
1379                 .dev_id = dev, \
1380                 .con_id = con, \
1381                 .clk = ck, \
1382         }
1383
1384 #define CLK1(name) \
1385         { \
1386                 .dev_id = NULL, \
1387                 .con_id = #name, \
1388                 .clk = &clk_##name, \
1389         }
1390
1391 static struct clk_lookup clks[] = {
1392         CLK(NULL, "xin24m", &xin24m),
1393         CLK(NULL, "extclk", &extclk),
1394         CLK(NULL, "otgphy0_clkin", &otgphy0_clkin),
1395         CLK(NULL, "otgphy1_clkin", &otgphy1_clkin),
1396         CLK(NULL, "gpsclk", &gpsclk),
1397
1398         CLK1(12m),
1399         CLK(NULL, "arm_pll", &arm_pll_clk),
1400         CLK(NULL, "ddr_pll", &ddr_pll_clk),
1401         CLK(NULL, "codec_pll", &codec_pll_clk),
1402         CLK(NULL, "periph_pll", &periph_pll_clk),
1403
1404         CLK1(core),
1405         CLK(NULL, "aclk_cpu", &aclk_cpu),
1406         CLK(NULL, "hclk_cpu", &hclk_cpu),
1407         CLK(NULL, "pclk_cpu", &pclk_cpu),
1408
1409         CLK(NULL, "aclk_periph", &aclk_periph),
1410         CLK(NULL, "hclk_periph", &hclk_periph),
1411         CLK(NULL, "pclk_periph", &pclk_periph),
1412
1413         CLK1(vip),
1414         CLK("rk29_otgphy.0", "otgphy", &clk_otgphy0),
1415         CLK("rk29_otgphy.1", "otgphy", &clk_otgphy1),
1416         CLK(NULL, "uhost", &clk_uhost),
1417         CLK(NULL, "mac_ref_div", &clk_mac_ref_div),
1418         CLK(NULL, "mac_ref", &clk_mac_ref),
1419
1420         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
1421         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
1422         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
1423         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
1424         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
1425         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
1426         CLK(NULL, "spdif_div", &clk_spdif_div),
1427         CLK(NULL, "spdif_frac_div", &clk_spdif_frac_div),
1428         CLK(NULL, "spdif", &clk_spdif),
1429
1430         CLK1(spi_src),
1431         CLK("rk29xx_spim.0", "spi0", &clk_spi0),
1432         CLK("rk29xx_spim.1", "spi1", &clk_spi1),
1433
1434         CLK1(saradc),
1435         CLK1(timer0),
1436         CLK1(timer1),
1437         CLK1(timer2),
1438         CLK1(timer3),
1439
1440         CLK1(sdmmc_src),
1441         CLK("rk29_sdmmc.0", "sdmmc", &clk_sdmmc0),
1442         CLK("rk29_sdmmc.1", "sdmmc", &clk_sdmmc1),
1443         CLK1(emmc),
1444         CLK1(ddr),
1445
1446         CLK1(uart01_src),
1447         CLK("rk29_serial.0", "uart", &clk_uart0),
1448         CLK("rk29_serial.0", "uart_div", &clk_uart0_div),
1449         CLK("rk29_serial.0", "uart_frac_div", &clk_uart0_frac_div),
1450         CLK("rk29_serial.1", "uart", &clk_uart1),
1451         CLK("rk29_serial.1", "uart_div", &clk_uart1_div),
1452         CLK("rk29_serial.1", "uart_frac_div", &clk_uart1_frac_div),
1453
1454         CLK1(uart23_src),
1455         CLK("rk29_serial.2", "uart", &clk_uart2),
1456         CLK("rk29_serial.2", "uart_div", &clk_uart2_div),
1457         CLK("rk29_serial.2", "uart_frac_div", &clk_uart2_frac_div),
1458         CLK("rk29_serial.3", "uart", &clk_uart3),
1459         CLK("rk29_serial.3", "uart_div", &clk_uart3_div),
1460         CLK("rk29_serial.3", "uart_frac_div", &clk_uart3_frac_div),
1461
1462         CLK1(hsadc_div),
1463         CLK1(hsadc_frac_div),
1464         CLK1(demod),
1465         CLK1(hsadc),
1466         CLK1(hsadc_div2),
1467         CLK1(hsadc_div2_inv),
1468         CLK1(hsadc_out),
1469
1470         CLK(NULL, "dclk_lcdc_div", &dclk_lcdc_div),
1471         CLK(NULL, "dclk_lcdc", &dclk_lcdc),
1472         CLK(NULL, "dclk_ebook", &dclk_ebook),
1473         CLK(NULL, "aclk_lcdc", &aclk_lcdc),
1474         CLK(NULL, "hclk_lcdc", &hclk_lcdc),
1475
1476         CLK(NULL, "aclk_vepu", &aclk_vepu),
1477         CLK(NULL, "hclk_vepu", &hclk_vepu),
1478         CLK(NULL, "aclk_vdpu", &aclk_vdpu),
1479         CLK(NULL, "hclk_vdpu", &hclk_vdpu),
1480         CLK1(gpu),
1481         CLK(NULL, "aclk_gpu", &aclk_gpu),
1482
1483         CLK("rk29_i2c.0", "i2c", &clk_i2c0),
1484         CLK("rk29_i2c.1", "i2c", &clk_i2c1),
1485         CLK("rk29_i2c.2", "i2c", &clk_i2c2),
1486         CLK("rk29_i2c.3", "i2c", &clk_i2c3),
1487
1488         CLK1(gpio0),
1489         CLK1(gpio1),
1490         CLK1(gpio2),
1491         CLK1(gpio3),
1492         CLK1(gpio4),
1493         CLK1(gpio5),
1494         CLK1(gpio6),
1495 };
1496
1497 static LIST_HEAD(clocks);
1498 static DEFINE_MUTEX(clocks_mutex);
1499 static DEFINE_SPINLOCK(clockfw_lock);
1500 #define LOCK() do { WARN_ON(in_irq()); if (!irqs_disabled()) spin_lock_bh(&clockfw_lock); } while (0)
1501 #define UNLOCK() do { if (!irqs_disabled()) spin_unlock_bh(&clockfw_lock); } while (0)
1502
1503 static int clk_enable_nolock(struct clk *clk)
1504 {
1505         int ret = 0;
1506
1507         if (clk->usecount == 0) {
1508                 if (clk->parent) {
1509                         ret = clk_enable_nolock(clk->parent);
1510                         if (ret)
1511                                 return ret;
1512                 }
1513
1514                 if (clk->mode) {
1515                         ret = clk->mode(clk, 1);
1516                         if (ret) {
1517                                 if (clk->parent)
1518                                         clk_disable_nolock(clk->parent);
1519                                 return ret;
1520                         }
1521                 }
1522                 pr_debug("%s enabled\n", clk->name);
1523         }
1524         clk->usecount++;
1525
1526         return ret;
1527 }
1528
1529 int clk_enable(struct clk *clk)
1530 {
1531         int ret = 0;
1532
1533         if (clk == NULL || IS_ERR(clk))
1534                 return -EINVAL;
1535
1536         LOCK();
1537         ret = clk_enable_nolock(clk);
1538         UNLOCK();
1539
1540         return ret;
1541 }
1542 EXPORT_SYMBOL(clk_enable);
1543
1544 static void clk_disable_nolock(struct clk *clk)
1545 {
1546         if (clk->usecount == 0) {
1547                 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", clk->name);
1548                 WARN_ON(1);
1549                 return;
1550         }
1551
1552         if (--clk->usecount == 0) {
1553                 if (clk->mode)
1554                         clk->mode(clk, 0);
1555                 pr_debug("%s disabled\n", clk->name);
1556                 if (clk->parent)
1557                         clk_disable_nolock(clk->parent);
1558         }
1559 }
1560
1561 void clk_disable(struct clk *clk)
1562 {
1563         if (clk == NULL || IS_ERR(clk))
1564                 return;
1565
1566         LOCK();
1567         clk_disable_nolock(clk);
1568         UNLOCK();
1569 }
1570 EXPORT_SYMBOL(clk_disable);
1571
1572 unsigned long clk_get_rate(struct clk *clk)
1573 {
1574         if (clk == NULL || IS_ERR(clk))
1575                 return 0;
1576
1577         return clk->rate;
1578 }
1579 EXPORT_SYMBOL(clk_get_rate);
1580
1581 /*-------------------------------------------------------------------------
1582  * Optional clock functions defined in include/linux/clk.h
1583  *-------------------------------------------------------------------------*/
1584
1585 /* Given a clock and a rate apply a clock specific rounding function */
1586 static long clk_round_rate_nolock(struct clk *clk, unsigned long rate)
1587 {
1588         if (clk->round_rate)
1589                 return clk->round_rate(clk, rate);
1590
1591         if (clk->flags & RATE_FIXED)
1592                 printk(KERN_ERR "clock: clk_round_rate called on fixed-rate clock %s\n", clk->name);
1593
1594         return clk->rate;
1595 }
1596
1597 long clk_round_rate(struct clk *clk, unsigned long rate)
1598 {
1599         long ret = 0;
1600
1601         if (clk == NULL || IS_ERR(clk))
1602                 return ret;
1603
1604         LOCK();
1605         ret = clk_round_rate_nolock(clk, rate);
1606         UNLOCK();
1607
1608         return ret;
1609 }
1610 EXPORT_SYMBOL(clk_round_rate);
1611
1612 static void __clk_recalc(struct clk *clk)
1613 {
1614         if (unlikely(clk->flags & RATE_FIXED))
1615                 return;
1616         if (clk->recalc)
1617                 clk->rate = clk->recalc(clk);
1618         else if (clk->parent)
1619                 clk->rate = clk->parent->rate;
1620         pr_debug("%s new clock rate is %lu\n", clk->name, clk->rate);
1621 }
1622
1623 static int clk_set_rate_nolock(struct clk *clk, unsigned long rate)
1624 {
1625         int ret;
1626
1627         if (rate == clk->rate)
1628                 return 0;
1629
1630         pr_debug("set_rate for clock %s to rate %ld\n", clk->name, rate);
1631
1632         if (clk->flags & CONFIG_PARTICIPANT)
1633                 return -EINVAL;
1634
1635         if (!clk->set_rate)
1636                 return -EINVAL;
1637
1638         ret = clk->set_rate(clk, rate);
1639
1640         if (ret == 0) {
1641                 __clk_recalc(clk);
1642                 __propagate_rate(clk);
1643         }
1644
1645         return ret;
1646 }
1647
1648 /* Set the clock rate for a clock source */
1649 int clk_set_rate(struct clk *clk, unsigned long rate)
1650 {
1651         int ret = -EINVAL;
1652
1653         if (clk == NULL || IS_ERR(clk))
1654                 return ret;
1655
1656         LOCK();
1657         ret = clk_set_rate_nolock(clk, rate);
1658         UNLOCK();
1659
1660         return ret;
1661 }
1662 EXPORT_SYMBOL(clk_set_rate);
1663
1664 static int clk_set_parent_nolock(struct clk *clk, struct clk *parent)
1665 {
1666         int ret;
1667         int enabled = clk->usecount > 0;
1668         struct clk *old_parent = clk->parent;
1669
1670         if (clk->parent == parent)
1671                 return 0;
1672
1673         /* if clk is already enabled, enable new parent first and disable old parent later. */
1674         if (enabled)
1675                 clk_enable_nolock(parent);
1676
1677         if (clk->set_parent)
1678                 ret = clk->set_parent(clk, parent);
1679         else
1680                 ret = clksel_set_parent(clk, parent);
1681
1682         if (ret == 0) {
1683                 /* OK */
1684                 __clk_reparent(clk, parent);
1685                 __clk_recalc(clk);
1686                 __propagate_rate(clk);
1687                 if (enabled)
1688                         clk_disable_nolock(old_parent);
1689         } else {
1690                 if (enabled)
1691                         clk_disable_nolock(parent);
1692         }
1693
1694         return ret;
1695 }
1696
1697 int clk_set_parent(struct clk *clk, struct clk *parent)
1698 {
1699         int ret = -EINVAL;
1700
1701         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
1702                 return ret;
1703
1704         if (clk->set_parent == NULL && clk->parents == NULL)
1705                 return ret;
1706
1707         LOCK();
1708         if (clk->usecount == 0)
1709                 ret = clk_set_parent_nolock(clk, parent);
1710         else
1711                 ret = -EBUSY;
1712         UNLOCK();
1713
1714         return ret;
1715 }
1716 EXPORT_SYMBOL(clk_set_parent);
1717
1718 struct clk *clk_get_parent(struct clk *clk)
1719 {
1720         return clk->parent;
1721 }
1722 EXPORT_SYMBOL(clk_get_parent);
1723
1724 static void __clk_reparent(struct clk *child, struct clk *parent)
1725 {
1726         if (child->parent == parent)
1727                 return;
1728         pr_debug("%s reparent to %s (was %s)\n", child->name, parent->name, ((child->parent) ? child->parent->name : "NULL"));
1729
1730         list_del_init(&child->sibling);
1731         if (parent)
1732                 list_add(&child->sibling, &parent->children);
1733         child->parent = parent;
1734 }
1735
1736 /* Propagate rate to children */
1737 static void __propagate_rate(struct clk *tclk)
1738 {
1739         struct clk *clkp;
1740
1741         list_for_each_entry(clkp, &tclk->children, sibling) {
1742                 __clk_recalc(clkp);
1743                 __propagate_rate(clkp);
1744         }
1745 }
1746
1747 static LIST_HEAD(root_clks);
1748
1749 /**
1750  * recalculate_root_clocks - recalculate and propagate all root clocks
1751  *
1752  * Recalculates all root clocks (clocks with no parent), which if the
1753  * clock's .recalc is set correctly, should also propagate their rates.
1754  * Called at init.
1755  */
1756 static void clk_recalculate_root_clocks_nolock(void)
1757 {
1758         struct clk *clkp;
1759
1760         list_for_each_entry(clkp, &root_clks, sibling) {
1761                 __clk_recalc(clkp);
1762                 __propagate_rate(clkp);
1763         }
1764 }
1765
1766 void clk_recalculate_root_clocks(void)
1767 {
1768         LOCK();
1769         clk_recalculate_root_clocks_nolock();
1770         UNLOCK();
1771 }
1772
1773
1774 /**
1775  * clk_preinit - initialize any fields in the struct clk before clk init
1776  * @clk: struct clk * to initialize
1777  *
1778  * Initialize any struct clk fields needed before normal clk initialization
1779  * can run.  No return value.
1780  */
1781 static void clk_preinit(struct clk *clk)
1782 {
1783         INIT_LIST_HEAD(&clk->children);
1784 }
1785
1786 static int clk_register(struct clk *clk)
1787 {
1788         if (clk == NULL || IS_ERR(clk))
1789                 return -EINVAL;
1790
1791         /*
1792          * trap out already registered clocks
1793          */
1794         if (clk->node.next || clk->node.prev)
1795                 return 0;
1796
1797         mutex_lock(&clocks_mutex);
1798
1799         if (clk->get_parent)
1800                 clk->parent = clk->get_parent(clk);
1801         else if (clk->parents)
1802                 clk->parent = clksel_get_parent(clk);
1803
1804         if (clk->parent)
1805                 list_add(&clk->sibling, &clk->parent->children);
1806         else
1807                 list_add(&clk->sibling, &root_clks);
1808
1809         list_add(&clk->node, &clocks);
1810
1811         mutex_unlock(&clocks_mutex);
1812
1813         return 0;
1814 }
1815
1816 static void clk_enable_init_clocks(void)
1817 {
1818         struct clk *clkp;
1819
1820         list_for_each_entry(clkp, &clocks, node) {
1821                 if (clkp->flags & ENABLE_ON_INIT)
1822                         clk_enable(clkp);
1823         }
1824 }
1825
1826 static void rk29_clock_common_init(void)
1827 {
1828         /* periph pll */
1829         clk_set_rate_nolock(&periph_pll_clk, 624000000);
1830         clk_set_parent_nolock(&aclk_periph, &periph_pll_clk);
1831         clk_set_parent_nolock(&clk_uhost, &periph_pll_clk);     // default
1832         clk_set_rate_nolock(&clk_uhost, 48000000);
1833         clk_set_parent_nolock(&clk_i2s0_div, &periph_pll_clk);  // default
1834         clk_set_parent_nolock(&clk_i2s1_div, &periph_pll_clk);  // default
1835         clk_set_parent_nolock(&clk_spdif_div, &periph_pll_clk); // default
1836         clk_set_parent_nolock(&clk_spi_src, &periph_pll_clk);   // default
1837         clk_set_parent_nolock(&clk_sdmmc_src, &periph_pll_clk);
1838         clk_set_parent_nolock(&clk_uart01_src, &periph_pll_clk);        // default
1839         clk_set_parent_nolock(&clk_uart23_src, &periph_pll_clk);        // default
1840         clk_set_parent_nolock(&dclk_lcdc_div, &periph_pll_clk);
1841         clk_set_parent_nolock(&aclk_lcdc, &periph_pll_clk);
1842         clk_set_parent_nolock(&aclk_vepu, &periph_pll_clk);     // default
1843         clk_set_parent_nolock(&aclk_vdpu, &periph_pll_clk);     // default
1844         clk_set_parent_nolock(&clk_gpu, &periph_pll_clk);       // default
1845         clk_set_parent_nolock(&aclk_gpu, &periph_pll_clk);      // default
1846         clk_set_parent_nolock(&clk_mac_ref_div, &periph_pll_clk);
1847         clk_set_parent_nolock(&clk_hsadc_div, &periph_pll_clk);
1848 }
1849
1850 void __init rk29_clock_init(void)
1851 {
1852         struct clk_lookup *lk;
1853
1854         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++)
1855                 clk_preinit(lk->clk);
1856
1857         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
1858                 clkdev_add(lk);
1859                 clk_register(lk->clk);
1860         }
1861
1862         clk_recalculate_root_clocks_nolock();
1863
1864         rk29_clock_common_init();
1865
1866         printk(KERN_INFO "Clocking rate (apll/dpll/cpll/ppll/core/aclk/hclk/pclk): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
1867                arm_pll_clk.rate / 1000000, ddr_pll_clk.rate / 1000000, codec_pll_clk.rate / 1000000, periph_pll_clk.rate / 1000000,
1868                clk_core.rate / 1000000, aclk_cpu.rate / 1000000, hclk_cpu.rate / 1000000, pclk_cpu.rate / 1000000);
1869
1870         /*
1871          * Only enable those clocks we will need, let the drivers
1872          * enable other clocks as necessary
1873          */
1874         clk_enable_init_clocks();
1875 }
1876
1877 #ifdef CONFIG_PROC_FS
1878 #include <linux/proc_fs.h>
1879 #include <linux/seq_file.h>
1880
1881 static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
1882 {
1883         struct clk* ck;
1884         int i;
1885         unsigned long rate = clk->rate;
1886
1887         for (i = 0; i < deep; i++)
1888                 seq_printf(s, "    ");
1889
1890         seq_printf(s, "%-9s ", clk->name);
1891
1892         if (clk->mode && (clk->gate_idx < CLK_GATE_MAX)) {
1893                 u32 reg;
1894                 int idx = clk->gate_idx;
1895                 u32 v;
1896
1897                 reg = CRU_CLKGATE0_CON;
1898                 reg += (idx >> 5) << 2;
1899                 idx &= 0x1F;
1900
1901                 v = cru_readl(reg) & (1 << idx);
1902
1903                 seq_printf(s, "%s ", v ? "off" : "on ");
1904         }
1905
1906         if (rate >= 1000000) {
1907                 if (rate % 1000000)
1908                         seq_printf(s, "%ld.%06ld MHz", rate / 1000000, rate % 1000000);
1909                 else
1910                         seq_printf(s, "%ld MHz", rate / 1000000);
1911         } else if (rate >= 1000) {
1912                 if (rate % 1000)
1913                         seq_printf(s, "%ld.%03ld KHz", rate / 1000, rate % 1000);
1914                 else
1915                         seq_printf(s, "%ld KHz", rate / 1000);
1916         } else {
1917                 seq_printf(s, "%ld Hz", rate);
1918         }
1919
1920         seq_printf(s, " usecount = %d", clk->usecount);
1921
1922         seq_printf(s, " parent = %s\n", clk->parent ? clk->parent->name : "NULL");
1923
1924         list_for_each_entry(ck, &clocks, node) {
1925                 if (ck->parent == clk)
1926                         dump_clock(s, ck, deep + 1);
1927         }
1928 }
1929
1930 static int proc_clk_show(struct seq_file *s, void *v)
1931 {
1932         struct clk* clk;
1933
1934         mutex_lock(&clocks_mutex);
1935         list_for_each_entry(clk, &clocks, node) {
1936                 if (!clk->parent)
1937                         dump_clock(s, clk, 0);
1938         }
1939         mutex_unlock(&clocks_mutex);
1940
1941         seq_printf(s, "\nRegisters:\n");
1942         seq_printf(s, "APLL     : 0x%08x\n", cru_readl(CRU_APLL_CON));
1943         seq_printf(s, "DPLL     : 0x%08x\n", cru_readl(CRU_DPLL_CON));
1944         seq_printf(s, "CPLL     : 0x%08x\n", cru_readl(CRU_CPLL_CON));
1945         seq_printf(s, "PPLL     : 0x%08x\n", cru_readl(CRU_PPLL_CON));
1946         seq_printf(s, "MODE     : 0x%08x\n", cru_readl(CRU_MODE_CON));
1947         seq_printf(s, "CLKSEL0  : 0x%08x\n", cru_readl(CRU_CLKSEL0_CON));
1948         seq_printf(s, "CLKSEL1  : 0x%08x\n", cru_readl(CRU_CLKSEL1_CON));
1949         seq_printf(s, "CLKSEL2  : 0x%08x\n", cru_readl(CRU_CLKSEL2_CON));
1950         seq_printf(s, "CLKSEL3  : 0x%08x\n", cru_readl(CRU_CLKSEL3_CON));
1951         seq_printf(s, "CLKSEL4  : 0x%08x\n", cru_readl(CRU_CLKSEL4_CON));
1952         seq_printf(s, "CLKSEL5  : 0x%08x\n", cru_readl(CRU_CLKSEL5_CON));
1953         seq_printf(s, "CLKSEL6  : 0x%08x\n", cru_readl(CRU_CLKSEL6_CON));
1954         seq_printf(s, "CLKSEL7  : 0x%08x\n", cru_readl(CRU_CLKSEL7_CON));
1955         seq_printf(s, "CLKSEL8  : 0x%08x\n", cru_readl(CRU_CLKSEL8_CON));
1956         seq_printf(s, "CLKSEL9  : 0x%08x\n", cru_readl(CRU_CLKSEL9_CON));
1957         seq_printf(s, "CLKSEL10 : 0x%08x\n", cru_readl(CRU_CLKSEL10_CON));
1958         seq_printf(s, "CLKSEL11 : 0x%08x\n", cru_readl(CRU_CLKSEL11_CON));
1959         seq_printf(s, "CLKSEL12 : 0x%08x\n", cru_readl(CRU_CLKSEL12_CON));
1960         seq_printf(s, "CLKSEL13 : 0x%08x\n", cru_readl(CRU_CLKSEL13_CON));
1961         seq_printf(s, "CLKSEL14 : 0x%08x\n", cru_readl(CRU_CLKSEL14_CON));
1962         seq_printf(s, "CLKSEL15 : 0x%08x\n", cru_readl(CRU_CLKSEL15_CON));
1963         seq_printf(s, "CLKSEL16 : 0x%08x\n", cru_readl(CRU_CLKSEL16_CON));
1964         seq_printf(s, "CLKSEL17 : 0x%08x\n", cru_readl(CRU_CLKSEL17_CON));
1965         seq_printf(s, "CLKGATE0 : 0x%08x\n", cru_readl(CRU_CLKGATE0_CON));
1966         seq_printf(s, "CLKGATE1 : 0x%08x\n", cru_readl(CRU_CLKGATE1_CON));
1967         seq_printf(s, "CLKGATE2 : 0x%08x\n", cru_readl(CRU_CLKGATE2_CON));
1968         seq_printf(s, "CLKGATE3 : 0x%08x\n", cru_readl(CRU_CLKGATE3_CON));
1969
1970         return 0;
1971 }
1972
1973 static int proc_clk_open(struct inode *inode, struct file *file)
1974 {
1975         return single_open(file, proc_clk_show, NULL);
1976 }
1977
1978 static const struct file_operations proc_clk_fops = {
1979         .open           = proc_clk_open,
1980         .read           = seq_read,
1981         .llseek         = seq_lseek,
1982         .release        = single_release,
1983 };
1984
1985 static int __init clk_proc_init(void)
1986 {
1987         proc_create("clocks", 0, NULL, &proc_clk_fops);
1988         return 0;
1989
1990 }
1991 late_initcall(clk_proc_init);
1992 #endif /* CONFIG_PROC_FS */
1993