1 /* arch/arm/mach-rk29/gpio.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
26 #include <linux/sysdev.h>
28 #include <mach/hardware.h>
29 #include <mach/gpio.h>
30 #include <mach/rk29_iomap.h>
31 #include <mach/iomux.h>
35 #define to_rk29_gpio_chip(c) container_of(c, struct rk29_gpio_chip, chip)
37 struct rk29_gpio_chip {
38 struct gpio_chip chip;
41 unsigned char __iomem *regbase; /* Base of register bank */
47 static struct lock_class_key gpio_lock_class;
49 static void rk29_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
50 static void rk29_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
51 static int rk29_gpiolib_get(struct gpio_chip *chip, unsigned offset);
52 static int rk29_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val);
53 static int rk29_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset);
54 static int rk29_gpiolib_PullUpDown(struct gpio_chip *chip, unsigned offset, unsigned enable);
55 static int rk29_gpiolib_to_irq(struct gpio_chip *chip,unsigned offset);
57 #define RK29_GPIO_CHIP(ID) \
60 .label = "gpio" #ID, \
61 .direction_input = rk29_gpiolib_direction_input, \
62 .direction_output = rk29_gpiolib_direction_output, \
63 .get = rk29_gpiolib_get, \
64 .set = rk29_gpiolib_set, \
65 .pull_updown = rk29_gpiolib_PullUpDown, \
66 .dbg_show = rk29_gpiolib_dbg_show, \
67 .to_irq = rk29_gpiolib_to_irq, \
68 .base = PIN_BASE + ID*NUM_GROUP, \
72 .irq = IRQ_GPIO##ID, \
73 .regbase = (unsigned char __iomem *) RK29_GPIO##ID##_BASE, \
76 static struct rk29_gpio_chip rk29gpio_chip[] = {
86 static inline void rk29_gpio_write(unsigned char __iomem *regbase, unsigned int regOff,unsigned int val)
88 __raw_writel(val,regbase + regOff);
91 static inline unsigned int rk29_gpio_read(unsigned char __iomem *regbase, unsigned int regOff)
93 return __raw_readl(regbase + regOff);
96 static inline void rk29_gpio_bitOp(unsigned char __iomem *regbase, unsigned int regOff,unsigned int mask,unsigned char opFlag)
98 unsigned int valTemp = 0;
100 if(opFlag == 0)//¶Ô¼Ä´æÆ÷ÏàӦλ½øÐÐÓë0²Ù×÷
102 valTemp = rk29_gpio_read(regbase,regOff);
104 rk29_gpio_write(regbase,regOff,valTemp);
106 else if(opFlag == 1)//¶Ô¼Ä´æÆ÷ÏàӦλ½øÐлò1²Ù×÷
108 valTemp = rk29_gpio_read(regbase,regOff);
110 rk29_gpio_write(regbase,regOff,valTemp);
114 static inline struct gpio_chip *pin_to_gpioChip(unsigned pin)
121 if (likely(pin < MAX_BANK))
122 return &(rk29gpio_chip[pin].chip);
126 static inline unsigned pin_to_mask(unsigned pin)
131 return 1ul << (pin % NUM_GROUP);
134 static inline unsigned offset_to_mask(unsigned offset)
136 return 1ul << (offset % NUM_GROUP);
139 static int GPIOSetPinLevel(struct gpio_chip *chip, unsigned int mask,eGPIOPinLevel_t level)
141 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
142 unsigned char __iomem *gpioRegBase = rk29_gpio->regbase;
145 if(!rk29_gpio || !gpioRegBase)
150 local_irq_save(flags);
151 rk29_gpio_bitOp(gpioRegBase,GPIO_SWPORT_DDR,mask,1);
152 rk29_gpio_bitOp(gpioRegBase,GPIO_SWPORT_DR,mask,level);
153 local_irq_restore(flags);
158 static int GPIOGetPinLevel(struct gpio_chip *chip, unsigned int mask)
160 unsigned int valTemp;
161 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
162 unsigned char __iomem *gpioRegBase = rk29_gpio->regbase;
164 if(!rk29_gpio || !gpioRegBase)
169 valTemp = rk29_gpio_read(gpioRegBase,GPIO_EXT_PORT);
170 return ((valTemp & mask) != 0);
173 static int GPIOSetPinDirection(struct gpio_chip *chip, unsigned int mask,eGPIOPinDirection_t direction)
175 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
176 unsigned char __iomem *gpioRegBase = rk29_gpio->regbase;
179 if(!rk29_gpio || !gpioRegBase)
184 local_irq_save(flags);
185 rk29_gpio_bitOp(gpioRegBase,GPIO_SWPORT_DDR,mask,direction);
186 /* Enable debounce may halt cpu on wfi, disable it by default */
187 //rk29_gpio_bitOp(gpioRegBase,GPIO_DEBOUNCE,mask,1);
188 local_irq_restore(flags);
193 static int GPIOEnableIntr(struct gpio_chip *chip, unsigned int mask)
195 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
196 unsigned char __iomem *gpioRegBase = rk29_gpio->regbase;
198 if(!rk29_gpio || !gpioRegBase)
203 rk29_gpio_bitOp(gpioRegBase,GPIO_INTEN,mask,1);
208 static int GPIODisableIntr(struct gpio_chip *chip, unsigned int mask)
210 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
211 unsigned char __iomem *gpioRegBase = rk29_gpio->regbase;
213 if(!rk29_gpio || !gpioRegBase)
218 rk29_gpio_bitOp(gpioRegBase,GPIO_INTEN,mask,0);
223 static int GPIOSetIntrType(struct gpio_chip *chip, unsigned int mask, eGPIOIntType_t IntType)
225 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
226 unsigned char __iomem *gpioRegBase = rk29_gpio->regbase;
228 if(!rk29_gpio || !gpioRegBase)
236 rk29_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,0);
237 rk29_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,0);
240 rk29_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,0);
241 rk29_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,1);
243 case GPIOEdgelFalling:
244 rk29_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,1);
245 rk29_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,0);
247 case GPIOEdgelRising:
248 rk29_gpio_bitOp(gpioRegBase,GPIO_INTTYPE_LEVEL,mask,1);
249 rk29_gpio_bitOp(gpioRegBase,GPIO_INT_POLARITY,mask,1);
257 static int gpio_irq_set_wake(unsigned int irq, unsigned int on)
259 unsigned int pin = irq_to_gpio(irq);
260 unsigned bank = (pin - PIN_BASE) / NUM_GROUP;
261 struct rk29_gpio_chip *rk29_gpio;
262 unsigned mask = pin_to_mask(pin);
264 if (unlikely(bank >= MAX_BANK))
267 rk29_gpio = &rk29gpio_chip[bank];
269 rk29_gpio->suspend_wakeup |= mask;
271 rk29_gpio->suspend_wakeup &= ~mask;
273 set_irq_wake(rk29_gpio->irq, on);
278 static int gpio_irq_type(unsigned irq, unsigned type)
280 unsigned int pin = irq_to_gpio(irq);
281 struct gpio_chip *chip = pin_to_gpioChip(pin);
282 unsigned mask = pin_to_mask(pin);
286 //ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬
287 GPIOSetPinDirection(chip,mask,GPIO_IN);
292 case IRQ_TYPE_EDGE_RISING:
293 GPIOSetIntrType(chip,mask,GPIOEdgelRising);
295 case IRQ_TYPE_EDGE_FALLING:
296 GPIOSetIntrType(chip,mask,GPIOEdgelFalling);
298 case IRQ_TYPE_EDGE_BOTH:
300 case IRQ_TYPE_LEVEL_HIGH:
301 GPIOSetIntrType(chip,mask,GPIOLevelHigh);
303 case IRQ_TYPE_LEVEL_LOW:
304 GPIOSetIntrType(chip,mask,GPIOLevelLow);
310 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
311 __set_irq_handler_unlocked(irq, handle_level_irq);
312 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
313 __set_irq_handler_unlocked(irq, handle_edge_irq);
318 static int GPIOAckIntr(struct gpio_chip *chip, unsigned int mask)
320 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
321 unsigned char __iomem *gpioRegBase = rk29_gpio->regbase;
323 if(!rk29_gpio || !gpioRegBase)
328 rk29_gpio_bitOp(gpioRegBase,GPIO_PORTS_EOI,mask,1);
332 static void gpio_irq_unmask(unsigned irq)
334 unsigned int pin = irq_to_gpio(irq);
335 struct gpio_chip *chip = pin_to_gpioChip(pin);
336 unsigned mask = pin_to_mask(pin);
339 GPIOEnableIntr(chip,mask);
342 static void gpio_irq_mask(unsigned irq)
344 unsigned int pin = irq_to_gpio(irq);
345 struct gpio_chip *chip = pin_to_gpioChip(pin);
346 unsigned mask = pin_to_mask(pin);
349 GPIODisableIntr(chip,mask);
352 static void gpio_ack_irq(u32 irq)
354 unsigned int pin = irq_to_gpio(irq);
355 struct gpio_chip *chip = pin_to_gpioChip(pin);
356 unsigned mask = pin_to_mask(pin);
359 GPIOAckIntr(chip,mask);
362 static int GPIOPullUpDown(struct gpio_chip *chip, unsigned int offset, unsigned enable)
364 unsigned int temp = 0;
365 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
366 unsigned char __iomem *pGrfRegBase = (unsigned char __iomem *)RK29_GRF_BASE;
369 if(!rk29_gpio || !pGrfRegBase)
379 local_irq_save(flags);
380 temp = __raw_readl(pGrfRegBase + 0x78 +(rk29_gpio->id)*4);
384 temp &= ~(1<<offset);
386 __raw_writel(temp,pGrfRegBase + 0x78 +(rk29_gpio->id)*4);
387 local_irq_restore(flags);
393 static int rk29_gpiolib_direction_output(struct gpio_chip *chip,unsigned offset, int val)
395 unsigned mask = offset_to_mask(offset);
397 if(GPIOSetPinDirection(chip,mask,GPIO_OUT) == 0)
399 return GPIOSetPinLevel(chip,mask,val);
407 static int rk29_gpiolib_direction_input(struct gpio_chip *chip,unsigned offset)
409 unsigned mask = offset_to_mask(offset);
411 return GPIOSetPinDirection(chip,mask,GPIO_IN);
415 static int rk29_gpiolib_get(struct gpio_chip *chip, unsigned offset)
417 unsigned mask = offset_to_mask(offset);
419 return GPIOGetPinLevel(chip,mask);
422 static void rk29_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
424 unsigned mask = offset_to_mask(offset);
426 GPIOSetPinLevel(chip,mask,val);
429 static int rk29_gpiolib_PullUpDown(struct gpio_chip *chip, unsigned offset, unsigned enable)
431 return GPIOPullUpDown(chip, offset, enable);
434 static int rk29_gpiolib_to_irq(struct gpio_chip *chip,
437 struct rk29_gpio_chip *rk29_gpio = to_rk29_gpio_chip(chip);
444 return offset + NR_IRQS;
447 static void rk29_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
452 for (i = 0; i < chip->ngpio; i++) {
453 unsigned pin = chip->base + i;
454 struct gpio_chip *chip = pin_to_gpioChip(pin);
455 unsigned mask = pin_to_mask(pin);
456 const char *gpio_label;
461 gpio_label = gpiochip_is_requested(chip, i);
463 seq_printf(s, "[%s] GPIO%s%d: ",
464 gpio_label, chip->label, i);
468 seq_printf(s, "!chip || !mask\t");
472 GPIOSetPinDirection(chip,mask,GPIO_IN);
473 seq_printf(s, "pin=%d,level=%d\t", pin,GPIOGetPinLevel(chip,mask));
479 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
482 struct rk29_gpio_chip *rk29_gpio;
485 rk29_gpio = get_irq_chip_data(irq+13);
487 // temporarily mask parent IRQ
488 desc->chip->mask(irq);
490 desc->chip->ack(irq);
492 isr = rk29_gpio_read(rk29_gpio->regbase, GPIO_INT_STATUS);
494 gpio_irq = gpio_to_irq(rk29_gpio->chip.base);
497 int irqoffset = fls(isr) - 1;
498 generic_handle_irq(gpio_irq + irqoffset);
499 isr &= ~(1 << irqoffset);
502 desc->chip->unmask(irq);
503 /* now it may re-trigger */
506 static struct irq_chip rk29gpio_irqchip = {
509 .disable = gpio_irq_mask,
510 .mask = gpio_irq_mask,
511 .unmask = gpio_irq_unmask,
512 .set_type = gpio_irq_type,
513 .set_wake = gpio_irq_set_wake,
516 static void __init rk29_gpio_irq_setup(void)
518 unsigned int i, j, pin;
519 struct rk29_gpio_chip *this;
521 this = rk29gpio_chip;
523 for (i = 0; i < MAX_BANK; i++) {
524 rk29_gpio_write(this->regbase,GPIO_INTEN,0);
525 for (j = 0; j < 32; j++) {
526 lockdep_set_class(&irq_desc[pin+j].lock, &gpio_lock_class);
527 set_irq_chip(pin+j, &rk29gpio_irqchip);
528 set_irq_handler(pin+j, handle_level_irq);
529 set_irq_flags(pin+j, IRQF_VALID);
532 set_irq_chip_data(NR_AIC_IRQS + this->id, this);
533 set_irq_chained_handler(this->irq, gpio_irq_handler);
537 printk("rk29_gpio_irq_setup: %d gpio irqs in 7 banks\n", pin - PIN_BASE);
540 void __init rk29_gpio_init(void)
543 struct rk29_gpio_chip *rk29_gpio;
545 for (i = 0; i < MAX_BANK; i++) {
546 rk29_gpio = &rk29gpio_chip[i];
547 rk29_gpio->clk = clk_get(NULL, rk29_gpio->chip.label);
548 clk_enable(rk29_gpio->clk);
549 gpiochip_add(&rk29_gpio->chip);
551 rk29_gpio_irq_setup();
554 __weak void rk29_setgpio_suspend_board(void);
556 __weak void rk29_setgpio_resume_board(void);
559 static int rk29_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
563 rk29_setgpio_suspend_board();
565 for (i = 0; i < MAX_BANK; i++) {
566 struct rk29_gpio_chip *rk29_gpio = &rk29gpio_chip[i];
568 rk29_gpio->saved_wakeup = rk29_gpio_read(rk29_gpio->regbase, GPIO_INTEN);
569 rk29_gpio_write(rk29_gpio->regbase, GPIO_INTEN, rk29_gpio->suspend_wakeup);
571 if (!rk29_gpio->suspend_wakeup)
572 clk_disable(rk29_gpio->clk);
578 static int rk29_gpio_resume(struct sys_device *dev)
581 for (i = 0; i < MAX_BANK; i++) {
582 struct rk29_gpio_chip *rk29_gpio = &rk29gpio_chip[i];
584 if (!rk29_gpio->suspend_wakeup)
585 clk_enable(rk29_gpio->clk);
587 /* keep enable for resume irq */
588 rk29_gpio_write(rk29_gpio->regbase, GPIO_INTEN, rk29_gpio->saved_wakeup | (rk29_gpio->suspend_wakeup & rk29_gpio_read(rk29_gpio->regbase, GPIO_INT_STATUS)));
590 rk29_setgpio_resume_board();
594 static struct sysdev_class rk29_gpio_sysclass = {
596 .suspend = rk29_gpio_suspend,
597 .resume = rk29_gpio_resume,
600 static struct sys_device rk29_gpio_device = {
601 .cls = &rk29_gpio_sysclass,
604 static int __init rk29_gpio_sysinit(void)
606 int ret = sysdev_class_register(&rk29_gpio_sysclass);
608 ret = sysdev_register(&rk29_gpio_device);
612 arch_initcall(rk29_gpio_sysinit);