arch/arm/mach-rk29/pm.c

   1 #define DEBUG
   2
   3 #include <linux/clk.h>
   4 #include <linux/delay.h>
   5 #include <linux/err.h>
   6 #include <linux/kernel.h>
   7 #include <linux/init.h>
   8 #include <linux/pm.h>
   9 #include <linux/suspend.h>
  10 #include <linux/random.h>
  11 #include <linux/crc32.h>
  12 #ifdef CONFIG_RK29_PWM_REGULATOR
  13 #include <linux/regulator/rk29-pwm-regulator.h>
  14 #endif
  15 #include <linux/io.h>
  16 #include <linux/wakelock.h>
  17 #include <asm/tlbflush.h>
  18 #include <asm/hardware/gic.h>
  19
  20 #include <mach/rk29_iomap.h>
  21 #include <mach/cru.h>
  22 #include <mach/pmu.h>
  23 #include <mach/board.h>
  24 #include <mach/system.h>
  25 #include <mach/sram.h>
  26 #include <mach/gpio.h>
  27 #include <mach/ddr.h>
  28 #include <mach/memtester.h>
  29
  30 #define cru_readl(offset)       readl(RK29_CRU_BASE + offset)
  31 #define cru_writel(v, offset)   do { writel(v, RK29_CRU_BASE + offset); readl(RK29_CRU_BASE + offset); } while (0)
  32 #define pmu_readl(offset)       readl(RK29_PMU_BASE + offset)
  33 #define pmu_writel(v, offset)   do { writel(v, RK29_PMU_BASE + offset); readl(RK29_PMU_BASE + offset); } while (0)
  34 static unsigned long save_sp;
  35
  36 #define LOOPS_PER_USEC  13
  37 #define LOOP(loops) do { int i = loops; barrier(); while (i--) barrier(); } while (0)
  38
  39 static inline void delay_500ns(void)
  40 {
  41         LOOP(LOOPS_PER_USEC);
  42 }
  43
  44 static inline void delay_300us(void)
  45 {
  46         LOOP(300 * LOOPS_PER_USEC);
  47 }
  48
  49 #ifdef DEBUG
  50 static void/* inline*/ __sramfunc printch(char byte)
  51 {
  52         unsigned long flags;
  53         u32 gate1, gate2;
  54
  55         local_irq_save(flags);
  56         gate1 = cru_readl(CRU_CLKGATE1_CON);
  57         gate2 = cru_readl(CRU_CLKGATE2_CON);
  58         cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
  59         cru_writel(gate2 & ~(1 << CLK_GATE_UART1 % 32), CRU_CLKGATE2_CON);
  60         delay_500ns();
  61
  62         writel(byte, RK29_UART1_BASE);
  63
  64         /* loop check LSR[6], Transmitter Empty bit */
  65         while (!(readl(RK29_UART1_BASE + 0x14) & 0x40))
  66                 barrier();
  67
  68         cru_writel(gate2, CRU_CLKGATE2_CON);
  69         cru_writel(gate1, CRU_CLKGATE1_CON);
  70         local_irq_restore(flags);
  71         if (byte == '\n')
  72                 printch('\r');
  73 }
  74
  75 static void __sramfunc printascii(const char *s)
  76 {
  77         while (*s) {
  78                 if (*s == '\n')
  79                 {
  80                     printch('\r');
  81                 }
  82             printch(*s);
  83             s++;
  84         }
  85 }
  86 void print(const char *s)
  87 {
  88     printascii(s);
  89 }
  90
  91 void __sramfunc print_Hex(unsigned int hex)
  92 {
  93         int i = 8;
  94         printch('0');
  95         printch('x');
  96         while (i--) {
  97                 unsigned char c = (hex & 0xF0000000) >> 28;
  98                 printch(c < 0xa ? c + '0' : c - 0xa + 'a');
  99                 hex <<= 4;
 100         }
 101 }
 102
 103 void __sramfunc print_Dec (uint32_t n)
 104 {
 105     if (n >= 10)
 106     {
 107         print_Dec(n / 10);
 108         n %= 10;
 109     }
 110     printch((char)(n + '0'));
 111 }
 112
 113 void print_Dec_3(uint32_t value)
 114 {
 115     if(value<10)
 116     {
 117         print("  ");
 118     }
 119     else if(value<100)
 120     {
 121         print(" ");
 122     }
 123     else
 124     {
 125     }
 126     print_Dec(value);
 127 }
 128
 129 static void /* inline*/ __sramfunc printhex(unsigned int hex)
 130 {
 131         int i = 8;
 132         printch('0');
 133         printch('x');
 134         while (i--) {
 135                 unsigned char c = (hex & 0xF0000000) >> 28;
 136                 printch(c < 0xa ? c + '0' : c - 0xa + 'a');
 137                 hex <<= 4;
 138         }
 139 }
 140 #else
 141 static void inline printch(char byte) {}
 142 static void inline printascii(const char *s) {}
 143 static void inline printhex(unsigned int hex) {}
 144 #endif /* DEBUG */
 145
 146 #ifdef CONFIG_RK29_PWM_REGULATOR
 147 #define pwm_write_reg(addr, val)        __raw_writel(val, addr + (RK29_PWM_BASE + 2*0x10))
 148 #define pwm_read_reg(addr)              __raw_readl(addr + (RK29_PWM_BASE + 2*0x10))
 149
 150 static u32 __sramdata pwm_lrc, pwm_hrc;
 151 static void __sramfunc rk29_set_core_voltage(int uV)
 152 {
 153         u32 gate1;
 154
 155         gate1 = cru_readl(CRU_CLKGATE1_CON);
 156         cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
 157
 158         /* iomux pwm2 */
 159         writel((readl(RK29_GRF_BASE + 0x58) & ~(0x3<<6)) | (0x2<<6), RK29_GRF_BASE + 0x58);
 160
 161         if (uV) {
 162                 pwm_lrc = pwm_read_reg(PWM_REG_LRC);
 163                 pwm_hrc = pwm_read_reg(PWM_REG_HRC);
 164         }
 165
 166         pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_RESET);
 167         if (uV == 1000000) {
 168                 pwm_write_reg(PWM_REG_LRC, 12);
 169                 pwm_write_reg(PWM_REG_HRC, 10);
 170         } else {
 171                 pwm_write_reg(PWM_REG_LRC, pwm_lrc);
 172                 pwm_write_reg(PWM_REG_HRC, pwm_hrc);
 173         }
 174         pwm_write_reg(PWM_REG_CNTR, 0);
 175         pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN);
 176
 177         LOOP(5 * 1000 * LOOPS_PER_USEC); /* delay 5ms */
 178
 179         cru_writel(gate1, CRU_CLKGATE1_CON);
 180 }
 181 #endif /* CONFIG_RK29_PWM_REGULATOR */
 182 /*volatile __sramdata */int ddr_debug;
 183 module_param(ddr_debug, int, 0644);
 184 #if 1
 185 static int inline calc_crc32(u32 addr, size_t len)
 186 {
 187      return crc32_le(~0,(const unsigned char *)addr,len);
 188 }
 189 void __sramfunc ddr_testmode(void)
 190 {
 191     int32_t g_crc1,g_crc2;
 192     uint32_t nMHz;
 193     uint32_t n = 0;
 194     extern char _stext[], _etext[];
 195     if(ddr_debug == 1)
 196     {
 197         for (;;)
 198         {
 199                 printch(' ');
 200                 printch('8');
 201                 printch('8');
 202                 printch('8');
 203                 printch(' ');
 204             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 205             nMHz = 333 + (random32()>>25);
 206             if(nMHz > 402)
 207                 nMHz = 402;
 208                 printhex(nMHz);
 209                 printch(' ');
 210                 printhex(n++);
 211             //ddr_print("%s change freq to: %d MHz\n", __func__, nMHz);
 212             ddr_change_freq(nMHz);
 213             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 214             if (g_crc1!=g_crc2)
 215             {
 216                     printch(' ');
 217                     printch('f');
 218                     printch('a');
 219                     printch('i');
 220                     printch('l');
 221                 }
 222                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 223            //     printascii("change freq success\n");
 224         }
 225     }
 226     else if(ddr_debug == 2)
 227     {
 228         for (;;)
 229         {
 230                 printch(' ');
 231                 printch('9');
 232                 printch('9');
 233                 printch('9');
 234                 printch(' ');
 235             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 236             nMHz = (random32()>>13);// 16.7s max
 237             ddr_suspend();
 238             delayus(nMHz);
 239             ddr_resume();
 240                 printhex(nMHz);
 241                 printch(' ');
 242                 printhex(n++);
 243             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 244             if (g_crc1!=g_crc2)
 245             {
 246                     printch(' ');
 247                     printch('f');
 248                     printch('a');
 249                     printch('i');
 250                     printch('l');
 251                 }
 252               // ddr_print("check image crc32 fail!, count:%d\n", n++);
 253             //    printascii("self refresh fail\n");
 254             //else
 255                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 256             //    printascii("self refresh success\n");
 257         }
 258     }
 259     else if(ddr_debug == 3)
 260     {
 261         memtester();
 262     }
 263 }
 264 #else
 265 void __sramfunc ddr_testmode(void)
 266 {}
 267
 268 #endif
 269 static void __sramfunc rk29_sram_suspend(void)
 270 {
 271         u32 clksel0;
 272
 273     if((ddr_debug == 1)||(ddr_debug == 2))
 274         ddr_testmode();
 275         printch('5');
 276         ddr_suspend();
 277
 278         printch('6');
 279 #ifdef CONFIG_RK29_PWM_REGULATOR
 280         rk29_set_core_voltage(1000000);
 281 #endif
 282         printch('7');
 283         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 284         /* set arm clk 24MHz/32 = 750KHz */
 285         cru_writel(clksel0 | 0x1F, CRU_CLKSEL0_CON);
 286
 287         printch('8');
 288         asm("wfi");
 289         printch('8');
 290
 291         /* resume arm clk */
 292         cru_writel(clksel0, CRU_CLKSEL0_CON);
 293         printch('7');
 294
 295 #ifdef CONFIG_RK29_PWM_REGULATOR
 296         rk29_set_core_voltage(0);
 297 #endif
 298         printch('6');
 299
 300         ddr_resume();
 301         printch('5');
 302 }
 303
 304 static void noinline rk29_suspend(void)
 305 {
 306         DDR_SAVE_SP(save_sp);
 307         rk29_sram_suspend();
 308         DDR_RESTORE_SP(save_sp);
 309 }
 310
 311 static void dump_irq(void)
 312 {
 313         u32 irq_gpio = (readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8) >> 23) & 0x7F;
 314         printk("wakeup irq: %08x %08x %01x\n",
 315                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 4),
 316                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8),
 317                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 12) & 0xf);
 318         if (irq_gpio & 1)
 319                 printk("wakeup gpio0: %08x\n", readl(RK29_GPIO0_BASE + GPIO_INT_STATUS));
 320         if (irq_gpio & 2)
 321                 printk("wakeup gpio1: %08x\n", readl(RK29_GPIO1_BASE + GPIO_INT_STATUS));
 322         if (irq_gpio & 4)
 323                 printk("wakeup gpio2: %08x\n", readl(RK29_GPIO2_BASE + GPIO_INT_STATUS));
 324         if (irq_gpio & 8)
 325                 printk("wakeup gpio3: %08x\n", readl(RK29_GPIO3_BASE + GPIO_INT_STATUS));
 326         if (irq_gpio & 0x10)
 327                 printk("wakeup gpio4: %08x\n", readl(RK29_GPIO4_BASE + GPIO_INT_STATUS));
 328         if (irq_gpio & 0x20)
 329                 printk("wakeup gpio5: %08x\n", readl(RK29_GPIO5_BASE + GPIO_INT_STATUS));
 330         if (irq_gpio & 0x40)
 331                 printk("wakeup gpio6: %08x\n", readl(RK29_GPIO6_BASE + GPIO_INT_STATUS));
 332 }
 333
 334 static int rk29_pm_enter(suspend_state_t state)
 335 {
 336         u32 apll, cpll, gpll, mode, clksel0;
 337         u32 clkgate[4];
 338
 339         // memory teseter
 340     if(ddr_debug == 3)
 341         ddr_testmode();
 342
 343         printch('0');
 344
 345 #ifdef CONFIG_RK29_PWM_REGULATOR
 346         /* touch TLB */
 347         flush_tlb_all();
 348         readl(RK29_PWM_BASE);
 349         readl(RK29_GRF_BASE);
 350 #endif
 351
 352         /* disable clock */
 353         clkgate[0] = cru_readl(CRU_CLKGATE0_CON);
 354         clkgate[1] = cru_readl(CRU_CLKGATE1_CON);
 355         clkgate[2] = cru_readl(CRU_CLKGATE2_CON);
 356         clkgate[3] = cru_clkgate3_con_mirror;
 357         cru_writel(~((1 << CLK_GATE_CORE)
 358                    | (1 << CLK_GATE_ACLK_CPU)
 359                    | (1 << CLK_GATE_ACLK_CPU2)
 360                    | (1 << CLK_GATE_PCLK_CPU)
 361                    | (1 << CLK_GATE_GIC)
 362                    | (1 << CLK_GATE_INTMEM)
 363                    | (1 << CLK_GATE_DDR_PHY)
 364                    | (1 << CLK_GATE_DDR_REG)
 365                    | (1 << CLK_GATE_DDR_CPU)
 366                    | (1 << CLK_GATE_GPIO0)
 367                    | (1 << CLK_GATE_RTC)
 368                    | (1 << CLK_GATE_GRF)
 369                    ) | clkgate[0], CRU_CLKGATE0_CON);
 370         cru_writel(~0, CRU_CLKGATE1_CON);
 371         cru_writel(~((1 << CLK_GATE_GPIO1 % 32)
 372                    | (1 << CLK_GATE_GPIO2 % 32)
 373                    | (1 << CLK_GATE_GPIO3 % 32)
 374                    | (1 << CLK_GATE_GPIO4 % 32)
 375                    | (1 << CLK_GATE_GPIO5 % 32)
 376                    | (1 << CLK_GATE_GPIO6 % 32)
 377                    | (1 << CLK_GATE_PWM % 32)
 378                    ) | clkgate[2], CRU_CLKGATE2_CON);
 379         cru_writel(~0, CRU_CLKGATE3_CON);
 380         printch('1');
 381
 382         mode = cru_readl(CRU_MODE_CON);
 383         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 384
 385         /* suspend arm pll */
 386         apll = cru_readl(CRU_APLL_CON);
 387         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 388         cru_writel(apll | PLL_BYPASS, CRU_APLL_CON);
 389         cru_writel(apll | PLL_PD | PLL_BYPASS, CRU_APLL_CON);
 390         delay_500ns();
 391         /* set core = aclk_cpu = hclk_cpu = pclk_cpu = 24MHz */
 392         cru_writel(clksel0 & 0xFFFFF000, CRU_CLKSEL0_CON);
 393         printch('2');
 394
 395         /* suspend codec pll */
 396         cpll = cru_readl(CRU_CPLL_CON);
 397         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 398         cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 399         cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 400         delay_500ns();
 401         printch('3');
 402
 403         /* suspend general pll */
 404         gpll = cru_readl(CRU_GPLL_CON);
 405         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 406         cru_writel(gpll | PLL_BYPASS, CRU_GPLL_CON);
 407         cru_writel(gpll | PLL_PD | PLL_BYPASS, CRU_GPLL_CON);
 408         delay_500ns();
 409         /* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
 410         cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
 411
 412         printch('4');
 413         rk29_suspend();
 414         printch('4');
 415
 416         /* resume general pll */
 417         cru_writel(gpll, CRU_GPLL_CON);
 418         delay_300us();
 419         /* restore aclk_periph/hclk_periph/pclk_periph */
 420         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0x7FC000), CRU_CLKSEL0_CON);
 421         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | (mode & CRU_GENERAL_MODE_MASK), CRU_MODE_CON);
 422         printch('3');
 423
 424         /* resume codec pll */
 425         cru_writel(cpll, CRU_CPLL_CON);
 426         delay_300us();
 427         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | (mode & CRU_CODEC_MODE_MASK), CRU_MODE_CON);
 428         printch('2');
 429
 430         /* resume arm pll */
 431         cru_writel(apll, CRU_APLL_CON);
 432         delay_300us();
 433         /* restore core/aclk_cpu/hclk_cpu/pclk_cpu */
 434         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0xFFF), CRU_CLKSEL0_CON);
 435         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | (mode & CRU_CPU_MODE_MASK), CRU_MODE_CON);
 436         printch('1');
 437
 438         /* enable clock */
 439         cru_writel(clkgate[0], CRU_CLKGATE0_CON);
 440         cru_writel(clkgate[1], CRU_CLKGATE1_CON);
 441         cru_writel(clkgate[2], CRU_CLKGATE2_CON);
 442         cru_writel(clkgate[3], CRU_CLKGATE3_CON);
 443         printascii("0\n");
 444
 445         dump_irq();
 446         return 0;
 447 }
 448
 449 static int rk29_pm_prepare(void)
 450 {
 451         /* disable entering rk29_idle() by disable_hlt() */
 452         disable_hlt();
 453         return 0;
 454 }
 455
 456 static void rk29_pm_finish(void)
 457 {
 458         enable_hlt();
 459 }
 460
 461 static struct platform_suspend_ops rk29_pm_ops = {
 462         .enter          = rk29_pm_enter,
 463         .valid          = suspend_valid_only_mem,
 464         .prepare        = rk29_pm_prepare,
 465         .finish         = rk29_pm_finish,
 466 };
 467
 468 static void rk29_idle(void)
 469 {
 470         if (!need_resched()) {
 471                 int allow_sleep = 1;
 472 #ifdef CONFIG_HAS_WAKELOCK
 473                 allow_sleep = !has_wake_lock(WAKE_LOCK_IDLE);
 474 #endif
 475                 if (allow_sleep) {
 476                         u32 mode_con = cru_readl(CRU_MODE_CON);
 477                         cru_writel((mode_con & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 478                         arch_idle();
 479                         cru_writel(mode_con, CRU_MODE_CON);
 480                 } else {
 481                         arch_idle();
 482                 }
 483         }
 484         local_irq_enable();
 485 }
 486
 487 static int __init rk29_pm_init(void)
 488 {
 489         suspend_set_ops(&rk29_pm_ops);
 490
 491         /* set idle function */
 492         pm_idle = rk29_idle;
 493         ddr_debug = 0;
 494
 495         return 0;
 496 }
 497 __initcall(rk29_pm_init);