arch/arm/mach-rk29/pm.c

   1 #define DEBUG
   2
   3 #include <linux/clk.h>
   4 #include <linux/delay.h>
   5 #include <linux/err.h>
   6 #include <linux/kernel.h>
   7 #include <linux/init.h>
   8 #include <linux/pm.h>
   9 #include <linux/suspend.h>
  10 #include <linux/random.h>
  11 #include <linux/crc32.h>
  12 #include <linux/io.h>
  13 #include <linux/wakelock.h>
  14 #include <asm/tlbflush.h>
  15 #include <asm/hardware/gic.h>
  16
  17 #include <mach/rk29_iomap.h>
  18 #include <mach/cru.h>
  19 #include <mach/pmu.h>
  20 #include <mach/board.h>
  21 #include <mach/system.h>
  22 #include <mach/sram.h>
  23 #include <mach/gpio.h>
  24 #include <mach/ddr.h>
  25 #include <mach/memtester.h>
  26 #include <mach/iomux.h>
  27 #include <mach/pm-vol.h>
  28
  29 #include <asm/vfp.h>
  30
  31 #define grf_readl(offset) readl(RK29_GRF_BASE + offset)
  32 #define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
  33
  34 static unsigned long save_sp;
  35
  36 static inline void delay_500ns(void)
  37 {
  38         LOOP(LOOPS_PER_USEC);
  39 }
  40
  41 static inline void delay_300us(void)
  42 {
  43         LOOP(300 * LOOPS_PER_USEC);
  44 }
  45
  46 #ifdef DEBUG
  47  void/* inline*/ __sramfunc sram_printch(char byte)
  48 {
  49         unsigned long flags;
  50         u32 gate1, gate2;
  51
  52         local_irq_save(flags);
  53         gate1 = cru_readl(CRU_CLKGATE1_CON);
  54         gate2 = cru_readl(CRU_CLKGATE2_CON);
  55         cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
  56         cru_writel(gate2 & ~(1 << CLK_GATE_UART1 % 32), CRU_CLKGATE2_CON);
  57         delay_500ns();
  58
  59         writel(byte, RK29_UART1_BASE);
  60
  61         /* loop check LSR[6], Transmitter Empty bit */
  62         while (!(readl(RK29_UART1_BASE + 0x14) & 0x40))
  63                 barrier();
  64
  65         cru_writel(gate2, CRU_CLKGATE2_CON);
  66         cru_writel(gate1, CRU_CLKGATE1_CON);
  67         local_irq_restore(flags);
  68         if (byte == '\n')
  69                 sram_printch('\r');
  70 }
  71
  72  void __sramfunc sram_printascii(const char *s)
  73 {
  74         while (*s) {
  75                 if (*s == '\n')
  76                 {
  77                     sram_printch('\r');
  78                 }
  79             sram_printch(*s);
  80             s++;
  81         }
  82 }
  83 void print(const char *s)
  84 {
  85     sram_printascii(s);
  86 }
  87
  88 void __sramfunc print_Hex(unsigned int hex)
  89 {
  90         int i = 8;
  91         sram_printch('0');
  92         sram_printch('x');
  93         while (i--) {
  94                 unsigned char c = (hex & 0xF0000000) >> 28;
  95                 sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
  96                 hex <<= 4;
  97         }
  98 }
  99
 100 void __sramfunc print_Dec (uint32_t n)
 101 {
 102     if (n >= 10)
 103     {
 104         print_Dec(n / 10);
 105         n %= 10;
 106     }
 107     sram_printch((char)(n + '0'));
 108 }
 109
 110 void print_Dec_3(uint32_t value)
 111 {
 112     if(value<10)
 113     {
 114         print("  ");
 115     }
 116     else if(value<100)
 117     {
 118         print(" ");
 119     }
 120     else
 121     {
 122     }
 123     print_Dec(value);
 124 }
 125
 126 static void /* inline*/ __sramfunc printhex(unsigned int hex)
 127 {
 128         int i = 8;
 129         sram_printch('0');
 130         sram_printch('x');
 131         while (i--) {
 132                 unsigned char c = (hex & 0xF0000000) >> 28;
 133                 sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
 134                 hex <<= 4;
 135         }
 136 }
 137 #else
 138 static void inline sram_printch(char byte) {}
 139 static void inline sram_printascii(const char *s) {}
 140 static void inline printhex(unsigned int hex) {}
 141 #endif /* DEBUG */
 142
 143 /*volatile __sramdata */int ddr_debug;
 144 module_param(ddr_debug, int, 0644);
 145 #if 1
 146 static int inline calc_crc32(u32 addr, size_t len)
 147 {
 148      return crc32_le(~0,(const unsigned char *)addr,len);
 149 }
 150 void __sramfunc ddr_testmode(void)
 151 {
 152     int32_t g_crc1,g_crc2;
 153     uint32_t nMHz;
 154     uint32_t n = 0;
 155     extern char _stext[], _etext[];
 156     if(ddr_debug == 1)
 157     {
 158         for (;;)
 159         {
 160                 sram_printch(' ');
 161                 sram_printch('8');
 162                 sram_printch('8');
 163                 sram_printch('8');
 164                 sram_printch(' ');
 165             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 166             nMHz = 333 + (random32()>>25);
 167             if(nMHz > 402)
 168                 nMHz = 402;
 169                 printhex(nMHz);
 170                 sram_printch(' ');
 171                 printhex(n++);
 172             //ddr_print("%s change freq to: %d MHz\n", __func__, nMHz);
 173             ddr_change_freq(nMHz);
 174             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 175             if (g_crc1!=g_crc2)
 176             {
 177                     sram_printch(' ');
 178                     sram_printch('f');
 179                     sram_printch('a');
 180                     sram_printch('i');
 181                     sram_printch('l');
 182                 }
 183                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 184            //     sram_printascii("change freq success\n");
 185         }
 186     }
 187     else if(ddr_debug == 2)
 188     {
 189         for (;;)
 190         {
 191                 sram_printch(' ');
 192                 sram_printch('9');
 193                 sram_printch('9');
 194                 sram_printch('9');
 195                 sram_printch(' ');
 196             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 197             nMHz = (random32()>>13);// 16.7s max
 198             ddr_suspend();
 199             delayus(nMHz);
 200             ddr_resume();
 201                 printhex(nMHz);
 202                 sram_printch(' ');
 203                 printhex(n++);
 204             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 205             if (g_crc1!=g_crc2)
 206             {
 207                     sram_printch(' ');
 208                     sram_printch('f');
 209                     sram_printch('a');
 210                     sram_printch('i');
 211                     sram_printch('l');
 212                 }
 213               // ddr_print("check image crc32 fail!, count:%d\n", n++);
 214             //    sram_printascii("self refresh fail\n");
 215             //else
 216                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 217             //    sram_printascii("self refresh success\n");
 218         }
 219     }
 220     else if(ddr_debug == 3)
 221     {
 222         memtester();
 223     }
 224 }
 225 #else
 226 void __sramfunc ddr_testmode(void)
 227 {}
 228
 229 #endif
 230 void __sramfunc pm_clk_switch_32k(void);
 231
 232 void __sramfunc pm_wfi(void)
 233 {
 234         u32 clksel0;
 235         sram_printch('7');
 236         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 237         /* set arm clk 24MHz/32 = 750KHz */
 238         cru_writel(clksel0 | 0x1F, CRU_CLKSEL0_CON);
 239
 240         sram_printch('8');
 241         dsb();
 242         asm("wfi");
 243         sram_printch('8');
 244
 245         /* resume arm clk */
 246         cru_writel(clksel0, CRU_CLKSEL0_CON);
 247         sram_printch('7');
 248
 249
 250 }
 251
 252 static void __sramfunc rk29_sram_suspend(void)
 253 {
 254         u32 vol;
 255
 256         if ((ddr_debug == 1) || (ddr_debug == 2))
 257                 ddr_testmode();
 258
 259         sram_printch('5');
 260         ddr_suspend();
 261
 262         sram_printch('6');
 263         vol=rk29_suspend_voltage_set(1000000);
 264 #ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
 265         pm_clk_switch_32k();
 266 #else
 267         pm_wfi();
 268 #endif
 269         rk29_suspend_voltage_resume(vol);
 270         sram_printch('6');
 271
 272         ddr_resume();
 273         sram_printch('5');
 274 }
 275
 276 static void noinline rk29_suspend(void)
 277 {
 278         DDR_SAVE_SP(save_sp);
 279         rk29_sram_suspend();
 280         DDR_RESTORE_SP(save_sp);
 281 }
 282
 283 static void dump_irq(void)
 284 {
 285         u32 irq_gpio = (readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8) >> 23) & 0x7F;
 286         printk("wakeup irq: %08x %08x %01x\n",
 287                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 4),
 288                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8),
 289                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 12) & 0xf);
 290         if (irq_gpio & 1)
 291                 printk("wakeup gpio0: %08x\n", readl(RK29_GPIO0_BASE + GPIO_INT_STATUS));
 292         if (irq_gpio & 2)
 293                 printk("wakeup gpio1: %08x\n", readl(RK29_GPIO1_BASE + GPIO_INT_STATUS));
 294         if (irq_gpio & 4)
 295                 printk("wakeup gpio2: %08x\n", readl(RK29_GPIO2_BASE + GPIO_INT_STATUS));
 296         if (irq_gpio & 8)
 297                 printk("wakeup gpio3: %08x\n", readl(RK29_GPIO3_BASE + GPIO_INT_STATUS));
 298         if (irq_gpio & 0x10)
 299                 printk("wakeup gpio4: %08x\n", readl(RK29_GPIO4_BASE + GPIO_INT_STATUS));
 300         if (irq_gpio & 0x20)
 301                 printk("wakeup gpio5: %08x\n", readl(RK29_GPIO5_BASE + GPIO_INT_STATUS));
 302         if (irq_gpio & 0x40)
 303                 printk("wakeup gpio6: %08x\n", readl(RK29_GPIO6_BASE + GPIO_INT_STATUS));
 304 }
 305
 306 #define DUMP_GPIO_INTEN(ID) \
 307 do { \
 308         u32 en = readl(RK29_GPIO##ID##_BASE + GPIO_INTEN); \
 309         if (en) { \
 310                 sram_printascii("GPIO" #ID "_INTEN: "); \
 311                 printhex(en); \
 312                 sram_printch('\n'); \
 313         } \
 314 } while (0)
 315
 316 static void dump_inten(void)
 317 {
 318         DUMP_GPIO_INTEN(0);
 319         DUMP_GPIO_INTEN(1);
 320         DUMP_GPIO_INTEN(2);
 321         DUMP_GPIO_INTEN(3);
 322         DUMP_GPIO_INTEN(4);
 323         DUMP_GPIO_INTEN(5);
 324         DUMP_GPIO_INTEN(6);
 325 }
 326
 327
 328
 329 #define DUMP_GPIO_PULL(ID) \
 330 do { \
 331         u32 state = readl(RK29_GRF_BASE + GRF_GPIO0_PULL + (ID<<2)); \
 332         sram_printascii("GPIO" #ID "_PULL: "); \
 333         printhex(state); \
 334         sram_printch('\n'); \
 335 } while (0)
 336
 337 static void dump_io_pull(void)
 338 {
 339         DUMP_GPIO_PULL(0);
 340         DUMP_GPIO_PULL(1);
 341         DUMP_GPIO_PULL(2);
 342         DUMP_GPIO_PULL(3);
 343         DUMP_GPIO_PULL(4);
 344         DUMP_GPIO_PULL(5);
 345         DUMP_GPIO_PULL(6);
 346 }
 347 #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 348 /*******************************neon powermain***********************/
 349 #define pmu_read(offset)                readl(RK29_PMU_BASE + (offset))
 350 #define pmu_write(offset, value)        writel((value), RK29_PMU_BASE + (offset))
 351 #define PMU_PG_CON 0x10
 352 #define vfpreg(_vfp_) #_vfp_
 353
 354 #define fmrx(_vfp_) ({                  \
 355         u32 __v;                        \
 356         asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx   %0, " #_vfp_    \
 357             : "=r" (__v) : : "cc");     \
 358         __v;                            \
 359  })
 360
 361 #define fmxr(_vfp_,_var_)               \
 362         asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr   " #_vfp_ ", %0" \
 363            : : "r" (_var_) : "cc")
 364 extern void vfp_save_state(void *location, u32 fpexc);
 365 extern void vfp_load_state(void *location, u32 fpexc);
 366 // extern  __sramdata u64  saveptr[33];
 367 static u32  saveptr[2][60]={};
 368 void  neon_powerdomain_off(void)
 369 {
 370         int ret,i=0;
 371         int *p;
 372         p=&saveptr[0][0];
 373
 374          unsigned int fpexc = fmrx(FPEXC);  //get neon Logic gate
 375
 376         fmxr(FPEXC, fpexc | FPEXC_EN);  //open neon Logic gate
 377         for(i=0;i<36;i++){
 378         vfp_save_state(p,fpexc);                        //save neon reg,32 D reg,2 control reg
 379         p++;
 380         }
 381         fmxr(FPEXC, fpexc & ~FPEXC_EN);    //close neon Logic gate
 382
 383          ret=pmu_read(PMU_PG_CON);                   //get power domain state
 384         pmu_write(PMU_PG_CON,ret|(0x1<<1));          //powerdomain off neon
 385         printk("neon powerdomain is off\n");
 386 }
 387 void   neon_powerdomain_on(void)
 388 {
 389         int ret,i=0;
 390         int *p;
 391         p=&saveptr[0][0];
 392
 393         ret=pmu_read(PMU_PG_CON);                   //get power domain state
 394         pmu_write(PMU_PG_CON,ret&~(0x1<<1));                //powerdomain on neon
 395         mdelay(4);
 396
 397         unsigned int fpexc = fmrx(FPEXC);              //get neon Logic gate
 398         fmxr(FPEXC, fpexc | FPEXC_EN);                   //open neon Logic gate
 399         for(i=0;i<36;i++){
 400         vfp_load_state(p,fpexc);   //recovery neon reg, 32 D reg,2 control reg
 401         p++;
 402         }
 403         fmxr(FPEXC, fpexc | FPEXC_EN);      //open neon Logic gate
 404         printk("neon powerdomain is on\n");
 405 }
 406 #endif
 407
 408 void pm_gpio_suspend(void);
 409 void pm_gpio_resume(void);
 410
 411 static int rk29_pm_enter(suspend_state_t state)
 412 {
 413         u32 apll, cpll, gpll, mode, clksel0;
 414         u32 clkgate[4];
 415
 416         #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 417         neon_powerdomain_off();
 418         #endif
 419
 420         // memory teseter
 421         if (ddr_debug == 3)
 422                 ddr_testmode();
 423
 424         // dump GPIO INTEN for debug
 425         dump_inten();
 426         // dump GPIO PULL state for debug
 427         //if you want to display the information, please enable the code.
 428 #if 0
 429         dump_io_pull();
 430 #endif
 431
 432         sram_printch('0');
 433         flush_tlb_all();
 434         interface_ctr_reg_pread();
 435
 436         /* disable clock */
 437         clkgate[0] = cru_readl(CRU_CLKGATE0_CON);
 438         clkgate[1] = cru_readl(CRU_CLKGATE1_CON);
 439         clkgate[2] = cru_readl(CRU_CLKGATE2_CON);
 440         clkgate[3] = cru_clkgate3_con_mirror;
 441         cru_writel(~((1 << CLK_GATE_CORE)
 442                    | (1 << CLK_GATE_ACLK_CPU)
 443                    | (1 << CLK_GATE_ACLK_CPU2)
 444                    | (1 << CLK_GATE_PCLK_CPU)
 445                    | (1 << CLK_GATE_GIC)
 446                    | (1 << CLK_GATE_INTMEM)
 447                    | (1 << CLK_GATE_DDR_PHY)
 448                    | (1 << CLK_GATE_DDR_REG)
 449                    | (1 << CLK_GATE_DDR_CPU)
 450                    | (1 << CLK_GATE_GPIO0)
 451                    | (1 << CLK_GATE_RTC)
 452                    | (1 << CLK_GATE_GRF)
 453 #ifdef CONFIG_RK29_JTAG
 454                    | (1 << CLK_GATE_PCLK_CORE)
 455                    | (1 << CLK_GATE_ATCLK_CORE)
 456                    | (1 << CLK_GATE_ATCLK_CPU)
 457                    | (1 << CLK_GATE_DEBUG)
 458                    | (1 << CLK_GATE_TPIU)
 459 #endif
 460                    ) | clkgate[0], CRU_CLKGATE0_CON);
 461         cru_writel(~0, CRU_CLKGATE1_CON);
 462         cru_writel(~((1 << CLK_GATE_GPIO1 % 32)
 463                    | (1 << CLK_GATE_GPIO2 % 32)
 464                    | (1 << CLK_GATE_GPIO3 % 32)
 465                    | (1 << CLK_GATE_GPIO4 % 32)
 466                    | (1 << CLK_GATE_GPIO5 % 32)
 467                    | (1 << CLK_GATE_GPIO6 % 32)
 468                    | (1 << CLK_GATE_PWM % 32)
 469 #ifdef CONFIG_RK29_JTAG
 470                    | (1 << CLK_GATE_JTAG % 32)
 471 #endif
 472                    ) | clkgate[2], CRU_CLKGATE2_CON);
 473         cru_writel(~0, CRU_CLKGATE3_CON);
 474         sram_printch('1');
 475
 476         mode = cru_readl(CRU_MODE_CON);
 477         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 478
 479         /* suspend arm pll */
 480         apll = cru_readl(CRU_APLL_CON);
 481         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 482         cru_writel(apll | PLL_BYPASS, CRU_APLL_CON);
 483         cru_writel(apll | PLL_PD | PLL_BYPASS, CRU_APLL_CON);
 484         delay_500ns();
 485         /* set core = aclk_cpu = hclk_cpu = pclk_cpu = 24MHz */
 486         cru_writel(clksel0 & 0xFFFFF000, CRU_CLKSEL0_CON);
 487         sram_printch('2');
 488
 489         /* suspend codec pll */
 490         cpll = cru_readl(CRU_CPLL_CON);
 491         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 492         cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 493         cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 494         delay_500ns();
 495         sram_printch('3');
 496
 497         /* suspend general pll */
 498         gpll = cru_readl(CRU_GPLL_CON);
 499         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 500         cru_writel(gpll | PLL_BYPASS, CRU_GPLL_CON);
 501         cru_writel(gpll | PLL_PD | PLL_BYPASS, CRU_GPLL_CON);
 502         delay_500ns();
 503         /* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
 504         cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
 505
 506         sram_printch('4');
 507
 508         rk29_suspend();
 509
 510         sram_printch('4');
 511
 512         /* resume general pll */
 513         cru_writel(gpll, CRU_GPLL_CON);
 514         delay_300us();
 515         /* restore aclk_periph/hclk_periph/pclk_periph */
 516         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0x7FC000), CRU_CLKSEL0_CON);
 517         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | (mode & CRU_GENERAL_MODE_MASK), CRU_MODE_CON);
 518         sram_printch('3');
 519
 520         /* resume codec pll */
 521         cru_writel(cpll, CRU_CPLL_CON);
 522         delay_300us();
 523         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | (mode & CRU_CODEC_MODE_MASK), CRU_MODE_CON);
 524         sram_printch('2');
 525
 526         /* resume arm pll */
 527         cru_writel(apll, CRU_APLL_CON);
 528         delay_300us();
 529         /* restore core/aclk_cpu/hclk_cpu/pclk_cpu */
 530         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0xFFF), CRU_CLKSEL0_CON);
 531         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | (mode & CRU_CPU_MODE_MASK), CRU_MODE_CON);
 532         sram_printch('1');
 533
 534         /* enable clock */
 535         cru_writel(clkgate[0], CRU_CLKGATE0_CON);
 536         cru_writel(clkgate[1], CRU_CLKGATE1_CON);
 537         cru_writel(clkgate[2], CRU_CLKGATE2_CON);
 538         cru_writel(clkgate[3], CRU_CLKGATE3_CON);
 539         sram_printascii("0\n");
 540
 541         dump_irq();
 542
 543         #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 544         neon_powerdomain_on();
 545         #endif
 546
 547         return 0;
 548 }
 549
 550 static int rk29_pm_prepare(void)
 551 {
 552         /* disable entering rk29_idle() by disable_hlt() */
 553         disable_hlt();
 554         return 0;
 555 }
 556
 557 static void rk29_pm_finish(void)
 558 {
 559         enable_hlt();
 560 }
 561
 562 static struct platform_suspend_ops rk29_pm_ops = {
 563         .enter          = rk29_pm_enter,
 564         .valid          = suspend_valid_only_mem,
 565         .prepare        = rk29_pm_prepare,
 566         .finish         = rk29_pm_finish,
 567 };
 568
 569 static void rk29_idle(void)
 570 {
 571         if (!need_resched()) {
 572                 int allow_sleep = 1;
 573 #ifdef CONFIG_HAS_WAKELOCK
 574                 allow_sleep = !has_wake_lock(WAKE_LOCK_IDLE);
 575 #endif
 576                 if (allow_sleep) {
 577                         u32 mode_con = cru_readl(CRU_MODE_CON);
 578                         cru_writel((mode_con & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 579                         arch_idle();
 580                         cru_writel(mode_con, CRU_MODE_CON);
 581                 } else {
 582                         arch_idle();
 583                 }
 584         }
 585         local_irq_enable();
 586 }
 587
 588 static int __init rk29_pm_init(void)
 589 {
 590         suspend_set_ops(&rk29_pm_ops);
 591
 592         /* set idle function */
 593         pm_idle = rk29_idle;
 594         ddr_debug = 0;
 595
 596         return 0;
 597 }
 598 __initcall(rk29_pm_init);