arch/arm/mach-rk29/pm.c

   1 #define DEBUG
   2
   3 #include <linux/clk.h>
   4 #include <linux/delay.h>
   5 #include <linux/err.h>
   6 #include <linux/kernel.h>
   7 #include <linux/init.h>
   8 #include <linux/pm.h>
   9 #include <linux/suspend.h>
  10 #include <linux/random.h>
  11 #include <linux/crc32.h>
  12 #include <linux/io.h>
  13 #include <linux/wakelock.h>
  14 #include <asm/tlbflush.h>
  15 #include <asm/hardware/gic.h>
  16
  17 #include <mach/rk29_iomap.h>
  18 #include <mach/cru.h>
  19 #include <mach/pmu.h>
  20 #include <mach/board.h>
  21 #include <mach/system.h>
  22 #include <mach/sram.h>
  23 #include <mach/gpio.h>
  24 #include <mach/ddr.h>
  25 #include <mach/memtester.h>
  26 #include <mach/iomux.h>
  27 #include <mach/pm-vol.h>
  28
  29 #include <asm/vfp.h>
  30
  31 #define grf_readl(offset) readl(RK29_GRF_BASE + offset)
  32 #define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
  33
  34 static unsigned long save_sp;
  35
  36 static inline void delay_500ns(void)
  37 {
  38         LOOP(LOOPS_PER_USEC);
  39 }
  40
  41 static inline void delay_300us(void)
  42 {
  43         LOOP(300 * LOOPS_PER_USEC);
  44 }
  45
  46 #ifdef DEBUG
  47  void/* inline*/ __sramfunc sram_printch(char byte)
  48 {
  49         unsigned long flags;
  50         u32 gate1, gate2;
  51
  52         local_irq_save(flags);
  53         gate1 = cru_readl(CRU_CLKGATE1_CON);
  54         gate2 = cru_readl(CRU_CLKGATE2_CON);
  55         cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
  56         cru_writel(gate2 & ~(1 << CLK_GATE_UART1 % 32), CRU_CLKGATE2_CON);
  57         delay_500ns();
  58
  59         writel(byte, RK29_UART1_BASE);
  60
  61         /* loop check LSR[6], Transmitter Empty bit */
  62         while (!(readl(RK29_UART1_BASE + 0x14) & 0x40))
  63                 barrier();
  64
  65         cru_writel(gate2, CRU_CLKGATE2_CON);
  66         cru_writel(gate1, CRU_CLKGATE1_CON);
  67         local_irq_restore(flags);
  68         if (byte == '\n')
  69                 sram_printch('\r');
  70 }
  71
  72 void print(const char *s)
  73 {
  74     sram_printascii(s);
  75 }
  76
  77 void __sramfunc print_Hex(unsigned int hex)
  78 {
  79         int i = 8;
  80         sram_printch('0');
  81         sram_printch('x');
  82         while (i--) {
  83                 unsigned char c = (hex & 0xF0000000) >> 28;
  84                 sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
  85                 hex <<= 4;
  86         }
  87 }
  88
  89 void __sramfunc print_Dec (uint32_t n)
  90 {
  91     if (n >= 10)
  92     {
  93         print_Dec(n / 10);
  94         n %= 10;
  95     }
  96     sram_printch((char)(n + '0'));
  97 }
  98
  99 void print_Dec_3(uint32_t value)
 100 {
 101     if(value<10)
 102     {
 103         print("  ");
 104     }
 105     else if(value<100)
 106     {
 107         print(" ");
 108     }
 109     else
 110     {
 111     }
 112     print_Dec(value);
 113 }
 114
 115 #else
 116 static void inline sram_printch(char byte) {}
 117 static void inline sram_printascii(const char *s) {}
 118 static void inline printhex(unsigned int hex) {}
 119 #endif /* DEBUG */
 120
 121 /*volatile __sramdata */int ddr_debug;
 122 module_param(ddr_debug, int, 0644);
 123 #if 1
 124 static int inline calc_crc32(u32 addr, size_t len)
 125 {
 126      return crc32_le(~0,(const unsigned char *)addr,len);
 127 }
 128 void __sramfunc ddr_testmode(void)
 129 {
 130     int32_t g_crc1,g_crc2;
 131     uint32_t nMHz;
 132     uint32_t n = 0;
 133     extern char _stext[], _etext[];
 134     if(ddr_debug == 1)
 135     {
 136         for (;;)
 137         {
 138                 sram_printascii("change freq\n");
 139             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 140             nMHz = 333 + random32();
 141             nMHz %= 490;
 142             if(nMHz < 100)
 143                 nMHz = 100;
 144             nMHz = ddr_change_freq(nMHz);
 145                 sram_printhex(nMHz);
 146                 sram_printch(' ');
 147                 sram_printhex(n++);
 148                 sram_printch(' ');
 149             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 150             if (g_crc1!=g_crc2)
 151             {
 152                     sram_printascii("fail\n");
 153                 }
 154                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 155            //     sram_printascii("change freq success\n");
 156         }
 157     }
 158     else if(ddr_debug == 2)
 159     {
 160         for (;;)
 161         {
 162                 sram_printch(' ');
 163                 sram_printch('9');
 164                 sram_printch('9');
 165                 sram_printch('9');
 166                 sram_printch(' ');
 167             g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 168             nMHz = (random32()>>13);// 16.7s max
 169             ddr_suspend();
 170             delayus(nMHz);
 171             ddr_resume();
 172                 sram_printhex(nMHz);
 173                 sram_printch(' ');
 174                 sram_printhex(n++);
 175             g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 176             if (g_crc1!=g_crc2)
 177             {
 178                     sram_printch(' ');
 179                     sram_printch('f');
 180                     sram_printch('a');
 181                     sram_printch('i');
 182                     sram_printch('l');
 183                 }
 184               // ddr_print("check image crc32 fail!, count:%d\n", n++);
 185             //    sram_printascii("self refresh fail\n");
 186             //else
 187                //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 188             //    sram_printascii("self refresh success\n");
 189         }
 190     }
 191     else if(ddr_debug == 3)
 192     {
 193         memtester();
 194     }
 195 }
 196 #else
 197 void __sramfunc ddr_testmode(void)
 198 {}
 199
 200 #endif
 201 void __sramfunc pm_clk_switch_32k(void);
 202
 203 void __sramfunc pm_wfi(void)
 204 {
 205         u32 clksel0;
 206         sram_printch('7');
 207         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 208         /* set arm clk 24MHz/32 = 750KHz */
 209         cru_writel(clksel0 | 0x1F, CRU_CLKSEL0_CON);
 210
 211         sram_printch('8');
 212         dsb();
 213         asm("wfi");
 214         sram_printch('8');
 215
 216         /* resume arm clk */
 217         cru_writel(clksel0, CRU_CLKSEL0_CON);
 218         sram_printch('7');
 219
 220
 221 }
 222
 223 static void __sramfunc rk29_sram_suspend(void)
 224 {
 225         u32 vol;
 226
 227         if (ddr_debug == 2)
 228                 ddr_testmode();
 229
 230         sram_printch('5');
 231         ddr_suspend();
 232
 233         sram_printch('6');
 234         vol=rk29_suspend_voltage_set(1000000);
 235 #ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
 236         pm_clk_switch_32k();
 237 #else
 238         pm_wfi();
 239 #endif
 240         rk29_suspend_voltage_resume(vol);
 241         sram_printch('6');
 242
 243         ddr_resume();
 244         sram_printch('5');
 245 }
 246
 247 static void noinline rk29_suspend(void)
 248 {
 249         DDR_SAVE_SP(save_sp);
 250         rk29_sram_suspend();
 251         DDR_RESTORE_SP(save_sp);
 252 }
 253
 254 static void dump_irq(void)
 255 {
 256         u32 irq_gpio = (readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8) >> 23) & 0x7F;
 257         printk("wakeup irq: %08x %08x %01x\n",
 258                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 4),
 259                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 8),
 260                 readl(RK29_GICPERI_BASE + GIC_DIST_PENDING_SET + 12) & 0xf);
 261         if (irq_gpio & 1)
 262                 printk("wakeup gpio0: %08x\n", readl(RK29_GPIO0_BASE + GPIO_INT_STATUS));
 263         if (irq_gpio & 2)
 264                 printk("wakeup gpio1: %08x\n", readl(RK29_GPIO1_BASE + GPIO_INT_STATUS));
 265         if (irq_gpio & 4)
 266                 printk("wakeup gpio2: %08x\n", readl(RK29_GPIO2_BASE + GPIO_INT_STATUS));
 267         if (irq_gpio & 8)
 268                 printk("wakeup gpio3: %08x\n", readl(RK29_GPIO3_BASE + GPIO_INT_STATUS));
 269         if (irq_gpio & 0x10)
 270                 printk("wakeup gpio4: %08x\n", readl(RK29_GPIO4_BASE + GPIO_INT_STATUS));
 271         if (irq_gpio & 0x20)
 272                 printk("wakeup gpio5: %08x\n", readl(RK29_GPIO5_BASE + GPIO_INT_STATUS));
 273         if (irq_gpio & 0x40)
 274                 printk("wakeup gpio6: %08x\n", readl(RK29_GPIO6_BASE + GPIO_INT_STATUS));
 275 }
 276
 277 #define DUMP_GPIO_INTEN(ID) \
 278 do { \
 279         u32 en = readl(RK29_GPIO##ID##_BASE + GPIO_INTEN); \
 280         if (en) { \
 281                 sram_printascii("GPIO" #ID "_INTEN: "); \
 282                 sram_printhex(en); \
 283                 sram_printch('\n'); \
 284         } \
 285 } while (0)
 286
 287 static void dump_inten(void)
 288 {
 289         DUMP_GPIO_INTEN(0);
 290         DUMP_GPIO_INTEN(1);
 291         DUMP_GPIO_INTEN(2);
 292         DUMP_GPIO_INTEN(3);
 293         DUMP_GPIO_INTEN(4);
 294         DUMP_GPIO_INTEN(5);
 295         DUMP_GPIO_INTEN(6);
 296 }
 297
 298
 299
 300 #define DUMP_GPIO_PULL(ID) \
 301 do { \
 302         u32 state = readl(RK29_GRF_BASE + GRF_GPIO0_PULL + (ID<<2)); \
 303         sram_printascii("GPIO" #ID "_PULL: "); \
 304         sram_printhex(state); \
 305         sram_printch('\n'); \
 306 } while (0)
 307
 308 static void dump_io_pull(void)
 309 {
 310         DUMP_GPIO_PULL(0);
 311         DUMP_GPIO_PULL(1);
 312         DUMP_GPIO_PULL(2);
 313         DUMP_GPIO_PULL(3);
 314         DUMP_GPIO_PULL(4);
 315         DUMP_GPIO_PULL(5);
 316         DUMP_GPIO_PULL(6);
 317 }
 318 #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 319 /*******************************neon powermain***********************/
 320 #define pmu_read(offset)                readl(RK29_PMU_BASE + (offset))
 321 #define pmu_write(offset, value)        writel((value), RK29_PMU_BASE + (offset))
 322 #define PMU_PG_CON 0x10
 323 #define vfpreg(_vfp_) #_vfp_
 324
 325 #define fmrx(_vfp_) ({                  \
 326         u32 __v;                        \
 327         asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx   %0, " #_vfp_    \
 328             : "=r" (__v) : : "cc");     \
 329         __v;                            \
 330  })
 331
 332 #define fmxr(_vfp_,_var_)               \
 333         asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr   " #_vfp_ ", %0" \
 334            : : "r" (_var_) : "cc")
 335 extern void vfp_save_state(void *location, u32 fpexc);
 336 extern void vfp_load_state(void *location, u32 fpexc);
 337 // extern  __sramdata u64  saveptr[33];
 338 static u32  saveptr[2][60]={};
 339 static void  neon_powerdomain_off(void)
 340 {
 341         int ret,i=0;
 342         int *p;
 343          u32 fpexc;
 344         p=&saveptr[0][0];
 345
 346
 347          fpexc= fmrx(FPEXC);  //get neon Logic gate
 348
 349         fmxr(FPEXC, fpexc | FPEXC_EN);  //open neon Logic gate
 350         for(i=0;i<36;i++){
 351         vfp_save_state(p,fpexc);                        //save neon reg,32 D reg,2 control reg
 352         p++;
 353         }
 354         fmxr(FPEXC, fpexc & ~FPEXC_EN);    //close neon Logic gate
 355
 356          ret=pmu_read(PMU_PG_CON);                   //get power domain state
 357         pmu_write(PMU_PG_CON,ret|(0x1<<1));          //powerdomain off neon
 358         printk("neon powerdomain is off\n");
 359 }
 360 static void   neon_powerdomain_on(void)
 361 {
 362         int ret,i=0;
 363         int *p;
 364         unsigned int fpexc ;
 365         p=&saveptr[0][0];
 366
 367         ret=pmu_read(PMU_PG_CON);                   //get power domain state
 368         pmu_write(PMU_PG_CON,ret&~(0x1<<1));                //powerdomain on neon
 369         mdelay(4);
 370
 371         fpexc = fmrx(FPEXC);              //get neon Logic gate
 372         fmxr(FPEXC, fpexc | FPEXC_EN);                   //open neon Logic gate
 373         for(i=0;i<36;i++){
 374         vfp_load_state(p,fpexc);   //recovery neon reg, 32 D reg,2 control reg
 375         p++;
 376         }
 377         fmxr(FPEXC, fpexc | FPEXC_EN);      //open neon Logic gate
 378         printk("neon powerdomain is on\n");
 379 }
 380 #endif
 381 /*******************************neon powermain***********************/
 382
 383 void pm_gpio_suspend(void);
 384 void pm_gpio_resume(void);
 385
 386 static int rk29_pm_enter(suspend_state_t state)
 387 {
 388         u32 apll, cpll, gpll, mode, clksel0;
 389         u32 clkgate[4];
 390
 391         #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 392         neon_powerdomain_off();
 393         #endif
 394
 395         // memory teseter
 396         if (ddr_debug != 2)
 397                 ddr_testmode();
 398
 399         // dump GPIO INTEN for debug
 400         dump_inten();
 401         // dump GPIO PULL state for debug
 402         //if you want to display the information, please enable the code.
 403 #if 0
 404         dump_io_pull();
 405 #endif
 406
 407         sram_printch('0');
 408         flush_tlb_all();
 409         #if defined(CONFIG_RK29_SPI_INSRAM) || defined(CONFIG_RK29_PWM_INSRAM)
 410         interface_ctr_reg_pread();
 411         #endif
 412         #if defined(CONFIG_RK29_I2C_INSRAM)
 413         i2c_interface_ctr_reg_pread();
 414         #endif
 415
 416         /* disable clock */
 417         clkgate[0] = cru_readl(CRU_CLKGATE0_CON);
 418         clkgate[1] = cru_readl(CRU_CLKGATE1_CON);
 419         clkgate[2] = cru_readl(CRU_CLKGATE2_CON);
 420         clkgate[3] = cru_clkgate3_con_mirror;
 421         cru_writel(~((1 << CLK_GATE_CORE)
 422                    | (1 << CLK_GATE_ACLK_CPU)
 423                    | (1 << CLK_GATE_ACLK_CPU2)
 424                    | (1 << CLK_GATE_PCLK_CPU)
 425                    | (1 << CLK_GATE_GIC)
 426                    | (1 << CLK_GATE_INTMEM)
 427                    | (1 << CLK_GATE_DDR_PHY)
 428                    | (1 << CLK_GATE_DDR_REG)
 429                    | (1 << CLK_GATE_DDR_CPU)
 430                    | (1 << CLK_GATE_GPIO0)
 431                    | (1 << CLK_GATE_RTC)
 432                    | (1 << CLK_GATE_GRF)
 433 #ifdef CONFIG_RK29_JTAG
 434                    | (1 << CLK_GATE_PCLK_CORE)
 435                    | (1 << CLK_GATE_ATCLK_CORE)
 436                    | (1 << CLK_GATE_ATCLK_CPU)
 437                    | (1 << CLK_GATE_DEBUG)
 438                    | (1 << CLK_GATE_TPIU)
 439 #endif
 440                    ) | clkgate[0], CRU_CLKGATE0_CON);
 441
 442 #ifdef CONFIG_PHONE_INCALL_IS_SUSPEND
 443 #if defined(CONFIG_SND_RK29_SOC_I2S_8CH)
 444         cru_writel(clkgate[0]&(~(1<<CLK_GATE_I2S0)),CRU_CLKGATE0_CON);
 445 #elif defined(CONFIG_SND_RK29_SOC_I2S_2CH)
 446         cru_writel(clkgate[0]&(~(1<<CLK_GATE_I2S1)),CRU_CLKGATE0_CON);
 447 #endif
 448 #endif
 449
 450         cru_writel(~0, CRU_CLKGATE1_CON);
 451         cru_writel(~((1 << CLK_GATE_GPIO1 % 32)
 452                    | (1 << CLK_GATE_GPIO2 % 32)
 453                    | (1 << CLK_GATE_GPIO3 % 32)
 454                    | (1 << CLK_GATE_GPIO4 % 32)
 455                    | (1 << CLK_GATE_GPIO5 % 32)
 456                    | (1 << CLK_GATE_GPIO6 % 32)
 457                    | (1 << CLK_GATE_PWM % 32)
 458 #ifdef CONFIG_RK29_JTAG
 459                    | (1 << CLK_GATE_JTAG % 32)
 460 #endif
 461                    ) | clkgate[2], CRU_CLKGATE2_CON);
 462         cru_writel(~0, CRU_CLKGATE3_CON);
 463         sram_printch('1');
 464
 465         mode = cru_readl(CRU_MODE_CON);
 466         clksel0 = cru_readl(CRU_CLKSEL0_CON);
 467
 468         /* suspend arm pll */
 469         apll = cru_readl(CRU_APLL_CON);
 470         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 471         cru_writel(apll | PLL_BYPASS, CRU_APLL_CON);
 472         cru_writel(apll | PLL_PD | PLL_BYPASS, CRU_APLL_CON);
 473         delay_500ns();
 474         /* set core = aclk_cpu = hclk_cpu = pclk_cpu = 24MHz */
 475         cru_writel(clksel0 & 0xFFFFF000, CRU_CLKSEL0_CON);
 476         sram_printch('2');
 477
 478         /* suspend codec pll */
 479         cpll = cru_readl(CRU_CPLL_CON);
 480         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
 481         cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
 482         cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
 483         delay_500ns();
 484         sram_printch('3');
 485
 486         /* suspend general pll */
 487         gpll = cru_readl(CRU_GPLL_CON);
 488         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
 489         cru_writel(gpll | PLL_BYPASS, CRU_GPLL_CON);
 490         cru_writel(gpll | PLL_PD | PLL_BYPASS, CRU_GPLL_CON);
 491         delay_500ns();
 492         /* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
 493         cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
 494
 495         sram_printch('4');
 496         pm_gpio_suspend();
 497         rk29_suspend();
 498         pm_gpio_resume();
 499         sram_printch('4');
 500
 501         /* resume general pll */
 502         cru_writel(gpll, CRU_GPLL_CON);
 503         delay_300us();
 504         /* restore aclk_periph/hclk_periph/pclk_periph */
 505         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0x7FC000), CRU_CLKSEL0_CON);
 506         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | (mode & CRU_GENERAL_MODE_MASK), CRU_MODE_CON);
 507         sram_printch('3');
 508
 509         /* resume codec pll */
 510         cru_writel(cpll, CRU_CPLL_CON);
 511         delay_300us();
 512         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | (mode & CRU_CODEC_MODE_MASK), CRU_MODE_CON);
 513         sram_printch('2');
 514
 515         /* resume arm pll */
 516         cru_writel(apll, CRU_APLL_CON);
 517         delay_300us();
 518         /* restore core/aclk_cpu/hclk_cpu/pclk_cpu */
 519         cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0xFFF), CRU_CLKSEL0_CON);
 520         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | (mode & CRU_CPU_MODE_MASK), CRU_MODE_CON);
 521         sram_printch('1');
 522
 523         /* enable clock */
 524         cru_writel(clkgate[0], CRU_CLKGATE0_CON);
 525         cru_writel(clkgate[1], CRU_CLKGATE1_CON);
 526         cru_writel(clkgate[2], CRU_CLKGATE2_CON);
 527         cru_writel(clkgate[3], CRU_CLKGATE3_CON);
 528         sram_printascii("0\n");
 529
 530         dump_irq();
 531
 532         #ifdef CONFIG_RK29_NEON_POWERDOMAIN_SET
 533         neon_powerdomain_on();
 534         #endif
 535
 536         return 0;
 537 }
 538
 539 static int rk29_pm_prepare(void)
 540 {
 541         /* disable entering rk29_idle() by disable_hlt() */
 542         disable_hlt();
 543         return 0;
 544 }
 545
 546 static void rk29_pm_finish(void)
 547 {
 548         enable_hlt();
 549 }
 550
 551 static struct platform_suspend_ops rk29_pm_ops = {
 552         .enter          = rk29_pm_enter,
 553         .valid          = suspend_valid_only_mem,
 554         .prepare        = rk29_pm_prepare,
 555         .finish         = rk29_pm_finish,
 556 };
 557
 558 static void rk29_idle(void)
 559 {
 560         if (!need_resched()) {
 561                 int allow_sleep = 1;
 562 #ifdef CONFIG_HAS_WAKELOCK
 563                 allow_sleep = !has_wake_lock(WAKE_LOCK_IDLE);
 564 #endif
 565                 if (allow_sleep) {
 566                         u32 mode_con = cru_readl(CRU_MODE_CON);
 567                         cru_writel((mode_con & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
 568                         arch_idle();
 569                         cru_writel(mode_con, CRU_MODE_CON);
 570                 } else {
 571                         arch_idle();
 572                 }
 573         }
 574         local_irq_enable();
 575 }
 576
 577 static int __init rk29_pm_init(void)
 578 {
 579         suspend_set_ops(&rk29_pm_ops);
 580
 581         /* set idle function */
 582         pm_idle = rk29_idle;
 583         ddr_debug = 0;
 584
 585 #ifdef CONFIG_EARLYSUSPEND
 586         pm_set_vt_switch(0); /* disable vt switch while suspend */
 587 #endif
 588
 589         return 0;
 590 }
 591 __initcall(rk29_pm_init);