arch/arm/mach-rk29/reset.c

   1 #include <linux/kernel.h>\r
   2 #include <linux/reboot.h>\r
   3 \r
   4 #include <asm/io.h>\r
   5 #include <asm/proc-fns.h>\r
   6 #include <asm/cacheflush.h>\r
   7 #include <asm/tlb.h>\r
   8 #include <asm/traps.h>\r
   9 #include <asm/sections.h>\r
  10 #include <asm/mach/arch.h>\r
  11 #include <asm/mach/map.h>\r
  12 #include <asm/stacktrace.h>\r
  13 \r
  14 #include <mach/rk29_iomap.h>\r
  15 #include <mach/cru.h>\r
  16 #include <mach/memory.h>\r
  17 #include <mach/sram.h>\r
  18 #include <mach/pmu.h>\r
  19 \r
  20 #include <asm/delay.h>\r
  21 #include <asm/tlbflush.h>\r
  22 #include <asm/cacheflush.h>\r
  23 \r
  24 #define LOOPS_PER_USEC  13\r
  25 #define LOOPS_PER_MSEC  12000\r
  26 #define LOOP(loops) do { int i = loops; barrier(); while (i--) barrier(); } while (0)\r
  27 \r
  28 static void  pwm2gpiodefault(void)\r
  29 {\r
  30         #define     REG_FILE_BASE_ADDR         RK29_GRF_BASE\r
  31         volatile unsigned int * pGRF_GPIO2L_IOMUX =  (volatile unsigned int *)(REG_FILE_BASE_ADDR + 0x58);\r
  32         #define     GPIO2_BASE_ADDR            RK29_GPIO2_BASE\r
  33         volatile unsigned int *pGPIO2_DIR = (volatile unsigned int *)(GPIO2_BASE_ADDR + 0x4);\r
  34 \r
  35         // iomux pwm2 to gpio2_a[3]\r
  36         *pGRF_GPIO2L_IOMUX &= ~(0x3<<6);\r
  37         // set gpio to input\r
  38         *pGPIO2_DIR &= ~(0x1<<3);\r
  39 \r
  40         memset((void *)RK29_PWM_BASE, 0, 0x40);\r
  41 } \r
  42 \r
  43 \r
  44 extern void __rb( void*  );\r
  45 void rb( void )\r
  46 {\r
  47     void(*cb)(void* ) ;\r
  48     \r
  49     void * uart_base = (unsigned int *)ioremap( RK29_UART1_PHYS , RK29_UART1_SIZE );\r
  50     local_irq_disable();\r
  51     cb =  (void(*)(void* ))__pa(__rb);\r
  52     __cpuc_flush_kern_all();\r
  53     __cpuc_flush_user_all();\r
  54     //printk("begin to jump to reboot,uart1 va=0x%p\n" , uart_base);\r
  55     //while(testflag);    \r
  56     cb( uart_base );\r
  57 }\r
  58 \r
  59 static void __sramfunc __noreturn rk29_rb_with_softreset(void)\r
  60 {\r
  61         u32 reg;\r
  62 \r
  63         asm volatile (\r
  64             "mrc        p15, 0, %0, c1, c0, 0\n\t"\r
  65             "bic        %0, %0, #(1 << 0)       @disable MMU\n\t"\r
  66             "bic        %0, %0, #(1 << 13)      @set vector to 0x00000000\n\t"\r
  67             "bic        %0, %0, #(1 << 12)      @disable I CACHE\n\t"\r
  68             "bic        %0, %0, #(1 << 2)       @disable D DACHE\n\t"\r
  69             "bic        %0, %0, #(1 << 11)      @disable Branch prediction\n\t"\r
  70             "bic        %0, %0, #(1 << 28)      @disable TEX Remap\n\t"\r
  71             "mcr        p15, 0, %0, c1, c0, 0\n\t"\r
  72             "mov        %0, #0\n\t"\r
  73             "mcr        p15, 0, %0, c8, c7, 0   @invalidate whole TLB\n\t"\r
  74             "mcr        p15, 0, %0, c7, c5, 6   @invalidate BTC\n\t"\r
  75             "dsb\n\t"\r
  76             "isb\n\t"\r
  77             "b          1f\n\t"\r
  78             ".align 5\n\t"\r
  79             "1:\n\t"\r
  80             : "=r" (reg));\r
  81 \r
  82         writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
  83         dsb();\r
  84         LOOP(10 * LOOPS_PER_USEC);\r
  85 \r
  86         writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
  87         writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST1_CON);\r
  88         writel(0xd9fdfdc0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);\r
  89         dsb();\r
  90 \r
  91         LOOP(100 * LOOPS_PER_USEC);\r
  92 \r
  93         writel(0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);\r
  94         writel(0, RK29_CRU_PHYS + CRU_SOFTRST1_CON);\r
  95         writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
  96         dsb();\r
  97         LOOP(10 * LOOPS_PER_USEC);\r
  98         writel(0, RK29_CRU_PHYS + CRU_SOFTRST2_CON);\r
  99         dsb();\r
 100         LOOP(10 * LOOPS_PER_USEC);\r
 101 \r
 102         asm volatile (\r
 103             "b 1f\n\t"\r
 104             ".align 5\n\t"\r
 105             "1:\n\t"\r
 106             "dsb\n\t"\r
 107             "isb\n\t"\r
 108             "mov        pc, #0");\r
 109 \r
 110         while (1);\r
 111 }\r
 112 \r
 113 void  rk29_arch_reset(int mode, const char *cmd)\r
 114 {\r
 115         void (*rb2)(void);\r
 116 \r
 117         rb2 = (void(*)(void))((u32)rk29_rb_with_softreset - SRAM_CODE_OFFSET + 0x10130000);\r
 118 \r
 119         local_irq_disable();\r
 120         local_fiq_disable();\r
 121 \r
 122 #ifdef CONFIG_MACH_RK29SDK\r
 123         /* from panic? loop for debug */\r
 124         if (system_state != SYSTEM_RESTART) {\r
 125                 printk("\nLoop for debug...\n");\r
 126                 while (1);\r
 127         }\r
 128 #endif\r
 129 \r
 130         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);\r
 131         LOOP(LOOPS_PER_USEC);\r
 132 \r
 133         /* from panic? */\r
 134         if (system_state != SYSTEM_RESTART)\r
 135                 machine_power_off();\r
 136 \r
 137         pwm2gpiodefault();\r
 138 \r
 139         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);\r
 140         LOOP(LOOPS_PER_USEC);\r
 141 \r
 142         cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);\r
 143         LOOP(LOOPS_PER_USEC);\r
 144 \r
 145         cru_writel(0, CRU_CLKGATE0_CON);\r
 146         cru_writel(0, CRU_CLKGATE1_CON);\r
 147         cru_writel(0, CRU_CLKGATE2_CON);\r
 148         cru_writel(0, CRU_CLKGATE3_CON);\r
 149         LOOP(LOOPS_PER_USEC);\r
 150 \r
 151         cru_writel(0, CRU_SOFTRST0_CON);\r
 152         cru_writel(0, CRU_SOFTRST1_CON);\r
 153         cru_writel(0, CRU_SOFTRST2_CON);\r
 154         LOOP(LOOPS_PER_USEC);\r
 155 \r
 156         cru_writel(1 << 16 | 1 << 13 | 1 << 11 | 1 << 1, CRU_CLKGATE3_CON);\r
 157         LOOP(LOOPS_PER_USEC);\r
 158 \r
 159         writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_VCODEC), RK29_PMU_BASE + PMU_PD_CON);\r
 160         dsb();\r
 161         while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_VCODEC))\r
 162                 ;\r
 163         LOOP(10 * LOOPS_PER_MSEC);\r
 164 \r
 165         writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_DISPLAY), RK29_PMU_BASE + PMU_PD_CON);\r
 166         dsb();\r
 167         while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_DISPLAY))\r
 168                 ;\r
 169         LOOP(10 * LOOPS_PER_MSEC);\r
 170 \r
 171         writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_GPU), RK29_PMU_BASE + PMU_PD_CON);\r
 172         dsb();\r
 173         while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_GPU))\r
 174                 ;\r
 175         LOOP(10 * LOOPS_PER_MSEC);\r
 176 \r
 177         cru_writel(0, CRU_CLKGATE3_CON);\r
 178         LOOP(LOOPS_PER_USEC);\r
 179 \r
 180         //SPI0 clock source = periph_pll_clk, SPI0 divider=8\r
 181         cru_writel((cru_readl(CRU_CLKSEL6_CON) & ~0x1FF) | (7 << 2), CRU_CLKSEL6_CON);\r
 182 \r
 183         //eMMC divider=0x17, SD/MMC0 clock source=arm_pll_clk\r
 184         cru_writel((cru_readl(CRU_CLKSEL7_CON) & ~(3 | (0x3f << 18))) | (0x17 << 18), CRU_CLKSEL7_CON);\r
 185 \r
 186         //UART1 clock divider=0, UART1 clk =24MHz , UART0 and UART1 clock source=periph_pll_clk\r
 187         cru_writel((cru_readl(CRU_CLKSEL8_CON) & ~(7 | (0x3f << 14) | (3 << 20))) | (2 << 20), CRU_CLKSEL8_CON);\r
 188 \r
 189         // remap bit control = 0, normal mode\r
 190         writel(readl(RK29_GRF_PHYS + 0xc0) & ~(1 << 21), RK29_GRF_PHYS + 0xc0);\r
 191         // emmc_and_boot_en control=0, normal mode\r
 192         writel(readl(RK29_GRF_PHYS + 0xbc) & ~(1 << 9), RK29_GRF_PHYS + 0xbc);\r
 193         dsb();\r
 194 \r
 195         writel(0, RK29_CPU_AXI_BUS0_PHYS);\r
 196         writel(0, RK29_AXI1_PHYS);\r
 197         dsb();\r
 198 \r
 199         // SDMMC_CLKSRC=0, clk_source=clock divider 0\r
 200         writel(0, RK29_EMMC_PHYS + 0x0c);\r
 201         // SDMMC_CTYPE=0, card_width=1 bit mode\r
 202         writel(0, RK29_EMMC_PHYS + 0x18);\r
 203         // SDMMC_BLKSIZ=0x200, Block size=512\r
 204         writel(0x200, RK29_EMMC_PHYS + 0x1c);\r
 205         dsb();\r
 206 \r
 207         __cpuc_flush_kern_all();\r
 208         __cpuc_flush_user_all();\r
 209         \r
 210         rb2();\r
 211 }\r
 212 \r
 213 \r