1 #include <linux/kernel.h>
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2 #include <linux/reboot.h>
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5 #include <asm/proc-fns.h>
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6 #include <asm/cacheflush.h>
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8 #include <asm/traps.h>
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9 #include <asm/sections.h>
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10 #include <asm/mach/arch.h>
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11 #include <asm/mach/map.h>
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12 #include <asm/stacktrace.h>
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14 #include <mach/rk29_iomap.h>
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15 #include <mach/cru.h>
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16 #include <mach/memory.h>
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17 #include <mach/sram.h>
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18 #include <mach/pmu.h>
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20 #include <asm/delay.h>
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21 #include <asm/tlbflush.h>
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22 #include <asm/cacheflush.h>
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24 #define LOOPS_PER_USEC 13
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25 #define LOOPS_PER_MSEC 12000
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26 #define LOOP(loops) do { int i = loops; barrier(); while (i--) barrier(); } while (0)
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28 static void pwm2gpiodefault(void)
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30 #define REG_FILE_BASE_ADDR RK29_GRF_BASE
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31 volatile unsigned int * pGRF_GPIO2L_IOMUX = (volatile unsigned int *)(REG_FILE_BASE_ADDR + 0x58);
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32 #define GPIO2_BASE_ADDR RK29_GPIO2_BASE
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33 volatile unsigned int *pGPIO2_DIR = (volatile unsigned int *)(GPIO2_BASE_ADDR + 0x4);
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35 // iomux pwm2 to gpio2_a[3]
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36 *pGRF_GPIO2L_IOMUX &= ~(0x3<<6);
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37 // set gpio to input
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38 *pGPIO2_DIR &= ~(0x1<<3);
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40 memset((void *)RK29_PWM_BASE, 0, 0x40);
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44 extern void __rb( void* );
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49 void * uart_base = (unsigned int *)ioremap( RK29_UART1_PHYS , RK29_UART1_SIZE );
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50 local_irq_disable();
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51 cb = (void(*)(void* ))__pa(__rb);
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52 __cpuc_flush_kern_all();
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53 __cpuc_flush_user_all();
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54 //printk("begin to jump to reboot,uart1 va=0x%p\n" , uart_base);
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59 static void __sramfunc __noreturn rk29_rb_with_softreset(void)
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64 "mrc p15, 0, %0, c1, c0, 0\n\t"
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65 "bic %0, %0, #(1 << 0) @disable MMU\n\t"
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66 "bic %0, %0, #(1 << 13) @set vector to 0x00000000\n\t"
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67 "bic %0, %0, #(1 << 12) @disable I CACHE\n\t"
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68 "bic %0, %0, #(1 << 2) @disable D DACHE\n\t"
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69 "bic %0, %0, #(1 << 11) @disable Branch prediction\n\t"
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70 "bic %0, %0, #(1 << 28) @disable TEX Remap\n\t"
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71 "mcr p15, 0, %0, c1, c0, 0\n\t"
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73 "mcr p15, 0, %0, c8, c7, 0 @invalidate whole TLB\n\t"
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74 "mcr p15, 0, %0, c7, c5, 6 @invalidate BTC\n\t"
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82 writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);
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84 LOOP(10 * LOOPS_PER_USEC);
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86 writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST2_CON);
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87 writel(0xffffffff, RK29_CRU_PHYS + CRU_SOFTRST1_CON);
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88 writel(0xd9fdfdc0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);
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91 LOOP(100 * LOOPS_PER_USEC);
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93 writel(0, RK29_CRU_PHYS + CRU_SOFTRST0_CON);
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94 writel(0, RK29_CRU_PHYS + CRU_SOFTRST1_CON);
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95 writel(0x00019a00, RK29_CRU_PHYS + CRU_SOFTRST2_CON);
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97 LOOP(10 * LOOPS_PER_USEC);
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98 writel(0, RK29_CRU_PHYS + CRU_SOFTRST2_CON);
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100 LOOP(10 * LOOPS_PER_USEC);
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113 void rk29_arch_reset(int mode, const char *cmd)
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117 rb2 = (void(*)(void))((u32)rk29_rb_with_softreset - SRAM_CODE_OFFSET + 0x10130000);
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119 local_irq_disable();
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120 local_fiq_disable();
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122 #ifdef CONFIG_MACH_RK29SDK
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123 /* from panic? loop for debug */
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124 if (system_state != SYSTEM_RESTART) {
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125 printk("\nLoop for debug...\n");
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130 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
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131 LOOP(LOOPS_PER_USEC);
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134 if (system_state != SYSTEM_RESTART)
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135 machine_power_off();
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139 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | CRU_GENERAL_MODE_SLOW, CRU_MODE_CON);
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140 LOOP(LOOPS_PER_USEC);
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142 cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | CRU_CODEC_MODE_SLOW, CRU_MODE_CON);
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143 LOOP(LOOPS_PER_USEC);
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145 cru_writel(0, CRU_CLKGATE0_CON);
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146 cru_writel(0, CRU_CLKGATE1_CON);
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147 cru_writel(0, CRU_CLKGATE2_CON);
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148 cru_writel(0, CRU_CLKGATE3_CON);
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149 LOOP(LOOPS_PER_USEC);
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151 cru_writel(0, CRU_SOFTRST0_CON);
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152 cru_writel(0, CRU_SOFTRST1_CON);
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153 cru_writel(0, CRU_SOFTRST2_CON);
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154 LOOP(LOOPS_PER_USEC);
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156 cru_writel(1 << 16 | 1 << 13 | 1 << 11 | 1 << 1, CRU_CLKGATE3_CON);
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157 LOOP(LOOPS_PER_USEC);
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159 writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_VCODEC), RK29_PMU_BASE + PMU_PD_CON);
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161 while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_VCODEC))
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163 LOOP(10 * LOOPS_PER_MSEC);
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165 writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_DISPLAY), RK29_PMU_BASE + PMU_PD_CON);
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167 while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_DISPLAY))
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169 LOOP(10 * LOOPS_PER_MSEC);
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171 writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << PD_GPU), RK29_PMU_BASE + PMU_PD_CON);
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173 while (readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << PD_GPU))
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175 LOOP(10 * LOOPS_PER_MSEC);
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177 cru_writel(0, CRU_CLKGATE3_CON);
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178 LOOP(LOOPS_PER_USEC);
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180 //SPI0 clock source = periph_pll_clk, SPI0 divider=8
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181 cru_writel((cru_readl(CRU_CLKSEL6_CON) & ~0x1FF) | (7 << 2), CRU_CLKSEL6_CON);
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183 //eMMC divider=0x17, SD/MMC0 clock source=arm_pll_clk
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184 cru_writel((cru_readl(CRU_CLKSEL7_CON) & ~(3 | (0x3f << 18))) | (0x17 << 18), CRU_CLKSEL7_CON);
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186 //UART1 clock divider=0, UART1 clk =24MHz , UART0 and UART1 clock source=periph_pll_clk
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187 cru_writel((cru_readl(CRU_CLKSEL8_CON) & ~(7 | (0x3f << 14) | (3 << 20))) | (2 << 20), CRU_CLKSEL8_CON);
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189 // remap bit control = 0, normal mode
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190 writel(readl(RK29_GRF_PHYS + 0xc0) & ~(1 << 21), RK29_GRF_PHYS + 0xc0);
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191 // emmc_and_boot_en control=0, normal mode
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192 writel(readl(RK29_GRF_PHYS + 0xbc) & ~(1 << 9), RK29_GRF_PHYS + 0xbc);
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195 writel(0, RK29_CPU_AXI_BUS0_PHYS);
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196 writel(0, RK29_AXI1_PHYS);
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199 // SDMMC_CLKSRC=0, clk_source=clock divider 0
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200 writel(0, RK29_EMMC_PHYS + 0x0c);
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201 // SDMMC_CTYPE=0, card_width=1 bit mode
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202 writel(0, RK29_EMMC_PHYS + 0x18);
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203 // SDMMC_BLKSIZ=0x200, Block size=512
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204 writel(0x200, RK29_EMMC_PHYS + 0x1c);
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207 __cpuc_flush_kern_all();
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208 __cpuc_flush_user_all();
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