1 #ifndef __MACH_RK2928_IOMUX_H
2 #define __MACH_RK2928_IOMUX_H
4 #include <plat/iomux.h>
6 #define GRF_IOMUX_BASE (RK2928_GRF_BASE + 0x00a8)
10 GPIO0_A0 = 0x0a00, I2C0_SCL,
11 GPIO0_A1 = 0x0a10, I2C0_SDA,
12 GPIO0_A2 = 0x0a20, I2C1_SCL,
13 GPIO0_A3 = 0x0a30, I2C1_SDA,
14 GPIO0_A6 = 0x0a60, I2C3_SCL, HDMI_DDCSCL,
15 GPIO0_A7 = 0x0a70, I2C3_SDA, HDMI_DDCSDA,
18 GPIO0_B0 = 0x0b00, MMC1_CMD,
19 GPIO0_B1 = 0x0b10, MMC1_CLKOUT,
20 GPIO0_B2 = 0x0b20, MMC1_DETN,
21 GPIO0_B3 = 0x0b30, MMC1_D0,
22 GPIO0_B4 = 0x0b40, MMC1_D1,
23 GPIO0_B5 = 0x0b50, MMC1_D2,
24 GPIO0_B6 = 0x0b60, MMC1_D3,
25 GPIO0_B7 = 0x0b70, HDMI_HOTPLUGIN,
28 GPIO0_C0 = 0x0c00, UART0_SOUT,
29 GPIO0_C1 = 0x0c10, UART0_SIN,
30 GPIO0_C2 = 0x0c20, UART0_RTSN,
31 GPIO0_C3 = 0x0c30, UART0_CTSN,
32 GPIO0_C4 = 0x0c40, HDMI_CECSDA,
33 GPIO0_C7 = 0x0c70, NAND_CS1,
36 GPIO0_D0 = 0x0d00, UART2_RTSN,
37 GPIO0_D1 = 0x0d10, UART2_CTSN,
38 GPIO0_D2 = 0x0d20, PWM0,
39 GPIO0_D3 = 0x0d30, PWM1,
40 GPIO0_D4 = 0x0d40, PWM2,
41 GPIO0_D5 = 0x0d50, MMC1_WRPRT,
42 GPIO0_D6 = 0x0d60, MMC1_PWREN,
43 GPIO0_D7 = 0x0d70, MMC1_BKEPWR,
46 GPIO1_A0 = 0x1a00, I2S0_MCLK,
47 GPIO1_A1 = 0x1a10, I2S0_SCLK,
48 GPIO1_A2 = 0x1a20, I2S0_LRCKRX, GPS_CLK,
49 GPIO1_A3 = 0x1a30, I2S0_LRCKTX,
50 GPIO1_A4 = 0x1a40, I2S0_SDO, GPS_MAG,
51 GPIO1_A5 = 0x1a50, I2S0_SDI, GPS_SIGN,
52 GPIO1_A6 = 0x1a60, MMC1_INTN,
53 GPIO1_A7 = 0x1a70, MMC0_WRPRT,
56 GPIO1_B0 = 0x1b00, SPI0_CLK, UART1_CTSN,
57 GPIO1_B1 = 0x1b10, SPI0_TXD, UART1_SOUT,
58 GPIO1_B2 = 0x1b20, SPI0_RXD, UART1_SIN,
59 GPIO1_B3 = 0x1b30, SPI0_CS0, UART1_RTSN,
60 GPIO1_B4 = 0x1b40, SPI0_CS1,
61 GPIO1_B5 = 0x1b50, MMC0_RSTNOUT,
62 GPIO1_B6 = 0x1b60, MMC0_PWREN,
63 GPIO1_B7 = 0x1b70, MMC0_CMD,
66 GPIO1_C0 = 0x1c00, MMC0_CLKOUT,
67 GPIO1_C1 = 0x1c10, MMC0_DETN,
68 GPIO1_C2 = 0x1c20, MMC0_D0,
69 GPIO1_C3 = 0x1c30, MMC0_D1,
70 GPIO1_C4 = 0x1c40, MMC0_D2,
71 GPIO1_C5 = 0x1c50, MMC0_D3,
72 GPIO1_C6 = 0x1c60, NAND_CS2, EMMC_CMD,
73 GPIO1_C7 = 0x1c70, NAND_CS3, EMMC_RSTNOUT,
76 GPIO1_D0 = 0x1d00, NAND_D0, EMMC_D0,
77 GPIO1_D1 = 0x1d10, NAND_D1, EMMC_D1,
78 GPIO1_D2 = 0x1d20, NAND_D2, EMMC_D2,
79 GPIO1_D3 = 0x1d30, NAND_D3, EMMC_D3,
80 GPIO1_D4 = 0x1d40, NAND_D4, EMMC_D4,
81 GPIO1_D5 = 0x1d50, NAND_D5, EMMC_D5,
82 GPIO1_D6 = 0x1d60, NAND_D6, EMMC_D6,
83 GPIO1_D7 = 0x1d70, NAND_D7, EMMC_D7,
86 GPIO2_A0 = 0x2a00, NAND_ALE,
87 GPIO2_A1 = 0x2a10, NAND_CLE,
88 GPIO2_A2 = 0x2a20, NAND_WRN,
89 GPIO2_A3 = 0x2a30, NAND_RDN,
90 GPIO2_A4 = 0x2a40, NAND_RDY,
91 GPIO2_A5 = 0x2a50, NAND_WP, EMMC_PWREN,
92 GPIO2_A6 = 0x2a60, NAND_CS0,
93 GPIO2_A7 = 0x2a70, NAND_DQS, EMMC_CLKOUT,
96 GPIO2_B0 = 0x2b00, LCDC0_DCLK, LCDC1_DCLK,
97 GPIO2_B1 = 0x2b10, LCDC0_HSYNC, LCDC1_HSYNC,
98 GPIO2_B2 = 0x2b20, LCDC0_VSYNC, LCDC1_VSYNC,
99 GPIO2_B3 = 0x2b30, LCDC0_DEN, LCDC1_DEN,
100 GPIO2_B4 = 0x2b40, LCDC0_D10, LCDC1_D10,
101 GPIO2_B5 = 0x2b50, LCDC0_D11, LCDC1_D11,
102 GPIO2_B6 = 0x2b60, LCDC0_D12, LCDC1_D12,
103 GPIO2_B7 = 0x2b70, LCDC0_D13, LCDC1_D13,
106 GPIO2_C0 = 0x2c00, LCDC0_D14, LCDC1_D14,
107 GPIO2_C1 = 0x2c10, LCDC0_D15, LCDC1_D15,
108 GPIO2_C2 = 0x2c20, LCDC0_D16, LCDC1_D16,
109 GPIO2_C3 = 0x2c30, LCDC0_D17, LCDC1_D17,
110 GPIO2_C4 = 0x2c40, LCDC0_D18, LCDC1_D18, I2C2_SDA,
111 GPIO2_C5 = 0x2c50, LCDC0_D19, LCDC1_D19, I2C2_SCL,
112 GPIO2_C6 = 0x2c60, LCDC0_D20, LCDC1_D20, UART2_SIN,
113 GPIO2_C7 = 0x2c70, LCDC0_D21, LCDC1_D21, UART2_SOUT,
116 GPIO2_D0 = 0x2d00, LCDC0_D22, LCDC1_D22,
117 GPIO2_D1 = 0x2d10, LCDC0_D23, LCDC1_D23,
122 GPIO3_C1 = 0x3c10, OTG_DRV_VBUS,
125 GPIO3_D7 = 0x3d70, TEST_CLK_OUT,
128 void __init iomux_init(void);