arch/arm/mach-rk2928/pm.c

   1 #include <linux/clk.h>
   2 #include <linux/delay.h>
   3 #include <linux/err.h>
   4 #include <linux/kernel.h>
   5 #include <linux/init.h>
   6 #include <linux/pm.h>
   7 #include <linux/suspend.h>
   8 #include <linux/random.h>
   9 #include <linux/crc32.h>
  10 #include <linux/io.h>
  11 #include <linux/wakelock.h>
  12 #include <asm/cacheflush.h>
  13 #include <asm/tlbflush.h>
  14 #include <asm/hardware/cache-l2x0.h>
  15 #include <asm/hardware/gic.h>
  16
  17 #include <mach/pmu.h>
  18 #include <mach/board.h>
  19 #include <mach/system.h>
  20 #include <mach/sram.h>
  21 #include <mach/gpio.h>
  22 #include <mach/iomux.h>
  23 #include <mach/cru.h>
  24
  25 #define cru_readl(offset)       readl_relaxed(RK2928_CRU_BASE + offset)
  26 #define cru_writel(v, offset)   do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
  27
  28 #define grf_readl(offset)       readl_relaxed(RK2928_GRF_BASE + offset)
  29 #define grf_writel(v, offset)   do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
  30
  31 #define gate_save_soc_clk(val, _save, cons, w_msk) \
  32         do { \
  33                 (_save) = cru_readl(cons); \
  34                 cru_writel(((~(val) | (_save)) & (w_msk)) | ((w_msk) << 16), cons); \
  35         } while (0)
  36
  37 void __sramfunc sram_printch(char byte)
  38 {
  39 #ifdef DEBUG_UART_BASE
  40         u32 clk_gate2, clk_gate4, clk_gate8;
  41
  42         gate_save_soc_clk(0
  43                           | (1 << CLK_GATE_ACLK_PERIPH % 16)
  44                           | (1 << CLK_GATE_HCLK_PERIPH % 16)
  45                           | (1 << CLK_GATE_PCLK_PERIPH % 16)
  46                           , clk_gate2, CRU_CLKGATES_CON(2), 0
  47                           | (1 << ((CLK_GATE_ACLK_PERIPH % 16) + 16))
  48                           | (1 << ((CLK_GATE_HCLK_PERIPH % 16) + 16))
  49                           | (1 << ((CLK_GATE_PCLK_PERIPH % 16) + 16)));
  50         gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
  51                           , clk_gate4, CRU_CLKGATES_CON(4),
  52                           (1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
  53         gate_save_soc_clk((1 << ((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16)),
  54                           clk_gate8, CRU_CLKGATES_CON(8),
  55                           (1 << (((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16) + 16)));
  56         sram_udelay(1);
  57
  58         writel_relaxed(byte, DEBUG_UART_BASE);
  59         dsb();
  60
  61         /* loop check LSR[6], Transmitter Empty bit */
  62         while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
  63                 barrier();
  64
  65         cru_writel(0xffff0000 | clk_gate2, CRU_CLKGATES_CON(2));
  66         cru_writel(0xffff0000 | clk_gate4, CRU_CLKGATES_CON(4));
  67         cru_writel(0xffff0000 | clk_gate8, CRU_CLKGATES_CON(8));
  68
  69         if (byte == '\n')
  70                 sram_printch('\r');
  71 #endif
  72 }
  73
  74 __weak void __sramfunc ddr_suspend(void) {}
  75 __weak void __sramfunc ddr_resume(void) {}
  76 __weak uint32_t __sramfunc ddr_change_freq(uint32_t nMHz) { return nMHz; }
  77
  78 #ifdef CONFIG_DDR_TEST
  79 static int ddr_debug=0;
  80 module_param(ddr_debug, int, 0644);
  81
  82 static int inline calc_crc32(u32 addr, size_t len)
  83 {
  84         return crc32_le(~0, (const unsigned char *)addr, len);
  85 }
  86
  87 static void ddr_testmode(void)
  88 {
  89         int32_t g_crc1, g_crc2;
  90         uint32_t nMHz;
  91         uint32_t n = 0;
  92         uint32_t min,max;
  93         extern char _stext[], _etext[];
  94
  95
  96         if (ddr_debug == 1) {
  97                 max=500;
  98                 min=100;
  99                 for (;;) {
 100                         sram_printascii("\n change freq:");
 101                         g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 102                         do
 103                         {
 104                             nMHz = min + random32();
 105                             nMHz %= max;
 106                         }while(nMHz < min);
 107                         sram_printhex(nMHz);
 108                         sram_printch(' ');
 109                         nMHz = ddr_change_freq(nMHz);
 110                         sram_printhex(n++);
 111                         sram_printch(' ');
 112                         g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 113                         if (g_crc1!=g_crc2) {
 114                                 sram_printascii("fail\n");
 115                         }
 116                         //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 117                         //     sram_printascii("change freq success\n");
 118                 }
 119         } else if(ddr_debug == 2) {
 120                 for (;;) {
 121                         sram_printch(' ');
 122                         sram_printch('9');
 123                         sram_printch('9');
 124                         sram_printch('9');
 125                         sram_printch(' ');
 126                         g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 127                         nMHz = (random32()>>13);// 16.7s max
 128                         ddr_suspend();
 129                         sram_udelay(nMHz);
 130                         ddr_resume();
 131                         sram_printhex(nMHz);
 132                         sram_printch(' ');
 133                         sram_printhex(n++);
 134                         g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
 135                         if (g_crc1 != g_crc2) {
 136                                 sram_printch(' ');
 137                                 sram_printch('f');
 138                                 sram_printch('a');
 139                                 sram_printch('i');
 140                                 sram_printch('l');
 141                         }
 142                         // ddr_print("check image crc32 fail!, count:%d\n", n++);
 143                         //    sram_printascii("self refresh fail\n");
 144                         //else
 145                         //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
 146                         //    sram_printascii("self refresh success\n");
 147                 }
 148         } else if (ddr_debug == 3) {
 149                 extern int memtester(void);
 150                 memtester();
 151         }
 152         else
 153         {
 154             ddr_change_freq(ddr_debug);
 155             ddr_debug=0;
 156         }
 157 }
 158 #else
 159 static void ddr_testmode(void) {}
 160 #endif
 161
 162 static noinline void rk2928_pm_dump_irq(void)
 163 {
 164         u32 irq_gpio = (readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + (IRQ_GPIO0 / 32) * 4) >> (IRQ_GPIO0 % 32)) & 0xF;
 165         printk("wakeup irq: %08x %08x %08x\n",
 166                 readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 4),
 167                 readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 8),
 168                 readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 12));
 169         if (irq_gpio & 1)
 170                 printk("wakeup gpio0: %08x\n", readl_relaxed(RK2928_GPIO0_BASE + GPIO_INT_STATUS));
 171         if (irq_gpio & 2)
 172                 printk("wakeup gpio1: %08x\n", readl_relaxed(RK2928_GPIO1_BASE + GPIO_INT_STATUS));
 173         if (irq_gpio & 4)
 174                 printk("wakeup gpio2: %08x\n", readl_relaxed(RK2928_GPIO2_BASE + GPIO_INT_STATUS));
 175         if (irq_gpio & 8)
 176                 printk("wakeup gpio3: %08x\n", readl_relaxed(RK2928_GPIO3_BASE + GPIO_INT_STATUS));
 177 }
 178
 179 #define DUMP_GPIO_INTEN(ID) \
 180 do { \
 181         u32 en = readl_relaxed(RK2928_GPIO##ID##_BASE + GPIO_INTEN); \
 182         if (en) { \
 183                 sram_printascii("GPIO" #ID "_INTEN: "); \
 184                 sram_printhex(en); \
 185                 sram_printch('\n'); \
 186         } \
 187 } while (0)
 188
 189 static noinline void rk2928_pm_dump_inten(void)
 190 {
 191         DUMP_GPIO_INTEN(0);
 192         DUMP_GPIO_INTEN(1);
 193         DUMP_GPIO_INTEN(2);
 194         DUMP_GPIO_INTEN(3);
 195 }
 196
 197 static void pm_pll_wait_lock(int pll_idx)
 198 {
 199         u32 pll_state[4] = { 1, 0, 2, 3 };
 200         u32 bit = 0x10u << pll_state[pll_idx];
 201         u32 delay = pll_idx == APLL_ID ? 24000000U : 2400000000U;
 202         while (delay > 0) {
 203                 if (grf_readl(GRF_SOC_STATUS0) & bit)
 204                         break;
 205                 delay--;
 206         }
 207         if (delay == 0) {
 208                 //CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
 209                 sram_printch('p');
 210                 sram_printch('l');
 211                 sram_printch('l');
 212                 sram_printhex(pll_idx);
 213                 sram_printch('\n');
 214         }
 215 }
 216
 217 #define power_on_pll(id) \
 218         cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
 219         pm_pll_wait_lock((id))
 220
 221 #define DDR_SAVE_SP(save_sp)            do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
 222 #define DDR_RESTORE_SP(save_sp)         do { ddr_save_sp(save_sp); } while (0)
 223
 224 static unsigned long save_sp;
 225
 226 static noinline void interface_ctr_reg_pread(void)
 227 {
 228         u32 addr;
 229
 230         flush_cache_all();
 231         outer_flush_all();
 232         local_flush_tlb_all();
 233
 234         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)SRAM_DATA_END; addr += PAGE_SIZE)
 235                 readl_relaxed(addr);
 236         readl_relaxed(RK2928_GRF_BASE);
 237         readl_relaxed(RK2928_DDR_PCTL_BASE);
 238         readl_relaxed(RK2928_DDR_PHY_BASE);
 239         readl_relaxed(RK2928_GPIO0_BASE);
 240         readl_relaxed(RK2928_GPIO1_BASE);
 241         readl_relaxed(RK2928_GPIO2_BASE);
 242         readl_relaxed(RK2928_GPIO3_BASE);
 243         #if defined (CONFIG_MACH_RK2928_SDK)
 244         readl_relaxed(RK2928_RKI2C1_BASE);
 245         #else
 246         readl_relaxed(RK2928_RKI2C0_BASE);
 247         #endif
 248 }
 249
 250 __weak void board_gpio_suspend(void) {}
 251 __weak void board_gpio_resume(void) {}
 252 __weak void __sramfunc board_pmu_suspend(void) {}
 253 __weak void __sramfunc board_pmu_resume(void) {}
 254 __weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol) {}
 255 __weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol) {}
 256
 257 __weak void rk30_pwm_suspend_voltage_set(void) {}
 258 __weak void rk30_pwm_resume_voltage_set(void) {}
 259
 260 __weak void __sramfunc rk30_pwm_logic_suspend_voltage(void) {}
 261 __weak void __sramfunc rk30_pwm_logic_resume_voltage(void) {}
 262
 263 static void __sramfunc rk2928_sram_suspend(void)
 264 {
 265         u32 cru_clksel0_con;
 266         u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
 267         int i;
 268
 269         sram_printch('5');
 270         ddr_suspend();
 271         sram_printch('6');
 272         rk30_suspend_voltage_set(1000000);
 273         rk30_pwm_logic_suspend_voltage();
 274         board_pmu_suspend();
 275         sram_printch('7');
 276
 277
 278         for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
 279                 clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
 280         }
 281         gate_save_soc_clk(0
 282                           | (1 << CLK_GATE_CORE_PERIPH)
 283                           | (1 << CLK_GATE_DDRPHY_SRC)
 284                           | (1 << CLK_GATE_ACLK_CPU)
 285                           | (1 << CLK_GATE_HCLK_CPU)
 286                           | (1 << CLK_GATE_PCLK_CPU)
 287                           | (1 << CLK_GATE_ACLK_CORE)
 288                           , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
 289         if (((clkgt_regs[8] >> (CLK_GATE_PCLK_GPIO0 % 16)) & 0xf) != 0xf) {
 290                 gate_save_soc_clk(0
 291                                   | (1 << CLK_GATE_PERIPH_SRC % 16)
 292                                   | (1 << CLK_GATE_PCLK_PERIPH % 16)
 293                                   , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
 294         } else {
 295                 gate_save_soc_clk(0, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
 296         }
 297         gate_save_soc_clk(0
 298                           | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
 299                           | (1 << CLK_GATE_ACLK_INTMEM % 16)
 300                           , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
 301         gate_save_soc_clk(0
 302                           | (1 << CLK_GATE_PCLK_GRF % 16)
 303                           | (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
 304                           , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
 305         gate_save_soc_clk(0, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
 306         gate_save_soc_clk(0
 307                           | (1 << CLK_GATE_CLK_L2C % 16)
 308                           , clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff);
 309
 310 //      board_pmu_suspend();
 311         cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
 312         cru_writel((0x1f << 16) | 0x1f, CRU_CLKSELS_CON(0));
 313
 314         dsb();
 315         wfi();
 316
 317         cru_writel((0x1f << 16) | cru_clksel0_con, CRU_CLKSELS_CON(0));
 318 //      board_pmu_resume();
 319
 320         for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
 321                 cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
 322         }
 323
 324         sram_printch('7');
 325         board_pmu_resume();
 326         rk30_pwm_logic_resume_voltage();
 327         rk30_suspend_voltage_resume(1100000);
 328
 329         sram_printch('6');
 330         ddr_resume();
 331         sram_printch('5');
 332 }
 333
 334 static void noinline rk2928_suspend(void)
 335 {
 336         DDR_SAVE_SP(save_sp);
 337         rk2928_sram_suspend();
 338         DDR_RESTORE_SP(save_sp);
 339 }
 340
 341 static int rk2928_pm_enter(suspend_state_t state)
 342 {
 343         u32 i;
 344         u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
 345         u32 clk_sel0, clk_sel1, clk_sel10;
 346         u32 cru_mode_con;
 347         u32 apll_con1,cpll_con1,gpll_con1;
 348         // dump GPIO INTEN for debug
 349         rk2928_pm_dump_inten();
 350
 351         sram_printch('0');
 352
 353 #ifdef CONFIG_DDR_TEST
 354         // memory tester
 355         if (ddr_debug != 0)
 356                 ddr_testmode();
 357 #endif
 358
 359         sram_printch('1');
 360         local_fiq_disable();
 361
 362         for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
 363                 clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
 364         }
 365
 366         gate_save_soc_clk(0
 367                           | (1 << CLK_GATE_CORE_PERIPH)
 368                           | (1 << CLK_GATE_CPU_GPLL)
 369                           | (1 << CLK_GATE_DDRPHY_SRC)
 370                           | (1 << CLK_GATE_ACLK_CPU)
 371                           | (1 << CLK_GATE_HCLK_CPU)
 372                           | (1 << CLK_GATE_PCLK_CPU)
 373                           | (1 << CLK_GATE_ACLK_CORE)
 374                           , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
 375         gate_save_soc_clk(0, clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
 376         gate_save_soc_clk(0
 377                           | (1 << CLK_GATE_PERIPH_SRC % 16)
 378                           | (1 << CLK_GATE_PCLK_PERIPH % 16)
 379                           | (1 << CLK_GATE_ACLK_PERIPH % 16)
 380                           , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
 381         gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xffff);
 382         gate_save_soc_clk(0
 383                           | (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16)
 384                           | (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16)
 385                           | (1 << CLK_GATE_ACLK_CPU_PERI % 16)
 386                           | (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16)
 387                           | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
 388                           | (1 << CLK_GATE_ACLK_INTMEM % 16)
 389                           , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
 390         gate_save_soc_clk(0
 391                           | (1 << CLK_GATE_PCLK_GRF % 16)
 392                           | (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
 393                           , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
 394         gate_save_soc_clk(0, clkgt_regs[6], CRU_CLKGATES_CON(6), 0xffff);
 395         gate_save_soc_clk(0
 396                           | (1 << CLK_GATE_PCLK_PWM01 % 16)
 397                           , clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
 398         gate_save_soc_clk(0
 399                           | (1 << CLK_GATE_PCLK_GPIO0 % 16)
 400                           | (1 << CLK_GATE_PCLK_GPIO1 % 16)
 401                           | (1 << CLK_GATE_PCLK_GPIO2 % 16)
 402                           | (1 << CLK_GATE_PCLK_GPIO3 % 16)
 403                           , clkgt_regs[8], CRU_CLKGATES_CON(8), 0xffff);
 404         cru_writel( ((1 << CLK_GATE_PCLK_GPIO0 % 16)<<16),  CRU_CLKGATES_CON(8));
 405         gate_save_soc_clk(0
 406                           | (1 << CLK_GATE_CLK_L2C % 16)
 407                           | (1 << CLK_GATE_HCLK_PERI_ARBI % 16)
 408                           | (1 << CLK_GATE_ACLK_PERI_NIU % 16)
 409                           , clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff);
 410
 411         sram_printch('2');
 412
 413         cru_mode_con = cru_readl(CRU_MODE_CON);
 414
 415         //apll
 416         clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
 417         clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
 418         apll_con1 = cru_readl(PLL_CONS(APLL_ID, 1));
 419
 420         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 421         cru_writel(CLK_CORE_DIV(1) | ACLK_CPU_DIV(1) | CPU_SEL_PLL(SEL_APLL), CRU_CLKSELS_CON(0));
 422         cru_writel(CLK_CORE_PERI_DIV(1) | ACLK_CORE_DIV(1) | HCLK_CPU_DIV(1) | PCLK_CPU_DIV(1), CRU_CLKSELS_CON(1));
 423         //cru_writel((0x01 <<(PLL_PWR_DN_SHIFT + 16))|(1<<PLL_PWR_DN_SHIFT), PLL_CONS(APLL_ID, 1));
 424         cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT) , PLL_CONS(APLL_ID, 1)); //power down apll
 425
 426         //cpll
 427         cpll_con1 =   cru_readl(PLL_CONS(CPLL_ID, 1));
 428
 429         cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
 430         cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT), PLL_CONS(CPLL_ID, 1));//power down cpll
 431
 432         //gpll
 433         clk_sel10 = cru_readl(CRU_CLKSELS_CON(10));
 434         gpll_con1 = cru_readl(PLL_CONS(GPLL_ID, 1));
 435
 436         cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
 437         cru_writel(PERI_SET_ACLK_DIV(1)
 438                    | PERI_SET_A2H_RATIO(RATIO_11)
 439                    | PERI_SET_A2P_RATIO(RATIO_11)
 440                    , CRU_CLKSELS_CON(10));
 441         cru_writel(CRU_W_MSK_SETBIT(0x01, PLL_PWR_DN_SHIFT), PLL_CONS(GPLL_ID, 1));//power down gpll
 442
 443         sram_printch('3');
 444         rk30_pwm_suspend_voltage_set();
 445
 446         board_gpio_suspend();
 447
 448         interface_ctr_reg_pread();
 449
 450         sram_printch('4');
 451         rk2928_suspend();
 452         sram_printch('4');
 453
 454         board_gpio_resume();
 455         rk30_pwm_resume_voltage_set();
 456         sram_printch('3');
 457
 458         //gpll
 459         cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01)|gpll_con1, PLL_CONS(GPLL_ID, 1));
 460         cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
 461         cru_writel(clk_sel10, CRU_CLKSELS_CON(10));
 462         cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
 463
 464         //cpll
 465         cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01)|cpll_con1, PLL_CONS(CPLL_ID, 1));
 466         cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
 467
 468         //apll
 469         cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01)|apll_con1, PLL_CONS(APLL_ID, 1));
 470         cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
 471         cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
 472         cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);
 473
 474         sram_printch('2');
 475
 476         for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
 477                 cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
 478         }
 479
 480         local_fiq_enable();
 481         sram_printch('1');
 482
 483         sram_printascii("0\n");
 484
 485         rk2928_pm_dump_irq();
 486
 487         return 0;
 488 }
 489
 490 static int rk2928_pm_prepare(void)
 491 {
 492         /* disable entering idle by disable_hlt() */
 493         disable_hlt();
 494         return 0;
 495 }
 496
 497 static void rk2928_pm_finish(void)
 498 {
 499         enable_hlt();
 500 }
 501
 502 static struct platform_suspend_ops rk2928_pm_ops = {
 503         .enter          = rk2928_pm_enter,
 504         .valid          = suspend_valid_only_mem,
 505         .prepare        = rk2928_pm_prepare,
 506         .finish         = rk2928_pm_finish,
 507 };
 508
 509 static int __init rk2928_pm_init(void)
 510 {
 511         suspend_set_ops(&rk2928_pm_ops);
 512
 513 #ifdef CONFIG_EARLYSUSPEND
 514         pm_set_vt_switch(0); /* disable vt switch while suspend */
 515 #endif
 516
 517         return 0;
 518 }
 519 __initcall(rk2928_pm_init);