2 #include <linux/delay.h>
4 #include <linux/kernel.h>
5 #include <linux/init.h>
7 #include <linux/suspend.h>
8 #include <linux/random.h>
9 #include <linux/crc32.h>
11 #include <linux/wakelock.h>
12 #include <asm/cacheflush.h>
13 #include <asm/tlbflush.h>
14 #include <asm/hardware/cache-l2x0.h>
15 #include <asm/hardware/gic.h>
18 #include <mach/board.h>
19 #include <mach/system.h>
20 #include <mach/sram.h>
21 #include <mach/gpio.h>
22 #include <mach/iomux.h>
25 #define cru_readl(offset) readl_relaxed(RK2928_CRU_BASE + offset)
26 #define cru_writel(v, offset) do { writel_relaxed(v, RK2928_CRU_BASE + offset); dsb(); } while (0)
28 #define grf_readl(offset) readl_relaxed(RK2928_GRF_BASE + offset)
29 #define grf_writel(v, offset) do { writel_relaxed(v, RK2928_GRF_BASE + offset); dsb(); } while (0)
31 #define gate_save_soc_clk(val, _save, cons, w_msk) \
33 (_save) = cru_readl(cons); \
34 cru_writel(((~(val) | (_save)) & (w_msk)) | ((w_msk) << 16), cons); \
37 void __sramfunc sram_printch(char byte)
39 #ifdef DEBUG_UART_BASE
40 u32 clk_gate2, clk_gate4, clk_gate8;
43 | (1 << CLK_GATE_ACLK_PERIPH % 16)
44 | (1 << CLK_GATE_HCLK_PERIPH % 16)
45 | (1 << CLK_GATE_PCLK_PERIPH % 16)
46 , clk_gate2, CRU_CLKGATES_CON(2), 0
47 | (1 << ((CLK_GATE_ACLK_PERIPH % 16) + 16))
48 | (1 << ((CLK_GATE_HCLK_PERIPH % 16) + 16))
49 | (1 << ((CLK_GATE_PCLK_PERIPH % 16) + 16)));
50 gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
51 , clk_gate4, CRU_CLKGATES_CON(4),
52 (1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
53 gate_save_soc_clk((1 << ((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16)),
54 clk_gate8, CRU_CLKGATES_CON(8),
55 (1 << (((CLK_GATE_PCLK_UART0 + CONFIG_RK_DEBUG_UART) % 16) + 16)));
58 writel_relaxed(byte, DEBUG_UART_BASE);
61 /* loop check LSR[6], Transmitter Empty bit */
62 while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
65 cru_writel(0xffff0000 | clk_gate2, CRU_CLKGATES_CON(2));
66 cru_writel(0xffff0000 | clk_gate4, CRU_CLKGATES_CON(4));
67 cru_writel(0xffff0000 | clk_gate8, CRU_CLKGATES_CON(8));
74 __weak void __sramfunc ddr_suspend(void) {}
75 __weak void __sramfunc ddr_resume(void) {}
76 __weak uint32_t __sramfunc ddr_change_freq(uint32_t nMHz) { return nMHz; }
78 #ifdef CONFIG_DDR_TEST
79 static int ddr_debug=0;
80 module_param(ddr_debug, int, 0644);
82 static int inline calc_crc32(u32 addr, size_t len)
84 return crc32_le(~0, (const unsigned char *)addr, len);
87 static void ddr_testmode(void)
89 int32_t g_crc1, g_crc2;
93 extern char _stext[], _etext[];
100 sram_printascii("\n change freq:");
101 g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
104 nMHz = min + random32();
109 nMHz = ddr_change_freq(nMHz);
112 g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
113 if (g_crc1!=g_crc2) {
114 sram_printascii("fail\n");
116 //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
117 // sram_printascii("change freq success\n");
119 } else if(ddr_debug == 2) {
126 g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
127 nMHz = (random32()>>13);// 16.7s max
134 g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
135 if (g_crc1 != g_crc2) {
142 // ddr_print("check image crc32 fail!, count:%d\n", n++);
143 // sram_printascii("self refresh fail\n");
145 //ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
146 // sram_printascii("self refresh success\n");
148 } else if (ddr_debug == 3) {
149 extern int memtester(void);
154 ddr_change_freq(ddr_debug);
159 static void ddr_testmode(void) {}
162 static noinline void rk2928_pm_dump_irq(void)
164 u32 irq_gpio = (readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + (IRQ_GPIO0 / 32) * 4) >> (IRQ_GPIO0 % 32)) & 0xF;
165 printk("wakeup irq: %08x %08x %08x\n",
166 readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 4),
167 readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 8),
168 readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 12));
170 printk("wakeup gpio0: %08x\n", readl_relaxed(RK2928_GPIO0_BASE + GPIO_INT_STATUS));
172 printk("wakeup gpio1: %08x\n", readl_relaxed(RK2928_GPIO1_BASE + GPIO_INT_STATUS));
174 printk("wakeup gpio2: %08x\n", readl_relaxed(RK2928_GPIO2_BASE + GPIO_INT_STATUS));
176 printk("wakeup gpio3: %08x\n", readl_relaxed(RK2928_GPIO3_BASE + GPIO_INT_STATUS));
179 #define DUMP_GPIO_INTEN(ID) \
181 u32 en = readl_relaxed(RK2928_GPIO##ID##_BASE + GPIO_INTEN); \
183 sram_printascii("GPIO" #ID "_INTEN: "); \
185 sram_printch('\n'); \
189 static noinline void rk2928_pm_dump_inten(void)
197 static void pm_pll_wait_lock(int pll_idx)
199 u32 pll_state[4] = { 1, 0, 2, 3 };
200 u32 bit = 0x10u << pll_state[pll_idx];
201 u32 delay = pll_idx == APLL_ID ? 24000000U : 2400000000U;
203 if (grf_readl(GRF_SOC_STATUS0) & bit)
208 //CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
212 sram_printhex(pll_idx);
217 #define power_on_pll(id) \
218 cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
219 pm_pll_wait_lock((id))
221 #define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
222 #define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
224 static unsigned long save_sp;
226 static noinline void interface_ctr_reg_pread(void)
232 local_flush_tlb_all();
234 for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)SRAM_DATA_END; addr += PAGE_SIZE)
236 readl_relaxed(RK2928_GRF_BASE);
237 readl_relaxed(RK2928_DDR_PCTL_BASE);
238 readl_relaxed(RK2928_DDR_PHY_BASE);
239 // readl_relaxed(RK2928_I2C1_BASE);
242 __weak void board_gpio_suspend(void) {}
243 __weak void board_gpio_resume(void) {}
244 __weak void __sramfunc board_pmu_suspend(void) {}
245 __weak void __sramfunc board_pmu_resume(void) {}
246 __weak void __sramfunc rk30_suspend_voltage_set(unsigned int vol) {}
247 __weak void __sramfunc rk30_suspend_voltage_resume(unsigned int vol) {}
249 __weak void rk30_pwm_suspend_voltage_set(void) {}
250 __weak void rk30_pwm_resume_voltage_set(void) {}
252 __weak void __sramfunc rk30_pwm_logic_suspend_voltage(void) {}
253 __weak void __sramfunc rk30_pwm_logic_resume_voltage(void) {}
255 static void __sramfunc rk2928_sram_suspend(void)
258 u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
264 rk30_suspend_voltage_set(1000000);
265 rk30_pwm_logic_suspend_voltage();
268 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
269 clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
272 | (1 << CLK_GATE_CORE_PERIPH)
273 | (1 << CLK_GATE_DDRPHY_SRC)
274 | (1 << CLK_GATE_ACLK_CPU)
275 | (1 << CLK_GATE_HCLK_CPU)
276 | (1 << CLK_GATE_PCLK_CPU)
277 | (1 << CLK_GATE_ACLK_CORE)
278 , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
279 if (((clkgt_regs[8] >> (CLK_GATE_PCLK_GPIO0 % 16)) & 0xf) != 0xf) {
281 | (1 << CLK_GATE_PERIPH_SRC % 16)
282 | (1 << CLK_GATE_PCLK_PERIPH % 16)
283 , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
285 gate_save_soc_clk(0, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
288 | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
289 | (1 << CLK_GATE_ACLK_INTMEM % 16)
290 , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
292 | (1 << CLK_GATE_PCLK_GRF % 16)
293 | (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
294 , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
295 gate_save_soc_clk(0, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
297 | (1 << CLK_GATE_CLK_L2C % 16)
298 , clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff);
301 cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
302 cru_writel((0x1f << 16) | 0x1f, CRU_CLKSELS_CON(0));
307 cru_writel((0x1f << 16) | cru_clksel0_con, CRU_CLKSELS_CON(0));
310 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
311 cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
315 rk30_pwm_logic_resume_voltage();
316 rk30_suspend_voltage_resume(1100000);
323 static void noinline rk2928_suspend(void)
325 DDR_SAVE_SP(save_sp);
326 rk2928_sram_suspend();
327 DDR_RESTORE_SP(save_sp);
330 static int rk2928_pm_enter(suspend_state_t state)
333 u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
334 u32 clk_sel0, clk_sel1, clk_sel10;
337 // dump GPIO INTEN for debug
338 rk2928_pm_dump_inten();
342 #ifdef CONFIG_DDR_TEST
351 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
352 clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
356 | (1 << CLK_GATE_CORE_PERIPH)
357 | (1 << CLK_GATE_CPU_GPLL)
358 | (1 << CLK_GATE_DDRPHY_SRC)
359 | (1 << CLK_GATE_ACLK_CPU)
360 | (1 << CLK_GATE_HCLK_CPU)
361 | (1 << CLK_GATE_PCLK_CPU)
362 | (1 << CLK_GATE_ACLK_CORE)
363 , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff);
364 gate_save_soc_clk(0, clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
366 | (1 << CLK_GATE_PERIPH_SRC % 16)
367 | (1 << CLK_GATE_PCLK_PERIPH % 16)
368 | (1 << CLK_GATE_ACLK_PERIPH % 16)
369 , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
370 gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xffff);
372 | (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16)
373 | (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16)
374 | (1 << CLK_GATE_ACLK_CPU_PERI % 16)
375 | (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16)
376 | (1 << CLK_GATE_ACLK_STRC_SYS % 16)
377 | (1 << CLK_GATE_ACLK_INTMEM % 16)
378 , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff);
380 | (1 << CLK_GATE_PCLK_GRF % 16)
381 | (1 << CLK_GATE_PCLK_DDRUPCTL % 16)
382 , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff);
383 gate_save_soc_clk(0, clkgt_regs[6], CRU_CLKGATES_CON(6), 0xffff);
385 | (1 << CLK_GATE_PCLK_PWM01 % 16)
386 , clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff);
388 | (1 << CLK_GATE_PCLK_GPIO0 % 16)
389 | (1 << CLK_GATE_PCLK_GPIO1 % 16)
390 | (1 << CLK_GATE_PCLK_GPIO2 % 16)
391 | (1 << CLK_GATE_PCLK_GPIO3 % 16)
392 , clkgt_regs[8], CRU_CLKGATES_CON(8), 0xffff);
394 | (1 << CLK_GATE_CLK_L2C % 16)
395 | (1 << CLK_GATE_HCLK_PERI_ARBI % 16)
396 | (1 << CLK_GATE_ACLK_PERI_NIU % 16)
397 , clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff);
401 cru_mode_con = cru_readl(CRU_MODE_CON);
404 clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
405 clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
406 cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
407 cru_writel(CLK_CORE_DIV(1) | ACLK_CPU_DIV(1) | CPU_SEL_PLL(SEL_APLL), CRU_CLKSELS_CON(0));
408 cru_writel(CLK_CORE_PERI_DIV(1) | ACLK_CORE_DIV(1) | HCLK_CPU_DIV(1) | PCLK_CPU_DIV(1), CRU_CLKSELS_CON(1));
411 cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
414 clk_sel10 = cru_readl(CRU_CLKSELS_CON(10));
415 cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
416 cru_writel(PERI_SET_ACLK_DIV(1)
417 | PERI_SET_A2H_RATIO(RATIO_11)
418 | PERI_SET_A2P_RATIO(RATIO_11)
419 , CRU_CLKSELS_CON(10));
422 rk30_pwm_suspend_voltage_set();
424 board_gpio_suspend();
426 interface_ctr_reg_pread();
433 rk30_pwm_resume_voltage_set();
437 cru_writel(0xffff0000 | clk_sel10, CRU_CLKSELS_CON(10));
438 cru_writel(clk_sel10, CRU_CLKSELS_CON(10));
439 cru_writel((PLL_MODE_MSK(GPLL_ID) << 16) | (PLL_MODE_MSK(GPLL_ID) & cru_mode_con), CRU_MODE_CON);
442 cru_writel((PLL_MODE_MSK(CPLL_ID) << 16) | (PLL_MODE_MSK(CPLL_ID) & cru_mode_con), CRU_MODE_CON);
445 cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
446 cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
447 cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);
451 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
452 cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
458 sram_printascii("0\n");
460 rk2928_pm_dump_irq();
465 static int rk2928_pm_prepare(void)
467 /* disable entering idle by disable_hlt() */
472 static void rk2928_pm_finish(void)
477 static struct platform_suspend_ops rk2928_pm_ops = {
478 .enter = rk2928_pm_enter,
479 .valid = suspend_valid_only_mem,
480 .prepare = rk2928_pm_prepare,
481 .finish = rk2928_pm_finish,
484 static int __init rk2928_pm_init(void)
486 suspend_set_ops(&rk2928_pm_ops);
488 #ifdef CONFIG_EARLYSUSPEND
489 pm_set_vt_switch(0); /* disable vt switch while suspend */
494 __initcall(rk2928_pm_init);