arch/arm/mach-rk30/clock_data-rk3066b.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include <mach/clock.h>
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29 #include <mach/ddr.h>
  30
  31 #define MHZ                     (1000*1000)
  32 #define KHZ                     (1000)
  33 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  34 #define CLK_LOOPS_RATE_REF (1200) //Mhz
  35 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  36 void rk30_clk_dump_regs(void);
  37
  38 //flags bit
  39 //has extern 27mhz
  40 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  41 //max i2s rate
  42 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  43 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  44 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  45 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  46 //uart 1m\3m
  47 #define CLK_FLG_UART_1_3M                       (1<<5)
  48
  49 #define ARCH_RK31
  50
  51 struct apll_clk_set {
  52         unsigned long rate;
  53         u32     pllcon0;
  54         u32     pllcon1;
  55         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  56         u32     rst_dly;//us
  57         u32     clksel0;
  58         u32     clksel1;
  59         unsigned long lpj;
  60 };
  61 struct pll_clk_set {
  62         unsigned long rate;
  63         u32     pllcon0;
  64         u32     pllcon1;
  65         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  66         u32     rst_dly;//us
  67 };
  68
  69 #define SET_PLL_DATA(_pll_id,_table) \
  70 {\
  71         .id=(_pll_id),\
  72         .table=(_table),\
  73 }
  74
  75
  76 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  77 { \
  78         .rate   = (_mhz) * KHZ, \
  79         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  80         .pllcon1 = PLL_CLKF_SET(nf),\
  81         .rst_dly=((nr*500)/24+1),\
  82 }
  83
  84
  85 #define _APLL_SET_LPJ(_mhz) \
  86         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  87
  88
  89 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  90                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  91 { \
  92         .rate   = _mhz * MHZ, \
  93         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  94         .pllcon1 = PLL_CLKF_SET(nf),\
  95         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
  96         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
  97         _APLL_SET_LPJ(_mhz),\
  98         .rst_dly=((nr*500)/24+1),\
  99 }
 100
 101 #define CRU_DIV_SET(mask,shift,max) \
 102         .div_mask=(mask),\
 103 .div_shift=(shift),\
 104 .div_max=(max)
 105
 106
 107 #define CRU_SRC_SET(mask,shift ) \
 108         .src_mask=(mask),\
 109 .src_shift=(shift)
 110
 111 #define CRU_PARENTS_SET(parents_array) \
 112         .parents=(parents_array),\
 113 .parents_num=ARRAY_SIZE((parents_array))
 114
 115 #define CRU_GATE_MODE_SET(_func,_IDX) \
 116         .mode=_func,\
 117 .gate_idx=(_IDX)
 118
 119 struct clk_src_sel {
 120         struct clk      *parent;
 121         u8      value;//crt bit
 122         u8      flag;
 123         //selgate
 124 };
 125
 126 #define GATE_CLK(NAME,PARENT,ID) \
 127         static struct clk clk_##NAME = { \
 128                 .name           = #NAME, \
 129                 .parent         = &PARENT, \
 130                 .mode           = gate_mode, \
 131                 .gate_idx       = CLK_GATE_##ID, \
 132         }
 133 #ifdef RK30_CLK_OFFBOARD_TEST
 134 u32 TEST_GRF_REG[0x240];
 135 u32 TEST_CRU_REG[0x240];
 136 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 137
 138 u32 cru_writel_is_pr(u32 offset)
 139 {
 140         return (offset == 0x4000);
 141 }
 142 void cru_writel(u32 v, u32 offset)
 143 {
 144
 145         u32 mask_v = v >> 16;
 146         TEST_CRU_REG[offset/4] &= (~mask_v);
 147
 148         v &= (mask_v);
 149
 150         TEST_CRU_REG[offset/4] |= v;
 151         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 152
 153         if(cru_writel_is_pr(offset)) {
 154                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 155
 156         }
 157
 158 }
 159 void cru_writel_i2s(u32 v, u32 offset)
 160 {
 161         TEST_CRU_REG[offset/4] = v;
 162 }
 163 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 164
 165 #define regfile_readl(offset)   (0xffffffff)
 166 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 167 void rk30_clkdev_add(struct clk_lookup *cl);
 168 #else
 169 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 170 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 171 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 172 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 173
 174 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 175 #endif
 176
 177 //#define DEBUG
 178 #ifdef DEBUG
 179 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 180 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 181 #else
 182 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 183 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 184 #endif
 185 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 186 #define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
 187
 188
 189 #define get_cru_bits(con,mask,shift)\
 190         ((cru_readl((con)) >> (shift)) & (mask))
 191
 192 #define set_cru_bits_w_msk(val,mask,shift,con)\
 193         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 194
 195
 196 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 197                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 198
 199
 200 static u32 rk30_clock_flags = 0;
 201 static struct clk codec_pll_clk;
 202 static struct clk general_pll_clk;
 203 static struct clk arm_pll_clk;
 204 static unsigned long lpj_gpll;
 205 static unsigned int __initdata armclk = 504 * MHZ;
 206
 207
 208 /************************clk recalc div rate*********************************/
 209
 210 //for free div
 211 static unsigned long clksel_recalc_div(struct clk *clk)
 212 {
 213         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 214
 215         unsigned long rate = clk->parent->rate / div;
 216         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 217         return rate;
 218 }
 219
 220 //for div 1 2 4 2^n
 221 static unsigned long clksel_recalc_shift(struct clk *clk)
 222 {
 223         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 224         unsigned long rate = clk->parent->rate >> shift;
 225         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 226         return rate;
 227 }
 228
 229
 230 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 231 {
 232         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 233         unsigned long rate = clk->parent->rate >> shift;
 234         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 235         return rate;
 236 }
 237
 238 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 239 {
 240         unsigned long rate = clk->parent->rate;
 241         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 242         return rate;
 243 }
 244 /********************************set div rate***********************************/
 245
 246 //for free div
 247 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 248 {
 249         u32 div;
 250         for (div = 0; div < clk->div_max; div++) {
 251                 u32 new_rate = clk->parent->rate / (div + 1);
 252                 if (new_rate <= rate) {
 253                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 254                         //clk->rate = new_rate;
 255                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 256                                         clk->name, rate, div + 1);
 257                         return 0;
 258                 }
 259         }
 260         return -ENOENT;
 261 }
 262
 263 //for div 1 2 4 2^n
 264 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 265 {
 266         u32 shift;
 267         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 268                 u32 new_rate = clk->parent->rate >> shift;
 269                 if (new_rate <= rate) {
 270                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 271                         clk->rate = new_rate;
 272                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 273                                         clk->name, rate, shift);
 274                         return 0;
 275                 }
 276         }
 277         return -ENOENT;
 278 }
 279
 280 //for div 2 4 2^n
 281 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 282 {
 283         u32 shift;
 284
 285         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 286                 u32 new_rate = clk->parent->rate >> shift;
 287                 if (new_rate <= rate) {
 288                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 289                         clk->rate = new_rate;
 290                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 291                                         clk->name, rate, shift);
 292                         return 0;
 293                 }
 294         }
 295         return -ENOENT;
 296 }
 297
 298
 299 //for div 1 2 4 2*n
 300 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 301 {
 302         u32 div;
 303         for (div = 2; div < clk->div_max; div += 2) {
 304                 u32 new_rate = clk->parent->rate / div;
 305                 if (new_rate <= rate) {
 306                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 307                         clk->rate = new_rate;
 308                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 309                                         __func__, clk->name, rate, div);
 310                         return 0;
 311                 }
 312         }
 313         return -ENOENT;
 314 }
 315
 316 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 317 {
 318        u32 div;
 319        unsigned long new_rate;
 320        for (div = 1; div < div_max; div += 2) {
 321                new_rate = rate / (div + 1);
 322                if (new_rate <= rate_out) {
 323                        return div + 1;
 324                }
 325        }
 326        return div_max ? div_max : 1;
 327 }
 328
 329 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 330 {
 331         u32 div;
 332         unsigned long new_rate;
 333         for (div = 0; div < div_max; div++) {
 334                 new_rate = rate / (div + 1);
 335                 if (new_rate <= rate_out) {
 336                         return div + 1;
 337                 }
 338         }
 339         return div_max ? div_max : 1;
 340 }
 341
 342 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 343        u32 div[2] = {0, 0};
 344        unsigned long new_rate[2] = {0, 0};
 345        u32 i;
 346
 347        if(clk->rate == rate)
 348                return clk->parent;
 349        for(i = 0; i < 2; i++) {
 350                div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 351                new_rate[i] = clk->parents[i]->rate / div[i];
 352                if(new_rate[i] == rate) {
 353                        *div_out = div[i];
 354                        return clk->parents[i];
 355                }
 356        }
 357        if(new_rate[0] < new_rate[1])
 358                i = 1;
 359        else
 360                i = 0;
 361        *div_out = div[i];
 362        return clk->parents[i];
 363 }
 364
 365 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 366         u32 div[2] = {0, 0};
 367         unsigned long new_rate[2] = {0, 0};
 368         u32 i;
 369
 370         if(clk->rate == rate)
 371                 return clk->parent;
 372         for(i = 0; i < 2; i++) {
 373                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 374                 new_rate[i] = clk->parents[i]->rate / div[i];
 375                 if(new_rate[i] == rate) {
 376                         *div_out = div[i];
 377                         return clk->parents[i];
 378                 }
 379         }
 380         if(new_rate[0] < new_rate[1])
 381                 i = 1;
 382         else
 383                 i = 0;
 384         *div_out = div[i];
 385         return clk->parents[i];
 386 }
 387
 388 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 389 {
 390        struct clk *p_clk;
 391        u32 div, old_div;
 392        int ret = 0;
 393        if(clk->rate == rate)
 394                return 0;
 395        p_clk = get_evendiv_parents_div(clk, rate, &div);
 396
 397        if(!p_clk)
 398                return -ENOENT;
 399
 400        CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 401        if (clk->parent != p_clk) {
 402                old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 403
 404                if(div > old_div) {
 405                        set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 406                }
 407                ret = clk_set_parent_nolock(clk, p_clk);
 408                if(ret) {
 409                        CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 410                        return -ENOENT;
 411                }
 412        }
 413        //set div
 414        set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 415        return 0;
 416 }
 417
 418 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 419 {
 420         struct clk *p_clk;
 421         u32 div, old_div;
 422         int ret = 0;
 423         if(clk->rate == rate)
 424                 return 0;
 425         p_clk = get_freediv_parents_div(clk, rate, &div);
 426
 427         if(!p_clk)
 428                 return -ENOENT;
 429
 430         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 431         if (clk->parent != p_clk) {
 432                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 433
 434                 if(div > old_div) {
 435                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 436                 }
 437                 ret = clk_set_parent_nolock(clk, p_clk);
 438                 if(ret) {
 439                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 440                         return -ENOENT;
 441                 }
 442         }
 443         //set div
 444         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 445         return 0;
 446 }
 447
 448 //rate==div rate //hdmi
 449 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 450 {
 451         struct clk *p_clk;
 452         u32 div, old_div;
 453         int ret;
 454         p_clk = get_freediv_parents_div(clk, rate, &div);
 455
 456         if(!p_clk)
 457                 return -ENOENT;
 458
 459         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 460                 return -ENOENT;
 461
 462         if (clk->parent != p_clk) {
 463                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 464                                 clk->div_shift, clk->div_mask) + 1;
 465                 if(div > old_div) {
 466                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 467                 }
 468                 ret = clk_set_parent_nolock(clk, p_clk);
 469                 if (ret) {
 470                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 471                         return ret;
 472                 }
 473         }
 474         //set div
 475         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 476         return 0;
 477 }
 478
 479 /***************************round********************************/
 480
 481 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 482 {
 483         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 484 }
 485
 486 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 487 {
 488         u32 div;
 489         struct clk *p_clk;
 490         if(clk->rate == rate)
 491                 return clk->rate;
 492         p_clk = get_freediv_parents_div(clk, rate, &div);
 493         if(!p_clk)
 494                 return 0;
 495         return p_clk->rate / div;
 496 }
 497
 498 /**************************************others seting************************************/
 499
 500 static struct clk *clksel_get_parent(struct clk *clk) {
 501         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 502 }
 503 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 504 {
 505         u32 i;
 506         if (unlikely(!clk->parents))
 507                 return -EINVAL;
 508         for (i = 0; (i < clk->parents_num); i++) {
 509                 if (clk->parents[i] != parent)
 510                         continue;
 511                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 512                 return 0;
 513         }
 514         return -EINVAL;
 515 }
 516
 517 static int gate_mode(struct clk *clk, int on)
 518 {
 519         int idx = clk->gate_idx;
 520         if (idx >= CLK_GATE_MAX)
 521                 return -EINVAL;
 522         if(on) {
 523                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 524                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 525                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 526         } else {
 527                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 528                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 529                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 530         }
 531         return 0;
 532 }
 533 /*****************************frac set******************************************/
 534
 535 static unsigned long clksel_recalc_frac(struct clk *clk)
 536 {
 537         unsigned long rate;
 538         u64 rate64;
 539         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 540         if (r == 0) // FPGA ?
 541                 return clk->parent->rate;
 542         numerator = r >> 16;
 543         denominator = r & 0xFFFF;
 544         rate64 = (u64)clk->parent->rate * numerator;
 545         do_div(rate64, denominator);
 546         rate = rate64;
 547         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 548         return rate;
 549 }
 550
 551 static u32 clk_gcd(u32 numerator, u32 denominator)
 552 {
 553         u32 a, b;
 554
 555         if (!numerator || !denominator)
 556                 return 0;
 557         if (numerator > denominator) {
 558                 a = numerator;
 559                 b = denominator;
 560         } else {
 561                 a = denominator;
 562                 b = numerator;
 563         }
 564         while (b != 0) {
 565                 int r = b;
 566                 b = a % b;
 567                 a = r;
 568         }
 569
 570         return a;
 571 }
 572
 573 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 574                 u32 *numerator, u32 *denominator)
 575 {
 576         u32 gcd_vl;
 577         gcd_vl = clk_gcd(rate, rate_out);
 578         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 579
 580         if (!gcd_vl) {
 581                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 582                 return -ENOENT;
 583         }
 584
 585         *numerator = rate_out / gcd_vl;
 586         *denominator = rate / gcd_vl;
 587
 588         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 589                         *numerator, *denominator, *denominator / *numerator);
 590
 591         if (*numerator > 0xffff || *denominator > 0xffff ||
 592                         (*denominator / (*numerator)) < 20) {
 593                 CLKDATA_ERR("can't get a available nume and deno\n");
 594                 return -ENOENT;
 595         }
 596
 597         return 0;
 598
 599 }
 600 /* *********************pll **************************/
 601
 602 #define rk30_clock_udelay(a) udelay(a);
 603
 604 /*********************pll lock status**********************************/
 605 //#define GRF_SOC_CON0       0x15c
 606 static void pll_wait_lock(int pll_idx)
 607 {
 608         u32 pll_state[4] = {1, 0, 2, 3};
 609         u32 bit = 0x20u << pll_state[pll_idx];
 610         int delay = 24000000;
 611         while (delay > 0) {
 612                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 613                         break;
 614                 delay--;
 615         }
 616         if (delay == 0) {
 617                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 618                 while(1);
 619         }
 620 }
 621
 622
 623
 624 /***************************pll function**********************************/
 625 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 626 {
 627         unsigned long rate;
 628
 629         if (PLLS_IN_NORM(pll_id)) {
 630                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 631                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 632
 633
 634                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 635
 636                 /*
 637                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 638                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 639                    */
 640
 641
 642                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 643                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 644                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 645
 646                 do_div(rate64, PLL_NR(pll_con0));
 647                 do_div(rate64, PLL_NO(pll_con0));
 648
 649                 rate = rate64;
 650                 /*
 651                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 652                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 653                    */
 654         } else {
 655                 rate = parent_rate;
 656                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 657         }
 658         return rate;
 659 }
 660 static unsigned long plls_clk_recalc(struct clk *clk)
 661 {
 662         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 663 }
 664
 665 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 666 {
 667         //enter slowmode
 668         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 669         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 670         dsb();
 671         dsb();
 672         dsb();
 673         dsb();
 674         dsb();
 675         dsb();
 676         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 677         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 678
 679         rk30_clock_udelay(1);
 680         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 681
 682         pll_wait_lock(pll_id);
 683
 684         //return form slow
 685         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 686
 687         /*
 688            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 689            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 690            */
 691
 692         return 0;
 693 }
 694 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 695 {
 696         struct _pll_data *pll_data = c->pll;
 697         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 698
 699         while(clk_set->rate) {
 700                 if (clk_set->rate == rate) {
 701                         break;
 702                 }
 703                 clk_set++;
 704         }
 705         if(clk_set->rate == rate) {
 706                 pll_clk_set_rate(clk_set, pll_data->id);
 707                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 708         } else {
 709                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 710                 return -1;
 711         }
 712         return 0;
 713 }
 714
 715 #define PLL_FREF_MIN (183*KHZ)
 716 #define PLL_FREF_MAX (1500*MHZ)
 717
 718 #define PLL_FVCO_MIN (300*MHZ)
 719 #define PLL_FVCO_MAX (1500*MHZ)
 720
 721 #define PLL_FOUT_MIN (18750*KHZ)
 722 #define PLL_FOUT_MAX (1500*MHZ)
 723
 724 #define PLL_NF_MAX (65536)
 725 #define PLL_NR_MAX (64)
 726 #define PLL_NO_MAX (64)
 727
 728 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 729 {
 730         u32 nr, nf, no, nonr;
 731         u32 n;
 732         u32 YFfenzi;
 733         u32 YFfenmu;
 734         unsigned long fref, fvco, fout;
 735         u32 gcd_val = 0;
 736
 737         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 738         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 739                 return 0;
 740         gcd_val = clk_gcd(fin_hz, fout_hz);
 741         YFfenzi = fout_hz / gcd_val;
 742         YFfenmu = fin_hz / gcd_val;
 743
 744         for(n = 1;; n++) {
 745                 nf = YFfenzi * n;
 746                 nonr = YFfenmu * n;
 747                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 748                         break;
 749                 for(no = 1; no <= PLL_NO_MAX; no++) {
 750                         if(!(no == 1 || !(no % 2)))
 751                                 continue;
 752
 753                         if(nonr % no)
 754                                 continue;
 755                         nr = nonr / no;
 756
 757                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 758                                 continue;
 759
 760                         fref = fin_hz / nr;
 761                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 762                                 continue;
 763
 764                         fvco = (fin_hz / nr) * nf;
 765                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 766                                 continue;
 767                         fout = fvco / no;
 768                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 769                                 continue;
 770                         *clk_nr = nr;
 771                         *clk_no = no;
 772                         *clk_nf = nf;
 773                         return 1;
 774
 775                 }
 776
 777         }
 778         return 0;
 779 }
 780
 781 static int pll_clk_mode(struct clk *clk, int on)
 782 {
 783         u8 pll_id = clk->pll->id;
 784         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 785         u32 dly = (nr * 500) / 24 + 1;
 786         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 787         if (on) {
 788                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 789                 rk30_clock_udelay(dly);
 790                 pll_wait_lock(pll_id);
 791                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 792         } else {
 793                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 794                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 795         }
 796         return 0;
 797 }
 798
 799 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 800 {
 801         struct _pll_data *pll_data = c->pll;
 802         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 803         struct pll_clk_set temp_clk_set;
 804         u32 clk_nr, clk_nf, clk_no;
 805
 806
 807         while(clk_set->rate) {
 808                 if (clk_set->rate == rate) {
 809                         break;
 810                 }
 811                 clk_set++;
 812         }
 813         if(clk_set->rate == rate) {
 814                 CLKDATA_DBG("cpll get a rate\n");
 815                 pll_clk_set_rate(clk_set, pll_data->id);
 816
 817         } else {
 818                 CLKDATA_DBG("cpll get auto calc a rate\n");
 819                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 820                         pr_err("cpll auto set rate error\n");
 821                         return -ENOENT;
 822                 }
 823                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 824                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 825                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 826                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 827                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 828
 829         }
 830         return 0;
 831 }
 832
 833
 834 /* ******************fixed input clk ***********************************************/
 835 static struct clk xin24m = {
 836         .name           = "xin24m",
 837         .rate           = 24 * MHZ,
 838         .flags          = RATE_FIXED,
 839 };
 840 #if 0
 841 static struct clk xin27m = {
 842         .name           = "xin27m",
 843         .rate           = 27 * MHZ,
 844         //CLK_GATE_XIN27M
 845         .flags          = RATE_FIXED,
 846
 847 };
 848 #endif
 849 static struct clk clk_12m = {
 850         .name           = "clk_12m",
 851         .parent         = &xin24m,
 852         .rate           = 12 * MHZ,
 853         .flags          = RATE_FIXED,
 854 };
 855
 856 /************************************pll func***************************/
 857 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 858                 struct apll_clk_set *tables) {
 859         const struct apll_clk_set *ps, *pt;
 860
 861         /* find the arm_pll we want. */
 862         ps = pt = tables;
 863         while (pt->rate) {
 864                 if (pt->rate == rate) {
 865                         ps = pt;
 866                         break;
 867                 }
 868                 // we are sorted, and ps->rate > pt->rate.
 869                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 870                         ps = pt;
 871                 if (pt->rate < rate)
 872                         break;
 873                 pt++;
 874         }
 875         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 876         return ps;
 877 }
 878 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 879 {
 880         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 881 }
 882 #if 1
 883 struct arm_clks_div_set {
 884         u32 rate;
 885         u32     clksel0;
 886         u32     clksel1;
 887 };
 888
 889 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 890 { \
 891         .rate    =_mhz,\
 892         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 893         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 894         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 895         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 896         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 897 }
 898 struct arm_clks_div_set arm_clk_div_tlb[] = {
 899         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 900         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 901         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 902         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 903         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
 904         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
 905         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
 906 };
 907 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
 908         int i = 0;
 909         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
 910                 if(arm_clk_div_tlb[i].rate >= rate)
 911                         return &arm_clk_div_tlb[i];
 912         }
 913         return NULL;
 914 }
 915
 916 #endif
 917
 918 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 919 {
 920         unsigned long flags;
 921         const struct apll_clk_set *ps;
 922         u32 pll_id = clk->pll->id;
 923         u32 temp_div;
 924         u32 old_aclk_div = 0, new_aclk_div;
 925
 926         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
 927
 928         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
 929         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
 930
 931         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
 932                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
 933
 934         if(general_pll_clk.rate > clk->rate) {
 935                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
 936         } else {
 937                 temp_div = 1;
 938         }
 939
 940         // ungating cpu gpll path
 941         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
 942         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 943
 944         local_irq_save(flags);
 945         //div arm clk for gpll
 946
 947         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
 948         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
 949
 950         loops_per_jiffy = lpj_gpll / temp_div;
 951         smp_wmb();
 952
 953         /*if core src don't select gpll ,apll neet to enter slow mode */
 954         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 955
 956
 957         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 958         dsb();
 959         dsb();
 960         dsb();
 961         dsb();
 962         dsb();
 963         dsb();
 964         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
 965         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
 966
 967         rk30_clock_udelay(1);
 968         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 969
 970         pll_wait_lock(pll_id);
 971
 972         //return form slow
 973         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 974         //reparent to apll
 975
 976         if(new_aclk_div>=old_aclk_div) {
 977                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 978                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 979         }
 980
 981         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
 982         if(old_aclk_div>new_aclk_div) {
 983                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 984                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 985         }
 986
 987         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
 988
 989         loops_per_jiffy = ps->lpj;
 990         smp_wmb();
 991
 992         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
 993
 994         local_irq_restore(flags);
 995
 996         //gate gpll path
 997         // FIXME
 998         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
 999         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1000
1001         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1002                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1003                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1004                         cru_readl(CRU_CLKSELS_CON(1)));
1005         return 0;
1006 }
1007
1008
1009 /************************************pll clocks***************************/
1010
1011 static const struct apll_clk_set apll_clks[] = {
1012         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1013         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1014         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1015         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1016         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1017         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1018         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1019         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1020         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1021         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1022         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1023         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1024         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1025         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1026         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1027         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1028         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1029         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1030         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1031         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1032         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1033         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1034         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1035         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1036         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1037         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1038         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1039         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1040         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1041         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1042         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1043         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1044         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1045         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1046
1047 };
1048 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1049 static struct clk arm_pll_clk = {
1050         .name           = "arm_pll",
1051         .parent         = &xin24m,
1052         .mode           = pll_clk_mode,
1053         .recalc         = plls_clk_recalc,
1054         .set_rate       = arm_pll_clk_set_rate,
1055         .round_rate     = arm_pll_clk_round_rate,
1056         .pll            = &apll_data,
1057 };
1058
1059 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1060 {
1061         /* do nothing here */
1062         return 0;
1063 }
1064 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1065 static struct clk ddr_pll_clk = {
1066         .name           = "ddr_pll",
1067         .parent         = &xin24m,
1068         .recalc         = plls_clk_recalc,
1069         .set_rate       = ddr_pll_clk_set_rate,
1070         .pll            = &dpll_data,
1071 };
1072
1073 static const struct pll_clk_set cpll_clks[] = {
1074         _PLL_SET_CLKS(360000, 1,  60,   4),
1075         _PLL_SET_CLKS(408000, 1,  68,   4),
1076         _PLL_SET_CLKS(456000, 1,  76,   4),
1077         _PLL_SET_CLKS(504000, 1,  84,   4),
1078         _PLL_SET_CLKS(552000, 1,  46,   2),
1079         _PLL_SET_CLKS(600000, 1,  50,   2),
1080         _PLL_SET_CLKS(742500, 8,  495,  2),
1081         _PLL_SET_CLKS(768000, 1,  64,   2),
1082         _PLL_SET_CLKS(798000, 2,  133,  2),
1083         _PLL_SET_CLKS(1188000, 2, 99,   1),
1084         _PLL_SET_CLKS(     0, 4,  133,  1),
1085 };
1086 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1087 static struct clk codec_pll_clk = {
1088         .name           = "codec_pll",
1089         .parent         = &xin24m,
1090         .mode           = pll_clk_mode,
1091         .recalc         = plls_clk_recalc,
1092         .set_rate       = cpll_clk_set_rate,
1093         .pll            = &cpll_data,
1094 };
1095
1096 static const struct pll_clk_set gpll_clks[] = {
1097         _PLL_SET_CLKS(148500,   2,      99,     8),
1098         _PLL_SET_CLKS(297000,   2,      198,    8),
1099         _PLL_SET_CLKS(300000,   1,      50,     4),
1100         _PLL_SET_CLKS(594000,   2,      198,    4),
1101         _PLL_SET_CLKS(1188000,  2,      99,     1),
1102         _PLL_SET_CLKS(1200000,  1,      50,     1),
1103         _PLL_SET_CLKS(0,        0,       0,     0),
1104 };
1105 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1106 static struct clk general_pll_clk = {
1107         .name           = "general_pll",
1108         .parent         = &xin24m,
1109         .recalc         = plls_clk_recalc,
1110         .set_rate       = gpll_clk_set_rate,
1111         .pll            = &gpll_data
1112 };
1113 /********************************clocks***********************************/
1114 /* core and cpu setting */
1115 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1116 {
1117         return 0;
1118 }
1119
1120 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1121 {
1122         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1123 }
1124 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1125 {
1126         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1127         unsigned long rate = clk->parent->recalc(clk->parent) >> shift;
1128         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1129         return rate;
1130 }
1131 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
1132 static struct clk clk_ddr = {
1133         .name           = "ddr",
1134         .parent         = &ddr_pll_clk,
1135         .recalc         = ddr_clk_recalc_rate,
1136         .set_rate       = ddr_clk_set_rate,
1137         .round_rate     = ddr_clk_round_rate,
1138         .clksel_con     = CRU_CLKSELS_CON(26),
1139         CRU_DIV_SET(0x3, 0, 4),
1140         CRU_SRC_SET(1, 8),
1141         CRU_PARENTS_SET(clk_ddr_parents),
1142 };
1143 static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
1144 {
1145         int ret;
1146
1147         ret = clk_set_rate_nolock(c->parent, rate);
1148         if (ret) {
1149                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1150                 return ret;
1151         }
1152         //set arm pll div 1
1153         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1154         return 0;
1155 }
1156 static unsigned long arm_core_clk_get_rate(struct clk *c)
1157 {
1158         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1159         //c->parent->rate=c->parent->recalc(c->parent);
1160         return c->parent->rate / div;
1161 }
1162 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1163 {
1164         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1165         return clk_round_rate_nolock(clk->parent, rate) / div;
1166 }
1167
1168 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1169 {
1170
1171         u32 temp_div;
1172         struct clk *old_prt;
1173
1174         if(clk->parent == new_prt)
1175                 return 0;
1176         if (unlikely(!clk->parents))
1177                 return -EINVAL;
1178         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1179         //arm
1180         old_prt = clk->parent;
1181
1182         if(clk->parents[0] == new_prt) {
1183                 new_prt->set_rate(new_prt, 300 * MHZ);
1184                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1185         } else if(clk->parents[1] == new_prt) {
1186
1187                 if(new_prt->rate > old_prt->rate) {
1188                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1189                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1190                 }
1191                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1192                 new_prt->set_rate(new_prt, 300 * MHZ);
1193         } else
1194                 return -1;
1195
1196
1197         return 0;
1198
1199 }
1200
1201 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1202 {
1203         u32 temp_div;
1204         u32 old_aclk_div = 0, new_aclk_div;
1205         struct arm_clks_div_set *temp_clk_div;
1206         unsigned long arm_gpll_rate, arm_gpll_lpj;
1207         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1208         arm_gpll_rate = c->parent->rate / temp_div;
1209
1210         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1211         if(!temp_clk_div)
1212                 temp_clk_div = &arm_clk_div_tlb[4];
1213
1214         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1215         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1216         if(c->rate >= rate) {
1217                 arm_gpll_lpj = lpj_gpll / temp_div;
1218                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1219         }
1220
1221         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1222         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1223                         CRU_CLKSELS_CON(0));
1224         if((c->rate < rate)) {
1225                 arm_gpll_lpj = lpj_gpll / temp_div;
1226                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1227         }
1228         return 0;
1229 }
1230 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1231 {
1232         return c->parent->rate;
1233 }
1234 static struct clk clk_core_gpll_path = {
1235         .name           = "cpu_gpll_path",
1236         .parent         = &general_pll_clk,
1237         .gate_idx       = CLK_GATE_CPU_GPLL_PATH,
1238         .recalc         = arm_core_gpll_clk_get_rate,
1239         .set_rate       = core_gpll_clk_set_rate,
1240         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1241 };
1242
1243
1244 static struct clk *clk_cpu_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1245
1246 static struct clk clk_core = {
1247         .name           = "core",
1248         .parent         = &arm_pll_clk,
1249         .set_rate       = arm_core_clk_set_rate,
1250         .recalc         = arm_core_clk_get_rate,
1251         .round_rate     = core_clk_round_rate,
1252         .set_parent     = core_clksel_set_parent,
1253         .clksel_con     = CRU_CLKSELS_CON(0),
1254         CRU_DIV_SET(0x1f, 9, 32),
1255         CRU_SRC_SET(1, 8),
1256         CRU_PARENTS_SET(clk_cpu_parents),
1257 };
1258 #ifdef ARCH_RK31
1259 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1260 static struct clk clk_cpu_div = {
1261         .name           = "cpu_div",
1262         .parent         = &arm_pll_clk,
1263         .set_rate       = clksel_set_rate_freediv,
1264         .recalc         = clksel_recalc_div,
1265         .clksel_con     = CRU_CLKSELS_CON(0),
1266         CRU_DIV_SET(0x1f, 0, 32),
1267         CRU_SRC_SET(1, 5),
1268         CRU_PARENTS_SET(clk_cpu_div_parents),
1269 };
1270
1271 #endif
1272 #ifdef ARCH_RK31
1273 GATE_CLK(l2c, clk_core, CLK_L2C);
1274 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1275 #endif
1276 static unsigned long aclk_recalc(struct clk *clk)
1277 {
1278         unsigned long rate;
1279         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1280
1281         BUG_ON(div > 5);
1282         if (div >= 5)
1283                 div = 8;
1284         rate = clk->parent->rate / div;
1285         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1286
1287         return rate;
1288 };
1289 static struct clk core_periph = {
1290         .name           = "core_periph",
1291         .parent         = &clk_core,
1292         .gate_idx       = CLK_GATE_CORE_PERIPH,
1293         .recalc         = clksel_recalc_shift_2,
1294         .clksel_con     = CRU_CLKSELS_CON(0),
1295         CRU_DIV_SET(0x3, 6, 16),
1296 };
1297 #ifdef ARCH_RK31
1298 static struct clk aclk_core = {
1299         .name           = "aclk_core",
1300         .parent         = &clk_core,
1301         .gate_idx       = CLK_GATE_ACLK_CORE,
1302         .recalc         = aclk_recalc,
1303         .clksel_con     = CRU_CLKSELS_CON(1),
1304         CRU_DIV_SET(0x7, 3, 8),
1305 };
1306 #endif
1307
1308 static struct clk aclk_cpu = {
1309         .name           = "aclk_cpu",
1310         .parent         = &clk_cpu_div,
1311         .gate_idx       = CLK_GATE_ACLK_CPU,
1312         .recalc         = aclk_recalc,
1313         .set_rate       = clksel_set_rate_shift,
1314         .clksel_con     = CRU_CLKSELS_CON(1),
1315         CRU_DIV_SET(0x7, 0, 8),
1316 };
1317
1318 static struct clk hclk_cpu = {
1319         .name           = "hclk_cpu",
1320         .parent         = &aclk_cpu,
1321         .gate_idx       = CLK_GATE_HCLK_CPU,
1322         .recalc         = clksel_recalc_shift,
1323         .set_rate       = clksel_set_rate_shift,
1324         .clksel_con     = CRU_CLKSELS_CON(1),
1325         CRU_DIV_SET(0x3, 8, 4),
1326
1327 };
1328
1329 static struct clk pclk_cpu = {
1330         .name           = "pclk_cpu",
1331         .parent         = &aclk_cpu,
1332         .gate_idx       = CLK_GATE_PCLK_CPU,
1333         .recalc         = clksel_recalc_shift,
1334         .set_rate       = clksel_set_rate_shift,
1335         .clksel_con     = CRU_CLKSELS_CON(1),
1336         CRU_DIV_SET(0x3, 12, 8),
1337 };
1338
1339 static struct clk ahb2apb_cpu = {
1340         .name           = "ahb2apb",
1341         .parent         = &hclk_cpu,
1342         .recalc         = clksel_recalc_shift,
1343         .set_rate       = clksel_set_rate_shift,
1344         .clksel_con     = CRU_CLKSELS_CON(1),
1345         CRU_DIV_SET(0x3, 14, 4),
1346 };
1347
1348
1349 static struct clk atclk_cpu = {
1350         .name           = "atclk_cpu",
1351         .parent         = &pclk_cpu,
1352         .gate_idx       = CLK_GATE_ATCLK_CPU,
1353 };
1354
1355 /* GPU setting test */
1356 #if 0   //for gpu rate test
1357
1358 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1359 {
1360         printk("gpu dbg clk %s set %lu\n",clk->name,rate);
1361         return clksel_set_rate_freediv(clk, rate);
1362 };
1363
1364 #define clk_gpu_set_rate_callback clk_gpu_set_rate
1365 #else
1366 #define clk_gpu_set_rate(clk,rate) clksel_set_rate_freediv((clk),(rate))
1367 #define clk_gpu_set_rate_callback clksel_set_rate_freediv
1368 #endif
1369
1370 #define   GPU_CORE_ACLK_CTR_TOGETHER
1371
1372 #ifdef GPU_CORE_ACLK_CTR_TOGETHER
1373 static struct clk aclk_gpu;
1374 static struct clk clk_gpu;
1375
1376 static int clk_gpu_ref_set_rate(struct clk *clk, unsigned long rate)
1377 {
1378         int ret = 0;
1379         ret=clk_gpu_set_rate(clk, rate);
1380         if(ret<0)
1381                 return ret;
1382         ret=clk_set_rate_nolock(&aclk_gpu, rate);
1383         return ret;
1384 };
1385 static long clk_gpu_ref_round_rate(struct clk *clk, unsigned long rate)
1386 {
1387         unsigned long rate_gpu;
1388         rate_gpu=clksel_freediv_round_rate(clk,rate);
1389 /*
1390         if(rate_gpu!=clksel_freediv_round_rate(&aclk_gpu,rate))
1391         {
1392                 CLKDATA_ERR("gpu rate is not equal ack gpu rate in %s\n",__FUNCTION__);
1393         }
1394 */
1395         return rate_gpu;
1396 }
1397 #endif
1398
1399 static struct clk *gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1400
1401 static struct clk clk_gpu = {
1402         .name           = "gpu",
1403         .mode           = gate_mode,
1404         .recalc         = clksel_recalc_div,
1405 #ifdef GPU_CORE_ACLK_CTR_TOGETHER
1406         .round_rate     = clk_gpu_ref_round_rate,
1407         .set_rate               = clk_gpu_ref_set_rate,
1408 #else
1409         .round_rate     = clksel_freediv_round_rate,
1410         .set_rate               = clk_gpu_set_rate_callback,
1411 #endif
1412         .clksel_con     = CRU_CLKSELS_CON(33),
1413         .gate_idx       = CLK_GATE_CLK_GPU,
1414         CRU_DIV_SET(0x1f, 0, 32),
1415         CRU_SRC_SET(0x1, 7),
1416         CRU_PARENTS_SET(gpu_parents),
1417 };
1418 #ifdef ARCH_RK31
1419 static struct clk *gpu_aclk_parents[2] = {&codec_pll_clk, &general_pll_clk};
1420 static struct clk aclk_gpu = {
1421         .name           = "aclk_gpu",
1422         .recalc         = clksel_recalc_div,
1423         .round_rate     = clksel_freediv_round_rate,
1424         .set_rate               = clk_gpu_set_rate_callback,
1425         .clksel_con     = CRU_CLKSELS_CON(34),
1426         CRU_DIV_SET(0x1f, 0, 32),
1427         CRU_SRC_SET(0x1, 7),
1428         CRU_PARENTS_SET(gpu_parents),
1429 };
1430
1431 #ifdef GPU_CORE_ACLK_CTR_TOGETHER
1432 static int clk_aclk_gpu_null_set_rate(struct clk *clk, unsigned long rate)
1433 {
1434         return 0;
1435 };
1436
1437 static long clk_aclk_gpu_null_round_rate(struct clk *clk, unsigned long rate)
1438 {
1439         return clk->parent->round_rate(clk->parent,rate);
1440 }
1441 static unsigned long  clk_aclk_gpu_null_recalc_div(struct clk *clk)
1442 {
1443                 return clk->parent->rate;
1444 }
1445 //gpu and gpu together ctr,this clk is following aclk gpu.
1446 static struct clk aclk_gpu_null = {
1447         .name           = "aclk_gpu_null",
1448         .parent         = &aclk_gpu,
1449         .recalc         = clk_aclk_gpu_null_recalc_div,
1450         .round_rate     = clk_aclk_gpu_null_round_rate,
1451         .set_rate       = clk_aclk_gpu_null_set_rate,
1452 };
1453 #endif
1454 static struct clk aclk_gpu_slv = {
1455         .name           = "aclk_gpu_slv",
1456         .parent         = &aclk_gpu,
1457         .mode           = gate_mode,
1458         .gate_idx       = CLK_GATE_ACLK_GPU_SLV,
1459 };
1460
1461 static struct clk aclk_gpu_mst = {
1462         .name           = "aclk_gpu_mst",
1463         .parent         = &aclk_gpu,
1464         .mode           = gate_mode,
1465         .gate_idx       = CLK_GATE_ACLK_GPU_MST,
1466 };
1467 #endif
1468
1469 /* vcodec setting */
1470 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1471 {
1472         unsigned long rate = clk->parent->rate / 4;
1473         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1474         return rate;
1475 }
1476
1477 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1478
1479 static struct clk aclk_vepu = {
1480         .name           = "aclk_vepu",
1481         .parent         = &codec_pll_clk,
1482         .mode           = gate_mode,
1483         .recalc         = clksel_recalc_div,
1484         //.set_rate     = clksel_set_rate_freediv,
1485         .set_rate       = clkset_rate_freediv_autosel_parents,
1486         .clksel_con     = CRU_CLKSELS_CON(32),
1487         .gate_idx       = CLK_GATE_ACLK_VEPU,
1488         CRU_DIV_SET(0x1f, 0, 32),
1489         CRU_SRC_SET(0x1, 7),
1490         CRU_PARENTS_SET(aclk_vepu_parents),
1491 };
1492
1493 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1494
1495 static struct clk aclk_vdpu = {
1496         .name           = "aclk_vdpu",
1497         .mode           = gate_mode,
1498         .recalc         = clksel_recalc_div,
1499         //.set_rate     = clksel_set_rate_freediv,
1500         .set_rate       = clkset_rate_freediv_autosel_parents,
1501         .clksel_con     = CRU_CLKSELS_CON(32),
1502         .gate_idx       = CLK_GATE_ACLK_VDPU,
1503         CRU_DIV_SET(0x1f, 8, 32),
1504         CRU_SRC_SET(0x1, 15),
1505         CRU_PARENTS_SET(aclk_vdpu_parents),
1506 };
1507 static struct clk hclk_vepu = {
1508         .name           = "hclk_vepu",
1509         .parent         = &aclk_vepu,
1510         .mode           = gate_mode,
1511         .recalc         = clksel_recalc_vpu_hclk,
1512         .gate_idx       = CLK_GATE_HCLK_VEPU,
1513 };
1514
1515 static struct clk hclk_vdpu = {
1516         .name           = "hclk_vdpu",
1517         .parent         = &aclk_vdpu,
1518         .mode           = gate_mode,
1519         .recalc         = clksel_recalc_vpu_hclk,
1520         .gate_idx       = CLK_GATE_HCLK_VDPU,
1521 };
1522
1523 /* aclk lcdc setting */
1524 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1525
1526 static struct clk aclk_lcdc0_pre = {
1527         .name           = "aclk_lcdc0_pre",
1528         .parent         = &codec_pll_clk,
1529         .mode           = gate_mode,
1530         .recalc         = clksel_recalc_div,
1531         .set_rate       = clkset_rate_freediv_autosel_parents,
1532         //.set_rate     = clksel_set_rate_freediv,
1533         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1534         .clksel_con     = CRU_CLKSELS_CON(31),
1535         CRU_DIV_SET(0x1f, 0, 32),
1536         CRU_SRC_SET(0x1, 7),
1537         CRU_PARENTS_SET(aclk_lcdc0_parents),
1538 };
1539
1540 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1541
1542 static struct clk aclk_lcdc1_pre = {
1543         .name           = "aclk_lcdc1_pre",
1544         .parent         = &codec_pll_clk,
1545         .mode           = gate_mode,
1546         .recalc         = clksel_recalc_div,
1547         .set_rate       = clkset_rate_freediv_autosel_parents,
1548         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1549         .clksel_con     = CRU_CLKSELS_CON(31),
1550         CRU_DIV_SET(0x1f, 8, 32),
1551         CRU_SRC_SET(0x1, 15),
1552         CRU_PARENTS_SET(aclk_lcdc1_parents),
1553 };
1554
1555 /* aclk/hclk/pclk periph setting */
1556 static struct clk *aclk_periph_parents[2] = {&general_pll_clk, &codec_pll_clk};
1557
1558 static struct clk aclk_periph = {
1559         .name           = "aclk_periph",
1560         .parent         = &general_pll_clk,
1561         .mode           = gate_mode,
1562         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1563         .recalc         = clksel_recalc_div,
1564         .set_rate       = clksel_set_rate_freediv,
1565         .clksel_con     = CRU_CLKSELS_CON(10),
1566         CRU_DIV_SET(0x1f, 0, 32),
1567         CRU_SRC_SET(1, 15),
1568         CRU_PARENTS_SET(aclk_periph_parents),
1569 };
1570 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1571
1572 static struct clk pclk_periph = {
1573         .name           = "pclk_periph",
1574         .parent         = &aclk_periph,
1575         .mode           = gate_mode,
1576         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1577         .recalc         = clksel_recalc_shift,
1578         .set_rate       = clksel_set_rate_shift,
1579         .clksel_con     = CRU_CLKSELS_CON(10),
1580         CRU_DIV_SET(0x3, 12, 8),
1581 };
1582
1583 static struct clk hclk_periph = {
1584         .name           = "hclk_periph",
1585         .parent         = &aclk_periph,
1586         .mode           = gate_mode,
1587         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1588         .recalc         = clksel_recalc_shift,
1589         .set_rate       = clksel_set_rate_shift,
1590         .clksel_con     = CRU_CLKSELS_CON(10),
1591         CRU_DIV_SET(0x3, 8, 4),
1592 };
1593 /* dclk lcdc setting */
1594 // FIXME
1595 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1596 {
1597         u32 div, old_div;
1598         int i;
1599         unsigned long new_rate;
1600         int ret = 0;
1601
1602         if(clk->rate == rate)
1603                 return 0;
1604         for(i = 0; i < 2; i++) {
1605                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1606                 new_rate = clk->parents[i]->rate / div;
1607                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1608                         break;
1609                 }
1610         }
1611         if(i >= 2) {
1612                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1613                 return -1;
1614         }
1615
1616         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1617
1618         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1619                         clk->div_shift, clk->div_mask) + 1;
1620         if(div > old_div)
1621                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1622
1623         if(clk->parents[i] != clk->parent) {
1624                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1625         }
1626
1627         if (ret) {
1628                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1629                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1630                 return ret;
1631         }
1632         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1633         return 0;
1634 }
1635
1636 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1637 {
1638         int ret = 0;
1639         struct clk *parent;
1640
1641         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1642                 parent = clk->parents[1];
1643                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1644         } else {
1645                 parent = clk->parents[0];
1646         }
1647         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1648         //clk->name,rate,parent->name,clk->parent->name);
1649
1650         if(parent != clk->parents[1]) {
1651                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1652                 if (ret) {
1653                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1654                         return ret;
1655                 }
1656         }
1657         if (clk->parent != parent) {
1658                 ret = clk_set_parent_nolock(clk, parent);
1659                 if (ret) {
1660                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1661                         return ret;
1662                 }
1663         }
1664         return ret;
1665 }
1666
1667 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1668 static struct clk dclk_lcdc0 = {
1669         .name           = "dclk_lcdc0",
1670         .mode           = gate_mode,
1671         .set_rate       = clkset_rate_evendiv_autosel_parents,
1672         .recalc         = clksel_recalc_div,
1673         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1674         .clksel_con     = CRU_CLKSELS_CON(27),
1675         CRU_SRC_SET(0x1, 0),
1676         CRU_DIV_SET(0xff, 8, 256),
1677         CRU_PARENTS_SET(dclk_lcdc0_parents),
1678 };
1679
1680 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1681 static struct clk dclk_lcdc1 = {
1682         .name           = "dclk_lcdc1",
1683         .mode           = gate_mode,
1684         .set_rate       = clkset_rate_evendiv_autosel_parents,
1685         .recalc         = clksel_recalc_div,
1686         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1687         .clksel_con     = CRU_CLKSELS_CON(28),
1688         CRU_SRC_SET(0x1, 0),
1689         CRU_DIV_SET(0xff, 8, 256),
1690         CRU_PARENTS_SET(dclk_lcdc1_parents),
1691 };
1692
1693 /* cif setting */
1694 // FIXME
1695 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1696 static struct clk cif_out_pll = {
1697         .name           = "cif_out_pll",
1698         .parent         = &general_pll_clk,
1699         .clksel_con     = CRU_CLKSELS_CON(29),
1700         CRU_SRC_SET(0x1, 0),
1701         CRU_PARENTS_SET(cifout_sel_pll_parents),
1702 };
1703
1704 static struct clk cif0_out_div = {
1705         .name           = "cif0_out_div",
1706         .parent         = &cif_out_pll,
1707         .mode           = gate_mode,
1708         .recalc         = clksel_recalc_div,
1709         .set_rate       = clksel_set_rate_freediv,
1710         .gate_idx       = CLK_GATE_CIF0_OUT,
1711         .clksel_con     = CRU_CLKSELS_CON(29),
1712         CRU_DIV_SET(0x1f, 1, 32),
1713 };
1714
1715 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1716 {
1717         int ret = 0;
1718         struct clk *parent;
1719
1720         if (rate == 24 * MHZ) {
1721                 parent = clk->parents[1];
1722         } else {
1723                 parent = clk->parents[0];
1724                 ret = clk_set_rate_nolock(parent, rate);
1725                 if (ret)
1726                         return ret;
1727         }
1728         if (clk->parent != parent)
1729                 ret = clk_set_parent_nolock(clk, parent);
1730
1731         return ret;
1732 }
1733
1734 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1735 static struct clk cif0_out = {
1736         .name           = "cif0_out",
1737         .parent         = &cif0_out_div,
1738         .set_rate       = cif_out_set_rate,
1739         .clksel_con     = CRU_CLKSELS_CON(29),
1740         CRU_SRC_SET(0x1, 7),
1741         CRU_PARENTS_SET(cif0_out_parents),
1742 };
1743
1744 static struct clk pclkin_cif0 = {
1745         .name           = "pclkin_cif0",
1746         .mode           = gate_mode,
1747         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1748 };
1749
1750 static struct clk inv_cif0 = {
1751         .name           = "inv_cif0",
1752         .parent         = &pclkin_cif0,
1753 };
1754
1755 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1756 static struct clk cif0_in = {
1757         .name           = "cif0_in",
1758         .parent         = &pclkin_cif0,
1759         .clksel_con     = CRU_CLKSELS_CON(30),
1760         CRU_SRC_SET(0x1, 8),
1761         CRU_PARENTS_SET(cif0_in_parents),
1762 };
1763
1764 /* i2s/spdif setting */
1765 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1766 static struct clk clk_i2s_pll = {
1767         .name           = "i2s_pll",
1768         .parent         = &general_pll_clk,
1769         .clksel_con     = CRU_CLKSELS_CON(2),
1770         CRU_SRC_SET(0x1, 15),
1771         CRU_PARENTS_SET(clk_i2s_div_parents),
1772 };
1773
1774 static struct clk clk_i2s0_div = {
1775         .name           = "i2s0_div",
1776         .parent         = &clk_i2s_pll,
1777         .mode           = gate_mode,
1778         .recalc         = clksel_recalc_div,
1779         .set_rate       = clksel_set_rate_freediv,
1780         .round_rate     = clksel_freediv_round_rate,
1781         .gate_idx       = CLK_GATE_I2S0_SRC,
1782         .clksel_con     = CRU_CLKSELS_CON(3),
1783         CRU_DIV_SET(0x7f, 0, 64),
1784 };
1785
1786 static struct clk clk_spdif_div = {
1787         .name           = "spdif_div",
1788         .parent         = &clk_i2s_pll,
1789         .recalc         = clksel_recalc_div,
1790         .set_rate       = clksel_set_rate_freediv,
1791         .round_rate     = clksel_freediv_round_rate,
1792         .mode           = gate_mode,
1793         .gate_idx       = CLK_GATE_SPDIF_SRC,
1794         .clksel_con     = CRU_CLKSELS_CON(5),
1795         CRU_DIV_SET(0x7f, 0, 64),
1796 };
1797 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1798 {
1799         u32 numerator, denominator;
1800         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1801         //clk->parent->parent
1802         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1803                                 &numerator, &denominator) == 0) {
1804                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1805                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1806                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1807         } else {
1808                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1809                 return -ENOENT;
1810         }
1811         return 0;
1812 }
1813
1814 static struct clk clk_i2s0_frac_div = {
1815         .name           = "i2s0_frac_div",
1816         .parent         = &clk_i2s0_div,
1817         .mode           = gate_mode,
1818         .gate_idx       = CLK_GATE_I2S0_FRAC,
1819         .recalc         = clksel_recalc_frac,
1820         .set_rate       = clk_i2s_fracdiv_set_rate,
1821         .clksel_con     = CRU_CLKSELS_CON(7),
1822 };
1823
1824 static struct clk clk_spdif_frac_div = {
1825         .name           = "spdif_frac_div",
1826         .parent         = &clk_spdif_div,
1827         .mode           = gate_mode,
1828         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1829         .recalc         = clksel_recalc_frac,
1830         .set_rate       = clk_i2s_fracdiv_set_rate,
1831         .clksel_con     = CRU_CLKSELS_CON(9),
1832 };
1833
1834 #define I2S_SRC_DIV     (0x0)
1835 #define I2S_SRC_FRAC    (0x1)
1836 #define I2S_SRC_12M     (0x2)
1837
1838 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1839 {
1840         int ret = -EINVAL;
1841         struct clk *parent;
1842
1843         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1844                 parent = clk->parents[I2S_SRC_12M];
1845         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1846                 parent = clk->parents[I2S_SRC_DIV];
1847         } else {
1848                 parent = clk->parents[I2S_SRC_FRAC];
1849         }
1850
1851         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1852                         clk->name, rate, parent->name, clk->parent->name);
1853
1854         if(parent != clk->parents[I2S_SRC_12M]) {
1855                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1856                 if (ret) {
1857                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1858                         return ret;
1859                 }
1860         }
1861
1862         if (clk->parent != parent) {
1863                 ret = clk_set_parent_nolock(clk, parent);
1864                 if (ret) {
1865                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1866                         return ret;
1867                 }
1868         }
1869
1870         return ret;
1871 };
1872
1873 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
1874
1875 static struct clk clk_i2s0 = {
1876         .name           = "i2s0",
1877         .set_rate       = i2s_set_rate,
1878         .clksel_con     = CRU_CLKSELS_CON(3),
1879         CRU_SRC_SET(0x3, 8),
1880         CRU_PARENTS_SET(clk_i2s0_parents),
1881 };
1882
1883 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
1884
1885 static struct clk clk_spdif = {
1886         .name           = "spdif",
1887         .parent         = &clk_spdif_frac_div,
1888         .set_rate       = i2s_set_rate,
1889         .clksel_con = CRU_CLKSELS_CON(5),
1890         CRU_SRC_SET(0x3, 8),
1891         CRU_PARENTS_SET(clk_spdif_parents),
1892 };
1893
1894 /* otgphy setting */
1895 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1896 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1897
1898 static struct clk clk_otgphy0_480m = {
1899         .name           = "otgphy0_480m",
1900         .parent         = &clk_otgphy0,
1901 };
1902 static struct clk clk_otgphy1_480m = {
1903         .name           = "otgphy1_480m",
1904         .parent         = &clk_otgphy1,
1905 };
1906
1907 /* hsicphy setting */
1908 #ifdef ARCH_RK31
1909 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
1910 static struct clk clk_hsicphy_480m = {
1911         .name           = "hsicphy_480m",
1912         .parent         = &clk_otgphy0_480m,
1913         .clksel_con      = CRU_CLKSELS_CON(30),
1914         CRU_SRC_SET(0x3, 0),
1915         CRU_PARENTS_SET(clk_hsicphy_parents),
1916 };
1917 static struct clk clk_hsicphy_12m = {
1918         .name           = "hsicphy_12m",
1919         .parent         = &clk_hsicphy_480m,
1920         .clksel_con     = CRU_CLKSELS_CON(11),
1921         CRU_DIV_SET(0x3f, 8, 64),
1922 };
1923 #endif
1924
1925 /* mac and rmii setting */
1926 // FIXME
1927 static struct clk rmii_clkin = {
1928         .name           = "rmii_clkin",
1929 };
1930 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
1931 static struct clk clk_mac_pll_div = {
1932         .name           = "mac_pll_div",
1933         .parent         = &general_pll_clk,
1934         .mode           = gate_mode,
1935         .gate_idx       = CLK_GATE_MAC_SRC,
1936         .recalc         = clksel_recalc_div,
1937         .set_rate       = clksel_set_rate_freediv,
1938         .clksel_con     = CRU_CLKSELS_CON(21),
1939         CRU_DIV_SET(0x1f, 8, 32),
1940         CRU_SRC_SET(0x1, 0),
1941         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1942 };
1943
1944 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1945 {
1946         if(clk->parent == clk->parents[1]) {
1947                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1948                 return -ENOENT;
1949         } else if(clk->parent == clk->parents[0]) {
1950                 return clk_set_rate_nolock(clk->parents[0], rate);
1951         }
1952         return -ENOENT;
1953 }
1954
1955 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
1956
1957 static struct clk clk_mac_ref = {
1958         .name           = "mac_ref",
1959         .parent         = &clk_mac_pll_div,
1960         .set_rate       = clksel_mac_ref_set_rate,
1961         .clksel_con     = CRU_CLKSELS_CON(21),
1962         CRU_SRC_SET(0x1, 4),
1963         CRU_PARENTS_SET(clk_mac_ref_parents),
1964 };
1965
1966 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1967 {
1968         return clk_set_parent_nolock(clk->parent, parent);
1969 }
1970
1971 static struct clk clk_mii_tx = {
1972         .name           = "mii_tx",
1973         .parent         = &clk_mac_ref,
1974         //.set_parent   = clk_set_mii_tx_parent,
1975         .mode           = gate_mode,
1976         .gate_idx       = CLK_GATE_MAC_LBTEST,
1977 };
1978
1979 /* hsadc and saradc */
1980 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
1981 static struct clk clk_hsadc_pll_div = {
1982         .name           = "hsadc_pll_div",
1983         .parent         = &general_pll_clk,
1984         .mode           = gate_mode,
1985         .gate_idx       = CLK_GATE_HSADC_SRC,
1986         .recalc         = clksel_recalc_div,
1987         .round_rate     = clk_freediv_round_autosel_parents_rate,
1988         .set_rate       = clkset_rate_freediv_autosel_parents,
1989         //.round_rate   = clksel_freediv_round_rate,
1990         //.set_rate     = clksel_set_rate_freediv,
1991         .clksel_con = CRU_CLKSELS_CON(22),
1992         CRU_DIV_SET(0xff, 8, 256),
1993         CRU_SRC_SET(0x1, 0),
1994         CRU_PARENTS_SET(clk_hsadc_pll_parents),
1995 };
1996 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
1997 {
1998         u32 numerator, denominator;
1999         //        clk_hsadc_pll_div->gpll/cpll
2000         //clk->parent->parent
2001         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2002                                 &numerator, &denominator) == 0) {
2003                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2004
2005                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2006
2007                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2008         } else {
2009                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2010                 return -ENOENT;
2011         }
2012         return 0;
2013 }
2014 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2015 {
2016         u32 numerator, denominator;
2017         u32 i, ret = 0;
2018         //        clk_hsadc_pll_div->gpll/cpll
2019         //clk->parent->parent
2020         for(i = 0; i < 2; i++) {
2021                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2022                                         &numerator, &denominator) == 0)
2023                         break;
2024         }
2025         if(i >= 2)
2026                 return -ENOENT;
2027
2028         if(clk->parent->parent != clk->parent->parents[i])
2029                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2030         if(ret == 0) {
2031                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2032
2033                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2034
2035                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2036         } else {
2037                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2038                 return -ENOENT;
2039         }
2040         return 0;
2041 }
2042
2043 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2044 {
2045         u32 numerator, denominator;
2046
2047         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2048         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2049                                 &numerator, &denominator) == 0)
2050                 return rate;
2051
2052         return 0;
2053 }
2054 static struct clk clk_hsadc_frac_div = {
2055         .name           = "hsadc_frac_div",
2056         .parent         = &clk_hsadc_pll_div,
2057         .mode           = gate_mode,
2058         .recalc         = clksel_recalc_frac,
2059         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2060         .round_rate     = clk_hsadc_fracdiv_round_rate,
2061         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
2062         .clksel_con     = CRU_CLKSELS_CON(23),
2063 };
2064
2065 #define HSADC_SRC_DIV 0x0
2066 #define HSADC_SRC_FRAC 0x1
2067 #define HSADC_SRC_EXT 0x2
2068 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2069 {
2070         int ret = -EINVAL;
2071         struct clk *parent;
2072
2073         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2074                 CLKDATA_DBG("hsadc clk is form ext\n");
2075                 return 0;
2076         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2077                 parent = clk->parents[HSADC_SRC_DIV];
2078         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2079                 parent = clk->parents[HSADC_SRC_FRAC];
2080         } else
2081                 parent = clk->parents[HSADC_SRC_DIV];
2082
2083         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2084                         clk->name, rate, parent->name, clk->parent->name);
2085
2086         ret = clk_set_rate_nolock(parent, rate);
2087         if (ret) {
2088                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2089                 return ret;
2090         }
2091         if (clk->parent != parent) {
2092                 ret = clk_set_parent_nolock(clk, parent);
2093                 if (ret) {
2094                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2095                         return ret;
2096                 }
2097         }
2098         return ret;
2099 }
2100
2101 static struct clk clk_hsadc_ext = {
2102         .name           = "hsadc_ext",
2103 };
2104
2105 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2106 static struct clk clk_hsadc_out = {
2107         .name           = "hsadc_out",
2108         .parent         = &clk_hsadc_pll_div,
2109         .set_rate       = clk_hsadc_set_rate,
2110         .clksel_con     = CRU_CLKSELS_CON(22),
2111         CRU_SRC_SET(0x3, 4),
2112         CRU_PARENTS_SET(clk_hsadc_out_parents),
2113 };
2114 static struct clk clk_hsadc_out_inv = {
2115         .name           = "hsadc_out_inv",
2116         .parent         = &clk_hsadc_pll_div,
2117 };
2118
2119 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2120 static struct clk clk_hsadc = {
2121         .name           = "hsadc",
2122         .parent         = &clk_hsadc_out,
2123         .clksel_con     = CRU_CLKSELS_CON(22),
2124         CRU_SRC_SET(0x1, 7),
2125         CRU_PARENTS_SET(clk_hsadc_parents),
2126 };
2127
2128 static struct clk clk_saradc = {
2129         .name           = "saradc",
2130         .parent         = &xin24m,
2131         .mode           = gate_mode,
2132         .recalc         = clksel_recalc_div,
2133         .set_rate       = clksel_set_rate_freediv,
2134         .gate_idx       = CLK_GATE_SARADC_SRC,
2135         .clksel_con     = CRU_CLKSELS_CON(24),
2136         CRU_DIV_SET(0xff, 8, 256),
2137 };
2138
2139 /* smc setting */
2140 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2141 static struct clk clkn_smc = {
2142         .name           = "smc_inv",
2143         .parent         = &clk_smc,
2144 };
2145
2146 /* spi setting */
2147 static struct clk clk_spi0 = {
2148         .name           = "spi0",
2149         .parent         = &pclk_periph,
2150         .mode           = gate_mode,
2151         .recalc         = clksel_recalc_div,
2152         .set_rate       = clksel_set_rate_freediv,
2153         .gate_idx       = CLK_GATE_SPI0_SRC,
2154         .clksel_con     = CRU_CLKSELS_CON(25),
2155         CRU_DIV_SET(0x7f, 0, 128),
2156 };
2157
2158 static struct clk clk_spi1 = {
2159         .name           = "spi1",
2160         .parent         = &pclk_periph,
2161         .mode           = gate_mode,
2162         .recalc         = clksel_recalc_div,
2163         .set_rate       = clksel_set_rate_freediv,
2164         .gate_idx       = CLK_GATE_SPI1_SRC,
2165         .clksel_con     = CRU_CLKSELS_CON(25),
2166         CRU_DIV_SET(0x7f, 8, 128),
2167 };
2168
2169 /* sdmmc/sdio/emmc setting */
2170 static struct clk clk_sdmmc = {
2171         .name           = "sdmmc",
2172         .parent         = &hclk_periph,
2173         .mode           = gate_mode,
2174         .recalc         = clksel_recalc_div,
2175         .set_rate       = clksel_set_rate_even,
2176         .gate_idx       = CLK_GATE_MMC0_SRC,
2177         .clksel_con     = CRU_CLKSELS_CON(11),
2178         CRU_DIV_SET(0x3f, 0, 64),
2179 };
2180
2181 static struct clk clk_sdio = {
2182         .name           = "sdio",
2183         .parent         = &hclk_periph,
2184         .mode           = gate_mode,
2185         .recalc         = clksel_recalc_div,
2186         .set_rate       = clksel_set_rate_even,
2187         .gate_idx       = CLK_GATE_SDIO_SRC,
2188         .clksel_con     = CRU_CLKSELS_CON(12),
2189         CRU_DIV_SET(0x3f, 0, 64),
2190
2191 };
2192
2193 static struct clk clk_emmc = {
2194         .name           = "emmc",
2195         .parent         = &hclk_periph,
2196         .mode           = gate_mode,
2197         .recalc         = clksel_recalc_div,
2198         .set_rate       = clksel_set_rate_freediv,
2199         .gate_idx       = CLK_GATE_EMMC_SRC,
2200         .clksel_con     = CRU_CLKSELS_CON(12),
2201         CRU_DIV_SET(0x3f, 8, 64),
2202 };
2203
2204 /* uart setting */
2205 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2206 static struct clk clk_uart_pll = {
2207         .name           = "uart_pll",
2208         .parent         = &general_pll_clk,
2209         .clksel_con     = CRU_CLKSELS_CON(12),
2210         CRU_SRC_SET(0x1, 15),
2211         CRU_PARENTS_SET(clk_uart_src_parents),
2212 };
2213 static struct clk clk_uart0_div = {
2214         .name           = "uart0_div",
2215         .parent         = &clk_uart_pll,
2216         .mode           = gate_mode,
2217         .gate_idx       = CLK_GATE_UART0_SRC,
2218         .recalc         = clksel_recalc_div,
2219         .set_rate       = clksel_set_rate_freediv,
2220         .round_rate     = clksel_freediv_round_rate,
2221         .clksel_con     = CRU_CLKSELS_CON(13),
2222         CRU_DIV_SET(0x7f, 0, 64),
2223 };
2224 static struct clk clk_uart1_div = {
2225         .name           = "uart1_div",
2226         .parent         = &clk_uart_pll,
2227         .mode           = gate_mode,
2228         .gate_idx       = CLK_GATE_UART1_SRC,
2229         .recalc         = clksel_recalc_div,
2230         .round_rate     = clksel_freediv_round_rate,
2231         .set_rate       = clksel_set_rate_freediv,
2232         .clksel_con     = CRU_CLKSELS_CON(14),
2233         CRU_DIV_SET(0x7f, 0, 64),
2234 };
2235
2236 static struct clk clk_uart2_div = {
2237         .name           = "uart2_div",
2238         .parent         = &clk_uart_pll,
2239         .mode           = gate_mode,
2240         .gate_idx       = CLK_GATE_UART2_SRC,
2241         .recalc         = clksel_recalc_div,
2242         .round_rate     = clksel_freediv_round_rate,
2243         .set_rate       = clksel_set_rate_freediv,
2244         .clksel_con     = CRU_CLKSELS_CON(15),
2245         CRU_DIV_SET(0x7f, 0, 64),
2246 };
2247
2248 static struct clk clk_uart3_div = {
2249         .name           = "uart3_div",
2250         .parent         = &clk_uart_pll,
2251         .mode           = gate_mode,
2252         .gate_idx       = CLK_GATE_UART3_SRC,
2253         .recalc         = clksel_recalc_div,
2254         .round_rate     = clksel_freediv_round_rate,
2255         .set_rate       = clksel_set_rate_freediv,
2256         .clksel_con     = CRU_CLKSELS_CON(16),
2257         CRU_DIV_SET(0x7f, 0, 64),
2258 };
2259 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2260 {
2261         u32 numerator, denominator;
2262         //clk_uart0_div->clk_uart_pll->gpll/cpll
2263         //clk->parent->parent
2264         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2265                                 &numerator, &denominator) == 0) {
2266                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2267
2268                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2269
2270                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2271         } else {
2272                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2273                 return -ENOENT;
2274         }
2275         return 0;
2276 }
2277
2278 static struct clk clk_uart0_frac_div = {
2279         .name           = "uart0_frac_div",
2280         .parent         = &clk_uart0_div,
2281         .mode           = gate_mode,
2282         .recalc         = clksel_recalc_frac,
2283         .set_rate       = clk_uart_fracdiv_set_rate,
2284         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2285         .clksel_con     = CRU_CLKSELS_CON(17),
2286 };
2287 static struct clk clk_uart1_frac_div = {
2288         .name           = "uart1_frac_div",
2289         .parent         = &clk_uart1_div,
2290         .mode           = gate_mode,
2291         .recalc         = clksel_recalc_frac,
2292         .set_rate       = clk_uart_fracdiv_set_rate,
2293         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2294         .clksel_con     = CRU_CLKSELS_CON(18),
2295 };
2296 static struct clk clk_uart2_frac_div = {
2297         .name           = "uart2_frac_div",
2298         .mode           = gate_mode,
2299         .parent         = &clk_uart2_div,
2300         .recalc         = clksel_recalc_frac,
2301         .set_rate       = clk_uart_fracdiv_set_rate,
2302         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2303         .clksel_con     = CRU_CLKSELS_CON(19),
2304 };
2305 static struct clk clk_uart3_frac_div = {
2306         .name           = "uart3_frac_div",
2307         .parent         = &clk_uart3_div,
2308         .mode           = gate_mode,
2309         .recalc         = clksel_recalc_frac,
2310         .set_rate       = clk_uart_fracdiv_set_rate,
2311         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2312         .clksel_con     = CRU_CLKSELS_CON(20),
2313 };
2314
2315 #define UART_SRC_DIV 0
2316 #define UART_SRC_FRAC 1
2317 #define UART_SRC_24M 2
2318
2319 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2320 {
2321         int ret = 0;
2322         struct clk *parent;
2323
2324         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2325                 parent = clk->parents[UART_SRC_24M];
2326         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2327                 parent = clk->parents[UART_SRC_DIV];
2328         } else {
2329                 parent = clk->parents[UART_SRC_FRAC];
2330         }
2331
2332         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2333                         clk->name, rate, parent->name, clk->parent->name);
2334
2335         if(parent != clk->parents[UART_SRC_24M]) {
2336                 ret = clk_set_rate_nolock(parent, rate);
2337                 if (ret) {
2338                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2339                         return ret;
2340                 }
2341         }
2342
2343         if (clk->parent != parent) {
2344                 ret = clk_set_parent_nolock(clk, parent);
2345                 if (ret) {
2346                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2347                         return ret;
2348                 }
2349         }
2350
2351         return ret;
2352 }
2353
2354 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2355 static struct clk clk_uart0 = {
2356         .name           = "uart0",
2357         .set_rate       = clk_uart_set_rate,
2358         .clksel_con     = CRU_CLKSELS_CON(13),
2359         CRU_SRC_SET(0x3, 8),
2360         CRU_PARENTS_SET(clk_uart0_parents),
2361 };
2362
2363 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2364 static struct clk clk_uart1 = {
2365         .name           = "uart1",
2366         .set_rate       = clk_uart_set_rate,
2367         .clksel_con     = CRU_CLKSELS_CON(14),
2368         CRU_SRC_SET(0x3, 8),
2369         CRU_PARENTS_SET(clk_uart1_parents),
2370 };
2371
2372 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2373 static struct clk clk_uart2 = {
2374         .name           = "uart2",
2375         .set_rate       = clk_uart_set_rate,
2376         .clksel_con     = CRU_CLKSELS_CON(15),
2377         CRU_SRC_SET(0x3, 8),
2378         CRU_PARENTS_SET(clk_uart2_parents),
2379 };
2380 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2381 static struct clk clk_uart3 = {
2382         .name           = "uart3",
2383         .set_rate       = clk_uart_set_rate,
2384         .clksel_con     = CRU_CLKSELS_CON(16),
2385         CRU_SRC_SET(0x3, 8),
2386         CRU_PARENTS_SET(clk_uart3_parents),
2387 };
2388
2389 /* timer setting */
2390 GATE_CLK(timer0, xin24m, TIMER0);
2391 GATE_CLK(timer1, xin24m, TIMER1);
2392 GATE_CLK(timer2, xin24m, TIMER2);
2393
2394 /*********************power domain*******************************/
2395 #if 1
2396 #ifdef RK30_CLK_OFFBOARD_TEST
2397 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2398 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2399 #else
2400 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2401 #define _pmu_set_power_domain pmu_set_power_domain
2402 #endif
2403
2404 static int pd_video_mode(struct clk *clk, int on)
2405 {
2406         u32 gate[3];
2407         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2408         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2409         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2410         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2411         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2412         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2413         pmu_set_power_domain(PD_VIDEO, on);
2414         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2415         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2416         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2417         return 0;
2418 }
2419
2420 static struct clk pd_video = {
2421         .name   = "pd_video",
2422         .flags  = IS_PD,
2423         .mode   = pd_video_mode,
2424         .gate_idx       = PD_VIDEO,
2425 };
2426 static int pd_display_mode(struct clk *clk, int on)
2427 {
2428         u32 gate[10];
2429         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2430         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2431         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2432         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2433         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2434         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2435         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2436         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2437         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2438         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2439         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2440         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2441         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2442         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2443         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2444         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2445         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2446         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2447         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2448         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2449         pmu_set_power_domain(PD_VIO, on);
2450         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2451         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2452         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2453         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2454         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2455         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2456         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2457         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2458         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2459         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2460         return 0;
2461 }
2462
2463 static struct clk pd_display = {
2464         .name   = "pd_vio",
2465         .flags  = IS_PD,
2466         .mode   = pd_display_mode,
2467         .gate_idx       = PD_VIO,
2468 };
2469 static struct clk pd_lcdc0 = {
2470         .parent = &pd_display,
2471         .name   = "pd_lcdc0",
2472 };
2473 static struct clk pd_lcdc1 = {
2474         .parent = &pd_display,
2475         .name   = "pd_lcdc1",
2476 };
2477 static struct clk pd_cif0 = {
2478         .parent = &pd_display,
2479         .name   = "pd_cif0",
2480 };
2481 static struct clk pd_rga = {
2482         .parent = &pd_display,
2483         .name   = "pd_rga",
2484 };
2485 static struct clk pd_ipp = {
2486         .parent = &pd_display,
2487         .name   = "pd_ipp",
2488 };
2489 static struct clk pd_hdmi = {
2490         .parent = &pd_display,
2491         .name   = "pd_hdmi",
2492 };
2493
2494
2495 static int pd_gpu_mode(struct clk *clk, int on)
2496 {
2497         u32 gate[3];
2498         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
2499         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
2500         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
2501         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
2502         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
2503         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
2504         pmu_set_power_domain(PD_GPU, on);
2505         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
2506         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
2507         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
2508         return 0;
2509 }
2510
2511 static struct clk pd_gpu = {
2512         .name   = "pd_gpu",
2513         .flags  = IS_PD,
2514         .mode   = pd_gpu_mode,
2515         .gate_idx       = PD_GPU,
2516 };
2517
2518 static int pm_off_mode(struct clk *clk, int on)
2519 {
2520         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2521         return 0;
2522 }
2523 static struct clk pd_peri = {
2524         .name   = "pd_peri",
2525         .flags  = IS_PD,
2526         .mode   = pm_off_mode,
2527         .gate_idx       = PD_PERI,
2528 };
2529
2530
2531 #define PD_CLK(name) \
2532 {\
2533         .dev_id = NULL,\
2534         .con_id = #name,\
2535         .clk = &name,\
2536 }
2537
2538 #endif
2539 /************************rk30 fixed div clock****************************************/
2540
2541 /*************************aclk_cpu***********************/
2542
2543 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2544 GATE_CLK(l2mem_con,     aclk_cpu,       ACLK_L2MEM_CON);
2545 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2546 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2547
2548 /*************************hclk_cpu***********************/
2549
2550 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2551 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2552 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2553 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2554 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2555 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2556 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2557 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2558 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2559 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2560 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2561 GATE_CLK(hclk_l2mem,    hclk_cpu,       HCLK_L2MEM);
2562 GATE_CLK(hclk_video_h2h, hclk_cpu,      HCLK_VIDEO_H2H);
2563 /*************************pclk_cpu***********************/
2564 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2565 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2566 GATE_CLK(pclk_timer1,   pclk_cpu,       PCLK_TIMER1);
2567 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2568 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2569 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2570 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2571 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2572 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2573 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2574 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2575 GATE_CLK(pclk_uart0,    pclk_cpu, PCLK_UART0);
2576 GATE_CLK(pclk_uart1,    pclk_cpu, PCLK_UART1);
2577 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2578 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2579 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2580 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2581 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2582
2583 /*************************aclk_periph***********************/
2584
2585 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2586 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2587 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2588 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2589 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2590
2591 /*************************hclk_periph***********************/
2592 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2593 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2594 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2595 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2596 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2597 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2598 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2599 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2600 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2601 GATE_CLK(hclk_gps, hclk_periph, HCLK_GPS);
2602 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2603 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2604 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2605 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2606 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2607 /*************************pclk_periph***********************/
2608 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2609 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2610 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2611 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2612 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2613 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2614 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2615 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2616 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2617 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2618 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2619 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2620 /*************************aclk_lcdc0***********************/
2621
2622 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2623
2624 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2625 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2626 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2627
2628 /*************************aclk_lcdc0***********************/
2629
2630 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2631 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2632 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2633
2634
2635 #if 1
2636 #define CLK(dev, con, ck) \
2637 {\
2638         .dev_id = dev,\
2639         .con_id = con,\
2640         .clk = ck,\
2641 }
2642
2643
2644 #define CLK1(name) \
2645 {\
2646         .dev_id = NULL,\
2647         .con_id = #name,\
2648         .clk = &clk_##name,\
2649 }
2650
2651 #endif
2652
2653 static struct clk_lookup clks[] = {
2654         CLK(NULL, "xin24m", &xin24m),
2655         //CLK(NULL, "xin27m", &xin27m),
2656         CLK(NULL, "xin12m", &clk_12m),
2657         CLK(NULL, "arm_pll", &arm_pll_clk),
2658         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2659         CLK(NULL, "codec_pll", &codec_pll_clk),
2660         CLK(NULL, "general_pll", &general_pll_clk),
2661
2662         CLK(NULL, "ddr", &clk_ddr),
2663         CLK(NULL, "cpu", &clk_core),
2664         CLK(NULL, "logic", &clk_cpu_div),
2665         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2666         CLK1(l2c),
2667         CLK1(core_dbg),
2668         CLK("smp_twd", NULL, &core_periph),
2669         CLK(NULL, "aclk_core", &aclk_core),
2670         CLK(NULL, "aclk_cpu", &aclk_cpu),
2671         CLK(NULL, "pclk_cpu", &pclk_cpu),
2672         CLK(NULL, "atclk_cpu", &atclk_cpu),
2673         CLK(NULL, "hclk_cpu", &hclk_cpu),
2674         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2675
2676         CLK1(gpu),
2677         #ifdef GPU_CORE_ACLK_CTR_TOGETHER
2678         CLK(NULL, "aclk_gpu_real",&aclk_gpu),
2679         CLK(NULL, "aclk_gpu",     &aclk_gpu_null),
2680         #else
2681         CLK(NULL, "aclk_gpu",   &aclk_gpu),
2682         #endif
2683         CLK(NULL, "gpu_slv",    &aclk_gpu_slv),
2684         CLK(NULL, "gpu_mst",    &aclk_gpu_mst),
2685
2686         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2687         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2688         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2689         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2690
2691         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2692         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2693
2694         CLK(NULL, "aclk_periph", &aclk_periph),
2695         CLK(NULL, "pclk_periph", &pclk_periph),
2696         CLK(NULL, "hclk_periph", &hclk_periph),
2697
2698         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2699         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2700
2701         CLK(NULL, "cif_out_pll", &cif_out_pll),
2702         CLK(NULL, "cif0_out_div", &cif0_out_div),
2703
2704         CLK(NULL, "cif0_out", &cif0_out),
2705         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2706         CLK(NULL, "inv_cif0", &inv_cif0),
2707         CLK(NULL, "cif0_in", &cif0_in),
2708
2709         CLK1(i2s_pll),
2710         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2711         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2712         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2713
2714         // actually no i2s1
2715         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2716         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2717         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2718
2719
2720         CLK1(spdif_div),
2721         CLK1(spdif_frac_div),
2722         CLK1(spdif),
2723
2724         CLK1(otgphy0),
2725         CLK1(otgphy1),
2726         CLK1(otgphy0_480m),
2727         CLK1(otgphy1_480m),
2728         CLK1(hsicphy_480m),
2729         CLK1(hsicphy_12m),
2730
2731         CLK(NULL, "rmii_clkin", &rmii_clkin),
2732         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2733         CLK1(mac_ref),
2734         CLK1(mii_tx),
2735
2736         CLK1(hsadc_pll_div),
2737         CLK1(hsadc_frac_div),
2738         CLK1(hsadc_ext),
2739         CLK1(hsadc_out),
2740         CLK1(hsadc_out_inv),
2741         CLK1(hsadc),
2742
2743         CLK1(saradc),
2744
2745         CLK1(smc),
2746         CLK(NULL, "smc_inv",    &clkn_smc),
2747
2748         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2749         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2750
2751         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2752         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2753         CLK1(emmc),
2754
2755         CLK1(uart_pll),
2756         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2757         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2758         CLK("rk_serial.0", "uart", &clk_uart0),
2759         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2760         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2761         CLK("rk_serial.1", "uart", &clk_uart1),
2762         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2763         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2764         CLK("rk_serial.2", "uart", &clk_uart2),
2765         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2766         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2767         CLK("rk_serial.3", "uart", &clk_uart3),
2768
2769         CLK1(timer0),
2770         CLK1(timer1),
2771         CLK1(timer2),
2772
2773         /*************************aclk_cpu***********************/
2774         CLK1(dma1),
2775         CLK1(l2mem_con),
2776         CLK1(intmem),
2777         CLK1(aclk_strc_sys),
2778
2779         /*************************hclk_cpu***********************/
2780         CLK1(rom),
2781         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2782         // actually no i2s1
2783         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2784         CLK1(hclk_spdif),
2785         CLK1(hclk_cpubus),
2786         CLK1(hclk_ahb2apb),
2787         CLK1(hclk_vio_bus),
2788         CLK1(hclk_lcdc0),
2789         CLK1(hclk_lcdc1),
2790         CLK1(hclk_cif0),
2791         CLK1(hclk_ipp),
2792         CLK1(hclk_rga),
2793         CLK1(hclk_video_h2h),
2794         CLK1(hclk_l2mem),
2795
2796         /*************************pclk_cpu***********************/
2797         CLK1(pwm01),
2798         CLK1(pclk_timer0),
2799         CLK1(pclk_timer1),
2800         CLK1(pclk_timer2),
2801         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2802         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2803         CLK1(gpio0),
2804         CLK1(gpio1),
2805         CLK1(gpio2),
2806         CLK1(efuse),
2807         CLK1(tzpc),
2808         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2809         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2810         CLK1(pclk_ddrupctl),
2811         CLK1(pclk_ddrpubl),
2812         CLK1(dbg),
2813         CLK1(grf),
2814         CLK1(pmu),
2815
2816         /*************************aclk_periph***********************/
2817         CLK1(dma2),
2818         CLK1(aclk_smc),
2819         CLK1(aclk_peri_niu),
2820         CLK1(aclk_cpu_peri),
2821         CLK1(aclk_peri_axi_matrix),
2822
2823         /*************************hclk_periph***********************/
2824         CLK1(hclk_peri_axi_matrix),
2825         CLK1(hclk_peri_ahb_arbi),
2826         CLK1(hclk_emem_peri),
2827         CLK1(hclk_mac),
2828         CLK1(nandc),
2829         CLK1(hclk_usb_peri),
2830         CLK1(hclk_otg0),
2831         CLK1(hclk_otg1),
2832         CLK1(hclk_hsic),
2833         CLK1(hclk_gps),
2834         CLK1(hclk_hsadc),
2835         CLK1(hclk_pidfilter),
2836         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2837         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2838         CLK1(hclk_emmc),
2839
2840         /*************************pclk_periph***********************/
2841         CLK1(pclk_peri_axi_matrix),
2842         CLK1(pwm23),
2843         CLK1(wdt),
2844         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2845         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2846         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2847         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2848         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2849         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2850         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2851         CLK1(gpio3),
2852         CLK1(pclk_saradc),
2853
2854         /*************************aclk_lcdc0***********************/
2855         CLK1(aclk_vio0),
2856         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2857         CLK1(aclk_cif0),
2858         CLK1(aclk_ipp),
2859
2860         /*************************aclk_lcdc1***********************/
2861         CLK1(aclk_vio1),
2862         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2863         CLK1(aclk_rga),
2864         /************************power domain**********************/
2865
2866         PD_CLK(pd_peri),
2867         PD_CLK(pd_display),
2868         PD_CLK(pd_video),
2869         PD_CLK(pd_lcdc0),
2870         PD_CLK(pd_lcdc1),
2871         PD_CLK(pd_cif0),
2872         //PD_CLK(pd_cif1),
2873         PD_CLK(pd_rga),
2874         PD_CLK(pd_ipp),
2875         PD_CLK(pd_video),
2876         PD_CLK(pd_gpu),
2877         //PD_CLK(pd_dbg),
2878 };
2879 static void __init rk30_init_enable_clocks(void)
2880 {
2881         #if 0
2882         //clk_enable_nolock(&xin24m);
2883         //clk_enable_nolock(&clk_12m);
2884         //clk_enable_nolock(&arm_pll_clk);
2885         //clk_enable_nolock(&ddr_pll_clk);
2886         //clk_enable_nolock(&codec_pll_clk);
2887         //clk_enable_nolock(&general_pll_clk);
2888         #endif
2889         clk_enable_nolock(&clk_ddr);
2890         //clk_enable_nolock(&clk_core);
2891         clk_enable_nolock(&clk_cpu_div);
2892         clk_enable_nolock(&clk_core_gpll_path);
2893         clk_enable_nolock(&clk_l2c);
2894         clk_enable_nolock(&clk_core_dbg);
2895         clk_enable_nolock(&core_periph);
2896         clk_enable_nolock(&aclk_core);
2897         //clk_enable_nolock(&aclk_cpu);
2898         //clk_enable_nolock(&pclk_cpu);
2899         clk_enable_nolock(&atclk_cpu);
2900         //clk_enable_nolock(&hclk_cpu);
2901         clk_enable_nolock(&ahb2apb_cpu);
2902         #if 0
2903          clk_enable_nolock(&clk_gpu);
2904          clk_enable_nolock(&aclk_gpu);
2905          clk_enable_nolock(&aclk_gpu_slv);
2906          clk_enable_nolock(&aclk_gpu_mst);
2907
2908          clk_enable_nolock(&aclk_vepu);
2909          clk_enable_nolock(&hclk_vepu);
2910          clk_enable_nolock(&aclk_vdpu);
2911          clk_enable_nolock(&hclk_vdpu);
2912
2913          clk_enable_nolock(&aclk_lcdc0_pre);
2914          clk_enable_nolock(&aclk_lcdc1_pre);
2915
2916          clk_enable_nolock(&aclk_periph);
2917         clk_enable_nolock(&pclk_periph);
2918         clk_enable_nolock(&hclk_periph);
2919         #endif
2920         #if 0
2921          clk_enable_nolock(&dclk_lcdc0);
2922          clk_enable_nolock(&dclk_lcdc1);
2923
2924          clk_enable_nolock(&cif_out_pll);
2925          clk_enable_nolock(&cif0_out_div);
2926
2927          clk_enable_nolock(&cif0_out);
2928          clk_enable_nolock(&pclkin_cif0);
2929          clk_enable_nolock(&inv_cif0);
2930          clk_enable_nolock(&cif0_in);
2931
2932          clk_enable_nolock(&clk_i2s_pll);
2933          clk_enable_nolock(&clk_i2s0_div);
2934          clk_enable_nolock(&clk_i2s0_frac_div);
2935          clk_enable_nolock(&clk_i2s0);
2936
2937           actually no i2s1
2938          clk_enable_nolock(&clk_i2s0_div);
2939          clk_enable_nolock(&clk_i2s0_frac_div);
2940          clk_enable_nolock(&clk_i2s0);
2941
2942         clk_enable_nolock(&clk_spdif_div);
2943         clk_enable_nolock(&clk_spdif_frac_div);
2944         clk_enable_nolock(&clk_spdif);
2945         #endif
2946         #if 0
2947         clk_enable_nolock(&clk_otgphy0);
2948         clk_enable_nolock(&clk_otgphy1);
2949         clk_enable_nolock(&clk_otgphy0_480m);
2950         clk_enable_nolock(&clk_otgphy1_480m);
2951         clk_enable_nolock(&clk_hsicphy_480m);
2952         clk_enable_nolock(&clk_hsicphy_12m);
2953         #endif
2954
2955         #if 0
2956         clk_enable_nolock(&rmii_clkin);
2957         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
2958         clk_enable_nolock(&clk_mac_ref);
2959         clk_enable_nolock(&clk_mii_tx);
2960         #endif
2961
2962         #if 0
2963         clk_enable_nolock(&clk_hsadc_pll_div);
2964         clk_enable_nolock(&clk_hsadc_frac_div);
2965         clk_enable_nolock(&clk_hsadc_ext);
2966         clk_enable_nolock(&clk_hsadc_out);
2967         clk_enable_nolock(&clk_hsadc_out_inv);
2968         clk_enable_nolock(&clk_hsadc);
2969
2970         clk_enable_nolock(&clk_saradc);
2971         #endif
2972         /*
2973         clk_enable_nolock(&clk_smc);
2974         clk_enable_nolock(&clkn_smc);
2975         */
2976         /*
2977         clk_enable_nolock(&clk_spi0);
2978         clk_enable_nolock(&clk_spi1);
2979         */
2980         /*
2981         clk_enable_nolock(&clk_sdmmc);
2982         clk_enable_nolock(&clk_sdio);
2983         clk_enable_nolock(&clk_emmc);
2984         */
2985         #if 0
2986         clk_enable_nolock(&clk_uart_pll);
2987         clk_enable_nolock(&clk_uart0_div);
2988         clk_enable_nolock(&clk_uart0_frac_div);
2989         clk_enable_nolock(&clk_uart0);
2990         clk_enable_nolock(&clk_uart1_div);
2991         clk_enable_nolock(&clk_uart1_frac_div);
2992         clk_enable_nolock(&clk_uart1);
2993         clk_enable_nolock(&clk_uart2_div);
2994         clk_enable_nolock(&clk_uart2_frac_div);
2995         clk_enable_nolock(&clk_uart2);
2996         clk_enable_nolock(&clk_uart3_div);
2997         clk_enable_nolock(&clk_uart3_frac_div);
2998         clk_enable_nolock(&clk_uart3);
2999         #endif
3000         #if CONFIG_RK_DEBUG_UART == 0
3001                 clk_enable_nolock(&clk_uart0);
3002                 clk_enable_nolock(&clk_pclk_uart0);
3003         #elif CONFIG_RK_DEBUG_UART == 1
3004                 clk_enable_nolock(&clk_uart1);
3005                 clk_enable_nolock(&clk_pclk_uart1);
3006
3007         #elif CONFIG_RK_DEBUG_UART == 2
3008                 clk_enable_nolock(&clk_uart2);
3009                 clk_enable_nolock(&clk_pclk_uart2);
3010
3011         #elif CONFIG_RK_DEBUG_UART == 3
3012                 clk_enable_nolock(&clk_uart3);
3013                 clk_enable_nolock(&clk_pclk_uart3);
3014
3015         #endif
3016         #if 0
3017         clk_enable_nolock(&clk_timer0);
3018         clk_enable_nolock(&clk_timer1);
3019         clk_enable_nolock(&clk_timer2);
3020         #endif
3021
3022         /*************************aclk_cpu***********************/
3023         clk_enable_nolock(&clk_dma1);
3024         clk_enable_nolock(&clk_l2mem_con);
3025         clk_enable_nolock(&clk_intmem);
3026         clk_enable_nolock(&clk_aclk_strc_sys);
3027
3028         /*************************hclk_cpu***********************/
3029         clk_enable_nolock(&clk_rom);
3030         #if 0
3031         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3032         // actually no i2s1
3033         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3034         clk_enable_nolock(&clk_hclk_spdif);
3035         #endif
3036         clk_enable_nolock(&clk_hclk_cpubus);
3037         clk_enable_nolock(&clk_hclk_ahb2apb);
3038         clk_enable_nolock(&clk_hclk_vio_bus);
3039         #if 0
3040         clk_enable_nolock(&clk_hclk_lcdc0);
3041         clk_enable_nolock(&clk_hclk_lcdc1);
3042         clk_enable_nolock(&clk_hclk_cif0);
3043         clk_enable_nolock(&clk_hclk_ipp);
3044         clk_enable_nolock(&clk_hclk_rga);
3045         #endif
3046         clk_enable_nolock(&clk_hclk_video_h2h);
3047         clk_enable_nolock(&clk_hclk_l2mem);
3048
3049         /*************************pclk_cpu***********************/
3050         #if 0
3051         clk_enable_nolock(&clk_pwm01);
3052         clk_enable_nolock(&clk_pclk_timer0);
3053         clk_enable_nolock(&clk_pclk_timer1);
3054         clk_enable_nolock(&clk_pclk_timer2);
3055         clk_enable_nolock(&clk_i2c0);
3056         clk_enable_nolock(&clk_i2c1);
3057         clk_enable_nolock(&clk_gpio0);
3058         clk_enable_nolock(&clk_gpio1);
3059         clk_enable_nolock(&clk_gpio2);
3060         clk_enable_nolock(&clk_efuse);
3061         #endif
3062         clk_enable_nolock(&clk_tzpc);
3063         //clk_enable_nolock(&clk_pclk_uart0);
3064         //clk_enable_nolock(&clk_pclk_uart1);
3065         clk_enable_nolock(&clk_pclk_ddrupctl);
3066         clk_enable_nolock(&clk_pclk_ddrpubl);
3067         clk_enable_nolock(&clk_dbg);
3068         clk_enable_nolock(&clk_grf);
3069         clk_enable_nolock(&clk_pmu);
3070
3071         /*************************aclk_periph***********************/
3072         clk_enable_nolock(&clk_dma2);
3073         clk_enable_nolock(&clk_aclk_smc);
3074         clk_enable_nolock(&clk_aclk_peri_niu);
3075         clk_enable_nolock(&clk_aclk_cpu_peri);
3076         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3077
3078         /*************************hclk_periph***********************/
3079         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3080         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3081         clk_enable_nolock(&clk_hclk_emem_peri);
3082         //clk_enable_nolock(&clk_hclk_mac);
3083         //clk_enable_nolock(&clk_nandc);
3084         clk_enable_nolock(&clk_hclk_usb_peri);
3085         #if 0
3086         clk_enable_nolock(&clk_hclk_otg0);
3087         clk_enable_nolock(&clk_hclk_otg1);
3088         clk_enable_nolock(&clk_hclk_hsic);
3089         clk_enable_nolock(&clk_hclk_gps);
3090         clk_enable_nolock(&clk_hclk_hsadc);
3091         clk_enable_nolock(&clk_hclk_pidfilter);
3092         clk_enable_nolock(&clk_hclk_sdmmc);
3093         clk_enable_nolock(&clk_hclk_sdio);
3094         clk_enable_nolock(&clk_hclk_emmc);
3095         #endif
3096
3097         /*************************pclk_periph***********************/
3098         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3099         #if 0
3100         clk_enable_nolock(&clk_pwm23);
3101         clk_enable_nolock(&clk_wdt);
3102         clk_enable_nolock(&clk_pclk_spi0);
3103         clk_enable_nolock(&clk_pclk_spi1);
3104         clk_enable_nolock(&clk_pclk_uart2);
3105         clk_enable_nolock(&clk_pclk_uart3);
3106         #endif
3107         #if 0
3108         clk_enable_nolock(&clk_i2c2);
3109         clk_enable_nolock(&clk_i2c3);
3110         clk_enable_nolock(&clk_i2c4);
3111         clk_enable_nolock(&clk_gpio3);
3112         clk_enable_nolock(&clk_pclk_saradc);
3113         #endif
3114         /*************************aclk_lcdc0***********************/
3115 #if 1
3116         //clk_enable_nolock(&clk_aclk_vio0);
3117         //clk_enable_nolock(&clk_aclk_lcdc0);
3118         //clk_enable_nolock(&clk_aclk_cif0);
3119         //clk_enable_nolock(&clk_aclk_ipp);
3120 #endif
3121         /*************************aclk_lcdc1***********************/
3122 #if 1
3123         //clk_enable_nolock(&clk_aclk_vio1);
3124         //clk_enable_nolock(&clk_aclk_lcdc1);
3125         //clk_enable_nolock(&clk_aclk_rga);
3126 #endif
3127         /************************power domain**********************/
3128
3129 }
3130 static void periph_clk_set_init(void)
3131 {
3132         unsigned long aclk_p, hclk_p, pclk_p;
3133         unsigned long ppll_rate = general_pll_clk.rate;
3134         //aclk 148.5
3135
3136         /* general pll */
3137         switch (ppll_rate) {
3138                 case 148500* KHZ:
3139                         aclk_p = 148500 * KHZ;
3140                         hclk_p = aclk_p >> 1;
3141                         pclk_p = aclk_p >> 2;
3142                         break;
3143                 case 1188*MHZ:
3144                         aclk_p = aclk_p >> 3; // 0
3145                         hclk_p = aclk_p >> 1;
3146                         pclk_p = aclk_p >> 2;
3147
3148                 case 297 * MHZ:
3149                         aclk_p = ppll_rate >> 1;
3150                         hclk_p = aclk_p >> 0;
3151                         pclk_p = aclk_p >> 1;
3152                         break;
3153
3154                 case 300 * MHZ:
3155                         aclk_p = ppll_rate >> 1;
3156                         hclk_p = aclk_p >> 0;
3157                         pclk_p = aclk_p >> 1;
3158                         break;
3159                 case 594 * MHZ:
3160                         aclk_p = ppll_rate >> 2;
3161                         hclk_p = aclk_p >> 0;
3162                         pclk_p = aclk_p >> 1;
3163                         break;
3164                 default:
3165                         aclk_p = 150 * MHZ;
3166                         hclk_p = 150 * MHZ;
3167                         pclk_p = 75 * MHZ;
3168                         break;
3169         }
3170         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3171         clk_set_rate_nolock(&aclk_periph, aclk_p);
3172         clk_set_rate_nolock(&hclk_periph, hclk_p);
3173         clk_set_rate_nolock(&pclk_periph, pclk_p);
3174 }
3175
3176 static void cpu_axi_init(void)
3177 {
3178         unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3179         unsigned long gpll_rate = general_pll_clk.rate;
3180
3181         switch (gpll_rate) {
3182                 case 297 * MHZ:
3183                         cpu_div_rate = gpll_rate;
3184                         aclk_cpu_rate = cpu_div_rate >> 0;
3185                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3186                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3187                         break;
3188
3189                 case 594 * MHZ:
3190                         cpu_div_rate = gpll_rate >> 1;
3191                         aclk_cpu_rate = cpu_div_rate >> 0;
3192                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3193                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3194                         break;
3195                 default:
3196                         aclk_cpu_rate = 150 * MHZ;
3197                         hclk_cpu_rate = 150 * MHZ;
3198                         pclk_cpu_rate = 75 * MHZ;
3199                         break;
3200         }
3201         ahb2apb_cpu_rate = pclk_cpu_rate;
3202
3203         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3204         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3205         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3206         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3207         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3208         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3209 }
3210
3211 void rk30_clock_common_i2s_init(void)
3212 {
3213         unsigned long i2s_rate;
3214         //20 times
3215         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3216                 i2s_rate = 49152000;
3217         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3218                 i2s_rate = 24576000;
3219         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3220                 i2s_rate = 22579000;
3221         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3222                 i2s_rate = 12288000;
3223         } else {
3224                 i2s_rate = 49152000;
3225         }
3226
3227         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3228                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3229         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3230                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3231         } else {
3232                 if(general_pll_clk.rate > codec_pll_clk.rate)
3233                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3234                 else
3235                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3236         }
3237 }
3238
3239 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3240 {
3241
3242         //general
3243         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3244         //code pll
3245         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3246
3247         cpu_axi_init();
3248         clk_set_rate_nolock(&clk_core, 312 * MHZ);
3249         //periph clk
3250         periph_clk_set_init();
3251
3252         //i2s
3253         rk30_clock_common_i2s_init();
3254
3255         // spi
3256         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3257         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3258
3259         // uart
3260         if(rk30_clock_flags & CLK_FLG_UART_1_3M)
3261                 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3262         else
3263                 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3264         //mac
3265         if(!(gpll_rate % (50 * MHZ)))
3266                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3267         else if(!(ddr_pll_clk.rate % (50 * MHZ)))
3268                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3269         else
3270                 CLKDATA_ERR("mac can't get 50mhz\n");
3271
3272         //hsadc
3273         //auto pll sel
3274         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3275
3276         //lcdc0 lcd auto sel pll
3277         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3278         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3279
3280         //cif
3281         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3282
3283         //axi lcdc auto sel
3284         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3285         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3286         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3287         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3288
3289         //axi vepu auto sel
3290         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3291         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3292
3293         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3294         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3295         //gpu auto sel
3296         clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
3297         clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
3298         clk_set_rate_nolock(&clk_gpu, 200 * MHZ);
3299         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3300
3301         clk_set_rate_nolock(&clk_uart0, 49500000);
3302         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3303         clk_set_rate_nolock(&clk_sdio, 24750000);
3304 }
3305
3306 static struct clk def_ops_clk = {
3307         .get_parent = clksel_get_parent,
3308         .set_parent = clksel_set_parent,
3309 };
3310
3311 #ifdef CONFIG_PROC_FS
3312 struct clk_dump_ops dump_ops;
3313 #endif
3314 void rk_dump_clock_info(void);
3315
3316 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3317 {
3318         struct clk_lookup *lk;
3319
3320         clk_register_dump_ops(&dump_ops);
3321         clk_register_default_ops_clk(&def_ops_clk);
3322         rk30_clock_flags = flags;
3323         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3324 #ifdef RK30_CLK_OFFBOARD_TEST
3325                 rk30_clkdev_add(lk);
3326 #else
3327                 clkdev_add(lk);
3328 #endif
3329                 clk_register(lk->clk);
3330         }
3331         clk_recalculate_root_clocks_nolock();
3332
3333         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3334
3335         /*
3336          * Only enable those clocks we will need, let the drivers
3337          * enable other clocks as necessary
3338          */
3339         rk30_init_enable_clocks();
3340 #if 0
3341         // print loader config
3342         rk_dump_clock_info();
3343         while(1);
3344 #endif
3345         /*
3346          * Disable any unused clocks left on by the bootloader
3347          */
3348         //clk_disable_unused();
3349         rk30_clock_common_init(gpll, cpll);
3350         preset_lpj = loops_per_jiffy;
3351
3352         //gpio6_b7
3353         //regfile_writel(0xc0004000,0x10c);
3354         //cru_writel(0x07000000,CRU_MISC_CON);
3355
3356 }
3357
3358 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3359 {
3360         _rk30_clock_data_init(gpll, cpll, flags);
3361         rk_dvfs_init();
3362 }
3363
3364 /*
3365  * You can override arm_clk rate with armclk= cmdline option.
3366  */
3367 static int __init armclk_setup(char *str)
3368 {
3369         get_option(&str, &armclk);
3370
3371         if (!armclk)
3372                 return 0;
3373         if (armclk < 10000)
3374                 armclk *= MHZ;
3375         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3376         return 0;
3377 }
3378 #ifndef RK30_CLK_OFFBOARD_TEST
3379 early_param("armclk", armclk_setup);
3380 #endif
3381
3382
3383 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3384 {
3385         struct clk *ck;
3386         int i;
3387         unsigned long rate = clk->rate;
3388         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3389         for (i = 0; i < deep; i++)
3390                 printk("    ");
3391
3392         printk("%-11s ", clk->name);
3393 #ifndef RK30_CLK_OFFBOARD_TEST
3394         if (clk->flags & IS_PD) {
3395                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3396         }
3397 #endif
3398         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3399                 int idx = clk->gate_idx;
3400                 u32 v;
3401                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3402                 printk("%s ", v ? "off" : "on ");
3403         }
3404
3405         if (clk->pll) {
3406                 u32 pll_mode;
3407                 u32 pll_id = clk->pll->id;
3408                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3409                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3410                         printk("slow   ");
3411                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3412                         printk("normal ");
3413                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3414                         printk("deep   ");
3415
3416                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3417                         printk("bypass ");
3418         } else if(clk == &clk_ddr) {
3419                 rate = clk->recalc(clk);
3420         }
3421
3422         if (rate >= MHZ) {
3423                 if (rate % MHZ)
3424                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3425                 else
3426                         printk("%ld MHz", rate / MHZ);
3427         } else if (rate >= KHZ) {
3428                 if (rate % KHZ)
3429                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3430                 else
3431                         printk("%ld KHz", rate / KHZ);
3432         } else {
3433                 printk("%ld Hz", rate);
3434         }
3435
3436         printk(" usecount = %d", clk->usecount);
3437
3438         if (clk->parent)
3439                 printk(" parent = %s", clk->parent->name);
3440
3441         printk("\n");
3442
3443         list_for_each_entry(ck, root_clocks, node) {
3444                 if (ck->parent == clk)
3445                         rk_dump_clock(ck, deep + 1, root_clocks);
3446         }
3447 }
3448
3449 #if 1
3450 struct list_head *get_rk_clocks_head(void);
3451
3452 void rk_dump_clock_info(void)
3453 {
3454         struct clk* clk;
3455         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3456                 if (!clk->parent)
3457                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3458         }
3459 }
3460 #endif
3461
3462 #ifdef CONFIG_PROC_FS
3463
3464 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3465 {
3466         struct clk *ck;
3467         int i;
3468         unsigned long rate = clk->rate;
3469         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3470         for (i = 0; i < deep; i++)
3471                 seq_printf(s, "    ");
3472
3473         seq_printf(s, "%-11s ", clk->name);
3474 #ifndef RK30_CLK_OFFBOARD_TEST
3475         if (clk->flags & IS_PD) {
3476                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3477         }
3478 #endif
3479         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3480                 int idx = clk->gate_idx;
3481                 u32 v;
3482                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3483                 seq_printf(s, "%s ", v ? "off" : "on ");
3484         }
3485
3486         if (clk->pll) {
3487                 u32 pll_mode;
3488                 u32 pll_id = clk->pll->id;
3489                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3490                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3491                         seq_printf(s, "slow   ");
3492                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3493                         seq_printf(s, "normal ");
3494                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3495                         seq_printf(s, "deep   ");
3496
3497                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3498                         seq_printf(s, "bypass ");
3499         } else if(clk == &clk_ddr) {
3500                 rate = clk->recalc(clk);
3501         }
3502
3503         if (rate >= MHZ) {
3504                 if (rate % MHZ)
3505                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3506                 else
3507                         seq_printf(s, "%ld MHz", rate / MHZ);
3508         } else if (rate >= KHZ) {
3509                 if (rate % KHZ)
3510                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3511                 else
3512                         seq_printf(s, "%ld KHz", rate / KHZ);
3513         } else {
3514                 seq_printf(s, "%ld Hz", rate);
3515         }
3516
3517         seq_printf(s, " usecount = %d", clk->usecount);
3518
3519         if (clk->parent)
3520                 seq_printf(s, " parent = %s", clk->parent->name);
3521
3522         seq_printf(s, "\n");
3523
3524         list_for_each_entry(ck, root_clocks, node) {
3525                 if (ck->parent == clk)
3526                         dump_clock(s, ck, deep + 1, root_clocks);
3527         }
3528 }
3529
3530 static void dump_regs(struct seq_file *s)
3531 {
3532         int i = 0;
3533         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3534         seq_printf(s, "\nPLLRegisters:\n");
3535         for(i = 0; i < END_PLL_ID; i++) {
3536                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3537                                 cru_readl(PLL_CONS(i, 0)),
3538                                 cru_readl(PLL_CONS(i, 1)),
3539                                 cru_readl(PLL_CONS(i, 2)),
3540                                 cru_readl(PLL_CONS(i, 3))
3541                           );
3542         }
3543         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3544
3545         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3546                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3547         }
3548         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3549                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3550         }
3551         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3552         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3553
3554         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3555                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3556         }
3557         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3558         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3559
3560 }
3561
3562 void rk30_clk_dump_regs(void)
3563 {
3564         int i = 0;
3565         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3566         printk("\nPLLRegisters:\n");
3567         for(i = 0; i < END_PLL_ID; i++) {
3568                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3569                                 cru_readl(PLL_CONS(i, 0)),
3570                                 cru_readl(PLL_CONS(i, 1)),
3571                                 cru_readl(PLL_CONS(i, 2)),
3572                                 cru_readl(PLL_CONS(i, 3))
3573                       );
3574         }
3575         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3576
3577         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3578                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3579         }
3580         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3581                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3582         }
3583         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3584         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3585
3586         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3587                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3588         }
3589         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3590         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3591
3592 }
3593
3594
3595 #ifdef CONFIG_PROC_FS
3596 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3597 struct clk_dump_ops dump_ops = {
3598         .dump_clk = dump_clock,
3599         .dump_regs = dump_regs,
3600 };
3601 #endif
3602
3603
3604 #endif /* CONFIG_PROC_FS */
3605
3606
3607
3608
3609 #ifdef RK30_CLK_OFFBOARD_TEST
3610 struct clk *test_get_parent(struct clk *clk) {
3611         return clk->parent;
3612 }
3613
3614 void i2s_test(void)
3615 {
3616         struct clk *i2s_clk = &clk_i2s0;
3617
3618         clk_enable_nolock(i2s_clk);
3619
3620         clk_set_rate_nolock(i2s_clk, 12288000);
3621         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3622         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3623         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3624         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3625         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3626
3627 }
3628
3629 void uart_test(void)
3630 {
3631         struct clk *uart_clk = &clk_uart0;
3632
3633         clk_enable_nolock(uart_clk);
3634
3635         clk_set_rate_nolock(uart_clk, 12288000);
3636         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3637         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3638         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3639         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3640         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3641
3642 }
3643 void hsadc_test(void)
3644 {
3645         struct clk *hsadc_clk = &clk_hsadc;
3646
3647         printk("******************hsadc_test**********************\n");
3648         clk_enable_nolock(hsadc_clk);
3649
3650         clk_set_rate_nolock(hsadc_clk, 12288000);
3651         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3652
3653
3654         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3655         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3656
3657         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3658
3659         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3660
3661         printk("******************hsadc out clock**********************\n");
3662
3663         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3664         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3665         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3666         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3667
3668
3669
3670 }
3671
3672 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3673 {
3674         //arm
3675         printk("*********arm_pll_clk***********\n");
3676         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3677
3678         printk("*********set clk_core parent***********\n");
3679         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3680         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3681
3682         //general
3683         printk("*********general_pll_clk***********\n");
3684         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3685
3686         //code pll
3687         printk("*********codec_pll_clk***********\n");
3688         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3689
3690
3691         printk("*********periph_clk_set_init***********\n");
3692         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3693         periph_clk_set_init();
3694
3695 #if 0 //
3696         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3697 #else
3698         printk("*********clk i2s***********\n");
3699         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3700         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3701         i2s_test();
3702 #endif
3703         // spi
3704         clk_enable_nolock(&clk_spi0);
3705         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3706         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3707         //saradc
3708         clk_enable_nolock(&clk_saradc);
3709         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3710         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3711         //sdio
3712         clk_enable_nolock(&clk_sdio);
3713         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3714         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3715         // uart
3716         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3717         uart_test();
3718         //mac
3719         printk("*********mac***********\n");
3720
3721         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3722         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3723
3724         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3725         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3726         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3727
3728         printk("*********mac mii set***********\n");
3729         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3730         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3731         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3732         //hsadc
3733         printk("*********hsadc 1***********\n");
3734         //auto pll
3735         hsadc_test();
3736         //lcdc
3737         clk_enable_nolock(&dclk_lcdc0);
3738
3739         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
3740         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
3741
3742         //cif
3743         clk_enable_nolock(&cif0_out);
3744
3745         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3746         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
3747
3748         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
3749         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3750
3751         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
3752         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3753         //cif_in
3754         clk_enable_nolock(&cif0_in);
3755         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
3756         //axi lcdc
3757         clk_enable_nolock(&aclk_lcdc0);
3758         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
3759         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
3760         //axi vepu
3761         clk_enable_nolock(&aclk_vepu);
3762         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3763         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
3764
3765         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
3766         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
3767
3768         printk("test end\n");
3769
3770         /* arm pll
3771            clk_set_rate_nolock(&arm_pll_clk, armclk);
3772            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
3773            */
3774         //
3775         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3776         //
3777         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3778         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3779
3780 }
3781
3782
3783
3784
3785
3786 static LIST_HEAD(rk30_clocks);
3787 static DEFINE_MUTEX(rk30_clocks_mutex);
3788
3789 static inline int __rk30clk_get(struct clk *clk)
3790 {
3791         return 1;
3792 }
3793 void rk30_clkdev_add(struct clk_lookup *cl)
3794 {
3795         mutex_lock(&rk30_clocks_mutex);
3796         list_add_tail(&cl->node, &rk30_clocks);
3797         mutex_unlock(&rk30_clocks_mutex);
3798 }
3799 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
3800         struct clk_lookup *p, *cl = NULL;
3801         int match, best = 0;
3802
3803         list_for_each_entry(p, &rk30_clocks, node) {
3804                 match = 0;
3805                 if (p->dev_id) {
3806                         if (!dev_id || strcmp(p->dev_id, dev_id))
3807                                 continue;
3808                         match += 2;
3809                 }
3810                 if (p->con_id) {
3811                         if (!con_id || strcmp(p->con_id, con_id))
3812                                 continue;
3813                         match += 1;
3814                 }
3815
3816                 if (match > best) {
3817                         cl = p;
3818                         if (match != 3)
3819                                 best = match;
3820                         else
3821                                 break;
3822                 }
3823         }
3824         return cl;
3825 }
3826
3827 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
3828         struct clk_lookup *cl;
3829
3830         mutex_lock(&rk30_clocks_mutex);
3831         cl = rk30_clk_find(dev_id, con_id);
3832         if (cl && !__rk30clk_get(cl->clk))
3833                 cl = NULL;
3834         mutex_unlock(&rk30_clocks_mutex);
3835
3836         return cl ? cl->clk : ERR_PTR(-ENOENT);
3837 }
3838 //EXPORT_SYMBOL(rk30_clk_get_sys);
3839
3840 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
3841         const char *dev_id = dev ? dev_name(dev) : NULL;
3842         return rk30_clk_get_sys(dev_id, con_id);
3843 }
3844 //EXPORT_SYMBOL(rk30_clk_get);
3845
3846
3847 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3848
3849 void rk30_clocks_test(void)
3850 {
3851         struct clk *test_gpll;
3852         test_gpll = rk30_clk_get(NULL, "general_pll");
3853         if(test_gpll) {
3854                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
3855                 printk("gpll rate=%lu\n", test_gpll->rate);
3856         }
3857         //while(1);
3858 }
3859
3860 void __init rk30_clock_init_test(void)
3861 {
3862
3863         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
3864         //while(1);
3865 }
3866
3867
3868 #endif
3869
3870