arch/arm/mach-rk30/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include <mach/clock.h>
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29 #include <mach/ddr.h>
  30
  31 #define MHZ                     (1000*1000)
  32 #define KHZ                     (1000)
  33 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  34 #define CLK_LOOPS_RATE_REF (1200) //Mhz
  35 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  36
  37 //flags bit
  38 //has extern 27mhz
  39 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  40 //max i2s rate
  41 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  42 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  43 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  44 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  45 //uart 1m\3m
  46 #define CLK_FLG_UART_1_3M                       (1<<5)
  47 #define CLK_CPU_HPCLK_11                                (1<<6)
  48
  49
  50
  51 struct apll_clk_set {
  52         unsigned long rate;
  53         u32     pllcon0;
  54         u32     pllcon1;
  55         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  56         u32 rst_dly;//us
  57         u32     clksel0;
  58         u32     clksel1;
  59         unsigned long lpj;
  60 };
  61 struct pll_clk_set {
  62         unsigned long rate;
  63         u32     pllcon0;
  64         u32     pllcon1;
  65         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  66         u32 rst_dly;//us
  67 };
  68
  69 #define SET_PLL_DATA(_pll_id,_table) \
  70 {\
  71         .id=(_pll_id),\
  72         .table=(_table),\
  73 }
  74
  75
  76 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  77 { \
  78         .rate   = (_mhz) * KHZ, \
  79         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  80         .pllcon1 = PLL_CLKF_SET(nf),\
  81         .pllcon2 = PLL_CLK_BWADJ_SET(nf/2-1),\
  82         .rst_dly=((nr*500)/24+1),\
  83         }
  84
  85
  86 #define _APLL_SET_LPJ(_mhz) \
  87         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  88
  89
  90 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
  91         { \
  92         .rate   = _mhz * MHZ, \
  93         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no),\
  94         .pllcon1 = PLL_CLKF_SET(nf),\
  95         .pllcon2 = PLL_CLK_BWADJ_SET(nf>>1),\
  96         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
  97         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
  98         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
  99         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 100         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 101         _APLL_SET_LPJ(_mhz),\
 102         .rst_dly=((nr*500)/24+1),\
 103         }
 104
 105 #define CRU_DIV_SET(mask,shift,max) \
 106         .div_mask=(mask),\
 107         .div_shift=(shift),\
 108         .div_max=(max)
 109
 110
 111 #define CRU_SRC_SET(mask,shift ) \
 112         .src_mask=(mask),\
 113         .src_shift=(shift)
 114
 115 #define CRU_PARENTS_SET(parents_array) \
 116         .parents=(parents_array),\
 117         .parents_num=ARRAY_SIZE((parents_array))
 118
 119 #define CRU_GATE_MODE_SET(_func,_IDX) \
 120         .mode=_func,\
 121         .gate_idx=(_IDX)
 122
 123 struct clk_src_sel {
 124         struct clk      *parent;
 125         u8      value;//crt bit
 126         u8      flag;
 127 //selgate
 128 };
 129
 130 #define GATE_CLK(NAME,PARENT,ID) \
 131 static struct clk clk_##NAME = { \
 132         .name           = #NAME, \
 133         .parent         = &PARENT, \
 134         .mode           = gate_mode, \
 135         .gate_idx       = CLK_GATE_##ID, \
 136 }
 137 #ifdef RK30_CLK_OFFBOARD_TEST
 138 u32 TEST_GRF_REG[0x240];
 139 u32 TEST_CRU_REG[0x240];
 140 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 141
 142 u32 cru_writel_is_pr(u32 offset)
 143 {
 144         return (offset==0x4000);
 145 }
 146 void cru_writel(u32 v, u32 offset)
 147 {
 148
 149         u32 mask_v=v>>16;
 150         TEST_CRU_REG[offset/4]&=(~mask_v);
 151
 152         v&=(mask_v);
 153
 154         TEST_CRU_REG[offset/4]|=v;
 155         TEST_CRU_REG[offset/4]&=0x0000ffff;
 156
 157         if(cru_writel_is_pr(offset))
 158         {
 159                 CRU_PRINTK_DBG("cru w offset=%d,set=%x,reg=%x\n",offset,v,TEST_CRU_REG[offset/4]);
 160
 161         }
 162
 163 }
 164 void cru_writel_i2s(u32 v, u32 offset)
 165 {
 166         TEST_CRU_REG[offset/4]=v;
 167 }
 168 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 169
 170 #define regfile_readl(offset)   (0xffffffff)
 171 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 172 void rk30_clkdev_add(struct clk_lookup *cl);
 173 #else
 174 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 175 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 176 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 177 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 178
 179 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 180 #endif
 181
 182 #ifdef DEBUG
 183 #define CRU_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
 184 #define CRU_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
 185 #else
 186 #define CRU_PRINTK_DBG(fmt, args...) do {} while(0)
 187 #define CRU_PRINTK_LOG(fmt, args...) do {} while(0)
 188 #endif
 189 #define CRU_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args)
 190
 191
 192 #define get_cru_bits(con,mask,shift)\
 193         ((cru_readl((con)) >> (shift)) & (mask))
 194
 195 #define set_cru_bits_w_msk(val,mask,shift,con)\
 196         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 197
 198
 199 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 200         &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 201
 202
 203 static u32 rk30_clock_flags=0;
 204 static struct clk codec_pll_clk;
 205 static struct clk general_pll_clk;
 206 static struct clk arm_pll_clk;
 207 static unsigned long lpj_gpll;
 208 static unsigned int __initdata armclk = 504*MHZ;
 209
 210
 211 /************************clk recalc div rate*********************************/
 212
 213 //for free div
 214 static unsigned long clksel_recalc_div(struct clk *clk)
 215 {
 216         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift) + 1;
 217
 218         unsigned long rate = clk->parent->rate / div;
 219         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 220         return rate;
 221 }
 222
 223 //for div 1 2 4 2^n
 224 static unsigned long clksel_recalc_shift(struct clk *clk)
 225 {
 226         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
 227         unsigned long rate = clk->parent->rate >> shift;
 228         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 229         return rate;
 230 }
 231
 232
 233 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 234 {
 235         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
 236         unsigned long rate = clk->parent->rate >> shift;
 237         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 238         return rate;
 239 }
 240
 241 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 242 {
 243         unsigned long rate = clk->parent->rate;
 244         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 245         return rate;
 246 }
 247 /********************************set div rate***********************************/
 248
 249 //for free div
 250 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 251 {
 252         u32 div;
 253         for (div = 0; div < clk->div_max; div++) {
 254                 u32 new_rate = clk->parent->rate / (div + 1);
 255                 if (new_rate <= rate) {
 256                         set_cru_bits_w_msk(div,clk->div_mask,clk->div_shift,clk->clksel_con);
 257                         //clk->rate = new_rate;
 258                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 259                         return 0;
 260                 }
 261         }
 262         return -ENOENT;
 263 }
 264
 265 //for div 1 2 4 2^n
 266 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 267 {
 268         u32 shift;
 269         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 270                 u32 new_rate = clk->parent->rate >> shift;
 271                 if (new_rate <= rate) {
 272                         set_cru_bits_w_msk(shift,clk->div_mask,clk->div_shift,clk->clksel_con);
 273                         clk->rate = new_rate;
 274                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 275                         return 0;
 276                 }
 277         }
 278         return -ENOENT;
 279 }
 280
 281 //for div 2 4 2^n
 282 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 283 {
 284         u32 shift;
 285
 286         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 287                 u32 new_rate = clk->parent->rate >> shift;
 288                 if (new_rate <= rate) {
 289                         set_cru_bits_w_msk(shift-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 290                         clk->rate = new_rate;
 291                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 292                         return 0;
 293                 }
 294         }
 295         return -ENOENT;
 296 }
 297 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate ,u32 div_max)
 298 {
 299         u32 div;
 300         unsigned long new_rate;
 301         for (div = 0; div <div_max; div++) {
 302                 new_rate = rate / (div + 1);
 303                 if (new_rate <= rate_out) {
 304                         return div+1;
 305                 }
 306         }
 307         return div_max?div_max:1;
 308 }
 309 struct clk *get_freediv_parents_div(struct clk *clk,unsigned long rate,u32 *div_out)
 310 {
 311         u32 div[2]={0,0};
 312         unsigned long new_rate[2]={0,0};
 313         u32 i;
 314
 315         if(clk->rate==rate)
 316                 return clk->parent;
 317         for(i=0;i<2;i++)
 318         {
 319                 div[i]=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
 320                 new_rate[i] = clk->parents[i]->rate/div[i];
 321                 if(new_rate[i]==rate)
 322                 {
 323                         *div_out=div[i];
 324                         return clk->parents[i];
 325                 }
 326         }
 327         if(new_rate[0]<new_rate[1])
 328                 i=1;
 329         else
 330                 i=0;
 331         *div_out=div[i];
 332         return clk->parents[i];
 333 }
 334
 335 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 336 {
 337         struct clk *p_clk;
 338         u32 div,old_div;
 339         int ret=0;
 340         if(clk->rate==rate)
 341                 return 0;
 342         p_clk=get_freediv_parents_div(clk,rate,&div);
 343
 344         if(!p_clk)
 345                 return -ENOENT;
 346
 347         CRU_PRINTK_DBG("%s %lu,form %s\n",clk->name,rate,p_clk->name);
 348         if (clk->parent != p_clk)
 349         {
 350                 old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),clk->div_shift,clk->div_mask)+1;
 351
 352                 if(div>old_div)
 353                 {
 354                         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 355                 }
 356                 ret=clk_set_parent_nolock(clk,p_clk);
 357                 if(ret)
 358                 {
 359                         CRU_PRINTK_ERR("%s can't set %lu,reparent err\n",clk->name,rate);
 360                         return -ENOENT;
 361                 }
 362         }
 363         //set div
 364         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 365         return 0;
 366 }
 367
 368 //rate==div rate //hdmi
 369 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 370 {
 371         struct clk *p_clk;
 372         u32 div,old_div;
 373         int ret;
 374         p_clk=get_freediv_parents_div(clk,rate,&div);
 375
 376         if(!p_clk)
 377         return -ENOENT;
 378
 379         if((p_clk->rate/div)!=rate||(p_clk->rate%div))
 380         return -ENOENT;
 381
 382         if (clk->parent != p_clk)
 383         {
 384                 old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
 385                                                                         clk->div_shift,clk->div_mask)+1;
 386                 if(div>old_div)
 387                 {
 388                         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 389                 }
 390                 ret=clk_set_parent_nolock(clk,p_clk);
 391                 if (ret)
 392                 {
 393                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
 394                         return ret;
 395                 }
 396         }
 397         //set div
 398         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 399         return 0;
 400 }
 401
 402 /***************************round********************************/
 403
 404 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 405 {
 406         return clk->parent->rate/clk_get_freediv(rate,clk->parent->rate,clk->div_max);
 407 }
 408
 409 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 410 {
 411         u32 div;
 412         struct clk *p_clk;
 413         if(clk->rate == rate)
 414                 return clk->rate;
 415         p_clk=get_freediv_parents_div(clk,rate,&div);
 416         if(!p_clk)
 417                 return 0;
 418         return p_clk->rate/div;
 419 }
 420
 421 /**************************************others seting************************************/
 422
 423 static struct clk* clksel_get_parent(struct clk *clk)
 424 {
 425         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 426 }
 427 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 428 {
 429         u32 i;
 430         if (unlikely(!clk->parents))
 431                 return -EINVAL;
 432         for (i = 0; (i <clk->parents_num); i++) {
 433                 if (clk->parents[i]!= parent)
 434                         continue;
 435                 set_cru_bits_w_msk(i,clk->src_mask,clk->src_shift,clk->clksel_con);
 436                 return 0;
 437         }
 438         return -EINVAL;
 439 }
 440
 441 static int gate_mode(struct clk *clk, int on)
 442 {
 443         int idx = clk->gate_idx;
 444         if (idx >= CLK_GATE_MAX)
 445                 return -EINVAL;
 446         if(on)
 447         {
 448                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 449                 //CRU_PRINTK_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 450                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 451         }
 452         else
 453         {
 454                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 455         //      CRU_PRINTK_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 456                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 457         }
 458         return 0;
 459 }
 460 /*****************************frac set******************************************/
 461
 462 static unsigned long clksel_recalc_frac(struct clk *clk)
 463 {
 464         unsigned long rate;
 465         u64 rate64;
 466         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 467         if (r == 0) // FPGA ?
 468                 return clk->parent->rate;
 469         numerator = r >> 16;
 470         denominator = r & 0xFFFF;
 471         rate64 = (u64)clk->parent->rate * numerator;
 472         do_div(rate64, denominator);
 473         rate = rate64;
 474         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 475         return rate;
 476 }
 477
 478 static u32 clk_gcd(u32 numerator, u32 denominator)
 479 {
 480         u32 a, b;
 481
 482         if (!numerator || !denominator)
 483                 return 0;
 484         if (numerator > denominator) {
 485                 a = numerator;
 486                 b = denominator;
 487         } else {
 488                 a = denominator;
 489                 b = numerator;
 490         }
 491         while (b != 0) {
 492                 int r = b;
 493                 b = a % b;
 494                 a = r;
 495         }
 496
 497         return a;
 498 }
 499
 500 static int frac_div_get_seting(unsigned long rate_out,unsigned long rate,
 501         u32 *numerator,u32 *denominator)
 502 {
 503         u32 gcd_vl;
 504         gcd_vl = clk_gcd(rate, rate_out);
 505         CRU_PRINTK_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n",rate_out,rate, gcd_vl);
 506
 507         if (!gcd_vl) {
 508                 CRU_PRINTK_ERR("gcd=0, i2s frac div is not be supported\n");
 509                 return -ENOENT;
 510         }
 511
 512         *numerator = rate_out / gcd_vl;
 513         *denominator = rate/ gcd_vl;
 514
 515         CRU_PRINTK_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 516                         *numerator, *denominator, *denominator / *numerator);
 517
 518         if (*numerator > 0xffff || *denominator > 0xffff||
 519                 (*denominator/(*numerator))<20) {
 520                 CRU_PRINTK_ERR("can't get a available nume and deno\n");
 521                 return -ENOENT;
 522         }
 523
 524         return 0;
 525
 526 }
 527 /* *********************pll **************************/
 528
 529 #define rk30_clock_udelay(a) udelay(a);
 530
 531 /*********************pll lock status**********************************/
 532 //#define GRF_SOC_CON0       0x15c
 533 static void pll_wait_lock(int pll_idx)
 534 {
 535         u32 pll_state[4]={1,0,2,3};
 536         u32 bit = 0x10u << pll_state[pll_idx];
 537         int delay = 24000000;
 538         while (delay > 0) {
 539                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 540                         break;
 541                 delay--;
 542         }
 543         if (delay == 0) {
 544                 CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
 545                 while(1);
 546         }
 547 }
 548
 549
 550
 551 /***************************pll function**********************************/
 552 static unsigned long pll_clk_recalc(u32 pll_id,unsigned long parent_rate)
 553 {
 554         unsigned long rate;
 555
 556         if (PLLS_IN_NORM(pll_id)) {
 557                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id,0));
 558                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id,1));
 559
 560
 561                 u64 rate64 = (u64)parent_rate*PLL_NF(pll_con1);
 562
 563                 /*
 564                 CRU_PRINTK_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 565                         ,PLL_CONS(pll_id,1),pll_con1, rate64);
 566                 */
 567
 568
 569                 //CRU_PRINTK_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 570         //CRU_PRINTK_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 571                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 572
 573                 do_div(rate64, PLL_NR(pll_con0));
 574                 do_div(rate64, PLL_NO(pll_con0));
 575
 576                 rate = rate64;
 577                 /*
 578                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 579                         pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 580                 */
 581         } else {
 582                 rate = parent_rate;
 583                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n",pll_id,rate);
 584         }
 585         return rate;
 586 }
 587 static unsigned long plls_clk_recalc(struct clk *clk)
 588 {
 589         return pll_clk_recalc(clk->pll->id,clk->parent->rate);
 590 }
 591
 592 static int pll_clk_set_rate(struct pll_clk_set *clk_set,u8 pll_id)
 593 {
 594         //enter slowmode
 595         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 596         //enter rest
 597         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 598         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id,0));
 599         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id,1));
 600         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2));
 601         rk30_clock_udelay(5);
 602
 603         //return form rest
 604         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 605
 606         //wating lock state
 607         rk30_clock_udelay(clk_set->rst_dly);
 608         pll_wait_lock(pll_id);
 609
 610         //return form slow
 611         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 612
 613         /*
 614         CRU_PRINTK_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 615                 cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 616         */
 617
 618
 619         return 0;
 620 }
 621 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 622 {
 623         struct _pll_data *pll_data=c->pll;
 624         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 625
 626         while(clk_set->rate)
 627         {
 628                 if (clk_set->rate == rate) {
 629                         break;
 630                 }
 631                 clk_set++;
 632         }
 633         if(clk_set->rate== rate)
 634         {
 635                 pll_clk_set_rate(clk_set,pll_data->id);
 636                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 637         }
 638         else
 639         {
 640                 CRU_PRINTK_ERR("gpll is no corresponding rate=%lu\n", rate);
 641                 return -1;
 642         }
 643         return 0;
 644 }
 645
 646 #define PLL_FREF_MIN (183*KHZ)
 647 #define PLL_FREF_MAX (1500*MHZ)
 648
 649 #define PLL_FVCO_MIN (300*MHZ)
 650 #define PLL_FVCO_MAX (1500*MHZ)
 651
 652 #define PLL_FOUT_MIN (18750*KHZ)
 653 #define PLL_FOUT_MAX (1500*MHZ)
 654
 655 #define PLL_NF_MAX (4096)
 656 #define PLL_NR_MAX (64)
 657 #define PLL_NO_MAX (16)
 658
 659 static int pll_clk_get_set(unsigned long fin_hz,unsigned long fout_hz,u32 *clk_nr,u32 *clk_nf,u32 *clk_no)
 660 {
 661         u32 nr,nf,no,nonr;
 662         u32 n;
 663         u32 YFfenzi;
 664         u32 YFfenmu;
 665         unsigned long fref,fvco,fout;
 666         u32 gcd_val=0;
 667
 668         CRU_PRINTK_DBG("pll_clk_get_set fin=%lu,fout=%lu\n",fin_hz,fout_hz);
 669         if(!fin_hz||!fout_hz||fout_hz==fin_hz)
 670                 return 0;
 671         gcd_val=clk_gcd(fin_hz,fout_hz);
 672         YFfenzi=fout_hz/gcd_val;
 673         YFfenmu=fin_hz/gcd_val;
 674
 675         for(n=1;;n++)
 676         {
 677                 nf=YFfenzi*n;
 678                 nonr=YFfenmu*n;
 679                 if(nf>PLL_NF_MAX||nonr>(PLL_NO_MAX*PLL_NR_MAX))
 680                  break;
 681                 for(no=1;no<=PLL_NO_MAX;no++)
 682                 {
 683                         if(!(no==1||!(no%2)))
 684                                 continue;
 685
 686                         if(nonr%no)
 687                                 continue;
 688                         nr=nonr/no;
 689
 690                         if(nr>PLL_NR_MAX)//PLL_NR_MAX
 691                                 continue;
 692
 693                         fref=fin_hz/nr;
 694                         if(fref<PLL_FREF_MIN||fref>PLL_FREF_MAX)
 695                                 continue;
 696
 697                         fvco=(fin_hz/nr)*nf;
 698                         if(fvco<PLL_FVCO_MIN||fvco>PLL_FVCO_MAX)
 699                                 continue;
 700                         fout=fvco/no;
 701                         if(fout<PLL_FOUT_MIN||fout>PLL_FOUT_MAX)
 702                                 continue;
 703                         *clk_nr=nr;
 704                         *clk_no=no;
 705                         *clk_nf=nf;
 706                         return 1;
 707
 708                 }
 709
 710         }
 711         return 0;
 712 }
 713
 714 static int pll_clk_mode(struct clk *clk, int on)
 715 {
 716         u8 pll_id=clk->pll->id;
 717         u32 nr=PLL_NR(cru_readl(PLL_CONS(pll_id,0)));
 718         u32 dly= (nr*500)/24+1;
 719         CRU_PRINTK_DBG("pll_mode %s(%d)",clk->name,on);
 720         if (on) {
 721                 cru_writel(PLL_PWR_ON|PLL_PWR_DN_W_MSK,PLL_CONS(pll_id,3));
 722                 rk30_clock_udelay(dly);
 723                 pll_wait_lock(pll_id);
 724                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 725         } else {
 726                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 727                 cru_writel(PLL_PWR_DN|PLL_PWR_DN_W_MSK, PLL_CONS(pll_id,3));
 728         }
 729         return 0;
 730 }
 731
 732 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 733 {
 734         struct _pll_data *pll_data=c->pll;
 735         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 736         struct pll_clk_set temp_clk_set;
 737         u32 clk_nr,clk_nf,clk_no;
 738
 739
 740         while(clk_set->rate)
 741         {
 742                 if (clk_set->rate == rate) {
 743                         break;
 744                 }
 745                 clk_set++;
 746         }
 747         if(clk_set->rate==rate)
 748         {
 749                 CRU_PRINTK_DBG("cpll get a rate\n");
 750                 pll_clk_set_rate(clk_set,pll_data->id);
 751
 752         }
 753         else
 754         {
 755                 CRU_PRINTK_DBG("cpll get auto calc a rate\n");
 756                 if(pll_clk_get_set(c->parent->rate,rate,&clk_nr,&clk_nf,&clk_no)==0)
 757                 {
 758                         pr_err("cpll auto set rate error\n");
 759                         return -ENOENT;
 760                 }
 761                 CRU_PRINTK_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n",clk_nr,clk_nf,clk_no);
 762                 temp_clk_set.pllcon0=PLL_CLKR_SET(clk_nr)|PLL_CLKOD_SET(clk_no);
 763                 temp_clk_set.pllcon1=PLL_CLKF_SET(clk_nf);
 764                 temp_clk_set.pllcon2=PLL_CLK_BWADJ_SET(clk_nf/2-1);
 765                 temp_clk_set.rst_dly=(clk_nr*500)/24+1;
 766                 pll_clk_set_rate(&temp_clk_set,pll_data->id);
 767
 768         }
 769         return 0;
 770 }
 771
 772
 773 /* ******************fixed input clk ***********************************************/
 774 static struct clk xin24m = {
 775         .name           = "xin24m",
 776         .rate           = 24 * MHZ,
 777         .flags          = RATE_FIXED,
 778 };
 779 static struct clk xin27m = {
 780         .name           = "xin27m",
 781         .rate           = 27 * MHZ,
 782         //CLK_GATE_XIN27M
 783         .flags          = RATE_FIXED,
 784
 785 };
 786 static struct clk clk_12m = {
 787         .name           = "clk_12m",
 788         .parent         =&xin24m,
 789         .rate           = 12 * MHZ,
 790         .flags          = RATE_FIXED,
 791 };
 792
 793 /************************************pll func***************************/
 794 static const struct apll_clk_set* arm_pll_clk_get_best_pll_set(unsigned long rate,
 795         struct apll_clk_set *tables)
 796 {
 797         const struct apll_clk_set *ps, *pt;
 798
 799         /* find the arm_pll we want. */
 800         ps = pt = tables;
 801         while (pt->rate) {
 802                 if (pt->rate == rate) {
 803                         ps = pt;
 804                         break;
 805                 }
 806                 // we are sorted, and ps->rate > pt->rate.
 807                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 808                         ps = pt;
 809                 if (pt->rate < rate)
 810                         break;
 811                 pt++;
 812         }
 813         //CRU_PRINTK_DBG("arm pll best rate=%lu\n",ps->rate);
 814         return ps;
 815 }
 816 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 817 {
 818         return arm_pll_clk_get_best_pll_set(rate,clk->pll->table)->rate;
 819 }
 820 #if 1
 821 struct arm_clks_div_set {
 822         u32 rate;
 823         u32     clksel0;
 824         u32     clksel1;
 825 };
 826
 827 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 828         { \
 829         .rate    =_mhz,\
 830         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 831         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 832         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 833         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 834         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 835 }
 836 struct arm_clks_div_set arm_clk_div_tlb[]={
 837         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 838         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 839         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 840         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 841         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
 842         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
 843         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
 844 };
 845 struct arm_clks_div_set * arm_clks_get_div(u32 rate)
 846 {
 847         int i=0;
 848         for(i=0;arm_clk_div_tlb[i].rate!=0;i++)
 849         {
 850                 if(arm_clk_div_tlb[i].rate>=rate)
 851                         return &arm_clk_div_tlb[i];
 852         }
 853         return NULL;
 854 }
 855
 856 #endif
 857
 858 u32 force_cpu_hpclk_11(u32 clksel1)
 859 {
 860         u8 p_bits=(clksel1&ACLK_PCLK_MSK)>>ACLK_PCLK_OFF;
 861         if(p_bits<3)
 862         {
 863                 return ((clksel1&(~(ACLK_HCLK_MSK|AHB2APB_MSK)))|AHB2APB_11|(p_bits<<ACLK_HCLK_OFF));
 864         }
 865         else
 866         {
 867                 return clksel1;
 868         }
 869
 870 }
 871 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 872 {
 873         unsigned long flags;
 874         const struct apll_clk_set *ps;
 875         u32 pll_id=clk->pll->id;
 876         u32 temp_div;
 877         u32 old_aclk_div=0,new_aclk_div,gpll_arm_aclk_div;
 878         struct arm_clks_div_set *temp_clk_div;
 879         unsigned long arm_gpll_rate, arm_gpll_lpj;
 880         u32 ps_clksel1;
 881
 882         ps = arm_pll_clk_get_best_pll_set(rate,(struct apll_clk_set *)clk->pll->table);
 883
 884         old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
 885         new_aclk_div=GET_CORE_ACLK_VAL(ps->clksel1&CORE_ACLK_MSK);
 886
 887         CRU_PRINTK_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
 888                 ps->rate,ps->pllcon0,ps->pllcon1,ps->pllcon2,ps->clksel0,ps->clksel1);
 889
 890         //rk30_l2_cache_latency(ps->rate/MHZ);
 891
 892         if(general_pll_clk.rate>clk->rate)
 893         {
 894                 temp_div=clk_get_freediv(clk->rate,general_pll_clk.rate,10);
 895         }
 896         else
 897         {
 898                 temp_div=1;
 899         }
 900         //sel gpll
 901         //cru_writel(CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 902
 903         arm_gpll_rate=general_pll_clk.rate/temp_div;
 904         arm_gpll_lpj = lpj_gpll / temp_div;
 905         temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
 906         if(!temp_clk_div)
 907                 temp_clk_div=&arm_clk_div_tlb[4];
 908         if(rk30_clock_flags&CLK_CPU_HPCLK_11)
 909         {
 910                 temp_clk_div->clksel1=force_cpu_hpclk_11(temp_clk_div->clksel1);
 911         }
 912
 913         gpll_arm_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
 914
 915         CRU_PRINTK_LOG("gpll_arm_rate=%lu,sel rate%u,sel0%x,sel1%x\n",arm_gpll_rate,temp_clk_div->rate,
 916                                         temp_clk_div->clksel0,temp_clk_div->clksel1);
 917
 918         local_irq_save(flags);
 919         //new div max first
 920         if(gpll_arm_aclk_div>=old_aclk_div)
 921         {
 922                 if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
 923                 {
 924                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 925                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 926                         cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
 927                                                                                                 CRU_CLKSELS_CON(0));
 928                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 929                 }
 930                 else
 931                 {
 932                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 933                         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
 934                                                                                 CRU_CLKSELS_CON(0));
 935                 }
 936         }
 937         // open gpu gpll path
 938         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 939         cru_writel(CORE_SEL_GPLL|CORE_SEL_PLL_W_MSK, CRU_CLKSELS_CON(0));
 940         loops_per_jiffy = arm_gpll_lpj;
 941         smp_wmb();
 942         //new div max late
 943         if(gpll_arm_aclk_div<old_aclk_div)
 944         {
 945                 if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
 946                 {
 947                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 948                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 949                         cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
 950                                                                                                 CRU_CLKSELS_CON(0));
 951                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 952                 }
 953                 else
 954                 {
 955                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 956                         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
 957                                                                                 CRU_CLKSELS_CON(0));
 958                 }
 959         }
 960
 961         /*if core src don't select gpll ,apll neet to enter slow mode */
 962         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 963
 964         //enter rest
 965         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 966         cru_writel(ps->pllcon0, PLL_CONS(pll_id,0));
 967         cru_writel(ps->pllcon1, PLL_CONS(pll_id,1));
 968         cru_writel(ps->pllcon2, PLL_CONS(pll_id,2));
 969
 970         rk30_clock_udelay(5);
 971
 972         //return form rest
 973         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 974
 975         //wating lock state
 976         ///rk30_clock_udelay(ps->rst_dly);//lcdc flash
 977
 978         pll_wait_lock(pll_id);
 979
 980         if(rk30_clock_flags&CLK_CPU_HPCLK_11)
 981         {
 982                 ps_clksel1=force_cpu_hpclk_11(ps->clksel1);
 983         }
 984         else
 985         {
 986                 ps_clksel1=ps->clksel1;
 987         }
 988         //return form slow
 989         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 990         //a/h/p clk sel
 991    if(new_aclk_div>=gpll_arm_aclk_div)
 992    {
 993                 if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
 994                 {
 995                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 996                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
 997                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 998                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 999                 }
1000                 else
1001                 {
1002                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
1003                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
1004                 }
1005         }
1006
1007         //reparent to apll
1008         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1009         loops_per_jiffy = ps->lpj;
1010         smp_wmb();
1011
1012    if(new_aclk_div<gpll_arm_aclk_div)
1013    {
1014                 if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
1015                 {
1016                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1017                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
1018                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
1019                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1020                 }
1021                 else
1022                 {
1023                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
1024                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
1025                 }
1026         }
1027         //CRU_PRINTK_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1028
1029         local_irq_restore(flags);
1030
1031         //gate gpll path
1032         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1033         , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1034
1035         CRU_PRINTK_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n",cru_readl(PLL_CONS(pll_id,0)),
1036                 cru_readl(PLL_CONS(pll_id,1)),cru_readl(PLL_CONS(pll_id,2)),
1037                 cru_readl(PLL_CONS(pll_id,3)),cru_readl(CRU_CLKSELS_CON(0)),
1038                 cru_readl(CRU_CLKSELS_CON(1)));
1039         return 0;
1040 }
1041
1042
1043 /************************************pll clocks***************************/
1044
1045 static const struct apll_clk_set apll_clks[] = {
1046         //rate, nr ,nf ,no,core_div,peri,axi,hclk,pclk,_ahb2apb
1047         //_APLL_SET_CLKS(1800, 1, 75, 1, 8, 41,  41,  81,21),
1048         //_APLL_SET_CLKS(1752, 1, 73, 1, 8, 41,  41,  81,21),
1049         //_APLL_SET_CLKS(1704, 1, 71, 1, 8, 41,  41,  81,21),
1050         //_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41,  41,  81,21),
1051         _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 21, 41, 21),
1052         _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 21, 41, 21),
1053         _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 21, 41, 21),
1054         _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 21, 41, 21),
1055         _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 21, 41, 21),
1056         _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 21, 41, 21),
1057         _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 21, 41, 21),
1058         _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 21, 41, 21),
1059         _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 21, 41, 21),
1060         _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 21, 41, 21),
1061         _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 21, 41, 21),
1062         _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 21, 41, 21),
1063         _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 21, 41, 21),
1064         _APLL_SET_CLKS(1008, 1, 42, 1, 8, 31, 21, 41, 21),
1065         _APLL_SET_CLKS(888,  1, 37, 1, 8, 31, 21, 41, 21),
1066         _APLL_SET_CLKS(816 , 1, 34, 1, 8, 31, 21, 41, 21),
1067         _APLL_SET_CLKS(792 , 1, 33, 1, 8, 31, 21, 41, 21),
1068         _APLL_SET_CLKS(696 , 1, 29, 1, 8, 31, 21, 41, 21),
1069         _APLL_SET_CLKS(600 , 1, 25, 1, 4, 31, 21, 41, 21),
1070         _APLL_SET_CLKS(504 , 1, 21, 1, 4, 21, 21, 41, 21),
1071         _APLL_SET_CLKS(408 , 1, 17, 1, 4, 21, 21, 41, 21),
1072         _APLL_SET_CLKS(312 , 1, 13, 1, 2, 21, 21, 21, 11),
1073         _APLL_SET_CLKS(252 , 1, 21, 2, 2, 21, 21, 21, 11),
1074         _APLL_SET_CLKS(216 , 1, 18, 2, 2, 21, 21, 21, 11),
1075         _APLL_SET_CLKS(126 , 1, 21, 4, 2, 21, 11, 11, 11),
1076         _APLL_SET_CLKS(48  , 1, 16, 8, 2, 11, 11, 11, 11),
1077         _APLL_SET_CLKS(0   , 1, 21, 4, 2, 21, 21, 41, 21),
1078
1079 };
1080 static struct _pll_data apll_data=SET_PLL_DATA(APLL_ID,(void *)apll_clks);
1081 static struct clk arm_pll_clk ={
1082         .name           = "arm_pll",
1083         .parent         = &xin24m,
1084         .mode = pll_clk_mode,
1085         .recalc         = plls_clk_recalc,
1086         .set_rate       = arm_pll_clk_set_rate,
1087         .round_rate     = arm_pll_clk_round_rate,
1088         .pll=&apll_data,
1089  };
1090
1091 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1092 {
1093         /* do nothing here */
1094         return 0;
1095 }
1096 static struct _pll_data dpll_data=SET_PLL_DATA(DPLL_ID,NULL);
1097 static struct clk ddr_pll_clk = {
1098         .name           = "ddr_pll",
1099         .parent         = &xin24m,
1100         .recalc         = plls_clk_recalc,
1101         .set_rate       = ddr_pll_clk_set_rate,
1102         .pll=&dpll_data,
1103 };
1104
1105 static const struct pll_clk_set cpll_clks[] = {
1106         _PLL_SET_CLKS(360000, 1,  15, 1),
1107         _PLL_SET_CLKS(408000, 1,  17, 1),
1108         _PLL_SET_CLKS(456000, 1,  19, 1),
1109         _PLL_SET_CLKS(504000, 1,  21, 1),
1110         _PLL_SET_CLKS(552000, 1,  23, 1),
1111         _PLL_SET_CLKS(600000, 1,  25, 1),
1112         _PLL_SET_CLKS(742500, 8,  495, 2),
1113         _PLL_SET_CLKS(768000, 1,  32, 1),
1114         _PLL_SET_CLKS(798000, 4,  133, 1),
1115         _PLL_SET_CLKS(1188000,2,  99,   1),
1116         _PLL_SET_CLKS(     0, 4,  133, 1),
1117 };
1118 static struct _pll_data cpll_data=SET_PLL_DATA(CPLL_ID,(void *)cpll_clks);
1119 static struct clk codec_pll_clk = {
1120         .name           = "codec_pll",
1121         .parent         = &xin24m,
1122         .mode           = pll_clk_mode,
1123         .recalc         = plls_clk_recalc,
1124         .set_rate       = cpll_clk_set_rate,
1125         .pll= &cpll_data,
1126 };
1127
1128 static const struct pll_clk_set gpll_clks[] = {
1129         _PLL_SET_CLKS(148500,   4,      99,     4),
1130         _PLL_SET_CLKS(297000,   2,      99,     4),
1131         _PLL_SET_CLKS(300000,   1,      25,     2),
1132         _PLL_SET_CLKS(1188000,  2,      99,     1),
1133         _PLL_SET_CLKS(0,        0,       0,     0),
1134 };
1135 static struct _pll_data gpll_data=SET_PLL_DATA(GPLL_ID,(void *)gpll_clks);
1136 static struct clk general_pll_clk = {
1137         .name           = "general_pll",
1138         .parent         = &xin24m,
1139         .recalc         = plls_clk_recalc,
1140         .set_rate       = gpll_clk_set_rate,
1141         .pll= &gpll_data
1142 };
1143 /********************************clocks***********************************/
1144 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1145 {
1146         return 0;
1147 }
1148
1149 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1150 {
1151         return ddr_set_pll(rate/MHZ,0)*MHZ;
1152 }
1153 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1154 {
1155         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
1156         unsigned long rate = clk->parent->recalc(clk->parent)>> shift;
1157         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1158         return rate;
1159 }
1160 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
1161 static struct clk clk_ddr = {
1162         .name           = "ddr",
1163         .parent         = &ddr_pll_clk,
1164         .recalc         = ddr_clk_recalc_rate,
1165         .set_rate       = ddr_clk_set_rate,
1166         .round_rate     = ddr_clk_round_rate,
1167         .clksel_con     = CRU_CLKSELS_CON(26),
1168         //CRU_DIV_SET(0x3,0,4),
1169         //CRU_SRC_SET(1,8),
1170         //CRU_PARENTS_SET(clk_ddr_parents),
1171 };
1172 static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
1173 {
1174         int ret;
1175         //set arm pll div 1
1176         //set_cru_bits_w_msk(0,c->div_mask,c->div_shift,c->clksel_con);
1177
1178         ret = clk_set_rate_nolock(c->parent, rate);
1179         if (ret) {
1180                 CRU_PRINTK_ERR("Failed to change clk pll %s to %lu\n",c->name,rate);
1181                 return ret;
1182         }
1183         return 0;
1184 }
1185 static unsigned long arm_core_clk_get_rate(struct clk *c)
1186 {
1187         u32 div=(get_cru_bits(c->clksel_con,c->div_mask,c->div_shift)+1);
1188         //c->parent->rate=c->parent->recalc(c->parent);
1189         return c->parent->rate/div;
1190 }
1191 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1192 {
1193         u32 div=(get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1);
1194         return clk_round_rate_nolock(clk->parent,rate)/div;
1195 }
1196
1197 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1198 {
1199
1200         u32 temp_div;
1201         struct clk *old_prt;
1202
1203         if(clk->parent==new_prt)
1204                 return 0;
1205         if (unlikely(!clk->parents))
1206                 return -EINVAL;
1207         CRU_PRINTK_DBG("%s,reparent %s\n",clk->name,new_prt->name);
1208         //arm
1209         old_prt=clk->parent;
1210
1211         if(clk->parents[0]==new_prt)
1212         {
1213                 new_prt->set_rate(new_prt,300*MHZ);
1214                 set_cru_bits_w_msk(0,clk->div_mask,clk->div_shift,clk->clksel_con);
1215         }
1216         else if(clk->parents[1]==new_prt)
1217         {
1218
1219                 if(new_prt->rate>old_prt->rate)
1220                 {
1221                         temp_div=clk_get_freediv(old_prt->rate,new_prt->rate,clk->div_max);
1222                         set_cru_bits_w_msk(temp_div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
1223                 }
1224                 set_cru_bits_w_msk(1,clk->src_mask,clk->src_shift,clk->clksel_con);
1225                 new_prt->set_rate(new_prt,300*MHZ);
1226         }
1227         else
1228                 return -1;
1229
1230
1231         return 0;
1232
1233 }
1234
1235 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1236 {
1237         unsigned long flags;
1238         u32 pll_id=APLL_ID;
1239         u32 temp_div;
1240         u32 old_aclk_div=0,new_aclk_div;
1241         struct arm_clks_div_set *temp_clk_div;
1242         unsigned long arm_gpll_rate, arm_gpll_lpj;
1243         temp_div=clk_get_freediv(rate,c->parent->rate,c->div_max);
1244         arm_gpll_rate=c->parent->rate/temp_div;
1245
1246         temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
1247         if(!temp_clk_div)
1248                 temp_clk_div=&arm_clk_div_tlb[4];
1249
1250         old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1251         new_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
1252         if(c->rate>=rate)
1253         {
1254                 arm_gpll_lpj = lpj_gpll / temp_div;
1255                 set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
1256         }
1257
1258         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1259         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
1260                                                                 CRU_CLKSELS_CON(0));
1261         if((c->rate<rate))
1262         {
1263                 arm_gpll_lpj = lpj_gpll / temp_div;
1264                 set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
1265         }
1266         return 0;
1267 }
1268 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1269 {
1270         return c->parent->rate;
1271 }
1272
1273 static struct clk clk_cpu_gpll_path = {
1274         .name   =  "cpu_gpll_path",
1275         .parent =  &general_pll_clk,
1276         .recalc =  arm_core_gpll_clk_get_rate,
1277         .set_rate = core_gpll_clk_set_rate,
1278         CRU_DIV_SET(0x1f,0,32),
1279         CRU_GATE_MODE_SET(gate_mode,CLK_GATE_CPU_GPLL_PATH),
1280 };
1281
1282
1283 static struct clk *clk_cpu_parents[2] = {&arm_pll_clk,&clk_cpu_gpll_path};
1284
1285 static struct clk clk_cpu = {
1286         .name   =  "cpu",
1287         .parent =  &arm_pll_clk,
1288         .set_rate =     arm_core_clk_set_rate,
1289         .recalc =  arm_core_clk_get_rate,
1290         .round_rate     = core_clk_round_rate,
1291         .set_parent = core_clksel_set_parent,
1292         .clksel_con     = CRU_CLKSELS_CON(0),
1293         CRU_DIV_SET(0x1f,0,32),
1294         CRU_SRC_SET(1,8),
1295         CRU_PARENTS_SET(clk_cpu_parents),
1296 };
1297 static unsigned long aclk_cpu_recalc(struct clk *clk)
1298 {
1299         unsigned long rate;
1300         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
1301
1302         BUG_ON(div > 5);
1303         if (div >= 5)
1304                 div = 8;
1305         rate = clk->parent->rate / div;
1306         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1307
1308         return rate;
1309 };
1310 static struct clk core_periph = {
1311         .name           = "core_periph",
1312         .parent         = &clk_cpu,
1313         .recalc         = clksel_recalc_shift_2,
1314         .clksel_con     = CRU_CLKSELS_CON(0),
1315         CRU_DIV_SET(0x3,6,16),
1316 };
1317
1318 static struct clk aclk_cpu = {
1319         .name           = "aclk_cpu",
1320         .parent         = &clk_cpu,
1321         .recalc         = aclk_cpu_recalc,
1322         .clksel_con     = CRU_CLKSELS_CON(1),
1323         CRU_DIV_SET(0x7,0,8),
1324 };
1325
1326 static struct clk hclk_cpu = {
1327         .name           = "hclk_cpu",
1328         .parent         = &aclk_cpu,
1329         .recalc         = clksel_recalc_shift,
1330         //.set_rate     = clksel_set_rate_shift,
1331         .clksel_con     = CRU_CLKSELS_CON(1),
1332         CRU_DIV_SET(0x3,8,4),
1333
1334 };
1335
1336 static struct clk pclk_cpu = {
1337         .name           = "pclk_cpu",
1338         .parent         = &aclk_cpu,
1339         .recalc         = clksel_recalc_shift,
1340         //.set_rate     = clksel_set_rate_shift,
1341         .clksel_con     = CRU_CLKSELS_CON(1),
1342         CRU_DIV_SET(0x3,12,8),
1343 };
1344 static struct clk ahb2apb_cpu = {
1345         .name           = "ahb2apb",
1346         .parent         = &hclk_cpu,
1347         .recalc         = clksel_recalc_shift,
1348         .clksel_con     = CRU_CLKSELS_CON(1),
1349         CRU_DIV_SET(0x3,14,4),
1350 };
1351
1352
1353 static struct clk atclk_cpu = {
1354         .name           = "atclk_cpu",
1355         .parent         = &pclk_cpu,
1356 };
1357
1358 static struct clk *clk_i2s_div_parents[]={&general_pll_clk,&codec_pll_clk};
1359 static struct clk clk_i2s_pll = {
1360         .name           = "i2s_pll",
1361         .parent         = &general_pll_clk,
1362         .clksel_con     = CRU_CLKSELS_CON(2),
1363         CRU_SRC_SET(0x1,16),
1364         CRU_PARENTS_SET(clk_i2s_div_parents),
1365 };
1366
1367 static struct clk clk_i2s0_div = {
1368         .name           = "i2s0_div",
1369         .parent = &clk_i2s_pll,
1370         .mode           = gate_mode,
1371         .recalc         = clksel_recalc_div,
1372         .set_rate       = clksel_set_rate_freediv,
1373         .round_rate     =clksel_freediv_round_rate,
1374         .gate_idx       = CLK_GATE_I2S0,
1375         .clksel_con     = CRU_CLKSELS_CON(2),
1376         CRU_DIV_SET(0x7f,0,64),
1377 };
1378
1379 static struct clk clk_i2s1_div = {
1380         .name           = "i2s1_div",
1381         .parent = &clk_i2s_pll,
1382         .recalc         = clksel_recalc_div,
1383         .set_rate       = clksel_set_rate_freediv,
1384         .round_rate     =clksel_freediv_round_rate,
1385         .mode           = gate_mode,
1386         .gate_idx       = CLK_GATE_I2S1,
1387         .clksel_con     = CRU_CLKSELS_CON(3),
1388         CRU_DIV_SET(0x7f,0,64),
1389 };
1390
1391
1392 static struct clk clk_i2s2_div = {
1393         .name           = "i2s2_div",
1394         .parent = &clk_i2s_pll,
1395         .recalc         = clksel_recalc_div,
1396         .set_rate       = clksel_set_rate_freediv,
1397         .round_rate     =clksel_freediv_round_rate,
1398         .mode           = gate_mode,
1399         .gate_idx       = CLK_GATE_I2S2,
1400         .clksel_con     = CRU_CLKSELS_CON(4),
1401         CRU_DIV_SET(0x7f,0,64),
1402 };
1403 static struct clk clk_spdif_div = {
1404         .name           = "spdif_div",
1405         .parent = &clk_i2s_pll,
1406         .recalc         = clksel_recalc_div,
1407         .set_rate       = clksel_set_rate_freediv,
1408         .round_rate     =clksel_freediv_round_rate,
1409         .mode           = gate_mode,
1410         .gate_idx       = CLK_GATE_SPDIF,
1411         .clksel_con     = CRU_CLKSELS_CON(5),
1412         CRU_DIV_SET(0x7f,0,64),
1413 };
1414 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1415 {
1416         u32 numerator, denominator;
1417         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1418         //clk->parent->parent
1419         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1420                         &numerator,&denominator)==0)
1421         {
1422                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1423                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1424                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1425         }
1426         else
1427         {
1428                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1429                 return -ENOENT;
1430         }
1431         return 0;
1432 }
1433
1434
1435 static struct clk clk_i2s0_frac_div = {
1436         .name           = "i2s0_frac_div",
1437         .parent         = &clk_i2s0_div,
1438         .mode           = gate_mode,
1439         .gate_idx       = CLK_GATE_I2S0_FRAC,
1440         .recalc         = clksel_recalc_frac,
1441         .set_rate       = clk_i2s_fracdiv_set_rate,
1442         .clksel_con     = CRU_CLKSELS_CON(6),
1443 };
1444
1445 static struct clk clk_i2s1_frac_div = {
1446         .name           = "i2s1_frac_div",
1447         .parent         = &clk_i2s1_div,
1448         .mode           = gate_mode,
1449         .gate_idx       = CLK_GATE_I2S1_FRAC,
1450         .recalc         = clksel_recalc_frac,
1451         .set_rate       = clk_i2s_fracdiv_set_rate,
1452         .clksel_con     = CRU_CLKSELS_CON(7),
1453 };
1454
1455 static struct clk clk_i2s2_frac_div = {
1456         .name           = "i2s2_frac_div",
1457         .mode           = gate_mode,
1458         .gate_idx       = CLK_GATE_I2S2_FRAC,
1459         .parent         = &clk_i2s2_div,
1460         .recalc         = clksel_recalc_frac,
1461         .set_rate       = clk_i2s_fracdiv_set_rate,
1462         .clksel_con     = CRU_CLKSELS_CON(8),
1463 };
1464 static struct clk clk_spdif_frac_div = {
1465         .name           = "spdif_frac_div",
1466         .parent         = &clk_spdif_div,
1467         .mode           = gate_mode,
1468         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1469         .recalc         = clksel_recalc_frac,
1470         .set_rate       = clk_i2s_fracdiv_set_rate,
1471         .clksel_con     = CRU_CLKSELS_CON(9),
1472 };
1473
1474 #define I2S_SRC_DIV  (0x0)
1475 #define I2S_SRC_FRAC  (0x1)
1476 #define I2S_SRC_12M  (0x2)
1477
1478 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1479 {
1480         int ret = -EINVAL;
1481         struct clk *parent;
1482
1483         if (rate == clk->parents[I2S_SRC_12M]->rate){
1484                 parent = clk->parents[I2S_SRC_12M];
1485         }else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV],rate)==rate)
1486         {
1487                 parent = clk->parents[I2S_SRC_DIV];
1488         }
1489         else
1490         {
1491                 parent =clk->parents[I2S_SRC_FRAC];
1492         }
1493
1494         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1495                 clk->name,rate,parent->name,clk->parent->name);
1496
1497         if(parent!=clk->parents[I2S_SRC_12M])
1498         {
1499                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
1500                 if (ret)
1501                 {
1502                         CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
1503                         return ret;
1504                 }
1505         }
1506
1507         if (clk->parent != parent)
1508         {
1509                 ret = clk_set_parent_nolock(clk, parent);
1510                 if (ret)
1511                 {
1512                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1513                         return ret;
1514                 }
1515         }
1516
1517         return ret;
1518 };
1519
1520 static struct clk *clk_i2s0_parents[3]={&clk_i2s0_div,&clk_i2s0_frac_div,&clk_12m};
1521
1522 static struct clk clk_i2s0 = {
1523         .name           = "i2s0",
1524         .set_rate       = i2s_set_rate,
1525         .clksel_con     = CRU_CLKSELS_CON(2),
1526         CRU_SRC_SET(0x3,8),
1527         CRU_PARENTS_SET(clk_i2s0_parents),
1528 };
1529
1530 static struct clk *clk_i2s1_parents[3]={&clk_i2s1_div,&clk_i2s1_frac_div,&clk_12m};
1531
1532 static struct clk clk_i2s1 = {
1533         .name           = "i2s1",
1534         .set_rate       = i2s_set_rate,
1535         .clksel_con     = CRU_CLKSELS_CON(3),
1536         CRU_SRC_SET(0x3,8),
1537         CRU_PARENTS_SET(clk_i2s1_parents),
1538 };
1539
1540 static struct clk *clk_i2s2_parents[3]={&clk_i2s2_div,&clk_i2s2_frac_div,&clk_12m};
1541
1542 static struct clk clk_i2s2 = {
1543         .name           = "i2s2",
1544         .set_rate       = i2s_set_rate,
1545         .clksel_con     = CRU_CLKSELS_CON(4),
1546         CRU_SRC_SET(0x3,8),
1547         CRU_PARENTS_SET(clk_i2s2_parents),
1548 };
1549
1550 static struct clk *clk_spdif_parents[3]={&clk_spdif_div,&clk_spdif_frac_div,&clk_12m};
1551
1552 static struct clk clk_spdif = {
1553         .name           = "spdif",
1554         .parent         = &clk_spdif_frac_div,
1555         .set_rate       = i2s_set_rate,
1556         .clksel_con = CRU_CLKSELS_CON(5),
1557         CRU_SRC_SET(0x3,8),
1558         CRU_PARENTS_SET(clk_spdif_parents),
1559 };
1560
1561 static struct clk *aclk_periph_parents[2]={&general_pll_clk,&codec_pll_clk};
1562
1563 static struct clk aclk_periph = {
1564         .name           = "aclk_periph",
1565         .parent         = &general_pll_clk,
1566         .mode           = gate_mode,
1567         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1568         .recalc         = clksel_recalc_div,
1569         .set_rate       = clksel_set_rate_freediv,
1570         .clksel_con     = CRU_CLKSELS_CON(10),
1571         CRU_DIV_SET(0x1f,0,32),
1572         CRU_SRC_SET(1,15),
1573         CRU_PARENTS_SET(aclk_periph_parents),
1574 };
1575 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1576
1577 static struct clk pclk_periph = {
1578         .name           = "pclk_periph",
1579         .parent         = &aclk_periph,
1580         .mode           = gate_mode,
1581         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1582         .recalc         = clksel_recalc_shift,
1583         .set_rate       = clksel_set_rate_shift,
1584         .clksel_con     = CRU_CLKSELS_CON(10),
1585         CRU_DIV_SET(0x3,12,8),
1586 };
1587
1588 static struct clk hclk_periph = {
1589         .name           = "hclk_periph",
1590         .parent         = &aclk_periph,
1591         .mode           = gate_mode,
1592         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1593         .recalc         = clksel_recalc_shift,
1594         .set_rate       = clksel_set_rate_shift,
1595         .clksel_con = CRU_CLKSELS_CON(10),
1596         CRU_DIV_SET(0x3,8,4),
1597 };
1598
1599 static struct clk clk_spi0 = {
1600         .name           = "spi0",
1601         .parent         = &pclk_periph,
1602         .mode           = gate_mode,
1603         .recalc         = clksel_recalc_div,
1604         .set_rate       = clksel_set_rate_freediv,
1605         .gate_idx       = CLK_GATE_SPI0,
1606         .clksel_con     = CRU_CLKSELS_CON(25),
1607         CRU_DIV_SET(0x7f,0,128),
1608 };
1609
1610 static struct clk clk_spi1 = {
1611         .name           = "spi1",
1612         .parent         = &pclk_periph,
1613         .mode           = gate_mode,
1614         .recalc         = clksel_recalc_div,
1615         .set_rate       = clksel_set_rate_freediv,
1616         .gate_idx       = CLK_GATE_SPI1,
1617         .clksel_con     = CRU_CLKSELS_CON(25),
1618         CRU_DIV_SET(0x7f,8,128),
1619 };
1620
1621 static struct clk clk_saradc = {
1622         .name           = "saradc",
1623         .parent         = &xin24m,
1624         .mode           = gate_mode,
1625         .recalc         = clksel_recalc_div,
1626         .set_rate       = clksel_set_rate_freediv,
1627         .gate_idx       =  CLK_GATE_SARADC,
1628         .clksel_con     =CRU_CLKSELS_CON(24),
1629         CRU_DIV_SET(0xff,8,256),
1630 };
1631 static struct clk clk_tsadc = {
1632         .name           = "tsadc",
1633         .parent         = &xin24m,
1634         .mode           = gate_mode,
1635         .recalc         = clksel_recalc_div,
1636         .set_rate       = clksel_set_rate_freediv,
1637         .gate_idx       = CLK_GATE_TSADC,
1638         .clksel_con =CRU_CLKSELS_CON(34),
1639         CRU_DIV_SET(0xffff,0,65536),
1640 };
1641 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1642 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1643
1644
1645 GATE_CLK(smc, pclk_periph, SMC);//smc
1646
1647 static struct clk clk_sdmmc = {
1648         .name           = "sdmmc",
1649         .parent         = &hclk_periph,
1650         .mode           = gate_mode,
1651         .recalc         = clksel_recalc_div,
1652         .set_rate       = clksel_set_rate_freediv,
1653         .gate_idx       = CLK_GATE_MMC0,
1654         .clksel_con =CRU_CLKSELS_CON(11),
1655         CRU_DIV_SET(0x3f,0,64),
1656 };
1657
1658 static struct clk clk_sdio = {
1659         .name           = "sdio",
1660         .parent         = &hclk_periph,
1661         .mode           = gate_mode,
1662         .recalc         = clksel_recalc_div,
1663         .set_rate       = clksel_set_rate_freediv,
1664         .gate_idx       = CLK_GATE_SDIO,
1665         .clksel_con =CRU_CLKSELS_CON(12),
1666         CRU_DIV_SET(0x3f,0,64),
1667
1668 };
1669
1670 static struct clk clk_emmc = {
1671         .name           = "emmc",
1672         .parent         = &hclk_periph,
1673         .mode           = gate_mode,
1674         .recalc         = clksel_recalc_div,
1675         .set_rate       = clksel_set_rate_freediv,
1676         .gate_idx       = CLK_GATE_EMMC,
1677         .clksel_con =CRU_CLKSELS_CON(12),
1678         CRU_DIV_SET(0x3f,8,64),
1679 };
1680
1681 static struct clk *clk_uart_src_parents[2]={&general_pll_clk,&codec_pll_clk};
1682 static struct clk clk_uart_pll = {
1683         .name           = "uart_pll",
1684         .parent         = &general_pll_clk,
1685         .clksel_con =CRU_CLKSELS_CON(12),
1686         CRU_SRC_SET(0x1,15),
1687         CRU_PARENTS_SET(clk_uart_src_parents),
1688 };
1689 static struct clk clk_uart0_div = {
1690         .name           = "uart0_div",
1691         .parent         = &clk_uart_pll,
1692         .mode           = gate_mode,
1693         .gate_idx       = CLK_GATE_UART0,
1694         .recalc         = clksel_recalc_div,
1695         .set_rate       = clksel_set_rate_freediv,
1696         .round_rate     =clksel_freediv_round_rate,
1697         .clksel_con     = CRU_CLKSELS_CON(13),
1698         CRU_DIV_SET(0x7f,0,64),
1699 };
1700 static struct clk clk_uart1_div = {
1701         .name           = "uart1_div",
1702         .parent         = &clk_uart_pll,
1703         .mode           = gate_mode,
1704         .gate_idx       = CLK_GATE_UART1,
1705         .recalc         = clksel_recalc_div,
1706         .round_rate     =clksel_freediv_round_rate,
1707         .set_rate       = clksel_set_rate_freediv,
1708         .clksel_con     = CRU_CLKSELS_CON(14),
1709         CRU_DIV_SET(0x7f,0,64),
1710 };
1711
1712 static struct clk clk_uart2_div = {
1713         .name           = "uart2_div",
1714         .parent         = &clk_uart_pll,
1715         .mode           = gate_mode,
1716         .gate_idx       = CLK_GATE_UART2,
1717         .recalc         = clksel_recalc_div,
1718         .round_rate     =clksel_freediv_round_rate,
1719         .set_rate       = clksel_set_rate_freediv,
1720         .clksel_con     = CRU_CLKSELS_CON(15),
1721         CRU_DIV_SET(0x7f,0,64),
1722 };
1723
1724 static struct clk clk_uart3_div = {
1725         .name           = "uart3_div",
1726         .parent         = &clk_uart_pll,
1727         .mode           = gate_mode,
1728         .gate_idx       = CLK_GATE_UART3,
1729         .recalc         = clksel_recalc_div,
1730         .round_rate     =clksel_freediv_round_rate,
1731         .set_rate       = clksel_set_rate_freediv,
1732         .clksel_con     = CRU_CLKSELS_CON(16),
1733         CRU_DIV_SET(0x7f,0,64),
1734 };
1735 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1736 {
1737         u32 numerator, denominator;
1738         //clk_uart0_div->clk_uart_pll->gpll/cpll
1739         //clk->parent->parent
1740         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1741                         &numerator,&denominator)==0)
1742         {
1743                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1744
1745                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1746
1747                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1748         }
1749         else
1750         {
1751                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1752                 return -ENOENT;
1753         }
1754         return 0;
1755 }
1756
1757 static struct clk clk_uart0_frac_div = {
1758         .name           = "uart0_frac_div",
1759         .parent         = &clk_uart0_div,
1760         .mode           = gate_mode,
1761         .recalc         = clksel_recalc_frac,
1762         .set_rate       = clk_uart_fracdiv_set_rate,
1763         .gate_idx       = CLK_GATE_FRAC_UART0,
1764         .clksel_con     = CRU_CLKSELS_CON(17),
1765 };
1766 static struct clk clk_uart1_frac_div = {
1767         .name           = "uart1_frac_div",
1768         .parent         = &clk_uart1_div,
1769         .mode           = gate_mode,
1770         .recalc         = clksel_recalc_frac,
1771         .set_rate       = clk_uart_fracdiv_set_rate,
1772         .gate_idx       = CLK_GATE_FRAC_UART1,
1773         .clksel_con     = CRU_CLKSELS_CON(18),
1774 };
1775 static struct clk clk_uart2_frac_div = {
1776         .name           = "uart2_frac_div",
1777         .mode           = gate_mode,
1778         .parent         = &clk_uart2_div,
1779         .recalc         = clksel_recalc_frac,
1780         .set_rate       = clk_uart_fracdiv_set_rate,
1781         .gate_idx       = CLK_GATE_FRAC_UART2,
1782         .clksel_con     = CRU_CLKSELS_CON(19),
1783 };
1784 static struct clk clk_uart3_frac_div = {
1785         .name           = "uart3_frac_div",
1786         .parent         = &clk_uart3_div,
1787         .mode           = gate_mode,
1788         .recalc         = clksel_recalc_frac,
1789         .set_rate       = clk_uart_fracdiv_set_rate,
1790         .gate_idx       = CLK_GATE_FRAC_UART3,
1791         .clksel_con     = CRU_CLKSELS_CON(20),
1792 };
1793
1794
1795 #define UART_SRC_DIV 0
1796 #define UART_SRC_FRAC 1
1797 #define UART_SRC_24M 2
1798
1799 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1800 {
1801         int ret = 0;
1802         struct clk *parent;
1803
1804         if(rate==clk->parents[UART_SRC_24M]->rate)//24m
1805         {
1806                 parent = clk->parents[UART_SRC_24M];
1807         }
1808         else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate)==rate)
1809         {
1810                 parent = clk->parents[UART_SRC_DIV];
1811         }
1812         else
1813         {
1814                 parent = clk->parents[UART_SRC_FRAC];
1815         }
1816
1817         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1818                 clk->name,rate,parent->name,clk->parent->name);
1819
1820
1821         if(parent!=clk->parents[UART_SRC_24M])
1822         {
1823                 ret = clk_set_rate_nolock(parent,rate);
1824                 if (ret)
1825                 {
1826                         CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
1827                         return ret;
1828                 }
1829         }
1830
1831         if (clk->parent != parent)
1832         {
1833                 ret = clk_set_parent_nolock(clk, parent);
1834                 if (ret)
1835                 {
1836                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1837                         return ret;
1838                 }
1839         }
1840
1841
1842         return ret;
1843 }
1844
1845
1846 static struct clk *clk_uart0_parents[3]={&clk_uart0_div,&clk_uart0_frac_div,&xin24m};
1847 static struct clk clk_uart0 = {
1848         .name           = "uart0",
1849         .set_rate       = clk_uart_set_rate,
1850         .clksel_con     = CRU_CLKSELS_CON(13),
1851         CRU_SRC_SET(0x3,8),
1852         CRU_PARENTS_SET(clk_uart0_parents),
1853 };
1854
1855 static struct clk *clk_uart1_parents[3]={&clk_uart1_div,&clk_uart1_frac_div,&xin24m};
1856 static struct clk clk_uart1 = {
1857         .name           = "uart1",
1858         .set_rate       = clk_uart_set_rate,
1859         .clksel_con     = CRU_CLKSELS_CON(14),
1860         CRU_SRC_SET(0x3,8),
1861         CRU_PARENTS_SET(clk_uart1_parents),
1862 };
1863
1864 static struct clk *clk_uart2_parents[3]={&clk_uart2_div,&clk_uart2_frac_div,&xin24m};
1865 static struct clk clk_uart2 = {
1866         .name           = "uart2",
1867         .set_rate       = clk_uart_set_rate,
1868         .clksel_con     = CRU_CLKSELS_CON(15),
1869         CRU_SRC_SET(0x3,8),
1870         CRU_PARENTS_SET(clk_uart2_parents),
1871 };
1872 static struct clk *clk_uart3_parents[3]={&clk_uart3_div,&clk_uart3_frac_div,&xin24m};
1873 static struct clk clk_uart3 = {
1874         .name           = "uart3",
1875         .set_rate       = clk_uart_set_rate,
1876         .clksel_con     = CRU_CLKSELS_CON(16),
1877         CRU_SRC_SET(0x3,8),
1878         CRU_PARENTS_SET(clk_uart3_parents),
1879 };
1880
1881 GATE_CLK(timer0, xin24m, TIMER0);
1882 GATE_CLK(timer1, xin24m, TIMER1);
1883 GATE_CLK(timer2, xin24m, TIMER2);
1884
1885 static struct clk rmii_clkin = {
1886         .name           = "rmii_clkin",
1887 };
1888 static struct clk *clk_mac_ref_div_parents[2]={&general_pll_clk,&ddr_pll_clk};
1889 static struct clk clk_mac_pll_div = {
1890         .name           = "mac_pll_div",
1891         .parent         = &ddr_pll_clk,
1892         .mode           = gate_mode,
1893         .gate_idx       = CLK_GATE_MAC,
1894         .recalc         = clksel_recalc_div,
1895         .set_rate       =clksel_set_rate_freediv,
1896         //.set_rate     = clksel_set_rate_freediv,
1897         .clksel_con     =CRU_CLKSELS_CON(21),
1898         CRU_DIV_SET(0x1f,8,32),
1899         CRU_SRC_SET(0x1,0),
1900         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1901 };
1902
1903 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1904 {
1905
1906         if(clk->parent==clk->parents[1])
1907         {
1908                 CRU_PRINTK_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1909                 return -ENOENT;
1910         }
1911         else if(clk->parent==clk->parents[0])
1912         {
1913         return clk_set_rate_nolock(clk->parents[0],rate);
1914         }
1915         return -ENOENT;
1916 }
1917
1918 static struct clk *clk_mac_ref_parents[2]={&clk_mac_pll_div,&rmii_clkin};
1919
1920 static struct clk clk_mac_ref = {
1921         .name           = "mac_ref",
1922         .parent         = &clk_mac_pll_div,
1923         .set_rate       = clksel_mac_ref_set_rate,
1924         .clksel_con =CRU_CLKSELS_CON(21),
1925         CRU_SRC_SET(0x1,4),
1926         CRU_PARENTS_SET(clk_mac_ref_parents),
1927 };
1928
1929 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1930 {
1931         return clk_set_parent_nolock(clk->parent,parent);
1932 }
1933
1934 static struct clk clk_mii_tx = {
1935         .name           = "mii_tx",
1936         .parent         = &clk_mac_ref,
1937         //.set_parent   = clk_set_mii_tx_parent,
1938         .mode           = gate_mode,
1939         .gate_idx       = CLK_GATE_MAC_LBTEST,//???
1940 };
1941
1942 static struct clk *clk_hsadc_pll_parents[2]={&general_pll_clk,&codec_pll_clk};
1943 static struct clk clk_hsadc_pll_div = {
1944         .name           = "hsadc_pll_div",
1945         .parent         = &general_pll_clk,
1946         .mode           = gate_mode,
1947         .gate_idx       = CLK_GATE_SARADC,
1948         .recalc         = clksel_recalc_div,
1949         .round_rate     =clk_freediv_round_autosel_parents_rate,
1950         .set_rate       = clkset_rate_freediv_autosel_parents,
1951         //.round_rate =clksel_freediv_round_rate,
1952         //.set_rate     = clksel_set_rate_freediv,
1953         .clksel_con =CRU_CLKSELS_CON(22),
1954         CRU_DIV_SET(0xff,8,256),
1955         CRU_SRC_SET(0x1,0),
1956         CRU_PARENTS_SET(clk_hsadc_pll_parents),
1957 };
1958
1959 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
1960 {
1961         u32 numerator, denominator;
1962         //        clk_hsadc_pll_div->gpll/cpll
1963         //clk->parent->parent
1964         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1965                         &numerator,&denominator)==0)
1966         {
1967                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1968
1969                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1970
1971                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1972         }
1973         else
1974         {
1975                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1976                 return -ENOENT;
1977         }
1978         return 0;
1979 }
1980 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
1981 {
1982         u32 numerator, denominator;
1983         u32 i,ret=0;
1984         //        clk_hsadc_pll_div->gpll/cpll
1985         //clk->parent->parent
1986         for(i=0;i<2;i++)
1987         {
1988                 if(frac_div_get_seting(rate,clk->parent->parents[i]->rate,
1989                         &numerator,&denominator)==0)
1990                         break;
1991         }
1992         if(i>=2)
1993                 return -ENOENT;
1994
1995         if(clk->parent->parent!=clk->parent->parents[i])
1996                 ret=clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
1997         if(ret==0)
1998         {
1999                 clk_set_rate_nolock(clk->parent,clk->parent->parents[i]->rate);//PLL:DIV 1:
2000
2001                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2002
2003                 CRU_PRINTK_DBG("clk_frac_div %s, rate=%lu\n",clk->name,rate);
2004         }
2005         else
2006         {
2007                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
2008                 return -ENOENT;
2009         }
2010         return 0;
2011 }
2012
2013 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2014 {
2015         u32 numerator, denominator;
2016
2017         CRU_PRINTK_ERR("clk_hsadc_fracdiv_round_rate\n");
2018         if(frac_div_get_seting(rate,clk->parent->parent->rate,
2019                         &numerator,&denominator)==0)
2020                 return rate;
2021
2022         return 0;
2023 }
2024 static struct clk clk_hsadc_frac_div = {
2025         .name           = "hsadc_frac_div",
2026         .parent         = &clk_hsadc_pll_div,
2027         .mode           = gate_mode,
2028         .recalc         = clksel_recalc_frac,
2029         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2030         .round_rate     =clk_hsadc_fracdiv_round_rate,
2031         .gate_idx       = CLK_GATE_HSADC_FRAC,
2032         .clksel_con     = CRU_CLKSELS_CON(23),
2033 };
2034
2035 #define HSADC_SRC_DIV 0x0
2036 #define HSADC_SRC_FRAC 0x1
2037 #define HSADC_SRC_EXT 0x2
2038 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2039 {
2040         int ret = -EINVAL;
2041         struct clk *parent;
2042
2043         if(clk->parent == clk->parents[HSADC_SRC_EXT]){
2044                 CRU_PRINTK_DBG("hsadc clk is form ext\n");
2045                 return 0;
2046         }
2047         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV],rate)==rate)
2048         {
2049                 parent =clk->parents[HSADC_SRC_DIV];
2050         }
2051         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC],rate)==rate)
2052         {
2053                 parent = clk->parents[HSADC_SRC_FRAC];
2054         }
2055         else
2056                 parent =clk->parents[HSADC_SRC_DIV];
2057
2058         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
2059                 clk->name,rate,parent->name,clk->parent->name);
2060
2061         ret = clk_set_rate_nolock(parent,rate);
2062         if (ret)
2063         {
2064                 CRU_PRINTK_ERR("%s set rate%lu err\n",clk->name,rate);
2065                 return ret;
2066         }
2067         if (clk->parent != parent)
2068         {
2069                 ret = clk_set_parent_nolock(clk, parent);
2070                 if (ret)
2071                 {
2072                         CRU_PRINTK_ERR("%s can't get rate%lu,reparent err\n",clk->name,rate);
2073                         return ret;
2074                 }
2075         }
2076         return ret;
2077 }
2078
2079 static struct clk clk_hsadc_ext = {
2080         .name           = "hsadc_ext",
2081 };
2082
2083 static struct clk *clk_hsadc_parents[3]={&clk_hsadc_pll_div,&clk_hsadc_frac_div,&clk_hsadc_ext};
2084 static struct clk clk_hsadc = {
2085         .name           = "hsadc",
2086         .parent         = &clk_hsadc_pll_div,
2087         .set_rate       = clk_hsadc_set_rate,
2088         .clksel_con     = CRU_CLKSELS_CON(22),
2089         CRU_SRC_SET(0x3,4),
2090         CRU_PARENTS_SET(clk_hsadc_parents),
2091 };
2092
2093 static struct clk *dclk_lcdc_div_parents[]={&codec_pll_clk,&general_pll_clk};
2094 static struct clk dclk_lcdc0_div = {
2095         .name           = "dclk_lcdc0_div",
2096         .parent         = &general_pll_clk,
2097         .recalc         = clksel_recalc_div,
2098         .set_rate       = clkset_rate_freediv_autosel_parents,
2099         .clksel_con     = CRU_CLKSELS_CON(27),
2100         CRU_DIV_SET(0xff,8,256),
2101         CRU_SRC_SET(0x1,0),
2102         CRU_PARENTS_SET(dclk_lcdc_div_parents),
2103 };
2104
2105 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
2106 {
2107         u32 div,old_div;
2108         int i;
2109         unsigned long new_rate;
2110         int ret=0;
2111
2112         if(clk->rate==rate)
2113                 return 0;
2114         for(i=0;i<2;i++)
2115         {
2116                 div=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
2117                 new_rate= clk->parents[i]->rate/div;
2118                 if((rate==new_rate)&&!(clk->parents[i]->rate%div))
2119                 {
2120                         break;
2121                 }
2122         }
2123         if(i>=2)
2124         {
2125                 CRU_PRINTK_ERR("%s can't set fixed rate%lu\n",clk->name,rate);
2126                 return -1;
2127         }
2128
2129         //CRU_PRINTK_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
2130
2131         old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
2132                                                                                 clk->div_shift,clk->div_mask)+1;
2133         if(div>old_div)
2134                 set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
2135
2136         if(clk->parents[i]!=clk->parent)
2137         {
2138                 ret=clk_set_parent_nolock(clk,clk->parents[i]);
2139         }
2140
2141         if (ret)
2142         {
2143                 CRU_PRINTK_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
2144                         clk->name,rate,clk->parents[i]->name,clk->parent->name);
2145                 return ret;
2146         }
2147         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
2148         return 0;
2149 }
2150 //hdmi
2151 static struct clk dclk_lcdc1_div = {
2152         .name           = "dclk_lcdc1_div",
2153         .parent         = &general_pll_clk,
2154         .recalc         = clksel_recalc_div,
2155         .set_rate       = clksel_set_rate_hdmi,//clk_freediv_autosel_parents_set_fixed_rate
2156         .clksel_con     = CRU_CLKSELS_CON(28),
2157         CRU_DIV_SET(0xff,8,256),
2158         CRU_SRC_SET(0x1,0),
2159         CRU_PARENTS_SET(dclk_lcdc_div_parents),
2160 };
2161
2162 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
2163 {
2164         int ret = 0;
2165         struct clk *parent;
2166
2167         if (rate == 27 * MHZ&&(rk30_clock_flags&CLK_FLG_EXT_27MHZ)) {
2168                 parent =clk->parents[1];
2169                 //CRU_PRINTK_DBG(" %s from=%s\n",clk->name,parent->name);
2170         } else {
2171                 parent=clk->parents[0];
2172         }
2173         //CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
2174                         //clk->name,rate,parent->name,clk->parent->name);
2175
2176         if(parent!=clk->parents[1])
2177         {
2178                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
2179                 if (ret)
2180                 {
2181                         CRU_PRINTK_DBG("%s set rate=%lu err\n",clk->name,rate);
2182                         return ret;
2183                 }
2184         }
2185         if (clk->parent != parent)
2186         {
2187                 ret = clk_set_parent_nolock(clk, parent);
2188                 if (ret)
2189                 {
2190                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
2191                         return ret;
2192                 }
2193         }
2194         return ret;
2195 }
2196
2197 static struct clk *dclk_lcdc0_parents[2]={&dclk_lcdc0_div,&xin27m};
2198 static struct clk dclk_lcdc0 = {
2199         .name           = "dclk_lcdc0",
2200         .mode           = gate_mode,
2201         .set_rate       = dclk_lcdc_set_rate,
2202         .gate_idx       = CLK_GATE_DCLK_LCDC0,
2203         .clksel_con     = CRU_CLKSELS_CON(27),
2204         CRU_SRC_SET(0x1,4),
2205         CRU_PARENTS_SET(dclk_lcdc0_parents),
2206 };
2207
2208 static struct clk *dclk_lcdc1_parents[2]={&dclk_lcdc1_div,&xin27m};
2209 static struct clk dclk_lcdc1 = {
2210         .name           = "dclk_lcdc1",
2211         .mode           = gate_mode,
2212         .set_rate       = dclk_lcdc_set_rate,
2213         .gate_idx       = CLK_GATE_DCLK_LCDC1,
2214         .clksel_con     = CRU_CLKSELS_CON(28),
2215         CRU_SRC_SET(0x1,4),
2216         CRU_PARENTS_SET(dclk_lcdc1_parents),
2217 };
2218
2219 static struct clk *cifout_sel_pll_parents[2]={&codec_pll_clk,&general_pll_clk};
2220 static struct clk cif_out_pll = {
2221         .name           = "cif_out_pll",
2222         .parent         = &general_pll_clk,
2223         .clksel_con     = CRU_CLKSELS_CON(29),
2224         CRU_SRC_SET(0x1,0),
2225         CRU_PARENTS_SET(cifout_sel_pll_parents),
2226 };
2227
2228 static struct clk cif0_out_div = {
2229         .name           = "cif0_out_div",
2230         .parent         = &cif_out_pll,
2231         .mode           = gate_mode,
2232         .recalc         = clksel_recalc_div,
2233         .set_rate       = clksel_set_rate_freediv,
2234         .gate_idx       =CLK_GATE_CIF0_OUT,
2235         .clksel_con     = CRU_CLKSELS_CON(29),
2236         CRU_DIV_SET(0x1f,1,32),
2237 };
2238
2239 static struct clk cif1_out_div = {
2240         .name           = "cif1_out_div",
2241         .parent         = &cif_out_pll,
2242         .mode           = gate_mode,
2243         .recalc         = clksel_recalc_div,
2244         .set_rate       = clksel_set_rate_freediv,
2245         .gate_idx       =       CLK_GATE_CIF1_OUT,
2246         .clksel_con     = CRU_CLKSELS_CON(29),
2247         CRU_DIV_SET(0x1f,8,32),
2248 };
2249
2250
2251 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
2252 {
2253         int ret = 0;
2254         struct clk *parent;
2255
2256         if (rate == 24 * MHZ) {
2257                 parent =clk->parents[1];
2258         } else {
2259                 parent=clk->parents[0];
2260                 ret = clk_set_rate_nolock(parent, rate);
2261                 if (ret)
2262                         return ret;
2263         }
2264         if (clk->parent != parent)
2265                 ret = clk_set_parent_nolock(clk, parent);
2266
2267         return ret;
2268 }
2269
2270 static struct clk *cif0_out_parents[2]={&cif0_out_div,&xin24m};
2271 static struct clk cif0_out = {
2272         .name           = "cif0_out",
2273         .parent         = &cif0_out_div,
2274         .set_rate       = cif_out_set_rate,
2275         .clksel_con     = CRU_CLKSELS_CON(29),
2276         CRU_SRC_SET(0x1,7),
2277         CRU_PARENTS_SET(cif0_out_parents),
2278 };
2279 static struct clk *cif1_out_parents[2]={&cif1_out_div,&xin24m};
2280
2281 static struct clk cif1_out = {
2282         .name           = "cif1_out",
2283         .parent         = &cif1_out_div,
2284         .set_rate       = cif_out_set_rate,
2285         .clksel_con     = CRU_CLKSELS_CON(29),
2286         CRU_SRC_SET(0x1,15),
2287         CRU_PARENTS_SET(cif1_out_parents),
2288 };
2289
2290 static struct clk pclkin_cif0 = {
2291         .name           = "pclkin_cif0",
2292         .mode           = gate_mode,
2293         .gate_idx       =CLK_GATE_PCLKIN_CIF0,
2294 };
2295
2296 static struct clk inv_cif0 = {
2297         .name           = "inv_cif0",
2298         .parent         = &pclkin_cif0,
2299 };
2300
2301 static struct clk *cif0_in_parents[2]={&pclkin_cif0,&inv_cif0};
2302 static struct clk cif0_in = {
2303         .name           = "cif0_in",
2304         .parent         = &pclkin_cif0,
2305         .clksel_con     = CRU_CLKSELS_CON(30),
2306         CRU_SRC_SET(0x1,8),
2307         CRU_PARENTS_SET(cif0_in_parents),
2308 };
2309
2310 static struct clk pclkin_cif1 = {
2311         .name           = "pclkin_cif1",
2312         .mode           = gate_mode,
2313         .gate_idx       =CLK_GATE_PCLKIN_CIF1,
2314 };
2315
2316 static struct clk inv_cif1 = {
2317         .name           = "inv_cif1",
2318         .parent         = &pclkin_cif1,
2319 };
2320 static struct clk *cif1_in_parents[2]={&pclkin_cif1,&inv_cif1};
2321
2322 static struct clk cif1_in = {
2323         .name           = "cif1_in",
2324         .parent         = &pclkin_cif1,
2325         .clksel_con     = CRU_CLKSELS_CON(30),
2326         CRU_SRC_SET(0x1,12),
2327         CRU_PARENTS_SET(cif1_in_parents),
2328 };
2329
2330 static struct clk *aclk_lcdc0_ipp_parents[]={&codec_pll_clk,&general_pll_clk};
2331
2332 static struct clk aclk_lcdc0_ipp_parent = {
2333         .name           = "aclk_lcdc0_ipp_parent",
2334         .parent         = &codec_pll_clk,
2335         .mode           = gate_mode,
2336         .recalc         = clksel_recalc_div,
2337         .set_rate       = clkset_rate_freediv_autosel_parents,
2338         //.set_rate     = clksel_set_rate_freediv,
2339         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
2340         .clksel_con     = CRU_CLKSELS_CON(31),
2341         CRU_DIV_SET(0x1f,0,32),
2342         CRU_SRC_SET(0x1,7),
2343         CRU_PARENTS_SET(aclk_lcdc0_ipp_parents),
2344 };
2345
2346 static struct clk *aclk_lcdc1_rga_parents[]={&codec_pll_clk,&general_pll_clk};
2347
2348 static struct clk aclk_lcdc1_rga_parent = {
2349         .name           = "aclk_lcdc1_rga_parent",
2350         .parent         = &codec_pll_clk,
2351         .mode           = gate_mode,
2352         .recalc         = clksel_recalc_div,
2353         .set_rate       = clkset_rate_freediv_autosel_parents,
2354         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
2355         .clksel_con     = CRU_CLKSELS_CON(31),
2356         CRU_DIV_SET(0x1f,8,32),
2357         CRU_SRC_SET(0x1,15),
2358         CRU_PARENTS_SET(aclk_lcdc1_rga_parents),
2359 };
2360
2361
2362 //for free div
2363 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
2364 {
2365         unsigned long rate = clk->parent->rate / 4;
2366         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
2367         return rate;
2368 }
2369
2370 static struct clk *aclk_vepu_parents[2]={&codec_pll_clk,&general_pll_clk};
2371
2372 static struct clk aclk_vepu = {
2373         .name           = "aclk_vepu",
2374         .parent         = &codec_pll_clk,
2375         .mode           = gate_mode,
2376         .recalc         = clksel_recalc_div,
2377         //.set_rate     = clksel_set_rate_freediv,
2378         .set_rate       =clkset_rate_freediv_autosel_parents,
2379         .clksel_con     = CRU_CLKSELS_CON(32),
2380         .gate_idx       = CLK_GATE_ACLK_VEPU,
2381         CRU_DIV_SET(0x1f,0,32),
2382         CRU_SRC_SET(0x1,7),
2383         CRU_PARENTS_SET(aclk_vepu_parents),
2384 };
2385
2386 static struct clk hclk_vepu = {
2387         .name           = "hclk_vepu",
2388         .parent         = &aclk_vepu,
2389         .mode           = gate_mode,
2390         .recalc         = clksel_recalc_vpu_hclk,
2391         .clksel_con     = CRU_CLKSELS_CON(32),
2392         .gate_idx       = CLK_GATE_HCLK_VEPU,
2393 };
2394
2395 static struct clk *aclk_vdpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2396
2397 static struct clk aclk_vdpu = {
2398         .name           = "aclk_vdpu",
2399         .mode           = gate_mode,
2400         .recalc         = clksel_recalc_div,
2401         //.set_rate     = clksel_set_rate_freediv,
2402         .set_rate       =clkset_rate_freediv_autosel_parents,
2403         .clksel_con     = CRU_CLKSELS_CON(32),
2404         .gate_idx       = CLK_GATE_ACLK_VDPU,
2405         CRU_DIV_SET(0x1f,8,32),
2406         CRU_SRC_SET(0x1,15),
2407         CRU_PARENTS_SET(aclk_vdpu_parents),
2408 };
2409 static struct clk hclk_vdpu = {
2410         .name           = "hclk_vdpu",
2411         .parent         = &aclk_vdpu,
2412         .mode           = gate_mode,
2413         .recalc         = clksel_recalc_vpu_hclk,
2414         .clksel_con     = CRU_CLKSELS_CON(32),
2415         .gate_idx       = CLK_GATE_HCLK_VDPU,
2416 };
2417
2418
2419 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
2420 {
2421         unsigned long max_rate = rate / 100 * 105;      /* +5% */
2422         return clkset_rate_freediv_autosel_parents(clk,max_rate);
2423 };
2424
2425 static struct clk *gpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2426
2427 static struct clk clk_gpu = {
2428         .name           = "gpu",
2429         .mode           = gate_mode,
2430         .recalc         = clksel_recalc_div,
2431         .round_rate     = clk_freediv_round_autosel_parents_rate,
2432         .set_rate       = clkset_rate_freediv_autosel_parents,
2433         .clksel_con = CRU_CLKSELS_CON(33),
2434         .gate_idx       =  CLK_GATE_GPU_SRC,
2435         CRU_DIV_SET(0x1f,0,32),
2436         CRU_SRC_SET(0x1,8),
2437         CRU_PARENTS_SET(gpu_parents),
2438 };
2439
2440 /*********************power domain*******************************/
2441 #ifdef RK30_CLK_OFFBOARD_TEST
2442 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on){};
2443         #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2444 #else
2445 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2446         #define _pmu_set_power_domain pmu_set_power_domain
2447 #endif
2448 static int pm_off_mode(struct clk *clk, int on)
2449 {
2450          _pmu_set_power_domain(clk->gate_idx,on);//on 1
2451          return 0;
2452 }
2453 static struct clk pd_peri = {
2454         .name   = "pd_peri",
2455         .flags  = IS_PD,
2456         .mode   = pm_off_mode,
2457         .gate_idx       = PD_PERI,
2458 };
2459
2460 static int pd_display_mode(struct clk *clk, int on)
2461 {
2462         u32 gate[10];
2463
2464         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2465         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2466         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2467         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2468         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2469         gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2470         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2471         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2472         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2473         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2474         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2475         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2476         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2477         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2478         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2479         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2480         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2481         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2482         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2483         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2484         pmu_set_power_domain(PD_VIO, on);
2485         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2486         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2487         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2488         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2489         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2490         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2491         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2492         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2493         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2494         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2495
2496         return 0;
2497 }
2498
2499 static struct clk pd_display = {
2500         .name   = "pd_display",
2501         .flags  = IS_PD,
2502         .mode   = pd_display_mode,
2503         .gate_idx       = PD_VIO,
2504 };
2505
2506 static struct clk pd_lcdc0 = {
2507         .parent = &pd_display,
2508         .name   = "pd_lcdc0",
2509 };
2510 static struct clk pd_lcdc1 = {
2511         .parent = &pd_display,
2512         .name   = "pd_lcdc1",
2513 };
2514 static struct clk pd_cif0 = {
2515         .parent = &pd_display,
2516         .name   = "pd_cif0",
2517 };
2518 static struct clk pd_cif1 = {
2519         .parent = &pd_display,
2520         .name   = "pd_cif1",
2521 };
2522 static struct clk pd_rga = {
2523         .parent = &pd_display,
2524         .name   = "pd_rga",
2525 };
2526 static struct clk pd_ipp = {
2527         .parent = &pd_display,
2528         .name   = "pd_ipp",
2529 };
2530
2531 static int pd_video_mode(struct clk *clk, int on)
2532 {
2533         u32 gate[3];
2534
2535         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2536         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2537         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2538         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2539         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2540         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2541         pmu_set_power_domain(PD_VIDEO, on);
2542         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2543         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2544         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2545
2546         return 0;
2547 }
2548
2549 static struct clk pd_video = {
2550         .name   = "pd_video",
2551         .flags  = IS_PD,
2552         .mode   = pd_video_mode,
2553         .gate_idx       = PD_VIDEO,
2554 };
2555
2556 static int pd_gpu_mode(struct clk *clk, int on)
2557 {
2558         u32 gate[2];
2559
2560         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2561         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2562         cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2563         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2564         pmu_set_power_domain(PD_GPU, on);
2565         cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2566         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2567
2568         return 0;
2569 }
2570
2571 static struct clk pd_gpu = {
2572         .name   = "pd_gpu",
2573         .flags  = IS_PD,
2574         .mode   = pd_gpu_mode,
2575         .gate_idx       = PD_GPU,
2576 };
2577 static struct clk pd_dbg = {
2578         .name   = "pd_dbg",
2579         .flags  = IS_PD,
2580         .mode   = pm_off_mode,
2581         .gate_idx       = PD_DBG,
2582 };
2583
2584 #define PD_CLK(name) \
2585 {\
2586         .dev_id = NULL,\
2587         .con_id = #name,\
2588         .clk = &name,\
2589 }
2590
2591
2592 /************************rk30 fixed div clock****************************************/
2593
2594 /*************************aclk_cpu***********************/
2595
2596 GATE_CLK(dma1, aclk_cpu,        ACLK_DMAC1);
2597 GATE_CLK(l2mem_con, aclk_cpu,   ACLK_L2MEM_CON);
2598 GATE_CLK(intmem, aclk_cpu,      ACLK_INTMEM);
2599 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2600
2601 /*************************hclk_cpu***********************/
2602
2603 GATE_CLK(rom, hclk_cpu, HCLK_ROM);
2604 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2605 GATE_CLK(hclk_i2s1_2ch, hclk_cpu,       HCLK_I2S1_2CH);
2606 GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
2607 GATE_CLK(hclk_i2s_8ch, hclk_cpu, HCLK_I2S_8CH);
2608 GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
2609 GATE_CLK(hclk_ahb2apb,  hclk_cpu, HCLK_AHB2APB);
2610 GATE_CLK(hclk_vio_bus,  hclk_cpu, HCLK_VIO_BUS);
2611 GATE_CLK(hclk_lcdc0,    hclk_cpu, HCLK_LCDC0);
2612 GATE_CLK(hclk_lcdc1,    hclk_cpu, HCLK_LCDC1);
2613 GATE_CLK(hclk_cif0,     hclk_cpu, HCLK_CIF0);
2614 GATE_CLK(hclk_cif1,     hclk_cpu, HCLK_CIF1);
2615 GATE_CLK(hclk_ipp,              hclk_cpu, HCLK_IPP);
2616 GATE_CLK(hclk_rga,              hclk_cpu, HCLK_RGA);
2617 GATE_CLK(hclk_hdmi,     hclk_cpu, HCLK_HDMI);
2618 //GATE_CLK(hclk_vidoe_h2h,      hclk_cpu, ); ???
2619 /*************************pclk_cpu***********************/
2620 GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2621 //GATE_CLK(pclk_pwm1,   pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2622 GATE_CLK(pclk_timer0,   pclk_cpu, PCLK_TIMER0);
2623 GATE_CLK(pclk_timer1,   pclk_cpu, PCLK_TIMER1);
2624 GATE_CLK(pclk_timer2,   pclk_cpu, PCLK_TIMER2);
2625 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2626 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2627 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2628 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2629 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2630 GATE_CLK(gpio6, pclk_cpu, PCLK_GPIO6);
2631 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2632 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2633 GATE_CLK(pclk_uart0,    pclk_cpu, PCLK_UART0);
2634 GATE_CLK(pclk_uart1,    pclk_cpu, PCLK_UART1);
2635 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2636 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2637 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2638 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2639 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2640
2641 /*************************aclk_periph***********************/
2642
2643 GATE_CLK(dma2, aclk_periph,ACLK_DMAC2);
2644 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2645 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2646 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2647 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2648
2649 /*************************hclk_periph***********************/
2650 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2651 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2652 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2653 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2654 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2655 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2656 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2657 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2658 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2659 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2660 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2661 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2662 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2663 /*************************pclk_periph***********************/
2664 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2665 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2666 //GATE_CLK(pclk_pwm3, pclk_periph, PCLK_PWM3);
2667 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2668 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2669 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2670 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2671 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2672 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2673 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2674 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2675 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2676 GATE_CLK(gpio4, pclk_periph, PCLK_GPIO4);
2677 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2678 GATE_CLK(pclk_tsadc, pclk_periph, PCLK_TSADC);
2679 /*************************aclk_lcdc0***********************/
2680 GATE_CLK(aclk_lcdc0, aclk_lcdc0_ipp_parent, ACLK_LCDC0);
2681 GATE_CLK(aclk_vio0, aclk_lcdc0_ipp_parent, ACLK_VIO0);
2682 GATE_CLK(aclk_cif0, aclk_lcdc0_ipp_parent, ACLK_CIF0);
2683 GATE_CLK(aclk_ipp,  aclk_lcdc0_ipp_parent, ACLK_IPP);
2684
2685 /*************************aclk_lcdc0***********************/
2686
2687 GATE_CLK(aclk_lcdc1, aclk_lcdc1_rga_parent, ACLK_LCDC1);
2688 GATE_CLK(aclk_vio1, aclk_lcdc1_rga_parent, ACLK_VIO1);
2689 GATE_CLK(aclk_cif1, aclk_lcdc1_rga_parent, ACLK_CIF0);
2690 GATE_CLK(aclk_rga,  aclk_lcdc1_rga_parent, ACLK_RGA);
2691
2692
2693 #if 1
2694 #define CLK(dev, con, ck) \
2695  {\
2696         .dev_id = dev,\
2697         .con_id = con,\
2698         .clk = ck,\
2699  }
2700
2701
2702 #define CLK1(name) \
2703         {\
2704         .dev_id = NULL,\
2705         .con_id = #name,\
2706         .clk = &clk_##name,\
2707         }
2708
2709 #endif
2710
2711
2712
2713
2714 static struct clk_lookup clks[] = {
2715         CLK(NULL, "xin24m", &xin24m),
2716         CLK(NULL, "xin27m", &xin27m),
2717         CLK(NULL, "xin12m", &clk_12m),
2718         CLK(NULL, "arm_pll", &arm_pll_clk),
2719         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2720         CLK(NULL, "codec_pll", &codec_pll_clk),
2721         CLK(NULL, "general_pll", &general_pll_clk),
2722
2723         CLK(NULL, "ddr", &clk_ddr),
2724         //CLK(NULL, "core_gpll_path", &clk_cpu_gpll_path),
2725         CLK(NULL, "cpu", &clk_cpu),
2726         CLK(NULL, "arm_gpll", &clk_cpu_gpll_path),
2727         CLK("smp_twd", NULL, &core_periph),
2728         CLK(NULL, "aclk_cpu", &aclk_cpu),
2729         CLK(NULL, "hclk_cpu", &hclk_cpu),
2730         CLK(NULL, "pclk_cpu", &pclk_cpu),
2731         CLK(NULL, "atclk_cpu", &atclk_cpu),
2732
2733
2734         CLK1(i2s_pll),
2735         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2736         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2737         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2738         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s_8ch),
2739
2740         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
2741         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
2742         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
2743         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2744
2745         CLK("rk29_i2s.2", "i2s_div", &clk_i2s2_div),
2746         CLK("rk29_i2s.2", "i2s_frac_div", &clk_i2s2_frac_div),
2747         CLK("rk29_i2s.2", "i2s", &clk_i2s2),
2748         CLK("rk29_i2s.2", "hclk_i2s", &clk_hclk_i2s1_2ch),
2749
2750         CLK1(spdif_div),
2751         CLK1(spdif_frac_div),
2752         CLK1(spdif),
2753         CLK1(hclk_spdif),
2754
2755         CLK(NULL, "aclk_periph", &aclk_periph),
2756         CLK(NULL, "pclk_periph", &pclk_periph),
2757         CLK(NULL, "hclk_periph", &hclk_periph),
2758
2759         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2760         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2761
2762         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2763         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2764
2765         CLK1(saradc),
2766         CLK1(pclk_saradc),
2767         CLK1(tsadc),
2768         CLK1(pclk_tsadc),
2769         CLK1(otgphy0),
2770         CLK1(otgphy1),
2771         CLK1(hclk_usb_peri),
2772         CLK1(hclk_otg0),
2773         CLK1(hclk_otg1),
2774
2775
2776
2777
2778
2779         CLK1(smc),
2780         CLK1(aclk_smc),
2781
2782         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2783         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2784         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2785         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2786
2787         CLK1(emmc),
2788         CLK1(hclk_emmc),
2789
2790
2791         CLK1(uart_pll),
2792         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2793         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2794         CLK("rk_serial.0", "uart", &clk_uart0),
2795         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2796         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2797         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2798         CLK("rk_serial.1", "uart", &clk_uart1),
2799         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2800         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2801         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2802         CLK("rk_serial.2", "uart", &clk_uart2),
2803         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2804         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2805         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2806         CLK("rk_serial.3", "uart", &clk_uart3),
2807         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2808
2809         CLK1(timer0),
2810         CLK1(pclk_timer0),
2811
2812         CLK1(timer1),
2813         CLK1(pclk_timer1),
2814
2815         CLK1(timer2),
2816         CLK1(pclk_timer2),
2817
2818         CLK(NULL, "rmii_clkin", &rmii_clkin),
2819         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2820         CLK1(mac_ref),
2821         CLK1(mii_tx),
2822         CLK1(hsadc_pll_div),
2823         CLK1(hsadc_frac_div),
2824         CLK1(hsadc_ext),
2825         CLK1(hsadc),
2826         CLK1(hclk_hsadc),
2827
2828         CLK(NULL, "aclk_lcdc0_ipp_parent", &aclk_lcdc0_ipp_parent),
2829         CLK(NULL, "aclk_lcdc1_rga_parent", &aclk_lcdc1_rga_parent),
2830
2831         CLK(NULL, "dclk_lcdc0_div", &dclk_lcdc0_div),
2832         CLK(NULL, "dclk_lcdc1_div", &dclk_lcdc1_div),
2833
2834         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2835         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2836         CLK1(hclk_lcdc0),
2837
2838         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2839         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2840         CLK1(hclk_lcdc1),
2841
2842         CLK(NULL, "cif_out_pll", &cif_out_pll),
2843         CLK(NULL, "cif0_out_div", &cif0_out_div),
2844         CLK(NULL, "cif1_out_div", &cif1_out_div),
2845
2846         CLK(NULL, "cif0_out", &cif0_out),
2847         CLK1(hclk_cif0),
2848
2849         CLK(NULL, "cif1_out", &cif1_out),
2850         CLK1(hclk_cif1),
2851
2852         CLK1(hclk_ipp),
2853         CLK1(hclk_rga),
2854         CLK1(hclk_hdmi),
2855
2856         CLK(NULL, "pclkin_cif0",        &pclkin_cif0),
2857         CLK(NULL, "inv_cif0",                   &inv_cif0),
2858         CLK(NULL, "cif0_in",                    &cif0_in),
2859         CLK(NULL, "pclkin_cif1", &pclkin_cif1),
2860         CLK(NULL, "inv_cif1",   &inv_cif1),
2861         CLK(NULL, "cif1_in",    &cif1_in),
2862         //CLK(NULL, "aclk_lcdc0",       &aclk_lcdc0),
2863         //CLK(NULL, "aclk_lcdc1",       &aclk_lcdc1),
2864         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2865         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2866         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2867         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2868         CLK1(gpu),
2869         CLK1(dma1),
2870         CLK1(l2mem_con),
2871         CLK1(intmem),
2872
2873         CLK1(aclk_strc_sys),
2874
2875         /*************************hclk_cpu***********************/
2876
2877         CLK1(rom),
2878         //CLK1(hclk_i2s0_2ch),
2879         //CLK1(hclk_i2s1_2ch),
2880         //CLK1(hclk_spdif),
2881         //CLK1(hclk_i2s_8ch),
2882         CLK1(hclk_cpubus),
2883         CLK1(hclk_ahb2apb),
2884         CLK1(hclk_vio_bus),
2885         //CLK1(hclk_lcdc0),
2886         //CLK1(hclk_lcdc1),
2887         //CLK1(hclk_cif0),
2888         //CLK1(hclk_cif1),
2889         //CLK1(hclk_ipp),
2890         //CLK1(hclk_rga),
2891         //CLK1(hclk_hdmi),
2892         //CLK1(hclk_vidoe_h2h,  hclk_cpu, ); ???
2893         /*************************pclk_cpu***********************/
2894         CLK1(pwm01),//pwm 0¡¢1
2895
2896         //CLK1(pclk_timer0),
2897         //CLK1(pclk_timer1),
2898         //CLK1(pclk_timer2),
2899
2900         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2901         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2902
2903         CLK1(gpio0),
2904         CLK1(gpio1),
2905         CLK1(gpio2),
2906         CLK1(gpio6),
2907         CLK1(efuse),
2908         CLK1(tzpc),
2909         //CLK1(pclk_uart0),
2910         //CLK1(pclk_uart1),
2911         CLK1(pclk_ddrupctl),
2912         CLK1(pclk_ddrpubl),
2913         CLK1(dbg),
2914         CLK1(grf),
2915         CLK1(pmu),
2916
2917         /*************************aclk_periph***********************/
2918
2919         CLK1(dma2),
2920         //CLK1(aclk_smc),
2921         CLK1(aclk_peri_niu),
2922         CLK1(aclk_cpu_peri),
2923         CLK1(aclk_peri_axi_matrix),
2924
2925         /*************************hclk_periph***********************/
2926         CLK1(hclk_peri_axi_matrix),
2927         CLK1(hclk_peri_ahb_arbi),
2928         CLK1(hclk_emem_peri),
2929         CLK1(hclk_mac),
2930         CLK1(nandc),
2931         //CLK1(hclk_usb_peri),
2932         //CLK1(hclk_usbotg0),
2933         //CLK1(hclk_usbotg1),
2934         //CLK1(hclk_hsadc),
2935         CLK1(hclk_pidfilter),
2936
2937         //CLK1(hclk_emmc),
2938         /*************************pclk_periph***********************/
2939         CLK1(pclk_peri_axi_matrix),
2940         CLK1(pwm23),
2941
2942         CLK1(wdt),
2943         //CLK1(pclk_spi0),
2944         //CLK1(pclk_spi1),
2945         //CLK1(pclk_uart2),
2946         //CLK1(pclk_uart3),
2947
2948         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2949         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2950         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2951
2952         CLK1(gpio3),
2953         CLK1(gpio4),
2954
2955         /*************************aclk_lcdc0***********************/
2956         //CLK1(aclk_vio0),
2957         CLK1(aclk_cif0),
2958         CLK1(aclk_ipp),
2959
2960         /*************************aclk_lcdc0***********************/
2961         //CLK1(aclk_vio1),
2962         CLK1(aclk_cif1),
2963         CLK1(aclk_rga),
2964         /************************power domain**********************/
2965         PD_CLK(pd_peri),
2966         PD_CLK(pd_display),
2967         PD_CLK(pd_video),
2968         PD_CLK(pd_lcdc0),
2969         PD_CLK(pd_lcdc1),
2970         PD_CLK(pd_cif0),
2971         PD_CLK(pd_cif1),
2972         PD_CLK(pd_rga),
2973         PD_CLK(pd_ipp),
2974         PD_CLK(pd_video),
2975         PD_CLK(pd_gpu),
2976         PD_CLK(pd_dbg),
2977 };
2978 static void __init rk30_init_enable_clocks(void)
2979 {
2980                 //clk_enable_nolock(&xin24m);
2981                 //clk_enable_nolock(&xin27m);
2982                 //clk_enable_nolock(&clk_12m);
2983                 //clk_enable_nolock(&arm_pll_clk);
2984                 //clk_enable_nolock(&ddr_pll_clk);
2985                 //clk_enable_nolock(&codec_pll_clk);
2986                 //clk_enable_nolock(&general_pll_clk);
2987                 //clk_enable_nolock(&clk_ddr);
2988
2989                 clk_enable_nolock(&clk_cpu);
2990                 clk_enable_nolock(&core_periph);
2991                 clk_enable_nolock(&aclk_cpu);
2992                 clk_enable_nolock(&hclk_cpu);
2993                 clk_enable_nolock(&pclk_cpu);
2994                 clk_enable_nolock(&atclk_cpu);
2995
2996                 #if 0
2997                 clk_enable_nolock(&clk_i2s_pll);
2998                 clk_enable_nolock(&clk_i2s0_div);
2999                 clk_enable_nolock(&clk_i2s0_frac_div);
3000                 clk_enable_nolock(&clk_i2s0);
3001                 clk_enable_nolock(&clk_hclk_i2s_8ch);
3002
3003                 clk_enable_nolock(&clk_i2s1_div);
3004                 clk_enable_nolock(&clk_i2s1_frac_div);
3005                 clk_enable_nolock(&clk_i2s1);
3006                 clk_enable_nolock(&clk_hclk_i2s0_2ch);
3007
3008                 clk_enable_nolock(&clk_i2s2_div);
3009                 clk_enable_nolock(&clk_i2s2_frac_div);
3010                 clk_enable_nolock(&clk_i2s2);
3011                 clk_enable_nolock(&clk_hclk_i2s1_2ch);
3012
3013                 clk_enable_nolock(&clk_spdif_div);
3014                 clk_enable_nolock(&clk_spdif_frac_div);
3015                 clk_enable_nolock(&clk_spdif);
3016                 clk_enable_nolock(&clk_hclk_spdif);
3017                 #endif
3018                 clk_enable_nolock(&aclk_periph);
3019                 clk_enable_nolock(&pclk_periph);
3020                 clk_enable_nolock(&hclk_periph);
3021
3022                 #if 0
3023                 clk_enable_nolock(&clk_spi0);
3024                 clk_enable_nolock(&clk_pclk_spi0);
3025
3026                 clk_enable_nolock(&clk_spi1);
3027                 clk_enable_nolock(&clk_pclk_spi1);
3028                 clk_enable_nolock(&clk_saradc);
3029                 clk_enable_nolock(&clk_pclk_saradc);
3030                 clk_enable_nolock(&clk_tsadc);
3031                 clk_enable_nolock(&clk_pclk_tsadc);
3032                 #endif
3033                 #if 0
3034                 clk_enable_nolock(&clk_otgphy0);
3035                 clk_enable_nolock(&clk_otgphy1);
3036                 clk_enable_nolock(&clk_hclk_usb_peri);
3037                 clk_enable_nolock(&clk_hclk_otg0);
3038                 clk_enable_nolock(&clk_hclk_otg1);
3039                 #endif
3040                 #if 0
3041                 clk_enable_nolock(&clk_smc);
3042                 clk_enable_nolock(&clk_aclk_smc);
3043
3044                 clk_enable_nolock(&clk_sdmmc);
3045                 clk_enable_nolock(&clk_hclk_sdmmc);
3046                 clk_enable_nolock(&clk_sdio);
3047                 clk_enable_nolock(&clk_hclk_sdio);
3048
3049                 clk_enable_nolock(&clk_emmc);
3050                 clk_enable_nolock(&clk_hclk_emmc);
3051
3052                 #endif
3053
3054         #if CONFIG_RK_DEBUG_UART == 0
3055                 clk_enable_nolock(&clk_uart0);
3056                 clk_enable_nolock(&clk_pclk_uart0);
3057         #elif CONFIG_RK_DEBUG_UART == 1
3058                 clk_enable_nolock(&clk_uart1);
3059                 clk_enable_nolock(&clk_pclk_uart1);
3060
3061         #elif CONFIG_RK_DEBUG_UART == 2
3062                 clk_enable_nolock(&clk_uart2);
3063                 clk_enable_nolock(&clk_pclk_uart2);
3064
3065         #elif CONFIG_RK_DEBUG_UART == 3
3066                 clk_enable_nolock(&clk_uart3);
3067                 clk_enable_nolock(&clk_pclk_uart3);
3068
3069         #endif
3070
3071                 #if 0
3072                 clk_enable_nolock(&clk_timer0);
3073                 clk_enable_nolock(&clk_pclk_timer0);
3074
3075                 clk_enable_nolock(&clk_timer1);
3076                 clk_enable_nolock(&clk_pclk_timer1);
3077
3078                 clk_enable_nolock(&clk_timer2);
3079                 clk_enable_nolock(&clk_pclk_timer2);
3080                 #endif
3081                 #if 0
3082                 clk_enable_nolock(&rmii_clkin);
3083                 clk_enable_nolock(&clk_mac_pll_div);
3084                 clk_enable_nolock(&clk_mac_ref);
3085                 clk_enable_nolock(&clk_mii_tx);
3086                 #endif
3087
3088                 #if 0
3089                 clk_enable_nolock(&clk_hsadc_pll_div);
3090                 clk_enable_nolock(&clk_hsadc_frac_div);
3091                 clk_enable_nolock(&clk_hsadc_ext);
3092                 clk_enable_nolock(&clk_hsadc);
3093                 clk_enable_nolock(&clk_hclk_hsadc);
3094                 #endif
3095
3096                 #if 0
3097                 clk_enable_nolock(&aclk_lcdc0_ipp_parent);
3098                 clk_enable_nolock(&aclk_lcdc1_rga_parent);
3099
3100                 clk_enable_nolock(&dclk_lcdc0_div);
3101                 clk_enable_nolock(&dclk_lcdc1_div);
3102
3103                 clk_enable_nolock(&dclk_lcdc0);
3104                 clk_enable_nolock(&clk_aclk_lcdc0);
3105                 clk_enable_nolock(&clk_hclk_lcdc0);
3106
3107                 clk_enable_nolock(&dclk_lcdc1);
3108                 clk_enable_nolock(&clk_aclk_lcdc1);
3109                 clk_enable_nolock(&clk_hclk_lcdc1);
3110
3111                 clk_enable_nolock(&cif_out_pll);
3112                 clk_enable_nolock(&cif0_out_div);
3113                 clk_enable_nolock(&cif1_out_div);
3114
3115                 clk_enable_nolock(&cif0_out);
3116                 clk_enable_nolock(&clk_hclk_cif0);
3117
3118                 clk_enable_nolock(&cif1_out);
3119                 clk_enable_nolock(&clk_hclk_cif1);
3120
3121                 clk_enable_nolock(&clk_hclk_ipp);
3122                 clk_enable_nolock(&clk_hclk_rga);
3123                 clk_enable_nolock(&clk_hclk_hdmi);
3124
3125                 clk_enable_nolock(&pclkin_cif0);
3126                 clk_enable_nolock(&inv_cif0);
3127                 clk_enable_nolock(&cif0_in);
3128                 clk_enable_nolock(&pclkin_cif1);
3129                 clk_enable_nolock(&inv_cif1);
3130                 clk_enable_nolock(&cif1_in);
3131                 //CLK(NULL, "aclk_lcdc0",       &aclk_lcdc0),
3132                 //CLK(NULL, "aclk_lcdc1",       &aclk_lcdc1),
3133                 clk_enable_nolock(&aclk_vepu);
3134                 clk_enable_nolock(&hclk_vepu);
3135                 clk_enable_nolock(&aclk_vdpu);
3136                 clk_enable_nolock(&hclk_vdpu);
3137                 clk_enable_nolock(&clk_gpu);
3138                 #endif
3139
3140                 clk_enable_nolock(&clk_dma1);
3141                 clk_enable_nolock(&clk_l2mem_con);
3142                 clk_enable_nolock(&clk_intmem);
3143
3144                 clk_enable_nolock(&clk_aclk_strc_sys);
3145
3146                 /*************************hclk_cpu***********************/
3147
3148                 clk_enable_nolock(&clk_rom);
3149
3150                 clk_enable_nolock(&clk_hclk_cpubus);
3151                 clk_enable_nolock(&clk_hclk_ahb2apb);
3152                 clk_enable_nolock(&clk_hclk_vio_bus);
3153
3154                 /*************************pclk_cpu***********************/
3155
3156                 //clk_enable_nolock(&clk_pwm01);//pwm 0¡¢1
3157                 #if 0
3158
3159
3160                 clk_enable_nolock(&clk_i2c0);
3161                 clk_enable_nolock(&clk_i2c1);
3162
3163                 clk_enable_nolock(&clk_gpio0);
3164                 clk_enable_nolock(&clk_gpio1);
3165                 clk_enable_nolock(&clk_gpio2);
3166                 clk_enable_nolock(&clk_gpio6);
3167                 clk_enable_nolock(&clk_efuse);
3168                 #endif
3169                 clk_enable_nolock(&clk_tzpc);
3170
3171                 //CLK1(pclk_uart0),
3172                 //CLK1(pclk_uart1),
3173                 clk_enable_nolock(&clk_pclk_ddrupctl);
3174                 clk_enable_nolock(&clk_pclk_ddrpubl);
3175                 clk_enable_nolock(&clk_dbg);
3176                 clk_enable_nolock(&clk_grf);
3177                 clk_enable_nolock(&clk_pmu);
3178
3179                 /*************************aclk_periph***********************/
3180
3181                 clk_enable_nolock(&clk_dma2);
3182                 //CLK1(aclk_smc),
3183                 clk_enable_nolock(&clk_aclk_peri_niu);
3184                 clk_enable_nolock(&clk_aclk_cpu_peri);
3185                 clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3186
3187                 /*************************hclk_periph***********************/
3188                 clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3189                 clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3190                 clk_enable_nolock(&clk_hclk_emem_peri);
3191                 clk_enable_nolock(&clk_hclk_mac);
3192                 clk_enable_nolock(&clk_nandc);
3193                 //CLK1(hclk_usb_peri),
3194                 //CLK1(hclk_usbotg0),
3195                 //CLK1(hclk_usbotg1),
3196                 //CLK1(hclk_hsadc),
3197                 clk_enable_nolock(&clk_hclk_pidfilter);
3198
3199                 /*************************pclk_periph***********************/
3200                 clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3201                 //clk_enable_nolock(&clk_pwm23);
3202
3203                 //clk_enable_nolock(&clk_wdt);
3204
3205                 #if 0
3206
3207                 clk_enable_nolock(&clk_i2c2);
3208                 clk_enable_nolock(&clk_i2c3);
3209                 clk_enable_nolock(&clk_i2c4);
3210
3211                 clk_enable_nolock(&clk_gpio3);
3212                 clk_enable_nolock(&clk_gpio4);
3213                 #endif
3214                 /*************************aclk_lcdc0***********************/
3215                 //clk_enable_nolock(&clk_aclk_vio0);
3216                 //clk_enable_nolock(&clk_aclk_cif0);
3217                 //clk_enable_nolock(&clk_aclk_ipp);
3218
3219                 /*************************aclk_lcdc0***********************/
3220                 //clk_enable_nolock(&clk_aclk_vio1);
3221                 //clk_enable_nolock(&clk_aclk_cif1);
3222                 //clk_enable_nolock(&clk_aclk_rga);
3223                 /************************power domain**********************/
3224 }
3225 static void periph_clk_set_init(void)
3226 {
3227         unsigned long aclk_p, hclk_p, pclk_p;
3228         unsigned long ppll_rate=general_pll_clk.rate;
3229         //aclk 148.5
3230
3231         /* general pll */
3232         switch (ppll_rate) {
3233         case 148500* KHZ:
3234                 aclk_p = 148500*KHZ;
3235                 hclk_p = aclk_p>>1;
3236                 pclk_p = aclk_p>>2;
3237                 break;
3238         case 1188*MHZ:
3239                 aclk_p = aclk_p>>3;// 0
3240                 hclk_p = aclk_p>>1;
3241                 pclk_p = aclk_p>>2;
3242
3243         case 297 * MHZ:
3244                 aclk_p = ppll_rate>>1;
3245                 hclk_p = aclk_p>>0;
3246                 pclk_p = aclk_p>>1;
3247                 break;
3248
3249         case 300 * MHZ:
3250                 aclk_p = ppll_rate>>1;
3251                 hclk_p = aclk_p>>0;
3252                 pclk_p = aclk_p>>1;
3253                 break;
3254         default:
3255                 aclk_p = 150 * MHZ;
3256                 hclk_p = 150 * MHZ;
3257                 pclk_p = 75 * MHZ;
3258                 break;
3259         }
3260         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3261         clk_set_rate_nolock(&aclk_periph, aclk_p);
3262         clk_set_rate_nolock(&hclk_periph, hclk_p);
3263         clk_set_rate_nolock(&pclk_periph, pclk_p);
3264 }
3265
3266
3267 void rk30_clock_common_i2s_init(void)
3268 {
3269         struct clk *max_clk,*min_clk;
3270         unsigned long i2s_rate;
3271         //20 times
3272         if(rk30_clock_flags&CLK_FLG_MAX_I2S_49152KHZ)
3273         {
3274                 i2s_rate=49152000;
3275         }else if(rk30_clock_flags&CLK_FLG_MAX_I2S_24576KHZ)
3276         {
3277                 i2s_rate=24576000;
3278         }
3279         else if(rk30_clock_flags&CLK_FLG_MAX_I2S_22579_2KHZ)
3280         {
3281                 i2s_rate=22579000;
3282         }
3283         else if(rk30_clock_flags&CLK_FLG_MAX_I2S_12288KHZ)
3284         {
3285                 i2s_rate=12288000;
3286         }
3287         else
3288         {
3289                 i2s_rate=49152000;
3290         }
3291
3292         if(((i2s_rate*20)<=general_pll_clk.rate)||!(general_pll_clk.rate%i2s_rate))
3293         {
3294                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3295         }
3296         else if(((i2s_rate*20)<=codec_pll_clk.rate)||!(codec_pll_clk.rate%i2s_rate))
3297         {
3298                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3299         }
3300         else
3301         {
3302                 if(general_pll_clk.rate>codec_pll_clk.rate)
3303                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3304                 else
3305                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3306         }
3307
3308
3309
3310
3311
3312
3313 }
3314 static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long cpll_rate)
3315 {
3316
3317         clk_set_rate_nolock(&clk_cpu, 816*MHZ);//816
3318         //general
3319         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3320         //code pll
3321         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3322
3323         //periph clk
3324         periph_clk_set_init();
3325
3326         //i2s
3327         rk30_clock_common_i2s_init();
3328
3329         // spi
3330         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3331         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3332
3333         // uart
3334         if(rk30_clock_flags&CLK_FLG_UART_1_3M)
3335                 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3336         else
3337                 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3338         //mac
3339         if(!(gpll_rate%(50*MHZ)))
3340                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3341         else if(!(ddr_pll_clk.rate%(50*MHZ)))
3342                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3343         else
3344                 CRU_PRINTK_ERR("mac can't get 50mhz\n");
3345
3346         //hsadc
3347         //auto pll sel
3348         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3349
3350         //lcdc1  hdmi
3351         clk_set_parent_nolock(&dclk_lcdc1_div, &general_pll_clk);
3352
3353         //lcdc0 lcd auto sel pll
3354         //clk_set_parent_nolock(&dclk_lcdc0_div, &general_pll_clk);
3355
3356         //cif
3357         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3358
3359         //axi lcdc auto sel
3360         //clk_set_parent_nolock(&aclk_lcdc0, &general_pll_clk);
3361         //clk_set_parent_nolock(&aclk_lcdc1, &general_pll_clk);
3362         clk_set_rate_nolock(&aclk_lcdc0_ipp_parent, 300*MHZ);
3363         clk_set_rate_nolock(&aclk_lcdc1_rga_parent, 300*MHZ);
3364
3365         //axi vepu auto sel
3366         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3367         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3368
3369         clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
3370         clk_set_rate_nolock(&aclk_vdpu, 300*MHZ);
3371         //gpu auto sel
3372         //clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
3373 }
3374
3375 static struct clk def_ops_clk={
3376         .get_parent=clksel_get_parent,
3377         .set_parent=clksel_set_parent,
3378 };
3379
3380 #ifdef CONFIG_PROC_FS
3381 struct clk_dump_ops dump_ops;
3382 #endif
3383
3384 static void clk_dump_regs(void);
3385
3386 void __init _rk30_clock_data_init(unsigned long gpll,unsigned long cpll,int flags)
3387 {
3388         struct clk_lookup *lk;
3389
3390         clk_register_dump_ops(&dump_ops);
3391         clk_register_default_ops_clk(&def_ops_clk);
3392         rk30_clock_flags=flags;
3393         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3394                 #ifdef RK30_CLK_OFFBOARD_TEST
3395                         rk30_clkdev_add(lk);
3396                 #else
3397                         clkdev_add(lk);
3398                 #endif
3399                 clk_register(lk->clk);
3400         }
3401         clk_recalculate_root_clocks_nolock();
3402
3403         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3404
3405         /*
3406          * Only enable those clocks we will need, let the drivers
3407          * enable other clocks as necessary
3408          */
3409         rk30_init_enable_clocks();
3410
3411         /*
3412          * Disable any unused clocks left on by the bootloader
3413          */
3414         //clk_disable_unused();
3415         rk30_clock_common_init(gpll,cpll);
3416         preset_lpj = loops_per_jiffy;
3417
3418         //gpio6_b7
3419         //regfile_writel(0xc0004000,0x10c);
3420         //cru_writel(0x07000000,CRU_MISC_CON);
3421
3422 }
3423
3424 void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags)
3425 {
3426         _rk30_clock_data_init(gpll,cpll,flags);
3427         rk30_dvfs_init();
3428 }
3429
3430 /*
3431  * You can override arm_clk rate with armclk= cmdline option.
3432  */
3433 static int __init armclk_setup(char *str)
3434 {
3435         get_option(&str, &armclk);
3436
3437         if (!armclk)
3438                 return 0;
3439         if (armclk < 10000)
3440                 armclk *= MHZ;
3441         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3442         return 0;
3443 }
3444 #ifndef RK30_CLK_OFFBOARD_TEST
3445 early_param("armclk", armclk_setup);
3446 #endif
3447
3448
3449
3450 #ifdef CONFIG_PROC_FS
3451
3452 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks)
3453 {
3454         struct clk* ck;
3455         int i;
3456         unsigned long rate = clk->rate;
3457         //CRU_PRINTK_DBG("dump_clock %s\n",clk->name);
3458         for (i = 0; i < deep; i++)
3459                 seq_printf(s, "    ");
3460
3461         seq_printf(s, "%-11s ", clk->name);
3462 #ifndef RK30_CLK_OFFBOARD_TEST
3463         if (clk->flags & IS_PD) {
3464                         seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3465         }
3466 #endif
3467         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3468                 int idx = clk->gate_idx;
3469                 u32 v;
3470                 v = cru_readl(CLK_GATE_CLKID_CONS(idx))&((0x1)<<(idx%16));
3471                 seq_printf(s, "%s ", v ? "off" : "on ");
3472         }
3473
3474         if (clk->pll)
3475         {
3476                 u32 pll_mode;
3477                 u32 pll_id=clk->pll->id;
3478                 pll_mode=cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3479                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3480                         seq_printf(s, "slow   ");
3481                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3482                         seq_printf(s, "normal ");
3483                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3484                         seq_printf(s, "deep   ");
3485
3486                 if(cru_readl(PLL_CONS(pll_id,3)) & PLL_BYPASS)
3487                         seq_printf(s, "bypass ");
3488         }
3489         else if(clk == &clk_ddr) {
3490                 rate = clk->recalc(clk);
3491         }
3492
3493         if (rate >= MHZ) {
3494                 if (rate % MHZ)
3495                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3496                 else
3497                         seq_printf(s, "%ld MHz", rate / MHZ);
3498         } else if (rate >= KHZ) {
3499                 if (rate % KHZ)
3500                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3501                 else
3502                         seq_printf(s, "%ld KHz", rate / KHZ);
3503         } else {
3504                 seq_printf(s, "%ld Hz", rate);
3505         }
3506
3507         seq_printf(s, " usecount = %d", clk->usecount);
3508
3509         if (clk->parent)
3510                 seq_printf(s, " parent = %s", clk->parent->name);
3511
3512         seq_printf(s, "\n");
3513
3514         list_for_each_entry(ck, root_clocks, node) {
3515                 if (ck->parent == clk)
3516                         dump_clock(s, ck, deep + 1,root_clocks);
3517         }
3518 }
3519
3520 static void dump_regs(struct seq_file *s)
3521 {
3522         int i=0;
3523         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3524         seq_printf(s, "\nPLLRegisters:\n");
3525         for(i=0;i<END_PLL_ID;i++)
3526         {
3527                 seq_printf(s,"pll%d        :cons:%x,%x,%x,%x\n",i,
3528                         cru_readl(PLL_CONS(i,0)),
3529                         cru_readl(PLL_CONS(i,1)),
3530                         cru_readl(PLL_CONS(i,2)),
3531                         cru_readl(PLL_CONS(i,3))
3532                         );
3533         }
3534                 seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3535
3536         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
3537         {
3538                 seq_printf(s,"CLKSEL%d     :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
3539         }
3540         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
3541         {
3542                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
3543         }
3544         seq_printf(s,"GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
3545         seq_printf(s,"GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
3546
3547         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
3548         {
3549                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
3550         }
3551         seq_printf(s,"CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
3552         seq_printf(s,"GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
3553
3554 }
3555
3556 void rk30_clk_dump_regs(void)
3557 {
3558         int i=0;
3559         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3560         printk("\nPLLRegisters:\n");
3561         for(i=0;i<END_PLL_ID;i++)
3562         {
3563                 printk("pll%d        :cons:%x,%x,%x,%x\n",i,
3564                         cru_readl(PLL_CONS(i,0)),
3565                         cru_readl(PLL_CONS(i,1)),
3566                         cru_readl(PLL_CONS(i,2)),
3567                         cru_readl(PLL_CONS(i,3))
3568                         );
3569         }
3570                 printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3571
3572         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
3573         {
3574                 printk("CLKSEL%d           :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
3575         }
3576         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
3577         {
3578                 printk("CLKGATE%d         :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
3579         }
3580         printk("GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
3581         printk("GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
3582
3583         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
3584         {
3585                 printk("SOFTRST%d         :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
3586         }
3587         printk("CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
3588         printk("GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
3589
3590 }
3591
3592
3593 #ifdef CONFIG_PROC_FS
3594 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
3595 struct clk_dump_ops dump_ops={
3596         .dump_clk=dump_clock,
3597         .dump_regs=dump_regs,
3598 };
3599 #endif
3600
3601
3602 #endif /* CONFIG_PROC_FS */
3603
3604
3605
3606
3607 #ifdef RK30_CLK_OFFBOARD_TEST
3608 struct clk *test_get_parent(struct clk *clk)
3609 {
3610         return clk->parent;
3611 }
3612
3613 void i2s_test(void)
3614 {
3615         struct clk *i2s_clk=&clk_i2s0;
3616
3617         clk_enable_nolock(i2s_clk);
3618
3619         clk_set_rate_nolock(i2s_clk, 12288000);
3620         printk("int %s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3621         clk_set_rate_nolock(i2s_clk, 297*MHZ/2);
3622         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3623         clk_set_rate_nolock(i2s_clk, 12*MHZ);
3624         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3625
3626 }
3627
3628 void uart_test(void)
3629 {
3630         struct clk *uart_clk=&clk_uart0;
3631
3632         clk_enable_nolock(uart_clk);
3633
3634         clk_set_rate_nolock(uart_clk, 12288000);
3635         printk("int %s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3636         clk_set_rate_nolock(uart_clk, 297*MHZ/2);
3637         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3638         clk_set_rate_nolock(uart_clk, 12*MHZ);
3639         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3640
3641 }
3642 void hsadc_test(void)
3643 {
3644         struct clk *hsadc_clk=&clk_hsadc;
3645
3646         printk("******************hsadc_test**********************\n");
3647         clk_enable_nolock(hsadc_clk);
3648
3649         clk_set_rate_nolock(hsadc_clk, 12288000);
3650         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3651
3652
3653         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3654         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3655
3656         clk_set_rate_nolock(hsadc_clk, 300*MHZ/2);
3657
3658         clk_set_rate_nolock(hsadc_clk, 296*MHZ/2);
3659
3660         printk("******************hsadc out clock**********************\n");
3661
3662         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3663         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3664         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3665         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3666
3667
3668
3669 }
3670
3671 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3672 {
3673         //arm
3674         printk("*********arm_pll_clk***********\n");
3675         clk_set_rate_nolock(&arm_pll_clk, 816*MHZ);
3676
3677         printk("*********set clk_cpu parent***********\n");
3678         clk_set_parent_nolock(&clk_cpu, &arm_pll_clk);
3679         clk_set_rate_nolock(&clk_cpu, 504*MHZ);
3680
3681         //general
3682         printk("*********general_pll_clk***********\n");
3683         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3684
3685         //code pll
3686         printk("*********codec_pll_clk***********\n");
3687         clk_set_rate_nolock(&codec_pll_clk, 600*MHZ);
3688
3689
3690         printk("*********periph_clk_set_init***********\n");
3691         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3692         periph_clk_set_init();
3693
3694         #if 0 //
3695                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3696         #else
3697                 printk("*********clk i2s***********\n");
3698                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3699                 printk("common %s parent is %s\n",clk_i2s_pll.name,test_get_parent(&clk_i2s_pll)->name);
3700                 i2s_test();
3701         #endif
3702 // spi
3703         clk_enable_nolock(&clk_spi0);
3704         clk_set_rate_nolock(&clk_spi0, 30*MHZ);
3705         printk("common %s parent is %s\n",clk_spi0.name,test_get_parent(&clk_spi0)->name);
3706 //saradc
3707         clk_enable_nolock(&clk_saradc);
3708         clk_set_rate_nolock(&clk_saradc, 6*MHZ);
3709         printk("common %s parent is %s\n",clk_saradc.name,test_get_parent(&clk_saradc)->name);
3710 //sdio
3711         clk_enable_nolock(&clk_sdio);
3712         clk_set_rate_nolock(&clk_sdio, 50*MHZ);
3713         printk("common %s parent is %s\n",clk_sdio.name,test_get_parent(&clk_sdio)->name);
3714 // uart
3715         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3716         uart_test();
3717 //mac
3718         printk("*********mac***********\n");
3719
3720         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3721         printk("common %s parent is %s\n",clk_mac_pll_div.name,test_get_parent(&clk_mac_pll_div)->name);
3722
3723         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3724         clk_set_rate_nolock(&clk_mac_ref, 50*MHZ);
3725         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3726
3727         printk("*********mac mii set***********\n");
3728         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3729         clk_set_rate_nolock(&clk_mac_ref, 20*MHZ);
3730         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3731 //hsadc
3732         printk("*********hsadc 1***********\n");
3733         //auto pll
3734         hsadc_test();
3735 //lcdc
3736         clk_enable_nolock(&dclk_lcdc0);
3737
3738         clk_set_rate_nolock(&dclk_lcdc0, 60*MHZ);
3739         clk_set_rate_nolock(&dclk_lcdc0, 27*MHZ);
3740
3741 //cif
3742         clk_enable_nolock(&cif0_out);
3743
3744         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3745         printk("common %s parent is %s\n",cif_out_pll.name,test_get_parent(&cif_out_pll)->name);
3746
3747         clk_set_rate_nolock(&cif0_out, 60*MHZ);
3748         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3749
3750         clk_set_rate_nolock(&cif0_out, 24*MHZ);
3751         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3752 //cif_in
3753         clk_enable_nolock(&cif0_in);
3754         clk_set_rate_nolock(&cif0_in, 24*MHZ);
3755 //axi lcdc
3756         clk_enable_nolock(&aclk_lcdc0);
3757         clk_set_rate_nolock(&aclk_lcdc0, 150*MHZ);
3758         printk("common %s parent is %s\n",aclk_lcdc0.name,test_get_parent(&aclk_lcdc0)->name);
3759 //axi vepu
3760         clk_enable_nolock(&aclk_vepu);
3761         clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
3762         printk("common %s parent is %s\n",aclk_vepu.name,test_get_parent(&aclk_vepu)->name);
3763
3764         clk_set_rate_nolock(&hclk_vepu, 300*MHZ);
3765         printk("common %s parent is %s\n",hclk_vepu.name,test_get_parent(&hclk_vepu)->name);
3766
3767         printk("test end\n");
3768
3769         /* arm pll
3770         clk_set_rate_nolock(&arm_pll_clk, armclk);
3771         clk_set_rate_nolock(&clk_cpu,   armclk);//pll:core =1:1
3772         */
3773         //
3774         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3775         //
3776         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3777         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3778
3779 }
3780
3781
3782
3783
3784
3785 static LIST_HEAD(rk30_clocks);
3786 static DEFINE_MUTEX(rk30_clocks_mutex);
3787
3788 static inline int __rk30clk_get(struct clk *clk)
3789 {
3790         return 1;
3791 }
3792 void rk30_clkdev_add(struct clk_lookup *cl)
3793 {
3794         mutex_lock(&rk30_clocks_mutex);
3795         list_add_tail(&cl->node, &rk30_clocks);
3796         mutex_unlock(&rk30_clocks_mutex);
3797 }
3798 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id)
3799 {
3800         struct clk_lookup *p, *cl = NULL;
3801         int match, best = 0;
3802
3803         list_for_each_entry(p, &rk30_clocks, node) {
3804                 match = 0;
3805                 if (p->dev_id) {
3806                         if (!dev_id || strcmp(p->dev_id, dev_id))
3807                                 continue;
3808                         match += 2;
3809                 }
3810                 if (p->con_id) {
3811                         if (!con_id || strcmp(p->con_id, con_id))
3812                                 continue;
3813                         match += 1;
3814                 }
3815
3816                 if (match > best) {
3817                         cl = p;
3818                         if (match != 3)
3819                                 best = match;
3820                         else
3821                                 break;
3822                 }
3823         }
3824         return cl;
3825 }
3826
3827 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id)
3828 {
3829         struct clk_lookup *cl;
3830
3831         mutex_lock(&rk30_clocks_mutex);
3832         cl = rk30_clk_find(dev_id, con_id);
3833         if (cl && !__rk30clk_get(cl->clk))
3834                 cl = NULL;
3835         mutex_unlock(&rk30_clocks_mutex);
3836
3837         return cl ? cl->clk : ERR_PTR(-ENOENT);
3838 }
3839 //EXPORT_SYMBOL(rk30_clk_get_sys);
3840
3841 struct clk *rk30_clk_get(struct device *dev, const char *con_id)
3842 {
3843         const char *dev_id = dev ? dev_name(dev) : NULL;
3844         return rk30_clk_get_sys(dev_id, con_id);
3845 }
3846 //EXPORT_SYMBOL(rk30_clk_get);
3847
3848
3849 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3850
3851 void rk30_clocks_test(void)
3852 {
3853     struct clk *test_gpll;
3854         test_gpll=rk30_clk_get(NULL,"general_pll");
3855         if(test_gpll)
3856         {
3857                 rk30_clk_set_rate(test_gpll,297*2*MHZ);
3858                 printk("gpll rate=%lu\n",test_gpll->rate);
3859         }
3860         //while(1);
3861 }
3862
3863 void __init rk30_clock_init_test(void){
3864
3865         rk30_clock_init(periph_pll_297mhz,codec_pll_360mhz,max_i2s_12288khz);
3866         //while(1);
3867 }
3868
3869
3870 #endif
3871
3872