2 * arch/arm/mach-rk30/ddr.c
4 * Function Driver for DDR controller
6 * Copyright (C) 2011 Fuzhou Rockchip Electronics Co.,Ltd
14 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/clk.h>
19 #include <asm/cacheflush.h>
20 #include <asm/tlbflush.h>
22 #include <mach/sram.h>
25 #include <plat/efuse.h>
26 #include <linux/rk_fb.h>
27 //#include <linux/delay.h>
29 typedef uint32_t uint32;
31 //#define ENABLE_DDR_CLCOK_GPLL_PATH //for RK3188
33 #define DDR3_DDR2_ODT_DLL_DISABLE_FREQ (333)
34 #define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
35 #define PD_IDLE (0X40) //unit:DDR clk cycle, and 0 for disable auto power-down
37 #if (DDR3_DDR2_ODT_DLL_DISABLE_FREQ > 333)
41 #define PMU_BASE_ADDR RK30_PMU_BASE
42 #define SDRAMC_BASE_ADDR RK30_DDR_PCTL_BASE
43 #define DDR_PUBL_BASE RK30_DDR_PUBL_BASE
44 #define CRU_BASE_ADDR RK30_CRU_BASE
45 #define REG_FILE_BASE_ADDR RK30_GRF_BASE
46 #define SysSrv_DdrConf (RK30_CPU_AXI_BUS_BASE+0x08)
47 #define SysSrv_DdrTiming (RK30_CPU_AXI_BUS_BASE+0x0c)
48 #define SysSrv_DdrMode (RK30_CPU_AXI_BUS_BASE+0x10)
49 #define SysSrv_ReadLatency (RK30_CPU_AXI_BUS_BASE+0x14)
51 #define ddr_print(x...) printk( "DDR DEBUG: " x )
53 /***********************************
55 ***********************************/
56 //MR0 (Device Information)
57 #define LPDDR2_DAI (0x1) // 0:DAI complete, 1:DAI still in progress
58 #define LPDDR2_DI (0x1<<1) // 0:S2 or S4 SDRAM, 1:NVM
59 #define LPDDR2_DNVI (0x1<<2) // 0:DNV not supported, 1:DNV supported
60 #define LPDDR2_RZQI (0x3<<3) // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
61 // 10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.
63 //MR1 (Device Feature)
64 #define LPDDR2_BL4 (0x2)
65 #define LPDDR2_BL8 (0x3)
66 #define LPDDR2_BL16 (0x4)
67 #define LPDDR2_nWR(n) (((n)-2)<<5)
69 //MR2 (Device Feature 2)
70 #define LPDDR2_RL3_WL1 (0x1)
71 #define LPDDR2_RL4_WL2 (0x2)
72 #define LPDDR2_RL5_WL2 (0x3)
73 #define LPDDR2_RL6_WL3 (0x4)
74 #define LPDDR2_RL7_WL4 (0x5)
75 #define LPDDR2_RL8_WL4 (0x6)
77 //MR3 (IO Configuration 1)
78 #define LPDDR2_DS_34 (0x1)
79 #define LPDDR2_DS_40 (0x2)
80 #define LPDDR2_DS_48 (0x3)
81 #define LPDDR2_DS_60 (0x4)
82 #define LPDDR2_DS_80 (0x6)
83 #define LPDDR2_DS_120 (0x7) //optional
85 //MR4 (Device Temperature)
86 #define LPDDR2_tREF_MASK (0x7)
87 #define LPDDR2_4_tREF (0x1)
88 #define LPDDR2_2_tREF (0x2)
89 #define LPDDR2_1_tREF (0x3)
90 #define LPDDR2_025_tREF (0x5)
91 #define LPDDR2_025_tREF_DERATE (0x6)
93 #define LPDDR2_TUF (0x1<<7)
95 //MR8 (Basic configuration 4)
96 #define LPDDR2_S4 (0x0)
97 #define LPDDR2_S2 (0x1)
98 #define LPDDR2_N (0x2)
99 #define LPDDR2_Density(mr8) (8<<(((mr8)>>2)&0xf)) // Unit:MB
100 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
103 #define LPDDR2_ZQINIT (0xFF)
104 #define LPDDR2_ZQCL (0xAB)
105 #define LPDDR2_ZQCS (0x56)
106 #define LPDDR2_ZQRESET (0xC3)
108 //MR16 (PASR Bank Mask)
110 #define LPDDR2_PASR_Full (0x0)
111 #define LPDDR2_PASR_1_2 (0x1)
112 #define LPDDR2_PASR_1_4 (0x2)
113 #define LPDDR2_PASR_1_8 (0x3)
115 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
117 //MR32 (DQ Calibration Pattern A)
119 //MR40 (DQ Calibration Pattern B)
121 /***********************************
123 ***********************************/
126 #define DDR3_BC4_8 (1)
128 #define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
129 #define DDR3_WR(n) (((n)&0x7)<<9)
130 #define DDR3_DLL_RESET (1<<8)
131 #define DDR3_DLL_DeRESET (0<<8)
134 #define DDR3_DLL_ENABLE (0)
135 #define DDR3_DLL_DISABLE (1)
136 #define DDR3_MR1_AL(n) (((n)&0x3)<<3)
138 #define DDR3_DS_40 (0)
139 #define DDR3_DS_34 (1<<1)
140 #define DDR3_Rtt_Nom_DIS (0)
141 #define DDR3_Rtt_Nom_60 (1<<2)
142 #define DDR3_Rtt_Nom_120 (1<<6)
143 #define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
146 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
147 #define DDR3_Rtt_WR_DIS (0)
148 #define DDR3_Rtt_WR_60 (1<<9)
149 #define DDR3_Rtt_WR_120 (2<<9)
151 /***********************************
153 ***********************************/
154 //MR; //Mode Register
157 #define DDR2_CL(n) (((n)&0x7)<<4)
158 #define DDR2_WR(n) ((((n)-1)&0x7)<<9)
159 #define DDR2_DLL_RESET (1<<8)
160 #define DDR2_DLL_DeRESET (0<<8)
162 //EMR; //Extended Mode Register
163 #define DDR2_DLL_ENABLE (0)
164 #define DDR2_DLL_DISABLE (1)
166 #define DDR2_STR_FULL (0)
167 #define DDR2_STR_REDUCE (1<<1)
168 #define DDR2_AL(n) (((n)&0x7)<<3)
169 #define DDR2_Rtt_Nom_DIS (0)
170 #define DDR2_Rtt_Nom_150 (0x40)
171 #define DDR2_Rtt_Nom_75 (0x4)
172 #define DDR2_Rtt_Nom_50 (0x44)
174 /***********************************
176 ***********************************/
180 #define mDDR_CL(n) (((n)&0x7)<<4)
182 #define mDDR_DS_Full (0)
183 #define mDDR_DS_1_2 (1<<5)
184 #define mDDR_DS_1_4 (2<<5)
185 #define mDDR_DS_1_8 (3<<5)
186 #define mDDR_DS_3_4 (4<<5)
190 #define idle_req_cpu_cfg (1<<1)
191 #define idle_req_peri_cfg (1<<2)
192 #define idle_req_gpu_cfg (1<<3)
193 #define idle_req_video_cfg (1<<4)
194 #define idle_req_vio_cfg (1<<5)
195 #define idle_req_core_cfg (1<<14)
196 #define idle_req_dma_cfg (1<<16)
199 #define idle_cpu (1<<26)
200 #define idle_peri (1<<25)
201 #define idle_gpu (1<<24)
202 #define idle_video (1<<23)
203 #define idle_vio (1<<22)
204 #define idle_core (1<<15)
205 #define idle_dma (1<<14)
207 #define pd_a9_0_pwr_st (1<<0)
208 #define pd_a9_1_pwr_st (1<<1)
209 #define pd_peri_pwr_st (1<<6)
210 #define pd_vio_pwr_st (1<<7)
211 #define pd_video_pwr_st (1<<8)
212 #define pd_gpu_pwr_st (1<<9)
216 typedef volatile struct tagPMU_FILE
218 uint32 PMU_WAKEUP_CFG[2];
219 uint32 PMU_PWRDN_CON;
227 uint32 PMU_DDRIO_PWRON_CNT;
228 uint32 PMU_WAKEUP_RST_CLR_CNT;
229 uint32 PMU_SCU_PWRDWN_CNT;
230 uint32 PMU_SCU_PWRUP_CNT;
231 uint32 PMU_MISC_CON1;
232 uint32 PMU_GPIO6_CON;
233 uint32 PMU_PMU_SYS_REG[4];
234 } PMU_FILE, *pPMU_FILE;
236 #define pPMU_Reg ((pPMU_FILE)PMU_BASE_ADDR)
238 #define PLL_RESET (((0x1<<5)<<16) | (0x1<<5))
239 #define PLL_DE_RESET (((0x1<<5)<<16) | (0x0<<5))
240 #define NR(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
241 #define NO(n) ((0xF<<16) | ((n)-1))
242 #define NF(n) ((0x1FFF<<16) | ((n)-1))
243 #define NB(n) ((0xFFF<<16) | ((n)-1))
246 #define PLL_RESET_RK3066B (((0x1<<1)<<16) | (0x1<<1))
247 #define PLL_DE_RESET_RK3066B (((0x1<<1)<<16) | (0x0<<1))
248 #define NR_RK3066B(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
249 #define NO_RK3066B(n) ((0x3F<<16) | ((n)-1))
250 #define NF_RK3066B(n) ((0xFFFF<<16) | ((n)-1))
253 typedef volatile struct tagCRU_STRUCT
255 uint32 CRU_PLL_CON[4][4];
257 uint32 CRU_CLKSEL_CON[35];
258 uint32 CRU_CLKGATE_CON[10];
260 uint32 CRU_GLB_SRST_FST_VALUE;
261 uint32 CRU_GLB_SRST_SND_VALUE;
263 uint32 CRU_SOFTRST_CON[9];
266 uint32 CRU_GLB_CNT_TH;
267 } CRU_REG, *pCRU_REG;
269 #define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
271 #define bank2_to_rank_en ((1<<2) | ((1<<2)<<16))
272 #define bank2_to_rank_dis ((0<<2) | ((1<<2)<<16))
273 #define rank_to_row15_en ((1<<1) | ((1<<1)<<16))
274 #define rank_to_row15_dis ((0<<1) | ((1<<1)<<16))
276 typedef struct tagGPIO_LH
282 typedef struct tagGPIO_IOMUX
291 typedef volatile struct tagREG_FILE
293 GPIO_LH_T GRF_GPIO_DIR[7];
294 GPIO_LH_T GRF_GPIO_DO[7];
295 GPIO_LH_T GRF_GPIO_EN[7];
296 GPIO_IOMUX_T GRF_GPIO_IOMUX[7];
297 GPIO_LH_T GRF_GPIO_PULL[7];
298 uint32 GRF_SOC_CON[3];
299 uint32 GRF_SOC_STATUS0;
300 uint32 GRF_DMAC1_CON[3];
301 uint32 GRF_DMAC2_CON[4];
302 uint32 GRF_UOC0_CON[3];
303 uint32 GRF_UOC1_CON[4];
304 uint32 GRF_DDRC_CON0;
305 uint32 GRF_DDRC_STAT;
306 uint32 reserved[(0x1c8-0x1a0)/4];
307 uint32 GRF_OS_REG[4];
308 } REG_FILE, *pREG_FILE;
310 #define pGRF_Reg ((pREG_FILE)REG_FILE_BASE_ADDR)
313 typedef volatile struct tagREG_FILE_RK3066B
315 GPIO_LH_T GRF_GPIO_DIR[4];
316 GPIO_LH_T GRF_GPIO_DO[4];
317 GPIO_LH_T GRF_GPIO_EN[4];
318 GPIO_IOMUX_T GRF_GPIO_IOMUX[4];
319 uint32 GRF_SOC_CON[3];
320 uint32 GRF_SOC_STATUS0;
321 uint32 GRF_DMAC0_CON[3];
322 uint32 GRF_DMAC1_CON[4];
323 uint32 reserved0[(0xec-0xcc)/4];
324 uint32 GRF_DDRC_CON0;
325 uint32 GRF_DDRC_STAT;
326 uint32 GRF_IO_CON[5];
328 uint32 GRF_UOC0_CON[4];
329 uint32 GRF_UOC1_CON[4];
330 uint32 GRF_UOC2_CON[2];
332 uint32 GRF_UOC3_CON[2];
333 uint32 GRF_HSIC_STAT;
334 uint32 GRF_OS_REG[8];
335 } REG_FILE_RK3066B, *pREG_FILE_RK3066B;
337 #define pGRF_Reg_RK3066B ((pREG_FILE_RK3066B)REG_FILE_BASE_ADDR)
340 #define INIT_STATE (0)
341 #define CFG_STATE (1)
343 #define SLEEP_STATE (3)
344 #define WAKEUP_STATE (4)
349 #define Config_req (2)
351 #define Access_req (4)
352 #define Low_power (5)
353 #define Low_power_entry_req (6)
354 #define Low_power_exit_req (7)
357 #define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
358 #define pd_idle(n) ((n)<<8)
359 #define mddr_en (2<<22)
360 #define lpddr2_en (3<<22)
361 #define ddr2_en (0<<5)
362 #define ddr3_en (1<<5)
363 #define lpddr2_s2 (0<<6)
364 #define lpddr2_s4 (1<<6)
365 #define mddr_lpddr2_bl_2 (0<<20)
366 #define mddr_lpddr2_bl_4 (1<<20)
367 #define mddr_lpddr2_bl_8 (2<<20)
368 #define mddr_lpddr2_bl_16 (3<<20)
369 #define ddr2_ddr3_bl_4 (0)
370 #define ddr2_ddr3_bl_8 (1)
371 #define tfaw_cfg(n) (((n)-4)<<18)
372 #define pd_exit_slow (0<<17)
373 #define pd_exit_fast (1<<17)
374 #define pd_type(n) ((n)<<16)
375 #define two_t_en(n) ((n)<<3)
376 #define bl8int_en(n) ((n)<<2)
377 #define cke_or_en(n) ((n)<<1)
380 #define power_up_start (1<<0)
383 #define power_up_done (1<<0)
386 #define dfi_init_complete (1<<0)
389 #define cmd_tstat (1<<0)
392 #define cmd_tstat_en (1<<1)
395 #define Deselect_cmd (0)
405 #define lpddr2_op(n) ((n)<<12)
406 #define lpddr2_ma(n) ((n)<<4)
408 #define bank_addr(n) ((n)<<17)
409 #define cmd_addr(n) ((n)<<4)
411 #define start_cmd (1u<<31)
413 typedef union STAT_Tag
418 unsigned ctl_stat : 3;
419 unsigned reserved3 : 1;
420 unsigned lp_trig : 3;
421 unsigned reserved7_31 : 25;
425 typedef union SCFG_Tag
430 unsigned hw_low_power_en : 1;
431 unsigned reserved1_5 : 5;
432 unsigned nfifo_nif1_dis : 1;
433 unsigned reserved7 : 1;
434 unsigned bbflags_timing : 4;
435 unsigned reserved12_31 : 20;
439 /* DDR Controller register struct */
440 typedef volatile struct DDR_REG_Tag
442 //Operational State, Control, and Status Registers
443 SCFG_T SCFG; //State Configuration Register
444 volatile uint32 SCTL; //State Control Register
445 STAT_T STAT; //State Status Register
446 volatile uint32 INTRSTAT; //Interrupt Status Register
447 uint32 reserved0[(0x40-0x10)/4];
448 //Initailization Control and Status Registers
449 volatile uint32 MCMD; //Memory Command Register
450 volatile uint32 POWCTL; //Power Up Control Registers
451 volatile uint32 POWSTAT; //Power Up Status Register
452 volatile uint32 CMDTSTAT; //Command Timing Status Register
453 volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
454 uint32 reserved1[(0x60-0x54)/4];
455 volatile uint32 MRRCFG0; //MRR Configuration 0 Register
456 volatile uint32 MRRSTAT0; //MRR Status 0 Register
457 volatile uint32 MRRSTAT1; //MRR Status 1 Register
458 uint32 reserved2[(0x7c-0x6c)/4];
459 //Memory Control and Status Registers
460 volatile uint32 MCFG1; //Memory Configuration 1 Register
461 volatile uint32 MCFG; //Memory Configuration Register
462 volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
463 volatile uint32 MSTAT; //Memory Status Register
464 volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
466 //DTU Control and Status Registers
467 volatile uint32 DTUPDES; //DTU Status Register
468 volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
469 volatile uint32 DTUNE; //DTU Number of Errors Register
470 volatile uint32 DTUPRD0; //DTU Parallel Read 0
471 volatile uint32 DTUPRD1; //DTU Parallel Read 1
472 volatile uint32 DTUPRD2; //DTU Parallel Read 2
473 volatile uint32 DTUPRD3; //DTU Parallel Read 3
474 volatile uint32 DTUAWDT; //DTU Address Width
475 uint32 reserved4[(0xc0-0xb4)/4];
476 //Memory Timing Registers
477 volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
478 volatile uint32 TINIT; //t_init Timing Register
479 volatile uint32 TRSTH; //Reset High Time Register
480 volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
481 volatile uint32 TREFI; //t_refi Timing Register
482 volatile uint32 TMRD; //t_mrd Timing Register
483 volatile uint32 TRFC; //t_rfc Timing Register
484 volatile uint32 TRP; //t_rp Timing Register
485 volatile uint32 TRTW; //t_rtw Timing Register
486 volatile uint32 TAL; //AL Latency Register
487 volatile uint32 TCL; //CL Timing Register
488 volatile uint32 TCWL; //CWL Register
489 volatile uint32 TRAS; //t_ras Timing Register
490 volatile uint32 TRC; //t_rc Timing Register
491 volatile uint32 TRCD; //t_rcd Timing Register
492 volatile uint32 TRRD; //t_rrd Timing Register
493 volatile uint32 TRTP; //t_rtp Timing Register
494 volatile uint32 TWR; //t_wr Timing Register
495 volatile uint32 TWTR; //t_wtr Timing Register
496 volatile uint32 TEXSR; //t_exsr Timing Register
497 volatile uint32 TXP; //t_xp Timing Register
498 volatile uint32 TXPDLL; //t_xpdll Timing Register
499 volatile uint32 TZQCS; //t_zqcs Timing Register
500 volatile uint32 TZQCSI; //t_zqcsi Timing Register
501 volatile uint32 TDQS; //t_dqs Timing Register
502 volatile uint32 TCKSRE; //t_cksre Timing Register
503 volatile uint32 TCKSRX; //t_cksrx Timing Register
504 volatile uint32 TCKE; //t_cke Timing Register
505 volatile uint32 TMOD; //t_mod Timing Register
506 volatile uint32 TRSTL; //Reset Low Timing Register
507 volatile uint32 TZQCL; //t_zqcl Timing Register
508 volatile uint32 TMRR; //t_mrr Timing Register
509 volatile uint32 TCKESR; //t_ckesr Timing Register
510 volatile uint32 TDPD; //t_dpd Timing Register
511 uint32 reserved5[(0x180-0x148)/4];
512 //ECC Configuration, Control, and Status Registers
513 volatile uint32 ECCCFG; //ECC Configuration Register
514 volatile uint32 ECCTST; //ECC Test Register
515 volatile uint32 ECCCLR; //ECC Clear Register
516 volatile uint32 ECCLOG; //ECC Log Register
517 uint32 reserved6[(0x200-0x190)/4];
518 //DTU Control and Status Registers
519 volatile uint32 DTUWACTL; //DTU Write Address Control Register
520 volatile uint32 DTURACTL; //DTU Read Address Control Register
521 volatile uint32 DTUCFG; //DTU Configuration Control Register
522 volatile uint32 DTUECTL; //DTU Execute Control Register
523 volatile uint32 DTUWD0; //DTU Write Data 0
524 volatile uint32 DTUWD1; //DTU Write Data 1
525 volatile uint32 DTUWD2; //DTU Write Data 2
526 volatile uint32 DTUWD3; //DTU Write Data 3
527 volatile uint32 DTUWDM; //DTU Write Data Mask
528 volatile uint32 DTURD0; //DTU Read Data 0
529 volatile uint32 DTURD1; //DTU Read Data 1
530 volatile uint32 DTURD2; //DTU Read Data 2
531 volatile uint32 DTURD3; //DTU Read Data 3
532 volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
533 volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
534 volatile uint32 DTUEAF; //DTU Error Address FIFO
535 //DFI Control Registers
536 volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
537 volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
538 volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
539 volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
540 //DFI Write Data Registers
541 volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
542 volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
543 uint32 reserved7[(0x260-0x258)/4];
544 volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
545 volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
546 uint32 reserved8[(0x270-0x268)/4];
547 //DFI Update Registers
548 volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
549 volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
550 volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
551 volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
552 volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
553 volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
554 volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
556 volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
557 volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
558 volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
559 uint32 reserved10[(0x2ac-0x29c)/4];
560 volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
561 volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
562 volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
563 volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
564 volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
565 //DFI Status Registers
566 volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
567 volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
568 volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
570 volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
571 volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
572 volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
573 volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
574 volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
575 uint32 reserved12[(0x2f0-0x2e4)/4];
576 //DFI Low Power Registers
577 volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
578 uint32 reserved13[(0x300-0x2f4)/4];
579 //DFI Training 2 Registers
580 volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
581 volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
582 volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
583 volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
584 volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
585 volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
586 volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
587 volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
588 volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
589 volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
590 volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
591 volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
592 volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
593 volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
594 volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
595 volatile uint32 DFITRCMD; //DFI Training Command Register
596 uint32 reserved14[(0x3f8-0x340)/4];
597 //IP Status Registers
598 volatile uint32 IPVR; //IP Version Register
599 volatile uint32 IPTR; //IP Type Register
600 }DDR_REG_T, *pDDR_REG_T;
602 #define pDDR_Reg ((pDDR_REG_T)SDRAMC_BASE_ADDR)
606 #define DLLSRST (1<<1)
607 #define DLLLOCK (1<<2)
609 #define ITMSRST (1<<4)
610 #define DRAMRST (1<<5)
611 #define DRAMINIT (1<<6)
613 #define EYETRN (1<<8)
615 #define DLLBYP (1<<17)
616 #define CTLDINIT (1<<18)
617 #define CLRSR (1<<28)
618 #define LOCKBYP (1<<29)
619 #define ZCALBYP (1<<30)
620 #define INITBYP (1u<<31)
623 #define DFTLMT(n) ((n)<<3)
624 #define DFTCMP(n) ((n)<<2)
625 #define DQSCFG(n) ((n)<<1)
626 #define ITMDMD(n) ((n)<<0)
627 #define RANKEN(n) ((n)<<18)
631 #define DLDONE (1<<1)
632 #define ZCDONE (1<<2)
633 #define DIDONE (1<<3)
634 #define DTDONE (1<<4)
636 #define DTIERR (1<<6)
637 #define DFTERR (1<<7)
641 #define tITMSRST(n) ((n)<<18)
642 #define tDLLLOCK(n) ((n)<<6)
643 #define tDLLSRST(n) ((n)<<0)
646 #define tDINIT1(n) ((n)<<19)
647 #define tDINIT0(n) ((n)<<0)
650 #define tDINIT3(n) ((n)<<17)
651 #define tDINIT2(n) ((n)<<0)
654 #define DQSGE(n) ((n)<<8)
655 #define DQSGX(n) ((n)<<5)
657 typedef union DCR_Tag
663 unsigned DDR8BNK : 1;
666 unsigned DDRTYPE : 2;
667 unsigned reserved10_26 : 17;
677 typedef volatile struct DATX8_REG_Tag
679 volatile uint32 DXGCR; //DATX8 General Configuration Register
680 volatile uint32 DXGSR[2]; //DATX8 General Status Register
681 volatile uint32 DXDLLCR; //DATX8 DLL Control Register
682 volatile uint32 DXDQTR; //DATX8 DQ Timing Register
683 volatile uint32 DXDQSTR; //DATX8 DQS Timing Register
684 uint32 reserved[0x80-0x76];
687 /* DDR PHY register struct */
688 typedef volatile struct DDRPHY_REG_Tag
690 volatile uint32 RIDR; //Revision Identification Register
691 volatile uint32 PIR; //PHY Initialization Register
692 volatile uint32 PGCR; //PHY General Configuration Register
693 volatile uint32 PGSR; //PHY General Status Register
694 volatile uint32 DLLGCR; //DLL General Control Register
695 volatile uint32 ACDLLCR; //AC DLL Control Register
696 volatile uint32 PTR[3]; //PHY Timing Registers 0-2
697 volatile uint32 ACIOCR; //AC I/O Configuration Register
698 volatile uint32 DXCCR; //DATX8 Common Configuration Register
699 volatile uint32 DSGCR; //DDR System General Configuration Register
700 DCR_T DCR; //DRAM Configuration Register
701 volatile uint32 DTPR[3]; //DRAM Timing Parameters Register 0-2
702 volatile uint32 MR[4]; //Mode Register 0-3
703 volatile uint32 ODTCR; //ODT Configuration Register
704 volatile uint32 DTAR; //Data Training Address Register
705 volatile uint32 DTDR[2]; //Data Training Data Register 0-1
707 uint32 reserved1[0x30-0x18];
708 uint32 DCU[0x38-0x30];
709 uint32 reserved2[0x40-0x38];
710 uint32 BIST[0x51-0x40];
711 uint32 reserved3[0x60-0x51];
713 volatile uint32 ZQ0CR[2]; //ZQ 0 Impedance Control Register 0-1
714 volatile uint32 ZQ0SR[2]; //ZQ 0 Impedance Status Register 0-1
715 volatile uint32 ZQ1CR[2]; //ZQ 1 Impedance Control Register 0-1
716 volatile uint32 ZQ1SR[2]; //ZQ 1 Impedance Status Register 0-1
717 volatile uint32 ZQ2CR[2]; //ZQ 2 Impedance Control Register 0-1
718 volatile uint32 ZQ2SR[2]; //ZQ 2 Impedance Status Register 0-1
719 volatile uint32 ZQ3CR[2]; //ZQ 3 Impedance Control Register 0-1
720 volatile uint32 ZQ3SR[2]; //ZQ 3 Impedance Status Register 0-1
722 DATX8_REG_T DATX8[9]; //DATX8 Register
723 }DDRPHY_REG_T, *pDDRPHY_REG_T;
725 #define pPHY_Reg ((pDDRPHY_REG_T)DDR_PUBL_BASE)
727 typedef enum DRAM_TYPE_Tag
738 typedef struct PCTRL_TIMING_Tag
741 //Memory Timing Registers
742 uint32 togcnt1u; //Toggle Counter 1U Register
743 uint32 tinit; //t_init Timing Register
744 uint32 trsth; //Reset High Time Register
745 uint32 togcnt100n; //Toggle Counter 100N Register
746 uint32 trefi; //t_refi Timing Register
747 uint32 tmrd; //t_mrd Timing Register
748 uint32 trfc; //t_rfc Timing Register
749 uint32 trp; //t_rp Timing Register
750 uint32 trtw; //t_rtw Timing Register
751 uint32 tal; //AL Latency Register
752 uint32 tcl; //CL Timing Register
753 uint32 tcwl; //CWL Register
754 uint32 tras; //t_ras Timing Register
755 uint32 trc; //t_rc Timing Register
756 uint32 trcd; //t_rcd Timing Register
757 uint32 trrd; //t_rrd Timing Register
758 uint32 trtp; //t_rtp Timing Register
759 uint32 twr; //t_wr Timing Register
760 uint32 twtr; //t_wtr Timing Register
761 uint32 texsr; //t_exsr Timing Register
762 uint32 txp; //t_xp Timing Register
763 uint32 txpdll; //t_xpdll Timing Register
764 uint32 tzqcs; //t_zqcs Timing Register
765 uint32 tzqcsi; //t_zqcsi Timing Register
766 uint32 tdqs; //t_dqs Timing Register
767 uint32 tcksre; //t_cksre Timing Register
768 uint32 tcksrx; //t_cksrx Timing Register
769 uint32 tcke; //t_cke Timing Register
770 uint32 tmod; //t_mod Timing Register
771 uint32 trstl; //Reset Low Timing Register
772 uint32 tzqcl; //t_zqcl Timing Register
773 uint32 tmrr; //t_mrr Timing Register
774 uint32 tckesr; //t_ckesr Timing Register
775 uint32 tdpd; //t_dpd Timing Register
778 typedef union DTPR_0_Tag
795 typedef union DTPR_1_Tag
805 unsigned reserved12_15 : 4;
808 unsigned tDQSCKmax : 3;
809 unsigned reserved30_31 : 2;
813 typedef union DTPR_2_Tag
822 unsigned reserved29_31 : 3;
826 typedef struct PHY_TIMING_Tag
831 uint32 mr[4]; //LPDDR2 no MR0, mr[2] is mDDR MR1
834 typedef union NOC_TIMING_Tag
839 unsigned ActToAct : 6;
840 unsigned RdToMiss : 6;
841 unsigned WrToMiss : 6;
842 unsigned BurstLen : 3;
845 unsigned BwRatio : 1;
849 typedef struct PCTL_REG_Tag
855 PCTL_TIMING_T pctl_timing;
856 //DFI Control Registers
857 uint32 DFITCTRLDELAY;
860 uint32 DFIODTRANKMAP;
861 //DFI Write Data Registers
862 uint32 DFITPHYWRDATA;
864 //DFI Read Data Registers
867 //DFI Update Registers
868 uint32 DFITPHYUPDTYPE0;
869 uint32 DFITPHYUPDTYPE1;
870 uint32 DFITPHYUPDTYPE2;
871 uint32 DFITPHYUPDTYPE3;
872 uint32 DFITCTRLUPDMIN;
873 uint32 DFITCTRLUPDMAX;
874 uint32 DFITCTRLUPDDLY;
878 //DFI Status Registers
881 uint32 DFITDRAMCLKEN;
882 uint32 DFITDRAMCLKDIS;
884 //DFI Low Power Register
888 typedef struct PUBL_REG_Tag
899 PHY_TIMING_T phy_timing;
926 typedef struct BACKUP_REG_Tag
931 NOC_TIMING_T noc_timing;
936 #define READ_CS_INFO() ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>11)&0x1)+1)
937 #define READ_BW_INFO() (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>2)&0x3))
938 #define READ_COL_INFO() (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>9)&0x3))
939 #define READ_BK_INFO() (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>8)&0x1))
940 #define READ_CS0_ROW_INFO() (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>6)&0x3))
941 #define READ_CS1_ROW_INFO() (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>4)&0x3))
942 #define READ_DIE_BW_INFO() (2>>(pPMU_Reg->PMU_PMU_SYS_REG[2]&0x3))
944 __sramdata BACKUP_REG_T ddr_reg;
946 uint8_t ddr_cfg_2_rbc[] =
948 /****************************/
949 // [7:6] bank(n:n bit bank)
951 // [3:2] bank(n:n bit bank)
953 /****************************/
954 //bank, row, bank, col
955 ((3<<6)|(2<<4)|(0<<2)|2), // 0 bank ahead
956 ((0<<6)|(2<<4)|(3<<2)|1), // 1
957 ((0<<6)|(1<<4)|(3<<2)|1), // 2
958 ((0<<6)|(0<<4)|(3<<2)|1), // 3
959 ((0<<6)|(2<<4)|(3<<2)|2), // 4
960 ((0<<6)|(1<<4)|(3<<2)|2), // 5
961 ((0<<6)|(0<<4)|(3<<2)|2), // 6
962 ((0<<6)|(1<<4)|(3<<2)|0), // 7
963 ((0<<6)|(0<<4)|(3<<2)|0), // 8
964 ((1<<6)|(2<<4)|(2<<2)|2), // 9
965 ((1<<6)|(1<<4)|(2<<2)|2), // 10
966 ((1<<6)|(2<<4)|(2<<2)|1), // 11
967 ((1<<6)|(1<<4)|(2<<2)|1), // 12
968 ((1<<6)|(2<<4)|(2<<2)|0), // 13
969 ((1<<6)|(1<<4)|(2<<2)|0), // 14
970 ((3<<6)|(2<<4)|(0<<2)|1), // 15 bank ahead
973 __attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
975 uint8_t __sramdata ddr3_cl_cwl[22][4]={
976 /* 0~330 330~400 400~533 speed
977 * tCK >3 2.5~3 1.875~2.5 1.5~1.875
978 * cl<<4, cwl cl<<4, cwl cl<<4, cwl */
979 {((5<<4)|5), ((5<<4)|5), 0 , 0}, //DDR3_800D
980 {((5<<4)|5), ((6<<4)|5), 0 , 0}, //DDR3_800E
982 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), 0}, //DDR3_1066E
983 {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), 0}, //DDR3_1066F
984 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), 0}, //DDR3_1066G
986 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_1333F
987 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7)}, //DDR3_1333G
988 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((9<<4)|7)}, //DDR3_1333H
989 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)}, //DDR3_1333J
991 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_1600G
992 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_1600H
993 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_1600J
994 {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), ((10<<4)|7)}, //DDR3_1600K
996 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_1866J
997 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7)}, //DDR3_1866K
998 {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_1866L
999 {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)}, //DDR3_1866M
1001 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_2133K
1002 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_2133L
1003 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_2133M
1004 {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_2133N
1006 {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)} //DDR3_DEFAULT
1009 uint16_t __sramdata ddr3_tRC_tFAW[22]={
1011 ((50<<8)|50), //DDR3_800D
1012 ((53<<8)|50), //DDR3_800E
1014 ((49<<8)|50), //DDR3_1066E
1015 ((51<<8)|50), //DDR3_1066F
1016 ((53<<8)|50), //DDR3_1066G
1018 ((47<<8)|45), //DDR3_1333F
1019 ((48<<8)|45), //DDR3_1333G
1020 ((50<<8)|45), //DDR3_1333H
1021 ((51<<8)|45), //DDR3_1333J
1023 ((45<<8)|40), //DDR3_1600G
1024 ((47<<8)|40), //DDR3_1600H
1025 ((48<<8)|40), //DDR3_1600J
1026 ((49<<8)|40), //DDR3_1600K
1028 ((45<<8)|35), //DDR3_1866J
1029 ((46<<8)|35), //DDR3_1866K
1030 ((47<<8)|35), //DDR3_1866L
1031 ((48<<8)|35), //DDR3_1866M
1033 ((44<<8)|35), //DDR3_2133K
1034 ((45<<8)|35), //DDR3_2133L
1035 ((46<<8)|35), //DDR3_2133M
1036 ((47<<8)|35), //DDR3_2133N
1038 ((53<<8)|50) //DDR3_DEFAULT
1041 __sramdata uint32_t mem_type; // 0:LPDDR, 1:DDR, 2:DDR2, 3:DDR3, 4:LPDDR2
1042 static __sramdata uint32_t ddr_speed_bin; // used for ddr3 only
1043 static __sramdata uint32_t ddr_capability_per_die; // one chip cs capability
1044 static __sramdata uint32_t ddr_freq;
1045 static __sramdata uint32_t ddr_sr_idle;
1047 /****************************************************************************
1048 Internal sram us delay function
1049 Cpu highest frequency is 1.6 GHz
1051 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1052 *****************************************************************************/
1053 static __sramdata volatile uint32_t loops_per_us;
1055 #define LPJ_100MHZ 999456UL
1057 /*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
1061 unsigned int i = (loops_per_us*us);
1064 asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1068 __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
1072 for(i=0; i<words; i++)
1078 uint32 ddr_get_row(void)
1083 if(pPMU_Reg->PMU_PMU_SYS_REG[2])
1085 row=READ_CS0_ROW_INFO();
1089 i = *(volatile uint32*)SysSrv_DdrConf;
1090 row = 13+((ddr_cfg_2_rbc[i]>>4)&0x3);
1091 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1092 if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<1))
1097 if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
1106 uint32 ddr_get_bank(void)
1111 if(pPMU_Reg->PMU_PMU_SYS_REG[2])
1113 bank = READ_BK_INFO();
1117 i = *(volatile uint32*)SysSrv_DdrConf;
1118 bank = ((ddr_cfg_2_rbc[i]>>6)&0x3) + ((ddr_cfg_2_rbc[i]>>2)&0x3);
1119 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1120 if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<2))
1125 if(pGRF_Reg->GRF_SOC_CON[2] & (1<<2))
1134 uint32 ddr_get_col(void)
1139 if(pPMU_Reg->PMU_PMU_SYS_REG[2])
1141 col=READ_COL_INFO();
1145 i = *(volatile uint32*)SysSrv_DdrConf;
1146 col = 9+(ddr_cfg_2_rbc[i]&0x3);
1147 if(pDDR_Reg->PPCFG & 1)
1155 uint32 ddr_get_bw(void)
1159 if(pDDR_Reg->PPCFG & 1)
1170 uint32 ddr_get_cs(void)
1174 switch((pPHY_Reg->PGCR>>18) & 0xF)
1191 uint32_t ddr_get_datatraing_addr(void)
1201 // caculate aglined physical address
1202 addr = __pa((unsigned long)ddr_data_training_buf);
1205 addr += (64-(addr&0x3F));
1208 // find out col£¬row£¬bank
1209 row = ddr_get_row();
1210 bank = ddr_get_bank();
1211 col = ddr_get_col();
1213 // according different address mapping, caculate DTAR register value
1214 i = (*(volatile uint32*)SysSrv_DdrConf);
1215 value |= (addr>>bw) & ((0x1<<col)-1); // col
1218 value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & 0x7FFF) << 12; // row
1219 value |= (((addr>>(bw+col+bank+15))&0x1)<<15)<<12;
1220 row = 15; //use for bank
1224 value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & ((0x1<<row)-1)) << 12; // row
1226 if(((ddr_cfg_2_rbc[i]>>6)&0x3)==1)
1228 value |= (((addr>>(bw+col)) & 0x3) << 28)
1229 | (((addr>>(bw+col+2+row)) & (bank-2)) << 30); // bank
1231 else if(((ddr_cfg_2_rbc[i]>>6)&0x3)==3)
1233 value |= (((addr>>(bw+col+row)) & ((0x1<<bank)-1)) << 28); // bank
1237 value |= (((addr>>(bw+col)) & 0x7) << 28); // bank
1243 __sramlocalfunc void ddr_reset_dll(void)
1245 pPHY_Reg->ACDLLCR &= ~0x40000000;
1246 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1247 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1248 if(!(pDDR_Reg->PPCFG & 1))
1250 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1251 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1254 pPHY_Reg->ACDLLCR |= 0x40000000;
1255 pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1256 pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1257 if(!(pDDR_Reg->PPCFG & 1))
1259 pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1260 pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1265 __sramfunc void ddr_move_to_Lowpower_state(void)
1267 volatile uint32 value;
1271 value = pDDR_Reg->STAT.b.ctl_stat;
1272 if(value == Low_power)
1279 pDDR_Reg->SCTL = CFG_STATE;
1281 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1283 pDDR_Reg->SCTL = GO_STATE;
1285 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1287 pDDR_Reg->SCTL = SLEEP_STATE;
1289 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1291 default: //Transitional state
1297 __sramfunc void ddr_move_to_Access_state(void)
1299 volatile uint32 value;
1301 //set auto self-refresh idle
1302 pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|ddr_sr_idle | (1<<31);
1307 value = pDDR_Reg->STAT.b.ctl_stat;
1308 if((value == Access)
1309 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1316 pDDR_Reg->SCTL = WAKEUP_STATE;
1318 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1319 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1322 pDDR_Reg->SCTL = CFG_STATE;
1324 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1326 pDDR_Reg->SCTL = GO_STATE;
1328 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1329 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1331 default: //Transitional state
1335 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1336 pGRF_Reg_RK3066B->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
1338 pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
1343 __sramfunc void ddr_move_to_Config_state(void)
1345 volatile uint32 value;
1346 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1347 pGRF_Reg_RK3066B->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
1349 pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
1355 value = pDDR_Reg->STAT.b.ctl_stat;
1363 pDDR_Reg->SCTL = WAKEUP_STATE;
1365 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1366 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1369 pDDR_Reg->SCTL = CFG_STATE;
1371 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1373 default: //Transitional state
1379 //arg°üÀ¨bank_addrºÍcmd_addr
1380 void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
1382 pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1384 while(pDDR_Reg->MCMD & start_cmd);
1387 //¶ÔtypeÀàÐ͵ÄDDRµÄ¼¸¸öcs½øÐÐDTT
1390 uint32_t __sramlocalfunc ddr_data_training(void)
1394 // disable auto refresh
1395 value = pDDR_Reg->TREFI;
1396 pDDR_Reg->TREFI = 0;
1398 if(mem_type != LPDDR2)
1401 pPHY_Reg->PGCR |= (1<<1);
1403 // clear DTDONE status
1404 pPHY_Reg->PIR |= CLRSR;
1405 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
1407 pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
1409 // wait echo byte DTDONE
1410 while((pPHY_Reg->DATX8[0].DXGSR[0] & cs) != cs);
1411 while((pPHY_Reg->DATX8[1].DXGSR[0] & cs) != cs);
1412 if(!(pDDR_Reg->PPCFG & 1))
1414 while((pPHY_Reg->DATX8[2].DXGSR[0] & cs) != cs);
1415 while((pPHY_Reg->DATX8[3].DXGSR[0] & cs) != cs);
1417 // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×ʱ¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
1420 ddr_send_command(cs, REF_cmd, 0);
1421 ddr_send_command(cs, REF_cmd, 0);
1422 ddr_send_command(cs, REF_cmd, 0);
1423 ddr_send_command(cs, REF_cmd, 0);
1427 ddr_send_command(cs, REF_cmd, 0);
1428 ddr_send_command(cs, REF_cmd, 0);
1430 if(mem_type != LPDDR2)
1433 pPHY_Reg->PGCR &= ~(1<<1);
1435 // resume auto refresh
1436 pDDR_Reg->TREFI = value;
1438 if(pPHY_Reg->PGSR & DTERR)
1448 void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
1452 pPHY_Reg->DLLGCR &= ~(1<<23);
1453 pPHY_Reg->ACDLLCR |= 0x80000000;
1454 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
1455 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
1456 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
1457 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
1458 pPHY_Reg->PIR |= DLLBYP;
1462 pPHY_Reg->DLLGCR |= (1<<23);
1463 pPHY_Reg->ACDLLCR |= 0x80000000;
1464 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
1465 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
1466 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
1467 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
1468 pPHY_Reg->PIR |= DLLBYP;
1472 pPHY_Reg->DLLGCR &= ~(1<<23);
1473 pPHY_Reg->ACDLLCR &= ~0x80000000;
1474 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
1475 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
1476 if(!(pDDR_Reg->PPCFG & 1))
1478 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
1479 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
1481 pPHY_Reg->PIR &= ~DLLBYP;
1485 static __sramdata uint32_t clkr;
1486 static __sramdata uint32_t clkf;
1487 static __sramdata uint32_t clkod;
1489 static __sramdata uint32_t dpllvaluel=0,gpllvaluel=0;
1490 static __sramdata uint32_t ddr_select_gpll_div=0; // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1492 static __sramdata bool ddr_soc_is_rk3188_plus=false;
1494 typedef enum PLL_ID_Tag
1503 uint32_t __sramlocalfunc ddr_get_pll_freq(PLL_ID pll_id) //APLL-1;CPLL-2;DPLL-3;GPLL-4
1507 // freq = (Fin/NR)*NF/OD
1508 if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1) // DPLL Normal mode
1509 ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0xffff)+1) // NF = 2*(CLKF+1)
1510 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1) // NR = CLKR+1
1511 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0x3F)+1)); // OD = 2^CLKOD
1518 static __sramdata bool ddr_rk3188_dpll_is_good=true;
1519 #if defined(CONFIG_ARCH_RK3188)
1520 bool ddr_get_dpll_status(void) //CPLL or DPLL bad rerurn false;good return true;
1522 if (rk_pll_flag() & 0x3)
1529 /*****************************************
1530 NR NO NF Fout freq Step finally use
1531 1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
1532 1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
1533 1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
1534 1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
1535 1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
1536 ******************************************/
1537 uint32_t __sramlocalfunc ddr_set_pll_3066(uint32_t nMHz, uint32_t set)
1541 uint32_t pll_id=1; //DPLL
1542 //NOÒ»¶¨ÒªÅ¼Êý,NR¾¡Á¿Ð¡£¬jitter¾Í»áС
1556 else if(nMHz <= 200)
1560 else if(nMHz <= 300)
1564 else if(nMHz <= 600)
1573 clkf=(nMHz*clkr*clkod)/24;
1574 ret = (24*clkf)/(clkr*clkod);
1578 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
1580 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
1581 pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
1582 pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
1583 pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1585 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
1590 if (pGRF_Reg->GRF_SOC_STATUS0 & (0x1<<4))
1594 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1595 | (0x0<<8) //clk_ddr_src = DDR PLL
1596 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1598 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
1606 /*****************************************
1608 NR NO NF Fout freq Step finally use
1609 1 14 46 - 91 78MHz - 157MHz 1.7MHz 78MHz<= 150MHz
1610 1 8 46 - 91 137MHz - 275MHz 3MHz 150MHz<= 200MHz
1611 1 6 46 - 91 183MHz - 366MHz 4MHz 200MHz<= 300MHz
1612 1 4 46 - 91 275MHz - 550MHz 6MHz 300MHz<= 550MHz
1613 1 2 46 - 91 550MHz - 1100MHz 12MHz 550MHz<= 1100MHz
1614 1 1 46 - 91 1100MHz - 2200MHz 24MHz 1100MHz<= 2200MHz
1615 ******************************************/
1616 uint32_t __sramlocalfunc ddr_set_pll_rk3066b(uint32_t nMHz, uint32_t set)
1620 uint32_t pll_id=1; //DPLL
1630 dpllvaluel = ddr_get_pll_freq(DPLL);
1631 gpllvaluel = ddr_get_pll_freq(GPLL);
1633 if(ddr_rk3188_dpll_is_good == false) //if rk3188 DPLL is bad,use GPLL
1635 if( (gpllvaluel < 200) ||(gpllvaluel > 2000))
1637 ddr_print("DPLL is bad and GPLL freq = %dMHz,Not suitable for ddr_clock\n",gpllvaluel);
1641 if(gpllvaluel > 1000) //GPLL:1000MHz-2000MHz
1643 ddr_select_gpll_div=4; //DDR_CLCOK:250MHz-500MHz
1645 else if(gpllvaluel > 800) //GPLL:800MHz-1000MHz
1648 ddr_select_gpll_div=2; //DDR_CLCOK:400MHz-500MHz
1650 ddr_select_gpll_div=4; //DDR_CLCOK:200MHz-250MHz
1652 else if(gpllvaluel > 500) //GPLL:500MHz-800MHz
1654 ddr_select_gpll_div=2; //DDR_CLCOK:250MHz-400MHz
1656 else //GPLL:200MHz-500MHz
1658 ddr_select_gpll_div=1; //DDR_CLCOK:200MHz-500MHz
1662 if(ddr_select_gpll_div > 0)
1664 if(ddr_select_gpll_div == 4)
1666 else if(ddr_select_gpll_div == 2)
1677 else if(nMHz <= 200)
1681 else if(nMHz <= 300)
1685 else if(nMHz <= 550)
1689 else if(nMHz <= 1100)
1698 clkf=(nMHz*clkr*clkod)/24;
1699 ret = (24*clkf)/(clkr*clkod);
1705 if(ddr_select_gpll_div > 0)
1707 if(ddr_select_gpll_div == 4)
1709 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1710 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1711 | (0x1<<8) //clk_ddr_src = G PLL
1712 | 2; //clk_ddr_src:clk_ddrphy = 4:1
1715 else if(ddr_select_gpll_div == 2)
1717 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1718 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1719 | (0x1<<8) //clk_ddr_src = G PLL
1720 | 1; //clk_ddr_src:clk_ddrphy = 2:1
1725 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1726 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1727 | (0x1<<8) //clk_ddr_src = G PLL
1728 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1732 else if((nMHz==dpllvaluel) && (set == 1))
1734 // ddr_pll_clk: clk_ddr=1:1
1735 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1736 | (0x0<<8) //clk_ddr_src = DDR PLL
1737 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1742 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
1745 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET_RK3066B;
1747 pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR_RK3066B(clkr) | NO_RK3066B(clkod);
1748 pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF_RK3066B(clkf);
1749 // pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1751 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET_RK3066B;
1756 if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
1762 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1763 | (0x0<<8) //clk_ddr_src = DDR PLL
1764 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1766 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
1775 /*****************************************
1776 NR NO NF Fout freq Step finally use
1777 1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
1778 1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
1779 1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
1780 1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
1781 1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
1782 ******************************************/
1783 uint32_t __sramlocalfunc ddr_set_pll_rk3188_plus(uint32_t nMHz, uint32_t set)
1787 uint32_t pll_id=1; //DPLL
1797 dpllvaluel = ddr_get_pll_freq(DPLL);
1798 gpllvaluel = ddr_get_pll_freq(GPLL);
1800 if(ddr_select_gpll_div > 0)
1802 if(ddr_select_gpll_div == 4)
1804 else if(ddr_select_gpll_div == 2)
1815 else if(nMHz <= 200)
1819 else if(nMHz <= 300)
1823 else if(nMHz <= 600)
1832 clkf=(nMHz*clkr*clkod)/24;
1833 ret = (24*clkf)/(clkr*clkod);
1839 if(ddr_select_gpll_div > 0)
1841 if(ddr_select_gpll_div == 4)
1843 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1844 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1845 | (0x1<<8) //clk_ddr_src = G PLL
1846 | 2; //clk_ddr_src:clk_ddrphy = 4:1
1849 if(ddr_select_gpll_div == 2)
1851 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1852 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1853 | (0x1<<8) //clk_ddr_src = G PLL
1854 | 1; //clk_ddr_src:clk_ddrphy = 2:1
1859 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1860 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1861 | (0x1<<8) //clk_ddr_src = G PLL
1862 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1866 else if((nMHz==dpllvaluel) && (set == 1))
1868 // ddr_pll_clk: clk_ddr=1:1
1869 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1870 | (0x0<<8) //clk_ddr_src = DDR PLL
1871 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1876 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
1879 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
1881 pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
1882 pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
1883 pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1885 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
1890 if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
1896 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1897 | (0x0<<8) //clk_ddr_src = DDR PLL
1898 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1900 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
1909 uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
1911 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1912 if(ddr_soc_is_rk3188_plus == true)
1913 return ddr_set_pll_rk3188_plus(nMHz,set);
1915 return ddr_set_pll_rk3066b(nMHz,set);
1917 return ddr_set_pll_3066(nMHz,set);
1921 uint32_t ddr_get_parameter(uint32_t nMHz)
1929 PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
1930 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
1931 NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
1933 p_pctl_timing->togcnt1u = nMHz;
1934 p_pctl_timing->togcnt100n = nMHz/10;
1935 p_pctl_timing->tinit = 200;
1936 p_pctl_timing->trsth = 500;
1938 if(mem_type == DDR3)
1940 if(ddr_speed_bin > DDR3_DEFAULT){
1945 #define DDR3_tREFI_7_8_us (78) //unit 100ns
1946 #define DDR3_tMRD (4) //tCK
1947 #define DDR3_tRFC_512Mb (90) //ns
1948 #define DDR3_tRFC_1Gb (110) //ns
1949 #define DDR3_tRFC_2Gb (160) //ns
1950 #define DDR3_tRFC_4Gb (300) //ns
1951 #define DDR3_tRFC_8Gb (350) //ns
1952 #define DDR3_tRTW (2) //register min valid value
1953 #define DDR3_tRAS (37) //ns
1954 #define DDR3_tRRD (10) //ns
1955 #define DDR3_tRTP (7) //ns
1956 #define DDR3_tWR (15) //ns
1957 #define DDR3_tWTR (7) //ns
1958 #define DDR3_tXP (7) //ns
1959 #define DDR3_tXPDLL (24) //ns
1960 #define DDR3_tZQCS (80) //ns
1961 #define DDR3_tZQCSI (0) //ns
1962 #define DDR3_tDQS (1) //tCK
1963 #define DDR3_tCKSRE (10) //ns
1964 #define DDR3_tCKE_400MHz (7) //ns
1965 #define DDR3_tCKE_533MHz (6) //ns
1966 #define DDR3_tMOD (15) //ns
1967 #define DDR3_tRSTL (100) //ns
1968 #define DDR3_tZQCL (320) //ns
1969 #define DDR3_tDLLK (512) //tCK
1989 if(nMHz < DDR3_DDR2_ODT_DLL_DISABLE_FREQ) //when dll bypss cl = cwl = 6;
1996 cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
1997 cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
2001 if(nMHz <= DDR3_DDR2_ODT_DLL_DISABLE_FREQ)
2003 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
2007 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
2009 p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
2010 p_publ_timing->mr[3] = 0;
2011 /**************************************************
2013 **************************************************/
2015 * tREFI, average periodic refresh interval, 7.8us
2017 p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
2021 p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
2022 p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
2024 * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
2026 if(ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
2028 tmp = DDR3_tRFC_512Mb;
2030 else if(ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
2032 tmp = DDR3_tRFC_1Gb;
2034 else if(ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
2036 tmp = DDR3_tRFC_2Gb;
2038 else if(ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
2040 tmp = DDR3_tRFC_4Gb;
2044 tmp = DDR3_tRFC_8Gb;
2046 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2047 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
2049 * tXSR, =tDLLK=512 tCK
2051 p_pctl_timing->texsr = DDR3_tDLLK;
2052 p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
2056 p_pctl_timing->trp = cl;
2057 p_publ_timing->dtpr0.b.tRP = cl;
2059 * WrToMiss=WL*tCK + tWR + tRP + tRCD
2061 p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
2065 p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2066 p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2067 p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0xF;
2069 p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
2070 p_publ_timing->dtpr1.b.tRTW = 0;
2071 p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
2072 p_pctl_timing->tal = al;
2073 p_pctl_timing->tcl = cl;
2074 p_pctl_timing->tcwl = cwl;
2076 * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
2078 p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
2079 p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x1F;
2083 p_pctl_timing->trcd = cl;
2084 p_publ_timing->dtpr0.b.tRCD = cl;
2086 * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2087 * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2088 * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2091 tmp = ((DDR3_tRRD*nMHz+999)/1000);
2096 p_pctl_timing->trrd = (tmp&0xF);
2097 p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
2099 * tRTP, max(4 tCK,7.5ns)
2101 tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2106 p_pctl_timing->trtp = tmp&0xF;
2107 p_publ_timing->dtpr0.b.tRTP = tmp;
2109 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2111 p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
2115 tmp = ((DDR3_tWR*nMHz+999)/1000);
2116 p_pctl_timing->twr = tmp&0x1F;
2121 bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2122 p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2125 * tWTR, max(4 tCK,7.5ns)
2127 tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2132 p_pctl_timing->twtr = tmp&0xF;
2133 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2134 p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
2136 * tXP, max(3 tCK, 7.5ns)(<933MHz)
2138 tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2143 p_pctl_timing->txp = tmp&0x7;
2145 * tXPDLL, max(10 tCK,24ns)
2147 tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2152 p_pctl_timing->txpdll = tmp & 0x3F;
2153 p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
2155 * tZQCS, max(64 tCK, 80ns)
2157 tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2162 p_pctl_timing->tzqcs = tmp&0x7F;
2166 p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2170 p_pctl_timing->tdqs = DDR3_tDQS;
2172 * tCKSRE, max(5 tCK, 10ns)
2174 tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2179 p_pctl_timing->tcksre = tmp & 0x1F;
2181 * tCKSRX, max(5 tCK, 10ns)
2183 p_pctl_timing->tcksrx = tmp & 0x1F;
2185 * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2189 tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2193 tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2199 p_pctl_timing->tcke = tmp & 0x7;
2200 p_publ_timing->dtpr2.b.tCKE = tmp;
2202 * tCKESR, =tCKE + 1tCK
2204 p_pctl_timing->tckesr = (tmp+1)&0xF;
2206 * tMOD, max(12 tCK,15ns)
2208 tmp = ((DDR3_tMOD*nMHz+999)/1000);
2213 p_pctl_timing->tmod = tmp&0x1F;
2214 p_publ_timing->dtpr1.b.tMOD = tmp;
2218 p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2220 * tZQCL, max(256 tCK, 320ns)
2222 tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2227 p_pctl_timing->tzqcl = tmp&0x3FF;
2231 p_pctl_timing->tmrr = 0;
2235 p_pctl_timing->tdpd = 0;
2237 /**************************************************
2239 **************************************************/
2241 * tCCD, BL/2 for DDR2 and 4 for DDR3
2243 p_publ_timing->dtpr0.b.tCCD = 0;
2247 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2249 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2250 * 1:ODT may not be turned on until one clock after the read post-amble
2252 p_publ_timing->dtpr1.b.tRTODT = 1;
2254 * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page) 50ns(533MHz 2KB page)
2256 p_publ_timing->dtpr1.b.tFAW = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000)&0x7F;
2260 p_publ_timing->dtpr1.b.tAOND = 0;
2264 p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2265 /**************************************************
2267 **************************************************/
2268 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2270 else if(mem_type == LPDDR2)
2272 #define LPDDR2_tREFI_3_9_us (38) //unit 100ns
2273 #define LPDDR2_tREFI_7_8_us (78) //unit 100ns
2274 #define LPDDR2_tMRD (5) //tCK
2275 #define LPDDR2_tRFC_8Gb (210) //ns
2276 #define LPDDR2_tRFC_4Gb (130) //ns
2277 #define LPDDR2_tRP_4_BANK (24) //ns
2278 #define LPDDR2_tRPab_SUB_tRPpb_4_BANK (0)
2279 #define LPDDR2_tRP_8_BANK (27) //ns
2280 #define LPDDR2_tRPab_SUB_tRPpb_8_BANK (3)
2281 #define LPDDR2_tRTW (1) //tCK register min valid value
2282 #define LPDDR2_tRAS (42) //ns
2283 #define LPDDR2_tRCD (24) //ns
2284 #define LPDDR2_tRRD (10) //ns
2285 #define LPDDR2_tRTP (7) //ns
2286 #define LPDDR2_tWR (15) //ns
2287 #define LPDDR2_tWTR_GREAT_200MHz (7) //ns
2288 #define LPDDR2_tWTR_LITTLE_200MHz (10) //ns
2289 #define LPDDR2_tXP (7) //ns
2290 #define LPDDR2_tXPDLL (0)
2291 #define LPDDR2_tZQCS (90) //ns
2292 #define LPDDR2_tZQCSI (0)
2293 #define LPDDR2_tDQS (1)
2294 #define LPDDR2_tCKSRE (1) //tCK
2295 #define LPDDR2_tCKSRX (2) //tCK
2296 #define LPDDR2_tCKE (3) //tCK
2297 #define LPDDR2_tMOD (0)
2298 #define LPDDR2_tRSTL (0)
2299 #define LPDDR2_tZQCL (360) //ns
2300 #define LPDDR2_tMRR (2) //tCK
2301 #define LPDDR2_tCKESR (15) //ns
2302 #define LPDDR2_tDPD_US (500)
2303 #define LPDDR2_tFAW_GREAT_200MHz (50) //ns
2304 #define LPDDR2_tFAW_LITTLE_200MHz (60) //ns
2305 #define LPDDR2_tDLLK (2) //tCK
2306 #define LPDDR2_tDQSCK_MAX (3) //tCK
2307 #define LPDDR2_tDQSCK_MIN (0) //tCK
2308 #define LPDDR2_tDQSS (1) //tCK
2319 bl = 4; //you can change burst here
2323 bl = 8; // freq < 200MHz, BL fixed 8
2325 /* 1066 933 800 667 533 400 333
2333 p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2339 p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2345 p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2351 p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2357 p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2363 p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2365 p_publ_timing->mr[3] = LPDDR2_DS_34;
2366 p_publ_timing->mr[0] = 0;
2367 /**************************************************
2369 **************************************************/
2371 * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2373 if(ddr_capability_per_die >= 0x10000000) // 2Gb
2375 p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2379 p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2383 * tMRD, (=tMRW), 5 tCK
2385 p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2386 p_publ_timing->dtpr0.b.tMRD = 3;
2388 * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2390 if(ddr_capability_per_die >= 0x40000000) // 8Gb
2392 p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2393 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000)&0xFF;
2395 * tXSR, max(2tCK,tRFC+10ns)
2397 tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
2401 p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2402 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000)&0xFF;
2403 tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
2409 p_pctl_timing->texsr = tmp&0x3FF;
2410 p_publ_timing->dtpr2.b.tXS = tmp&0x3FF;
2413 * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
2415 if(pPHY_Reg->DCR.b.DDR8BNK)
2417 trp_tmp = ((LPDDR2_tRP_8_BANK*nMHz+999)/1000);
2422 p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
2426 trp_tmp = ((LPDDR2_tRP_4_BANK*nMHz+999)/1000);
2431 p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
2433 p_publ_timing->dtpr0.b.tRP = trp_tmp;
2435 * tRAS, max(3tCK,42ns)
2437 tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
2442 p_pctl_timing->tras = (tras_tmp&0x3F);
2443 p_publ_timing->dtpr0.b.tRAS = tras_tmp&0x1F;
2446 * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
2448 trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
2453 p_pctl_timing->trcd = (trcd_tmp&0xF);
2454 p_publ_timing->dtpr0.b.tRCD = trcd_tmp&0xF;
2457 * tRTP, max(2tCK, 7.5ns)
2459 trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2464 p_pctl_timing->trtp = trtp_tmp&0xF;
2465 p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
2468 * tWR, max(3tCK,15ns)
2470 twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
2475 p_pctl_timing->twr = twr_tmp&0x1F;
2476 bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2477 p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
2480 * WrToMiss=WL*tCK + tDQSS + tWR + tRP + tRCD
2482 p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+twr_tmp+trp_tmp+trcd_tmp)&0x3F);
2484 * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2486 p_noc_timing->b.RdToMiss = ((trtp_tmp+trp_tmp+trcd_tmp-(bl>>1))&0x3F);
2490 p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
2491 p_noc_timing->b.ActToAct = ((tras_tmp+trp_tmp)&0x3F);
2492 p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp)&0xF;
2495 * RdToWr=RL+tDQSCK-WL
2497 p_pctl_timing->trtw = (cl+LPDDR2_tDQSCK_MAX+(bl/2)+1-cwl);//LPDDR2_tRTW;
2498 p_publ_timing->dtpr1.b.tRTW = 0;
2499 p_noc_timing->b.RdToWr = ((cl+LPDDR2_tDQSCK_MAX+1-cwl)&0x1F);
2500 p_pctl_timing->tal = al;
2501 p_pctl_timing->tcl = cl;
2502 p_pctl_timing->tcwl = cwl;
2504 * tRRD, max(2tCK,10ns)
2506 tmp=((LPDDR2_tRRD*nMHz+999)/1000);
2511 p_pctl_timing->trrd = (tmp&0xF);
2512 p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
2514 * tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz))
2518 tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2522 tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2528 p_pctl_timing->twtr = tmp&0xF;
2529 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2531 * WrToRd=WL+tDQSS+tWTR
2533 p_noc_timing->b.WrToRd = ((cwl+LPDDR2_tDQSS+tmp)&0x1F);
2535 * tXP, max(2tCK,7.5ns)
2537 tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
2542 p_pctl_timing->txp = tmp&0x7;
2543 p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
2547 p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2551 p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2555 if(pDDR_Reg->MCFG &= lpddr2_s4)
2557 p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2561 p_pctl_timing->tzqcsi = 0;
2566 p_pctl_timing->tdqs = LPDDR2_tDQS;
2570 p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2574 p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2578 p_pctl_timing->tcke = LPDDR2_tCKE;
2579 p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2583 p_pctl_timing->tmod = LPDDR2_tMOD;
2584 p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2588 p_pctl_timing->trstl = LPDDR2_tRSTL;
2592 p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2596 p_pctl_timing->tmrr = LPDDR2_tMRR;
2598 * tCKESR, max(3tCK,15ns)
2600 tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
2605 p_pctl_timing->tckesr = tmp&0xF;
2609 p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2611 /**************************************************
2613 **************************************************/
2615 * tCCD, BL/2 for DDR2 and 4 for DDR3
2617 p_publ_timing->dtpr0.b.tCCD = 0;
2621 p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2625 p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2627 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2628 * 1:ODT may not be turned on until one clock after the read post-amble
2630 p_publ_timing->dtpr1.b.tRTODT = 1;
2632 * tFAW,max(8tCK, 50ns(200-533MHz) 60ns(166MHz))
2636 tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
2640 tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
2646 p_publ_timing->dtpr1.b.tFAW = tmp&0x7F;
2650 p_publ_timing->dtpr1.b.tAOND = 0;
2654 p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2655 /**************************************************
2657 **************************************************/
2658 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2665 uint32_t __sramlocalfunc ddr_update_timing(void)
2667 uint32_t i,bl_tmp=0;
2668 PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
2669 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
2670 NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
2672 ddr_copy((uint32_t *)&(pDDR_Reg->TOGCNT1U), (uint32_t*)&(p_pctl_timing->togcnt1u), 34);
2673 ddr_copy((uint32_t *)&(pPHY_Reg->DTPR[0]), (uint32_t*)&(p_publ_timing->dtpr0), 3);
2674 *(volatile uint32_t *)SysSrv_DdrTiming = p_noc_timing->d32;
2676 if(mem_type == DDR3)
2678 bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
2679 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
2680 if((ddr_freq <= DDR3_DDR2_ODT_DLL_DISABLE_FREQ) && ddr_soc_is_rk3188_plus)
2682 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-3;
2686 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
2688 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
2690 else if(mem_type == LPDDR2)
2692 if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
2694 bl_tmp = mddr_lpddr2_bl_8;
2696 else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
2698 bl_tmp = mddr_lpddr2_bl_4;
2700 else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
2702 bl_tmp = mddr_lpddr2_bl_16;
2706 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
2710 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
2712 i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
2713 pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8); //tDQSCKmax-tDQSCK
2714 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-1;
2715 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL;
2721 uint32_t __sramlocalfunc ddr_update_mr(void)
2723 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
2724 uint32_t cs,dll_off;
2726 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2727 dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
2728 ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
2729 if((mem_type == DDR3) || (mem_type == DDR2))
2731 if(ddr_freq>DDR3_DDR2_ODT_DLL_DISABLE_FREQ)
2733 if(dll_off) // off -> on
2735 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1]))); //DLL enable
2736 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
2737 ddr_delayus(2); //at least 200 DDR cycle
2738 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
2742 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
2743 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
2748 pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
2749 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE)); //DLL disable
2750 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
2752 ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
2754 else if(mem_type == LPDDR2)
2756 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
2757 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
2758 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
2762 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
2763 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
2768 void __sramlocalfunc ddr_update_odt(void)
2772 //adjust DRV and ODT
2773 if((mem_type == DDR3) || (mem_type == DDR2))
2775 if(ddr_freq <= DDR3_DDR2_ODT_DLL_DISABLE_FREQ)
2777 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
2778 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
2779 if(!(pDDR_Reg->PPCFG & 1))
2781 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
2782 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
2787 pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9); //dynamic RTT enable
2788 pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
2789 if(!(pDDR_Reg->PPCFG & 1))
2791 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
2792 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
2798 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
2799 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
2800 if(!(pDDR_Reg->PPCFG & 1))
2802 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
2803 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
2806 tmp = (0x1<<28) | (0x2<<15) | (0x2<<10) | (0xb<<5) | 0xb; //DS=34ohm,ODT=171ohm
2807 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2810 pPHY_Reg->ZQ1CR[0] = tmp;
2813 pPHY_Reg->ZQ0CR[0] = tmp;
2817 __sramfunc void ddr_adjust_config(uint32_t dram_type)
2820 unsigned long save_sp;
2823 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
2825 //get data training address before idle port
2826 value = ddr_get_datatraing_addr();
2828 /** 1. Make sure there is no host access */
2833 DDR_SAVE_SP(save_sp);
2840 n= pDDR_Reg->SCFG.d32;
2842 n= pCRU_Reg->CRU_PLL_CON[0][0];
2843 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
2844 n= *(volatile uint32_t *)SysSrv_DdrConf;
2845 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
2846 n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
2848 n= pGRF_Reg->GRF_SOC_STATUS0;
2852 //enter config state
2853 ddr_move_to_Config_state();
2855 //set data training address
2856 pPHY_Reg->DTAR = value;
2858 //set auto power down idle
2859 pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
2862 pPHY_Reg->PGCR &= ~(0x3<<12);
2864 //enable the hardware low-power interface
2865 pDDR_Reg->SCFG.b.hw_low_power_en = 1;
2867 if(pDDR_Reg->PPCFG & 1)
2869 pPHY_Reg->DATX8[2].DXGCR &= ~(1); //disable byte
2870 pPHY_Reg->DATX8[3].DXGCR &= ~(1);
2871 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000; //disable DLL
2872 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2877 //enter access state
2878 ddr_move_to_Access_state();
2880 DDR_RESTORE_SP(save_sp);
2884 void __sramlocalfunc idle_port(void)
2887 uint32 clk_gate[10];
2889 //save clock gate status
2891 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
2893 //enable all clock gate for request idle
2895 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
2897 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
2899 #ifdef CONFIG_ARCH_RK3188
2900 pPMU_Reg->PMU_MISC_CON1 |= idle_req_dma_cfg;
2902 while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) == 0 );
2904 pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
2906 while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
2910 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
2912 pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
2914 while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
2917 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
2919 pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
2921 while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
2924 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
2926 pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
2928 while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
2931 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
2933 pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
2935 while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
2938 //resume clock gate status
2940 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
2943 void __sramlocalfunc deidle_port(void)
2946 uint32 clk_gate[10];
2948 //save clock gate status
2950 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
2952 //enable all clock gate for request idle
2954 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
2956 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
2959 #ifdef CONFIG_ARCH_RK3188
2960 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_dma_cfg;
2962 while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) != 0 );
2964 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
2966 while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
2969 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
2971 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
2973 while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
2976 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
2978 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
2980 while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
2983 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
2985 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
2987 while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
2990 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
2992 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
2994 while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
2997 //resume clock gate status
2999 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
3003 void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
3005 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
3008 ddr_move_to_Config_state();
3009 pDDR_Reg->TZQCSI = 0;
3010 if((nMHz<=DDR3_DDR2_ODT_DLL_DISABLE_FREQ) && ((mem_type == DDR3) || (mem_type == DDR2))) // DLL disable
3012 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3013 pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3014 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));
3016 ddr_move_to_Lowpower_state();
3018 ddr_set_dll_bypass(0); //dll bypass
3019 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
3023 void __sramlocalfunc ddr_selfrefresh_exit(void)
3027 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
3029 ddr_set_dll_bypass(ddr_freq);
3031 //ddr_delayus(10); //wait DLL lock
3033 ddr_move_to_Config_state();
3034 ddr_update_timing();
3037 n = ddr_data_training();
3038 ddr_move_to_Access_state();
3041 sram_printascii("DTT failed!\n");
3045 #if defined(CONFIG_ARCH_RK3066B)
3046 static __sramdata uint32_t data8_dqstr[25][4];
3047 static __sramdata uint32_t min_ddr_freq,dqstr_flag=false;
3049 int ddr_get_datatraing_value_3168(bool end_flag,uint32_t dqstr_value,uint32_t min_freq)
3051 if(end_flag == true)
3053 dqstr_flag = true; //complete learn data training value flag
3054 min_ddr_freq = min_freq;
3058 data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3059 data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3060 data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3061 data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3063 ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3064 clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3065 data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3068 EXPORT_SYMBOL(ddr_get_datatraing_value_3168);
3070 void __sramlocalfunc ddr_set_pll_enter_3168(uint32_t freq_slew)
3072 uint32_t value_1u,value_100n;
3073 ddr_move_to_Config_state();
3077 value_100n = ddr_reg.pctl.pctl_timing.togcnt100n;
3078 value_1u = ddr_reg.pctl.pctl_timing.togcnt1u;
3079 ddr_reg.pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3080 ddr_reg.pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3081 ddr_update_timing();
3083 ddr_reg.pctl.pctl_timing.togcnt100n = value_100n;
3084 ddr_reg.pctl.pctl_timing.togcnt1u = value_1u;
3088 pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
3089 pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
3092 pDDR_Reg->TZQCSI = 0;
3093 ddr_move_to_Lowpower_state();
3095 ddr_set_dll_bypass(0); //dll bypass
3096 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
3100 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32_t dqstr_value)
3102 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
3104 ddr_set_dll_bypass(ddr_freq);
3107 if(dqstr_flag==true)
3109 pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3110 pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3111 pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3112 pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3116 ddr_move_to_Config_state();
3119 pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
3120 pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
3121 pDDR_Reg->TZQCSI = ddr_reg.pctl.pctl_timing.tzqcsi;
3125 ddr_update_timing();
3128 ddr_data_training();
3129 ddr_move_to_Access_state();
3133 uint32_t __sramfunc ddr_change_freq_sram(uint32_t nMHz , struct ddr_freq_t ddr_freq_t)
3138 unsigned long flags;
3139 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3140 unsigned long save_sp;
3143 #if defined(CONFIG_ARCH_RK3066B)
3144 uint32_t freq_slew=0,dqstr_value=0;
3145 if(dqstr_flag==true)
3147 dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
3148 freq_slew = (nMHz>ddr_freq)? 1 : 0;
3152 freq = ddr_get_pll_freq(APLL); //APLL
3154 loops_per_us = LPJ_100MHZ*freq / 1000000;
3156 ret=ddr_set_pll(nMHz,0);
3158 ddr_get_parameter(ret);
3160 /** 1. Make sure there is no host access */
3161 local_irq_save(flags);
3162 local_fiq_disable();
3167 DDR_SAVE_SP(save_sp);
3169 #if defined(CONFIG_ARCH_RK30)
3170 #define SRAM_SIZE RK30_IMEM_SIZE
3171 #elif defined(CONFIG_ARCH_RK3188)
3172 #define SRAM_SIZE RK3188_IMEM_SIZE
3174 for(i=0;i<SRAM_SIZE/4096;i++)
3180 n= pDDR_Reg->SCFG.d32;
3182 n= pCRU_Reg->CRU_PLL_CON[0][0];
3183 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3184 n= *(volatile uint32_t *)SysSrv_DdrConf;
3185 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3186 n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
3188 n= pGRF_Reg->GRF_SOC_STATUS0;
3192 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3193 n = ddr_freq_t.screen_ft_us;
3197 if(ddr_freq_t.screen_ft_us > 0)
3199 ddr_freq_t.t1 = cpu_clock(0);
3200 ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0); //ns
3202 //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
3203 if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe))
3205 DDR_RESTORE_SP(save_sp);
3207 local_irq_restore(flags);
3212 rk_fb_poll_wait_frame_complete();
3217 /** 2. ddr enter self-refresh mode or precharge power-down mode */
3219 #if defined(CONFIG_ARCH_RK3066B)
3220 ddr_set_pll_enter_3168(freq_slew);
3222 ddr_selfrefresh_enter(ret);
3225 /** 3. change frequence */
3229 /** 5. Issues a Mode Exit command */
3230 #if defined(CONFIG_ARCH_RK3066B)
3231 ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3233 ddr_selfrefresh_exit();
3237 DDR_RESTORE_SP(save_sp);
3239 local_irq_restore(flags);
3243 uint32_t ddr_change_freq_gpll_dpll(uint32_t nMHz)
3245 uint32_t gpll_freq,gpll_div;
3246 struct ddr_freq_t ddr_freq_t;
3247 ddr_freq_t.screen_ft_us = 0;
3249 gpllvaluel = ddr_get_pll_freq(GPLL);
3251 if((200 < gpllvaluel) ||( gpllvaluel <1600)) //GPLL:200MHz~1600MHz
3253 if( gpllvaluel > 800) //800-1600MHz /4:200MHz-400MHz
3255 gpll_freq = gpllvaluel/4;
3258 else if( gpllvaluel > 400) //400-800MHz /2:200MHz-400MHz
3260 gpll_freq = gpllvaluel/2;
3263 else //200-400MHz /1:200MHz-400MHz
3265 gpll_freq = gpllvaluel;
3269 ddr_select_gpll_div=gpll_div; //select GPLL
3270 ddr_change_freq_sram(gpll_freq,ddr_freq_t);
3271 ddr_select_gpll_div=0;
3273 ddr_set_pll(nMHz,0); //count DPLL
3274 ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3278 ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3281 return ddr_change_freq_sram(nMHz,ddr_freq_t);
3285 /*****************************************
3286 if rk3188 DPLL is bad,use GPLL
3288 1000MHz-2000MHz 4:250MHz-500MHz
3289 800MHz-1000MHz 4:200MHz-250MHz 2:400MHz-500MHz
3290 500MHz-800MHz 2:250MHz-400MHz
3291 200MHz-500MHz 1:200MHz-500MHz
3292 ******************************************/
3293 uint32_t ddr_change_freq(uint32_t nMHz)
3295 struct ddr_freq_t ddr_freq_t;
3296 ddr_freq_t.screen_ft_us = 0;
3298 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH) && defined(CONFIG_ARCH_RK3188)
3299 return ddr_change_freq_gpll_dpll(nMHz);
3301 return ddr_change_freq_sram(nMHz,ddr_freq_t);
3304 EXPORT_SYMBOL(ddr_change_freq);
3306 void ddr_set_auto_self_refresh(bool en)
3308 //set auto self-refresh idle
3309 ddr_sr_idle = en ? SR_IDLE : 0;
3311 EXPORT_SYMBOL(ddr_set_auto_self_refresh);
3320 #define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
3321 #define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
3323 #define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
3324 #define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
3326 #define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
3328 #define PERI_ACLK_DIV_MASK 0x1f
3329 #define PERI_ACLK_DIV_OFF 0
3331 #define PERI_HCLK_DIV_MASK 0x3
3332 #define PERI_HCLK_DIV_OFF 8
3334 #define PERI_PCLK_DIV_MASK 0x3
3335 #define PERI_PCLK_DIV_OFF 12
3336 static __sramdata u32 cru_sel32_sram;
3337 void __sramfunc ddr_suspend(void)
3341 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3344 if(pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8))
3348 /** 1. Make sure there is no host access */
3353 #if defined(CONFIG_ARCH_RK30)
3354 #define SRAM_SIZE RK30_IMEM_SIZE
3355 #elif defined(CONFIG_ARCH_RK3188)
3356 #define SRAM_SIZE RK3188_IMEM_SIZE
3358 for(i=0;i<SRAM_SIZE/4096;i++)
3364 n= pDDR_Reg->SCFG.d32;
3366 n= pCRU_Reg->CRU_PLL_CON[0][0];
3367 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3368 n= *(volatile uint32_t *)SysSrv_DdrConf;
3369 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3370 n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
3372 n= pGRF_Reg->GRF_SOC_STATUS0;
3376 ddr_selfrefresh_enter(0);
3378 pCRU_Reg->CRU_MODE_CON = PLL_MODE_SLOW(pll_idx); //PLL slow-mode
3381 pCRU_Reg->CRU_PLL_CON[pll_idx][3] = ((0x1<<1)<<16) | (0x1<<1); //PLL power-down
3384 if(pll_idx==GPLL_IDX)
3386 cru_sel32_sram= pCRU_Reg->CRU_CLKSEL_CON[10];
3388 pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
3389 | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
3390 |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
3392 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29))); //CKOE
3394 EXPORT_SYMBOL(ddr_suspend);
3396 void __sramfunc ddr_resume(void)
3400 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3406 if(pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8))
3417 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29)); //CKOE
3420 if(pll_idx==GPLL_IDX)
3421 pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
3425 pCRU_Reg->CRU_PLL_CON[pll_idx][3] = ((0x1<<1)<<16) | (0x0<<1); //PLL no power-down
3430 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3431 if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (1<<5))
3434 if (pGRF_Reg->GRF_SOC_STATUS0 & (1<<4))
3440 pCRU_Reg->CRU_MODE_CON = PLL_MODE_NORM(pll_idx); //PLL normal
3443 ddr_selfrefresh_exit();
3445 EXPORT_SYMBOL(ddr_resume);
3447 //»ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
3448 uint32 ddr_get_cap(void)
3452 if(pPMU_Reg->PMU_PMU_SYS_REG[2])
3454 cap = (1 << (READ_CS0_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
3455 if(READ_CS_INFO()>1)
3457 cap +=(1 << (READ_CS1_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
3462 cap = (1 << (ddr_get_row()+ddr_get_col()+ddr_get_bank()+ddr_get_bw()))*ddr_get_cs();
3467 EXPORT_SYMBOL(ddr_get_cap);
3469 void ddr_reg_save(void)
3472 ddr_reg.pctl.SCFG = pDDR_Reg->SCFG.d32;
3473 ddr_reg.pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
3474 ddr_reg.pctl.MCFG1 = pDDR_Reg->MCFG1;
3475 ddr_reg.pctl.MCFG = pDDR_Reg->MCFG;
3476 ddr_reg.pctl.pctl_timing.ddrFreq = ddr_freq;
3477 ddr_reg.pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
3478 ddr_reg.pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
3479 ddr_reg.pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
3480 ddr_reg.pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
3481 ddr_reg.pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
3482 ddr_reg.pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
3483 ddr_reg.pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
3484 ddr_reg.pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
3485 ddr_reg.pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
3486 ddr_reg.pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
3487 ddr_reg.pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
3488 ddr_reg.pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
3489 ddr_reg.pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
3490 ddr_reg.pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
3491 ddr_reg.pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
3493 ddr_reg.pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
3494 ddr_reg.pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
3495 ddr_reg.pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
3496 ddr_reg.pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
3497 ddr_reg.pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
3498 ddr_reg.pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
3499 ddr_reg.pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
3500 ddr_reg.pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
3501 ddr_reg.pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
3504 ddr_reg.publ.PIR = pPHY_Reg->PIR;
3505 ddr_reg.publ.PGCR = pPHY_Reg->PGCR;
3506 ddr_reg.publ.DLLGCR = pPHY_Reg->DLLGCR;
3507 ddr_reg.publ.ACDLLCR = pPHY_Reg->ACDLLCR;
3508 ddr_reg.publ.PTR[0] = pPHY_Reg->PTR[0];
3509 ddr_reg.publ.PTR[1] = pPHY_Reg->PTR[1];
3510 ddr_reg.publ.PTR[2] = pPHY_Reg->PTR[2];
3511 ddr_reg.publ.ACIOCR = pPHY_Reg->ACIOCR;
3512 ddr_reg.publ.DXCCR = pPHY_Reg->DXCCR;
3513 ddr_reg.publ.DSGCR = pPHY_Reg->DSGCR;
3514 ddr_reg.publ.DCR = pPHY_Reg->DCR.d32;
3515 ddr_reg.publ.ODTCR = pPHY_Reg->ODTCR;
3516 ddr_reg.publ.DTAR = pPHY_Reg->DTAR;
3517 ddr_reg.publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
3518 ddr_reg.publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
3520 ddr_reg.publ.DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
3521 ddr_reg.publ.DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
3522 ddr_reg.publ.DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
3523 ddr_reg.publ.DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
3525 ddr_reg.publ.DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
3526 ddr_reg.publ.DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
3527 ddr_reg.publ.DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
3528 ddr_reg.publ.DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
3530 ddr_reg.publ.DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
3531 ddr_reg.publ.DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
3532 ddr_reg.publ.DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
3533 ddr_reg.publ.DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
3535 ddr_reg.publ.DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
3536 ddr_reg.publ.DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
3537 ddr_reg.publ.DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
3538 ddr_reg.publ.DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
3541 ddr_reg.DdrConf = *(volatile uint32_t *)SysSrv_DdrConf;
3542 ddr_reg.DdrMode = *(volatile uint32_t *)SysSrv_DdrMode;
3543 ddr_reg.ReadLatency = *(volatile uint32_t *)SysSrv_ReadLatency;
3545 EXPORT_SYMBOL(ddr_reg_save);
3547 __attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
3549 #include "ddr_reg_resume.inc"
3552 int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
3554 volatile uint32_t value = 0;
3558 ddr_print("version 1.00 201300810 \n");
3560 mem_type = pPHY_Reg->DCR.b.DDRMD;
3561 ddr_speed_bin = dram_speed_bin;
3566 ddr_freq = clk_get_rate(clk_get(NULL, "ddr"))/1000000;
3570 #if defined(CONFIG_ARCH_RK3188)
3571 ddr_soc_is_rk3188_plus = soc_is_rk3188plus();
3572 ddr_rk3188_dpll_is_good = ddr_get_dpll_status();
3577 if(pPMU_Reg->PMU_PMU_SYS_REG[2])
3579 die = (8<<READ_BW_INFO())/(8<<READ_DIE_BW_INFO());
3583 if(pDDR_Reg->PPCFG & 1)
3592 ddr_print("DDR3 Device\n");
3595 ddr_print("LPDDR2 Device\n");
3598 ddr_print("DDR2 Device\n");
3601 ddr_print("DDR Device\n");
3604 ddr_print("LPDDR Device\n");
3607 //get capability per chip, not total size, used for calculate tRFC
3608 ddr_capability_per_die = ddr_get_cap()/(ddr_get_cs()*die);
3609 ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
3612 (0x1<<(ddr_get_bank())), \
3615 (ddr_get_cap()>>20));
3616 ddr_adjust_config(mem_type);
3618 if(ddr_rk3188_dpll_is_good == true)
3621 value=ddr_change_freq(freq);
3623 value=ddr_change_freq(clk_get_rate(clk_get(NULL, "ddr"))/1000000);
3625 clk_set_rate(clk_get(NULL, "ddr"), 0);
3626 ddr_print("init success!!! freq=%luMHz\n", clk_get_rate(clk_get(NULL, "ddr"))/1000000);
3628 for(value=0;value<4;value++)
3630 gsr = pPHY_Reg->DATX8[value].DXGSR[0];
3631 dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
3632 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
3633 (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
3635 ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
3636 (pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
3637 (pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
3638 pPHY_Reg->ZQ0SR[1]&0x3,\
3639 (pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
3640 (pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
3641 (pPHY_Reg->ZQ0SR[1]>>6)&0x3);
3642 ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", pPHY_Reg->ZQ0SR[0]&0x1F, (pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
3643 ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
3647 EXPORT_SYMBOL(ddr_init);