1 /* arch/arm/mach-rk30/rk30_dvfs.c
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3 * Copyright (C) 2012 ROCKCHIP, Inc.
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5 * This software is licensed under the terms of the GNU General Public
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6 * License version 2, as published by the Free Software Foundation, and
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7 * may be copied, distributed, and modified under those terms.
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9 * This program is distributed in the hope that it will be useful,
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 * GNU General Public License for more details.
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16 #include <linux/kernel.h>
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17 #include <linux/err.h>
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18 #include <linux/spinlock.h>
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19 #include <linux/list.h>
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20 #include <linux/slab.h>
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21 #include <linux/clk.h>
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22 #include <linux/cpufreq.h>
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24 #include <mach/dvfs.h>
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25 #include <mach/clock.h>
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26 #include <linux/regulator/consumer.h>
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27 #include <linux/delay.h>
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29 #define JUMP_RATE 816000000
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30 #define LOGIC_VOLT_SCALING
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31 #define DVFS_DBG(fmt, args...) {while(0);} //pr_debug(fmt, ##args)
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32 #define DVFS_ERR(fmt, args...) pr_err(fmt, ##args)
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33 #define DVFS_LOG(fmt, args...) pr_debug(fmt, ##args)//while(0)
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35 #define dvfs_regulator_get(dev,id) regulator_get((dev),(id))
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36 #define dvfs_regulator_put(regu) regulator_put((regu))
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37 #define dvfs_regulator_set_voltage(regu,min_uV,max_uV) regulator_set_voltage((regu),(min_uV),(max_uV))
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38 #define dvfs_regulator_get_voltage(regu) regulator_get_voltage((regu))
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40 #define dvfs_clk_get(a,b) clk_get((a),(b))
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41 #define dvfs_clk_get_rate_kz(a) (clk_get_rate((a))/1000)
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42 #define dvfs_clk_set_rate(a,b) clk_set_rate((a),(b))
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43 #define dvfs_clk_enable(a) clk_enable((a))
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44 #define dvfs_clk_disable(a) clk_disable((a))
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46 #define DVFS_MHZ (1000*1000)
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47 #define DVFS_KHZ (1000)
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49 #define DVFS_V (1000*1000)
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50 #define DVFS_MV (1000)
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53 static LIST_HEAD(rk_dvfs_tree);
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54 static DEFINE_MUTEX(mutex);
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56 extern int rk30_clk_notifier_register(struct clk *clk, struct notifier_block *nb);
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57 extern int rk30_clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
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62 int is_support_dvfs(struct clk_node *dvfs_info)
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64 return (dvfs_info->vd && dvfs_info->vd->vd_dvfs_target && dvfs_info->enable_dvfs);
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67 int dvfs_set_rate(struct clk *clk, unsigned long rate)
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71 DVFS_DBG("%s(%s(%lu))\n", __func__, clk->name, rate);
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72 if (!clk->dvfs_info) {
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73 DVFS_ERR("%s :This clk do not support dvfs!\n", __func__);
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76 vd = clk->dvfs_info->vd;
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77 mutex_lock(&vd->dvfs_mutex);
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78 ret = vd->vd_dvfs_target(clk, rate);
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79 mutex_unlock(&vd->dvfs_mutex);
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81 DVFS_DBG("%s(%s(%lu)),is end\n", __func__, clk->name, rate);
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85 static int dvfs_clk_get_ref_volt(struct clk_node *dvfs_clk, int rate_khz,
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86 struct cpufreq_frequency_table *clk_fv)
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89 if (rate_khz == 0 || !dvfs_clk || !dvfs_clk->dvfs_table) {
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93 clk_fv->frequency = rate_khz;
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96 for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {
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97 if (dvfs_clk->dvfs_table[i].frequency >= rate_khz) {
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98 clk_fv->frequency = dvfs_clk->dvfs_table[i].frequency;
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99 clk_fv->index = dvfs_clk->dvfs_table[i].index;
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100 // DVFS_DBG("%s,%s rate=%ukhz(vol=%d)\n",__func__,dvfs_clk->name,
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101 // clk_fv->frequency, clk_fv->index);
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105 clk_fv->frequency = 0;
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107 // DVFS_DBG("%s get corresponding voltage error! out of bound\n", dvfs_clk->name);
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111 static int dvfs_pd_get_newvolt_byclk(struct pd_node *pd, struct clk_node *dvfs_clk)
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113 struct clk_list *child;
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116 if (!pd || !dvfs_clk)
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119 if (dvfs_clk->set_volt >= pd->cur_volt) {
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120 return dvfs_clk->set_volt;
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123 list_for_each_entry(child, &pd->clk_list, node) {
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124 //DVFS_DBG("%s ,pd(%s),dvfs(%s),volt(%u)\n",__func__,pd->name,
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125 //dvfs_clk->name,dvfs_clk->set_volt);
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126 volt_max = max(volt_max, child->dvfs_clk->set_volt);
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131 void dvfs_update_clk_pds_volt(struct clk_node *dvfs_clk)
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133 struct pd_node *pd;
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137 for (i = 0; (dvfs_clk->pds[i].pd != NULL); i++) {
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138 pd = dvfs_clk->pds[i].pd;
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139 // DVFS_DBG("%s dvfs(%s),pd(%s)\n",__func__,dvfs_clk->name,pd->name);
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140 pd->cur_volt = dvfs_pd_get_newvolt_byclk(pd, dvfs_clk);
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144 static int dvfs_vd_get_newvolt_bypd(struct vd_node *vd)
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146 struct pd_node *pd;
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147 int volt_max_vd = 0;
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148 list_for_each_entry(pd, &vd->pd_list, node) {
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149 //DVFS_DBG("%s pd(%s,%u)\n",__func__,pd->name,pd->cur_volt);
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150 volt_max_vd = max(volt_max_vd, pd->cur_volt);
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152 return volt_max_vd;
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155 static int dvfs_vd_get_newvolt_byclk(struct clk_node *dvfs_clk)
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159 dvfs_update_clk_pds_volt(dvfs_clk);
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160 return dvfs_vd_get_newvolt_bypd(dvfs_clk->vd);
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163 void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target)
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165 struct clk_node *dvfs_clk = clk_get_dvfs_info(clk);
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166 dvfs_clk->clk_dvfs_target = clk_dvfs_target;
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169 struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk)
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171 struct clk_node *info = clk_get_dvfs_info(clk);
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172 struct cpufreq_frequency_table *table;
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173 if (!info || !info->dvfs_table) {
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176 mutex_lock(&mutex);
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177 table = info->dvfs_table;
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178 mutex_unlock(&mutex);
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182 int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table)
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184 struct clk_node *info = clk_get_dvfs_info(clk);
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185 if (!table || !info)
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188 mutex_lock(&mutex);
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189 info->dvfs_table = table;
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190 mutex_unlock(&mutex);
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194 int clk_enable_dvfs(struct clk *clk)
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196 struct regulator *regulator;
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197 struct clk_node *dvfs_clk;
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198 struct cpufreq_frequency_table clk_fv;
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200 DVFS_ERR("clk enable dvfs error\n");
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203 dvfs_clk = clk_get_dvfs_info(clk);
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204 if (!dvfs_clk || !dvfs_clk->vd) {
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205 DVFS_ERR("%s clk(%s) not support dvfs!\n", __func__, clk->name);
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208 if (dvfs_clk->enable_dvfs == 0) {
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210 if (!dvfs_clk->vd->regulator) {
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212 if (dvfs_clk->vd->regulator_name)
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213 regulator = dvfs_regulator_get(NULL, dvfs_clk->vd->regulator_name);
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215 //DVFS_DBG("dvfs_regulator_get(%s)\n",dvfs_clk->vd->regulator_name);
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216 dvfs_clk->vd->regulator = regulator;
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218 dvfs_clk->vd->regulator = NULL;
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219 dvfs_clk->enable_dvfs = 0;
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220 DVFS_ERR("%s can't get regulator in %s\n", dvfs_clk->name, __func__);
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224 dvfs_clk->vd->cur_volt = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);
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225 //DVFS_DBG("%s(%s) vd volt=%u\n",__func__,dvfs_clk->name,dvfs_clk->vd->cur_volt);
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228 dvfs_clk->set_freq = dvfs_clk_get_rate_kz(clk);
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229 //DVFS_DBG("%s ,%s get freq%u!\n",__func__,dvfs_clk->name,dvfs_clk->set_freq);
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231 if (dvfs_clk_get_ref_volt(dvfs_clk, dvfs_clk->set_freq, &clk_fv)) {
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232 dvfs_clk->enable_dvfs = 0;
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235 dvfs_clk->set_volt = clk_fv.index;
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236 //DVFS_DBG("%s,%s,freq%u(ref vol %u)\n",__func__,dvfs_clk->name,
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237 // dvfs_clk->set_freq,dvfs_clk->set_volt);
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239 if (dvfs_clk->dvfs_nb) {
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240 // must unregister when clk disable
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241 rk30_clk_notifier_register(clk, dvfs_clk->dvfs_nb);
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244 dvfs_vd_get_newvolt_byclk(dvfs_clk);
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245 dvfs_clk->enable_dvfs++;
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247 DVFS_ERR("dvfs already enable clk enable = %d!\n", dvfs_clk->enable_dvfs);
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248 dvfs_clk->enable_dvfs++;
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253 int clk_disable_dvfs(struct clk *clk)
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255 struct clk_node *dvfs_clk;
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256 dvfs_clk = clk->dvfs_info;
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257 if (!dvfs_clk->enable_dvfs) {
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258 DVFS_DBG("clk is already closed!\n");
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261 dvfs_clk->enable_dvfs--;
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262 if (0 == dvfs_clk->enable_dvfs) {
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263 DVFS_ERR("clk closed!\n");
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264 rk30_clk_notifier_unregister(clk, dvfs_clk->dvfs_nb);
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265 DVFS_DBG("clk unregister nb!\n");
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271 static int rk_dvfs_clk_notifier_event(struct notifier_block *this,
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272 unsigned long event, void *ptr)
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274 struct clk_notifier_data *noti_info;
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276 struct clk_node *dvfs_clk;
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277 noti_info = (struct clk_notifier_data *)ptr;
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278 clk = noti_info->clk;
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279 dvfs_clk = clk->dvfs_info;
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282 case CLK_PRE_RATE_CHANGE:
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283 DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);
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285 case CLK_POST_RATE_CHANGE:
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286 DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);
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288 case CLK_ABORT_RATE_CHANGE:
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289 DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);
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291 case CLK_PRE_ENABLE:
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292 DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);
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294 case CLK_POST_ENABLE:
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295 DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);
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297 case CLK_ABORT_ENABLE:
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298 DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);
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300 case CLK_PRE_DISABLE:
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301 DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);
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303 case CLK_POST_DISABLE:
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304 DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);
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305 dvfs_clk->set_freq = 0;
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307 case CLK_ABORT_DISABLE:
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308 DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);
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317 static struct notifier_block rk_dvfs_clk_notifier = {
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318 .notifier_call = rk_dvfs_clk_notifier_event,
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321 static int rk_regist_vd(struct vd_node *vd)
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325 mutex_lock(&mutex);
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326 mutex_init(&vd->dvfs_mutex);
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327 list_add(&vd->node, &rk_dvfs_tree);
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328 INIT_LIST_HEAD(&vd->pd_list);
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330 mutex_unlock(&mutex);
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334 static int rk_regist_pd(struct pd_node_lookup *pd_lookup)
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336 struct vd_node *vd;
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337 struct pd_node *pd;
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339 mutex_lock(&mutex);
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340 pd = pd_lookup->pd;
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342 list_for_each_entry(vd, &rk_dvfs_tree, node) {
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343 if (vd == pd->vd) {
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344 list_add(&pd->node, &vd->pd_list);
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345 INIT_LIST_HEAD(&pd->clk_list);
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349 mutex_unlock(&mutex);
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353 static int rk_regist_clk(struct clk_node *dvfs_clk)
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355 struct pd_node *pd;
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356 struct clk_list *child;
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363 if (!dvfs_clk->pds)
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365 mutex_lock(&mutex);
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366 dvfs_clk->enable_dvfs = 0;
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367 dvfs_clk->vd = dvfs_clk->pds[0].pd->vd;
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368 for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {
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369 child = &(dvfs_clk->pds[i].clk_list);
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370 child->dvfs_clk = dvfs_clk;
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371 pd = dvfs_clk->pds[i].pd;
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372 list_add(&child->node, &pd->clk_list);
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374 clk = dvfs_clk_get(NULL, dvfs_clk->name);
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375 dvfs_clk->ck = clk;
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376 clk_register_dvfs(dvfs_clk, clk);
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377 mutex_unlock(&mutex);
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381 #define get_volt_up_delay(new_volt, old_volt) \
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382 ((new_volt) > (old_volt) ? (((new_volt) - (old_volt)) >> 10) : 0)
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384 #ifdef LOGIC_VOLT_SCALING
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385 #define DVFS_LOGIC_VOLT_H 1175000
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386 #define DVFS_LOGIC_VOLT_L 1025000
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387 static int dvfs_up_volt_logic(void)
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389 struct regulator *vdd_core;
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391 DVFS_DBG("second jump > 816M\n");
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392 vdd_core = dvfs_regulator_get(NULL, "vdd_core");
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393 ret = dvfs_regulator_set_voltage(vdd_core, DVFS_LOGIC_VOLT_H, DVFS_LOGIC_VOLT_H);
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395 DVFS_DBG("DVFS > 816M\n");
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397 DVFS_ERR("%s err, ret = %d\n", __func__, ret);
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400 dvfs_regulator_put(vdd_core);
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404 static int dvfs_down_volt_logic(void)
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406 struct regulator *vdd_core;
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408 DVFS_DBG("first jump %d\n", JUMP_RATE);
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409 vdd_core = dvfs_regulator_get(NULL, "vdd_core");
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410 ret = dvfs_regulator_set_voltage(vdd_core, DVFS_LOGIC_VOLT_L, DVFS_LOGIC_VOLT_L);
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412 DVFS_DBG("DVFS <= 816M\n");
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414 DVFS_ERR("%s err, ret = %d\n", __func__, ret);
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417 dvfs_regulator_put(vdd_core);
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421 static int flag_core_set_volt_err = 0;
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422 int dvfs_target_core(struct clk *clk, unsigned long rate_hz)
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424 struct clk_node *dvfs_clk;
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425 unsigned int volt_new = 0, volt_old = 0, volt_clk_old = 0;
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426 struct cpufreq_frequency_table clk_fv = {0, 0};
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428 int flag_set_volt_correct = 0;
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429 unsigned long temp_hz;
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432 DVFS_ERR("%s is not clk\n", __func__);
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435 dvfs_clk = clk_get_dvfs_info(clk);
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437 if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {
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438 DVFS_ERR("%s can't get dvfs regulater\n", clk->name);
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442 temp_hz = rate_hz;//clk_round_rate_nolock(clk, rate_hz);
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444 //DVFS_DBG("dvfs(%s) round rate(%lu)(rount %lu)\n",dvfs_clk->name,rate_hz,temp_hz);
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446 /* find the clk corresponding voltage */
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447 if (dvfs_clk_get_ref_volt(dvfs_clk, temp_hz / 1000, &clk_fv)) {
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448 DVFS_ERR("%s--%s:rate%lu,Get corresponding voltage error!\n",
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449 __func__, dvfs_clk->name, temp_hz);
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452 volt_old = dvfs_clk->vd->cur_volt;
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454 volt_clk_old = dvfs_clk->set_volt;
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456 dvfs_clk->set_volt = clk_fv.index;
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458 volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);
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460 DVFS_LOG("dvfs--(%s),volt=%d(was %dmV),rate=%lu(was %lu),vd%u=(was%u)\n",
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461 dvfs_clk->name, clk_fv.index, dvfs_clk->set_volt, temp_hz, clk_get_rate(clk)
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462 , volt_new, volt_old);
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464 if (flag_core_set_volt_err) {
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465 /* It means the last time set voltage error */
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466 flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);
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467 if (flag_set_volt_correct <= 0) {
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468 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt error %d!!! stop scaling\n",
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469 __func__, dvfs_clk->name, volt_new, volt_old,
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470 temp_hz, clk_get_rate(clk), flag_set_volt_correct);
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474 flag_core_set_volt_err = 0;
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475 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt! core_volt_correct = %d\n",
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476 __func__, dvfs_clk->name, volt_new, volt_old,
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477 temp_hz, clk_get_rate(clk), flag_set_volt_correct);
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479 /* Reset vd's voltage */
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480 dvfs_clk->vd->cur_volt = flag_set_volt_correct;
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481 volt_old = dvfs_clk->vd->cur_volt;
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484 /* if up the voltage */
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485 if (volt_old < volt_new) {
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486 if (dvfs_clk->vd->regulator) {
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487 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
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489 flag_core_set_volt_err = 1;
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490 DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
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491 __func__, dvfs_clk->name, ret,
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492 temp_hz, clk_get_rate(clk), volt_new, volt_old);
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497 DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);
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501 dvfs_clk->vd->cur_volt = volt_new;
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502 udelay(get_volt_up_delay(volt_new, volt_old));
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503 DVFS_LOG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n",
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504 __func__, dvfs_clk->name, ret, volt_new, volt_old, temp_hz, clk_get_rate(clk));
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507 if (dvfs_clk->clk_dvfs_target) {
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508 ret = dvfs_clk->clk_dvfs_target(clk, temp_hz, clk_set_rate_locked);
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510 ret = clk_set_rate_locked(clk, temp_hz);
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515 dvfs_clk->set_volt = volt_old;
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516 dvfs_vd_get_newvolt_byclk(dvfs_clk);
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517 DVFS_ERR("set rate err\n");
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520 dvfs_clk->set_freq = temp_hz / 1000;
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522 /* if down the voltage */
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523 if (volt_old > volt_new) {
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524 if (dvfs_clk->vd->regulator) {
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525 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
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527 flag_core_set_volt_err = 1;
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528 DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
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529 __func__, dvfs_clk->name, ret, temp_hz, clk_get_rate(clk),
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530 volt_new, volt_old);
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535 DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);
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539 dvfs_clk->vd->cur_volt = volt_new;
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540 DVFS_LOG("dvfs %s set volt ok dn\n", dvfs_clk->name);
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547 static int flag_arm_set_volt_err = 0;
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548 int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)
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550 struct clk_node *dvfs_clk;
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551 int volt_new = 0, volt_old = 0;
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552 struct cpufreq_frequency_table clk_fv;
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554 int flag_set_volt_correct = 0;
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555 unsigned long temp_hz, pre_rate_hz;
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559 DVFS_ERR("%s is not clk\n", __func__);
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562 dvfs_clk = clk_get_dvfs_info(clk);
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564 if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {
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565 DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);
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569 /* need round rate */
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570 temp_hz = clk_round_rate_nolock(clk, rate_hz);
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571 DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu)\n", dvfs_clk->name, rate_hz, temp_hz);
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573 pre_rate_hz = clk_get_rate(clk);
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574 /* find the clk corresponding voltage */
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575 if (0 != dvfs_clk_get_ref_volt(dvfs_clk, temp_hz / 1000, &clk_fv)) {
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576 DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);
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580 volt_old = dvfs_clk->vd->cur_volt;
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581 volt_new = clk_fv.index;
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582 if (flag_arm_set_volt_err) {
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583 /* It means the last time set voltage error */
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584 flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);
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585 if (flag_set_volt_correct <= 0) {
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586 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt error %d!!! stop scaling\n",
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587 __func__, dvfs_clk->name, volt_new, volt_old,
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588 temp_hz, clk_get_rate(clk), flag_set_volt_correct);
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592 flag_arm_set_volt_err = 0;
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593 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt! arm_volt_correct = %d\n",
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594 __func__, dvfs_clk->name, volt_new, volt_old,
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595 temp_hz, clk_get_rate(clk), flag_set_volt_correct);
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597 /* Reset vd's voltage */
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598 dvfs_clk->vd->cur_volt = flag_set_volt_correct;
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599 volt_old = dvfs_clk->vd->cur_volt;
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601 #ifdef LOGIC_VOLT_SCALING
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602 if (temp_hz > JUMP_RATE && pre_rate_hz <= JUMP_RATE) {
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603 ret = dvfs_up_volt_logic();
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605 DVFS_ERR("%s up logic volt error %d", __func__, ret);
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610 /* if up the voltage */
\r
611 if (volt_old < volt_new) {
\r
612 if (dvfs_clk->vd->regulator) {
\r
613 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
\r
615 flag_arm_set_volt_err = 1;
\r
616 DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
\r
617 __func__, dvfs_clk->name, ret, temp_hz, clk_get_rate(clk),
\r
618 volt_new, volt_old);
\r
623 DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);
\r
627 dvfs_clk->vd->cur_volt = volt_new;
\r
628 udelay(get_volt_up_delay(volt_new, volt_old));
\r
629 DVFS_LOG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n",
\r
630 __func__, dvfs_clk->name, ret, volt_new, volt_old, temp_hz, clk_get_rate(clk));
\r
633 if (dvfs_clk->clk_dvfs_target) {
\r
634 ret = dvfs_clk->clk_dvfs_target(clk, temp_hz, clk_set_rate_locked);
\r
636 ret = clk_set_rate_locked(clk, temp_hz);
\r
640 DVFS_ERR("set rate err\n");
\r
643 dvfs_clk->set_freq = temp_hz / 1000;
\r
645 DVFS_LOG("dvfs %s set rate%lu ok\n", dvfs_clk->name, clk_get_rate(clk));
\r
647 /* if down the voltage */
\r
648 if (volt_old > volt_new) {
\r
649 if (dvfs_clk->vd->regulator) {
\r
650 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
\r
652 flag_arm_set_volt_err = 1;
\r
653 DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
\r
654 __func__, dvfs_clk->name, ret, temp_hz, clk_get_rate(clk),
\r
655 volt_new, volt_old);
\r
660 DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);
\r
664 dvfs_clk->vd->cur_volt = volt_new;
\r
665 DVFS_LOG("dvfs %s set volt ok dn\n", dvfs_clk->name);
\r
668 #ifdef LOGIC_VOLT_SCALING
\r
669 if (temp_hz <= JUMP_RATE && pre_rate_hz > JUMP_RATE) {
\r
670 ret = dvfs_down_volt_logic();
\r
672 DVFS_ERR("%s down logic volt error %d", __func__, ret);
\r
682 /*****************************init**************************/
\r
684 * rate must be raising sequence
\r
686 static struct cpufreq_frequency_table cpu_dvfs_table[] = {
\r
687 //{.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},
\r
688 //{.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},
\r
689 // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},
\r
690 // {.frequency = 504 * DVFS_KHZ, .index = 1060 * DVFS_MV},
\r
691 {.frequency = 816 * DVFS_KHZ, .index = 1080 * DVFS_MV},
\r
692 // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
693 {.frequency = CPUFREQ_TABLE_END},
\r
696 static struct cpufreq_frequency_table ddr_dvfs_table[] = {
\r
697 //{.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
698 {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},
\r
699 {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
700 {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
701 {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},
\r
702 {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},
\r
703 {.frequency = CPUFREQ_TABLE_END},
\r
706 static struct cpufreq_frequency_table gpu_dvfs_table[] = {
\r
707 {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},
\r
708 {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
709 {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
710 {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},
\r
711 {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},
\r
712 {.frequency = CPUFREQ_TABLE_END},
\r
715 static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {
\r
716 {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},
\r
717 {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
718 {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},
\r
719 {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
720 {.frequency = CPUFREQ_TABLE_END},
\r
723 static struct vd_node vd_cpu = {
\r
725 .regulator_name = "vdd_cpu",
\r
726 .vd_dvfs_target = dvfs_target_cpu,
\r
729 static struct vd_node vd_core = {
\r
731 .regulator_name = "vdd_core",
\r
732 .vd_dvfs_target = dvfs_target_core,
\r
735 static struct vd_node vd_rtc = {
\r
737 .regulator_name = "vdd_rtc",
\r
738 .vd_dvfs_target = NULL,
\r
741 static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};
\r
743 static struct pd_node pd_a9_0 = {
\r
747 static struct pd_node pd_a9_1 = {
\r
751 static struct pd_node pd_debug = {
\r
752 .name = "pd_debug",
\r
755 static struct pd_node pd_scu = {
\r
759 static struct pd_node pd_video = {
\r
760 .name = "pd_video",
\r
763 static struct pd_node pd_vio = {
\r
767 static struct pd_node pd_gpu = {
\r
771 static struct pd_node pd_peri = {
\r
775 static struct pd_node pd_cpu = {
\r
779 static struct pd_node pd_alive = {
\r
780 .name = "pd_alive",
\r
783 static struct pd_node pd_rtc = {
\r
787 #define LOOKUP_PD(_ppd) \
\r
791 static struct pd_node_lookup rk30_pds[] = {
\r
792 LOOKUP_PD(&pd_a9_0),
\r
793 LOOKUP_PD(&pd_a9_1),
\r
794 LOOKUP_PD(&pd_debug),
\r
795 LOOKUP_PD(&pd_scu),
\r
796 LOOKUP_PD(&pd_video),
\r
797 LOOKUP_PD(&pd_vio),
\r
798 LOOKUP_PD(&pd_gpu),
\r
799 LOOKUP_PD(&pd_peri),
\r
800 LOOKUP_PD(&pd_cpu),
\r
801 LOOKUP_PD(&pd_alive),
\r
802 LOOKUP_PD(&pd_rtc),
\r
805 #define CLK_PDS(_ppd) \
\r
810 static struct pds_list cpu_pds[] = {
\r
816 static struct pds_list ddr_pds[] = {
\r
821 static struct pds_list gpu_pds[] = {
\r
826 #define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \
\r
828 .name = _clk_name, \
\r
830 .dvfs_table = _dvfs_table, \
\r
831 .dvfs_nb = _dvfs_nb, \
\r
834 static struct pds_list aclk_periph_pds[] = {
\r
840 static struct clk_node rk30_clks[] = {
\r
841 RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),
\r
842 RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),
\r
843 RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),
\r
844 RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),
\r
847 int rk30_dvfs_init(void)
\r
850 for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {
\r
851 rk_regist_vd(rk30_vds[i]);
\r
853 for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {
\r
854 rk_regist_pd(&rk30_pds[i]);
\r
856 for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {
\r
857 rk_regist_clk(&rk30_clks[i]);
\r
863 //#define DVFS_DUMP_DBG
\r
864 #ifdef DVFS_DUMP_DBG
\r
866 * dump_dbg_map() : Draw all informations of dvfs while debug
\r
868 static void dump_dbg_map(void)
\r
871 struct vd_node *vd;
\r
872 struct pd_node *pd, *clkparent;
\r
873 struct clk_list *child;
\r
874 struct clk_node *dvfs_clk;
\r
876 DVFS_DBG("-------------DVFS DEBUG-----------\n\n\n");
\r
877 DVFS_DBG("RK30 DVFS TREE:\n");
\r
878 list_for_each_entry(vd, &rk_dvfs_tree, node) {
\r
879 DVFS_DBG("|\n|- voltage domain:%s\n", vd->name);
\r
880 DVFS_DBG("|- current voltage:%d\n", vd->cur_volt);
\r
882 list_for_each_entry(pd, &vd->pd_list, node) {
\r
883 DVFS_DBG("| |\n| |- power domain:%s, status = %s, current volt = %d\n",
\r
884 pd->name, (pd->pd_status == PD_ON) ? "ON" : "OFF", pd->cur_volt);
\r
886 list_for_each_entry(child, &pd->clk_list, node) {
\r
887 dvfs_clk = child->dvfs_clk;
\r
888 DVFS_DBG("| | |\n| | |- clock: %s current: rate %d, volt = %d, enable_dvfs = %s\n",
\r
889 dvfs_clk->name, dvfs_clk->set_freq, dvfs_clk->set_volt,
\r
890 dvfs_clk->enable_dvfs == 0 ? "DISABLE" : "ENABLE");
\r
891 for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {
\r
892 clkparent = dvfs_clk->pds[i].pd;
\r
893 DVFS_DBG("| | | |- clock parents: %s, vd_parent = %s\n",
\r
894 clkparent->name, clkparent->vd->name);
\r
897 for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {
\r
898 DVFS_DBG("| | | |- freq = %d, volt = %d\n",
\r
899 dvfs_clk->dvfs_table[i].frequency,
\r
900 dvfs_clk->dvfs_table[i].index);
\r
906 DVFS_DBG("-------------DVFS DEBUG END------------\n");
\r