1 /* arch/arm/mach-rk30/rk30_dvfs.c
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3 * Copyright (C) 2012 ROCKCHIP, Inc.
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5 * This software is licensed under the terms of the GNU General Public
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6 * License version 2, as published by the Free Software Foundation, and
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7 * may be copied, distributed, and modified under those terms.
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9 * This program is distributed in the hope that it will be useful,
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 * GNU General Public License for more details.
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16 #include <linux/kernel.h>
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17 #include <linux/err.h>
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18 #include <linux/spinlock.h>
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19 #include <linux/list.h>
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20 #include <linux/slab.h>
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21 #include <linux/clk.h>
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22 #include <linux/cpufreq.h>
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24 #include <mach/dvfs.h>
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25 #include <mach/clock.h>
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26 #include <linux/regulator/consumer.h>
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27 #include <linux/delay.h>
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29 #define DVFS_DBG(fmt, args...) {while(0);}
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30 #define DVFS_ERR(fmt, args...) pr_err(fmt, ##args)
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31 #define DVFS_LOG(fmt, args...) pr_debug(fmt, ##args)
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32 //#define DVFS_LOG(fmt, args...) pr_err(fmt, ##args)
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34 #define dvfs_regulator_get(dev,id) regulator_get((dev),(id))
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35 #define dvfs_regulator_put(regu) regulator_put((regu))
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36 #define dvfs_regulator_set_voltage(regu,min_uV,max_uV) regulator_set_voltage((regu),(min_uV),(max_uV))
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37 #define dvfs_regulator_get_voltage(regu) regulator_get_voltage((regu))
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39 #define dvfs_clk_get(a,b) clk_get((a),(b))
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40 #define dvfs_clk_get_rate_kz(a) (clk_get_rate((a))/1000)
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41 #define dvfs_clk_set_rate(a,b) clk_set_rate((a),(b))
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42 #define dvfs_clk_enable(a) clk_enable((a))
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43 #define dvfs_clk_disable(a) clk_disable((a))
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45 #define DVFS_MHZ (1000*1000)
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46 #define DVFS_KHZ (1000)
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48 #define DVFS_V (1000*1000)
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49 #define DVFS_MV (1000)
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52 static LIST_HEAD(rk_dvfs_tree);
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53 static DEFINE_MUTEX(mutex);
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55 extern int rk30_clk_notifier_register(struct clk *clk, struct notifier_block *nb);
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56 extern int rk30_clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
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58 // #define DVFS_DUMP_TREE
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59 #ifdef DVFS_DUMP_TREE
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60 static void dump_dbg_map(void);
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66 int is_support_dvfs(struct clk_node *dvfs_info)
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68 return (dvfs_info->vd && dvfs_info->vd->vd_dvfs_target && dvfs_info->enable_dvfs);
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71 int dvfs_set_rate(struct clk *clk, unsigned long rate)
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75 DVFS_DBG("%s(%s(%lu))\n", __func__, clk->name, rate);
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76 if (!clk->dvfs_info) {
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77 DVFS_ERR("%s :This clk do not support dvfs!\n", __func__);
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80 vd = clk->dvfs_info->vd;
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81 mutex_lock(&vd->dvfs_mutex);
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82 ret = vd->vd_dvfs_target(clk, rate);
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83 mutex_unlock(&vd->dvfs_mutex);
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85 DVFS_DBG("%s(%s(%lu)),is end\n", __func__, clk->name, rate);
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89 static int dvfs_clk_get_ref_volt_depend(struct depend_list *depend, int rate_khz,
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90 struct cpufreq_frequency_table *clk_fv)
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93 if (rate_khz == 0 || !depend || !depend->dep_table) {
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96 clk_fv->frequency = rate_khz;
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99 for (i = 0; (depend->dep_table[i].frequency != CPUFREQ_TABLE_END); i++) {
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100 if (depend->dep_table[i].frequency >= rate_khz) {
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101 clk_fv->frequency = depend->dep_table[i].frequency;
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102 clk_fv->index = depend->dep_table[i].index;
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106 clk_fv->frequency = 0;
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110 static int dvfs_clk_get_ref_volt(struct clk_node *dvfs_clk, int rate_khz,
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111 struct cpufreq_frequency_table *clk_fv)
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114 if (rate_khz == 0 || !dvfs_clk || !dvfs_clk->dvfs_table) {
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115 /* since no need */
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118 clk_fv->frequency = rate_khz;
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121 for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {
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122 if (dvfs_clk->dvfs_table[i].frequency >= rate_khz) {
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123 clk_fv->frequency = dvfs_clk->dvfs_table[i].frequency;
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124 clk_fv->index = dvfs_clk->dvfs_table[i].index;
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125 // DVFS_DBG("%s,%s rate=%ukhz(vol=%d)\n",__func__,dvfs_clk->name,
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126 // clk_fv->frequency, clk_fv->index);
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130 clk_fv->frequency = 0;
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132 // DVFS_DBG("%s get corresponding voltage error! out of bound\n", dvfs_clk->name);
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136 static int dvfs_pd_get_newvolt_byclk(struct pd_node *pd, struct clk_node *dvfs_clk)
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138 struct clk_list *child;
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141 if (!pd || !dvfs_clk)
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144 if (dvfs_clk->set_volt >= pd->cur_volt) {
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145 return dvfs_clk->set_volt;
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148 list_for_each_entry(child, &pd->clk_list, node) {
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149 // DVFS_DBG("%s ,pd(%s),dvfs(%s),volt(%u)\n",__func__,pd->name,
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150 // dvfs_clk->name,dvfs_clk->set_volt);
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151 volt_max = max(volt_max, child->dvfs_clk->set_volt);
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156 void dvfs_update_clk_pds_volt(struct clk_node *dvfs_clk)
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158 struct pd_node *pd;
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162 for (i = 0; (dvfs_clk->pds[i].pd != NULL); i++) {
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163 pd = dvfs_clk->pds[i].pd;
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164 // DVFS_DBG("%s dvfs(%s),pd(%s)\n",__func__,dvfs_clk->name,pd->name);
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165 pd->cur_volt = dvfs_pd_get_newvolt_byclk(pd, dvfs_clk);
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169 static int dvfs_vd_get_newvolt_bypd(struct vd_node *vd)
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171 struct pd_node *pd;
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172 struct depend_list *depend;
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173 int volt_max_vd = 0;
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174 list_for_each_entry(pd, &vd->pd_list, node) {
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175 // DVFS_DBG("%s pd(%s,%u)\n",__func__,pd->name,pd->cur_volt);
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176 volt_max_vd = max(volt_max_vd, pd->cur_volt);
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179 /* some clks depend on this voltage domain */
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180 if (!list_empty(&vd->req_volt_list)) {
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181 list_for_each_entry(depend, &vd->req_volt_list, node2vd) {
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182 volt_max_vd = max(volt_max_vd, depend->req_volt);
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185 return volt_max_vd;
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188 static int dvfs_vd_get_newvolt_byclk(struct clk_node *dvfs_clk)
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192 dvfs_update_clk_pds_volt(dvfs_clk);
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193 return dvfs_vd_get_newvolt_bypd(dvfs_clk->vd);
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196 void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target)
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198 struct clk_node *dvfs_clk = clk_get_dvfs_info(clk);
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199 dvfs_clk->clk_dvfs_target = clk_dvfs_target;
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202 struct cpufreq_frequency_table *dvfs_get_freq_volt_table(struct clk *clk)
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204 struct clk_node *info = clk_get_dvfs_info(clk);
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205 struct cpufreq_frequency_table *table;
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206 if (!info || !info->dvfs_table) {
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209 mutex_lock(&mutex);
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210 table = info->dvfs_table;
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211 mutex_unlock(&mutex);
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215 int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table)
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217 struct clk_node *info = clk_get_dvfs_info(clk);
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218 if (!table || !info)
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221 mutex_lock(&mutex);
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222 info->dvfs_table = table;
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223 mutex_unlock(&mutex);
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227 int dvfs_set_depend_table(struct clk *clk, char *vd_name, struct cpufreq_frequency_table *table)
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229 struct vd_node *vd;
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230 struct depend_list *depend;
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231 struct clk_node *info;
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232 info = clk_get_dvfs_info(clk);
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233 if (!table || !info || !vd_name) {
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234 DVFS_ERR("%s :DVFS SET DEPEND TABLE ERROR! table or info or name empty\n", __func__);
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238 list_for_each_entry(vd, &rk_dvfs_tree, node) {
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239 if (0 == strcmp(vd->name, vd_name)) {
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240 DVFS_LOG("FOUND A MATCH\n");
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241 mutex_lock(&mutex);
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242 list_for_each_entry(depend, &info->depend_list, node2clk) {
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243 if (vd == depend->dep_vd && info == depend->dvfs_clk) {
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244 depend->dep_table = table;
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248 mutex_unlock(&mutex);
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249 #ifdef DVFS_DUMP_TREE
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255 DVFS_ERR("%s :DVFS SET DEPEND TABLE ERROR! can not find vd:%s\n", __func__, vd_name);
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260 int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table,
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261 struct cpufreq_frequency_table *cpu_dvfs_table,
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262 struct cpufreq_frequency_table *dep_cpu2core_table)
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265 for (i = 0; dvfs_cpu_logic_table[i].frequency != CPUFREQ_TABLE_END; i++) {
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266 cpu_dvfs_table[i].frequency = dvfs_cpu_logic_table[i].frequency;
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267 cpu_dvfs_table[i].index = dvfs_cpu_logic_table[i].cpu_volt;
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269 dep_cpu2core_table[i].frequency = dvfs_cpu_logic_table[i].frequency;
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270 dep_cpu2core_table[i].index = dvfs_cpu_logic_table[i].logic_volt;
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273 cpu_dvfs_table[i].frequency = CPUFREQ_TABLE_END;
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274 dep_cpu2core_table[i].frequency = CPUFREQ_TABLE_END;
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276 dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), cpu_dvfs_table);
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277 dvfs_set_depend_table(clk_get(NULL, "cpu"), "vd_core", dep_cpu2core_table);
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281 int clk_enable_dvfs(struct clk *clk)
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283 struct regulator *regulator;
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284 struct clk_node *dvfs_clk;
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285 struct cpufreq_frequency_table clk_fv;
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287 DVFS_ERR("clk enable dvfs error\n");
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290 dvfs_clk = clk_get_dvfs_info(clk);
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291 if (!dvfs_clk || !dvfs_clk->vd) {
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292 DVFS_ERR("%s clk(%s) not support dvfs!\n", __func__, clk->name);
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295 if (dvfs_clk->enable_dvfs == 0) {
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297 if (!dvfs_clk->vd->regulator) {
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299 if (dvfs_clk->vd->regulator_name)
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300 regulator = dvfs_regulator_get(NULL, dvfs_clk->vd->regulator_name);
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302 // DVFS_DBG("dvfs_regulator_get(%s)\n",dvfs_clk->vd->regulator_name);
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303 dvfs_clk->vd->regulator = regulator;
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305 dvfs_clk->vd->regulator = NULL;
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306 dvfs_clk->enable_dvfs = 0;
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307 DVFS_ERR("%s can't get regulator in %s\n", dvfs_clk->name, __func__);
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311 dvfs_clk->vd->cur_volt = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);
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312 // DVFS_DBG("%s(%s) vd volt=%u\n",__func__,dvfs_clk->name,dvfs_clk->vd->cur_volt);
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315 dvfs_clk->set_freq = dvfs_clk_get_rate_kz(clk);
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316 // DVFS_DBG("%s ,%s get freq%u!\n",__func__,dvfs_clk->name,dvfs_clk->set_freq);
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318 if (dvfs_clk_get_ref_volt(dvfs_clk, dvfs_clk->set_freq, &clk_fv)) {
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319 if (dvfs_clk->dvfs_table[0].frequency == CPUFREQ_TABLE_END) {
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320 DVFS_ERR("%s table empty\n", __func__);
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321 dvfs_clk->enable_dvfs = 0;
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324 DVFS_ERR("WARNING: %s table all value are smaller than default, use default, just enable dvfs\n", __func__);
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325 dvfs_clk->enable_dvfs++;
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330 if (dvfs_clk_get_ref_volt(dvfs_clk, dvfs_clk->set_freq, &clk_fv)) {
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331 dvfs_clk->enable_dvfs = 0;
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334 dvfs_clk->set_volt = clk_fv.index;
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335 // DVFS_DBG("%s,%s,freq%u(ref vol %u)\n",__func__,dvfs_clk->name,
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336 // dvfs_clk->set_freq,dvfs_clk->set_volt);
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338 if (dvfs_clk->dvfs_nb) {
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339 // must unregister when clk disable
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340 rk30_clk_notifier_register(clk, dvfs_clk->dvfs_nb);
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343 dvfs_vd_get_newvolt_byclk(dvfs_clk);
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344 dvfs_clk->enable_dvfs++;
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346 DVFS_ERR("dvfs already enable clk enable = %d!\n", dvfs_clk->enable_dvfs);
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347 dvfs_clk->enable_dvfs++;
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352 int clk_disable_dvfs(struct clk *clk)
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354 struct clk_node *dvfs_clk;
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355 dvfs_clk = clk->dvfs_info;
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356 if (!dvfs_clk->enable_dvfs) {
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357 DVFS_DBG("clk is already closed!\n");
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360 dvfs_clk->enable_dvfs--;
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361 if (0 == dvfs_clk->enable_dvfs) {
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362 DVFS_ERR("clk closed!\n");
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363 rk30_clk_notifier_unregister(clk, dvfs_clk->dvfs_nb);
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364 DVFS_DBG("clk unregister nb!\n");
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370 static int rk_dvfs_clk_notifier_event(struct notifier_block *this,
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371 unsigned long event, void *ptr)
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373 struct clk_notifier_data *noti_info;
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375 struct clk_node *dvfs_clk;
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376 noti_info = (struct clk_notifier_data *)ptr;
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377 clk = noti_info->clk;
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378 dvfs_clk = clk->dvfs_info;
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381 case CLK_PRE_RATE_CHANGE:
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382 DVFS_DBG("%s CLK_PRE_RATE_CHANGE\n", __func__);
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384 case CLK_POST_RATE_CHANGE:
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385 DVFS_DBG("%s CLK_POST_RATE_CHANGE\n", __func__);
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387 case CLK_ABORT_RATE_CHANGE:
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388 DVFS_DBG("%s CLK_ABORT_RATE_CHANGE\n", __func__);
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390 case CLK_PRE_ENABLE:
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391 DVFS_DBG("%s CLK_PRE_ENABLE\n", __func__);
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393 case CLK_POST_ENABLE:
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394 DVFS_DBG("%s CLK_POST_ENABLE\n", __func__);
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396 case CLK_ABORT_ENABLE:
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397 DVFS_DBG("%s CLK_ABORT_ENABLE\n", __func__);
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399 case CLK_PRE_DISABLE:
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400 DVFS_DBG("%s CLK_PRE_DISABLE\n", __func__);
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402 case CLK_POST_DISABLE:
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403 DVFS_DBG("%s CLK_POST_DISABLE\n", __func__);
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404 dvfs_clk->set_freq = 0;
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406 case CLK_ABORT_DISABLE:
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407 DVFS_DBG("%s CLK_ABORT_DISABLE\n", __func__);
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416 static struct notifier_block rk_dvfs_clk_notifier = {
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417 .notifier_call = rk_dvfs_clk_notifier_event,
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420 static struct clk_node *dvfs_get_dvfs_clk_byname(char *name)
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422 struct vd_node *vd;
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423 struct pd_node *pd;
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424 struct clk_list *child;
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425 list_for_each_entry(vd, &rk_dvfs_tree, node) {
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426 list_for_each_entry(pd, &vd->pd_list, node) {
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427 list_for_each_entry(child, &pd->clk_list, node) {
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428 if (0 == strcmp(child->dvfs_clk->name, name)) {
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429 return child->dvfs_clk;
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436 static int rk_regist_vd(struct vd_node *vd)
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440 mutex_lock(&mutex);
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441 mutex_init(&vd->dvfs_mutex);
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442 list_add(&vd->node, &rk_dvfs_tree);
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443 INIT_LIST_HEAD(&vd->pd_list);
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444 INIT_LIST_HEAD(&vd->req_volt_list);
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446 mutex_unlock(&mutex);
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450 static int rk_regist_pd(struct pd_node_lookup *pd_lookup)
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452 struct vd_node *vd;
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453 struct pd_node *pd;
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455 mutex_lock(&mutex);
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456 pd = pd_lookup->pd;
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458 list_for_each_entry(vd, &rk_dvfs_tree, node) {
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459 if (vd == pd->vd) {
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460 list_add(&pd->node, &vd->pd_list);
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461 INIT_LIST_HEAD(&pd->clk_list);
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465 mutex_unlock(&mutex);
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469 static int rk_regist_clk(struct clk_node *dvfs_clk)
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471 struct pd_node *pd;
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472 struct clk_list *child;
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479 if (!dvfs_clk->pds)
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481 mutex_lock(&mutex);
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482 dvfs_clk->enable_dvfs = 0;
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483 dvfs_clk->vd = dvfs_clk->pds[0].pd->vd;
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484 for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {
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485 child = &(dvfs_clk->pds[i].clk_list);
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486 child->dvfs_clk = dvfs_clk;
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487 pd = dvfs_clk->pds[i].pd;
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488 list_add(&child->node, &pd->clk_list);
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490 clk = dvfs_clk_get(NULL, dvfs_clk->name);
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491 dvfs_clk->clk = clk;
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492 clk_register_dvfs(dvfs_clk, clk);
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493 INIT_LIST_HEAD(&dvfs_clk->depend_list);
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494 mutex_unlock(&mutex);
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498 static int rk_regist_depends(struct depend_lookup *dep_node)
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500 struct depend_list *depend_list;
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501 struct clk_node *dvfs_clk;
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504 DVFS_ERR("%s : DVFS BAD depend node!\n", __func__);
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508 if (!dep_node->clk_name || !dep_node->dep_vd) {
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509 DVFS_ERR("%s : DVFS BAD depend members!\n", __func__);
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513 depend_list = &dep_node->dep_list;
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514 dvfs_clk = dvfs_get_dvfs_clk_byname(dep_node->clk_name);
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516 mutex_lock(&mutex);
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518 depend_list->dvfs_clk = dvfs_clk;
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519 depend_list->dep_vd = dep_node->dep_vd;
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520 depend_list->dep_table = dep_node->dep_table;
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522 list_add(&depend_list->node2clk, &dvfs_clk->depend_list);
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523 list_add(&depend_list->node2vd, &depend_list->dep_vd->req_volt_list);
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525 mutex_unlock(&mutex);
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529 #define get_volt_up_delay(new_volt, old_volt) \
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530 ((new_volt) > (old_volt) ? (((new_volt) - (old_volt)) >> 10) : 0)
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532 static int dvfs_set_depend_pre(struct clk_node *dvfs_clk, unsigned long rate_old, unsigned long rate_new)
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534 struct depend_list *depend;
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535 struct cpufreq_frequency_table clk_fv;
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538 struct regulator *regulator;
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540 if (rate_old >= rate_new) {
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543 list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {
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544 ret = dvfs_clk_get_ref_volt_depend(depend, rate_new / 1000, &clk_fv);
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546 DVFS_ERR("%s LOGIC DVFS CAN NOT GET REF VOLT!, frequency too large!\n", __func__);
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550 if (!depend->dep_vd->regulator) {
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551 DVFS_LOG("%s regulator empty\n", __func__);
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552 regulator = dvfs_regulator_get(NULL, depend->dep_vd->regulator_name);
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554 DVFS_ERR("%s get regulator err\n", __func__);
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558 depend->dep_vd->regulator = regulator;
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560 if (!depend->dep_vd->regulator) {
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561 DVFS_ERR("%s vd's(%s) regulator empty\n", __func__, depend->dep_vd->name);
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565 if (clk_fv.index == dvfs_regulator_get_voltage(depend->dep_vd->regulator)) {
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566 depend->req_volt = clk_fv.index;
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567 DVFS_LOG("%s same voltage\n", __func__);
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571 depend->req_volt = clk_fv.index;
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572 volt = dvfs_vd_get_newvolt_bypd(depend->dep_vd);
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573 DVFS_LOG("%s setting voltage = %d\n", __func__, volt);
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574 ret = dvfs_regulator_set_voltage(depend->dep_vd->regulator, volt, volt);
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576 DVFS_ERR("%s set voltage = %d ERROR, ret = %d\n", __func__, volt, ret);
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580 DVFS_LOG("%s set voltage = %d OK, ret = %d\n", __func__, volt, ret);
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582 DVFS_ERR("%s err, ret = %d\n", __func__, ret);
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590 static int dvfs_set_depend_post(struct clk_node *dvfs_clk, unsigned long rate_old, unsigned long rate_new)
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592 struct depend_list *depend;
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593 struct cpufreq_frequency_table clk_fv;
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596 struct regulator *regulator;
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598 if (rate_old <= rate_new)
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600 list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {
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601 ret = dvfs_clk_get_ref_volt_depend(depend, rate_new / 1000, &clk_fv);
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603 DVFS_ERR("%s LOGIC DVFS CAN NOT GET REF VOLT!, frequency too large!\n", __func__);
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607 if (!depend->dep_vd->regulator) {
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608 DVFS_LOG("%s regulator empty\n", __func__);
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609 regulator = dvfs_regulator_get(NULL, depend->dep_vd->regulator_name);
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611 DVFS_ERR("%s get regulator err\n", __func__);
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615 depend->dep_vd->regulator = regulator;
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617 if (!depend->dep_vd->regulator) {
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618 DVFS_ERR("%s vd's(%s) regulator empty\n", __func__, depend->dep_vd->name);
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622 if (clk_fv.index == dvfs_regulator_get_voltage(depend->dep_vd->regulator)) {
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623 depend->req_volt = clk_fv.index;
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624 DVFS_LOG("%s same voltage\n", __func__);
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628 depend->req_volt = clk_fv.index;
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629 volt = dvfs_vd_get_newvolt_bypd(depend->dep_vd);
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630 DVFS_LOG("%s setting voltage = %d\n", __func__, volt);
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631 ret = dvfs_regulator_set_voltage(depend->dep_vd->regulator, volt, volt);
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633 DVFS_ERR("%s set voltage = %d ERROR, ret = %d\n", __func__, volt, ret);
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637 DVFS_LOG("%s set voltage = %d OK, ret = %d\n", __func__, volt, ret);
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639 DVFS_ERR("%s err, ret = %d\n", __func__, ret);
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647 static int flag_core_set_volt_err = 0;
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648 int dvfs_target_core(struct clk *clk, unsigned long rate_hz)
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650 struct clk_node *dvfs_clk;
\r
651 unsigned int volt_new = 0, volt_old = 0, volt_clk_old = 0;
\r
652 struct cpufreq_frequency_table clk_fv = {0, 0};
\r
654 int flag_set_volt_correct = 0;
\r
655 unsigned long rate_new, rate_old;
\r
658 DVFS_ERR("%s is not clk\n", __func__);
\r
661 dvfs_clk = clk_get_dvfs_info(clk);
\r
663 if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {
\r
664 DVFS_ERR("%s can't get dvfs regulater\n", clk->name);
\r
668 // clk_round_rate_nolock(clk, rate_hz);
\r
669 rate_new = rate_hz;
\r
670 rate_old = clk_get_rate(clk);
\r
672 // DVFS_DBG("dvfs(%s) round rate(%lu)(rount %lu)\n",dvfs_clk->name,rate_hz,rate_new);
\r
674 /* find the clk corresponding voltage */
\r
675 if (dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {
\r
676 DVFS_ERR("%s--%s:rate%lu,Get corresponding voltage error!\n",
\r
677 __func__, dvfs_clk->name, rate_new);
\r
680 volt_old = dvfs_clk->vd->cur_volt;
\r
682 volt_clk_old = dvfs_clk->set_volt;
\r
684 dvfs_clk->set_volt = clk_fv.index;
\r
686 volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);
\r
688 DVFS_DBG("dvfs--(%s),volt=%d(was %dmV),rate=%lu(was %lu),vd%u=(was%u)\n",
\r
689 dvfs_clk->name, clk_fv.index, dvfs_clk->set_volt, rate_new, rate_old
\r
690 , volt_new, volt_old);
\r
692 if (flag_core_set_volt_err) {
\r
693 /* It means the last time set voltage error */
\r
694 flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);
\r
695 if (flag_set_volt_correct <= 0) {
\r
696 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt error %d!!! stop scaling\n",
\r
697 __func__, dvfs_clk->name, volt_new, volt_old,
\r
698 rate_new, rate_old, flag_set_volt_correct);
\r
702 flag_core_set_volt_err = 0;
\r
703 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt! core_volt_correct = %d\n",
\r
704 __func__, dvfs_clk->name, volt_new, volt_old,
\r
705 rate_new, rate_old, flag_set_volt_correct);
\r
707 /* Reset vd's voltage */
\r
708 dvfs_clk->vd->cur_volt = flag_set_volt_correct;
\r
709 volt_old = dvfs_clk->vd->cur_volt;
\r
712 /* if up the voltage */
\r
713 if (volt_old < volt_new) {
\r
714 if (dvfs_clk->vd->regulator) {
\r
715 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
\r
717 flag_core_set_volt_err = 1;
\r
718 DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
\r
719 __func__, dvfs_clk->name, ret,
\r
720 rate_new, rate_old, volt_new, volt_old);
\r
725 DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);
\r
729 dvfs_clk->vd->cur_volt = volt_new;
\r
730 udelay(get_volt_up_delay(volt_new, volt_old));
\r
731 DVFS_DBG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n",
\r
732 __func__, dvfs_clk->name, ret, volt_new, volt_old, rate_new, rate_old);
\r
735 if (dvfs_clk->clk_dvfs_target) {
\r
736 ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);
\r
738 ret = clk_set_rate_locked(clk, rate_new);
\r
743 dvfs_clk->set_volt = volt_old;
\r
744 dvfs_vd_get_newvolt_byclk(dvfs_clk);
\r
745 DVFS_ERR("set rate err\n");
\r
748 dvfs_clk->set_freq = rate_new / 1000;
\r
750 /* if down the voltage */
\r
751 if (volt_old > volt_new) {
\r
752 if (dvfs_clk->vd->regulator) {
\r
753 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
\r
755 flag_core_set_volt_err = 1;
\r
756 DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
\r
757 __func__, dvfs_clk->name, ret, rate_new, rate_old,
\r
758 volt_new, volt_old);
\r
763 DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);
\r
767 dvfs_clk->vd->cur_volt = volt_new;
\r
768 DVFS_DBG("dvfs %s set volt ok dn\n", dvfs_clk->name);
\r
775 static int flag_arm_set_volt_err = 0;
\r
776 int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)
\r
778 struct clk_node *dvfs_clk;
\r
779 int volt_new = 0, volt_old = 0;
\r
780 struct cpufreq_frequency_table clk_fv;
\r
782 int flag_set_volt_correct = 0;
\r
783 unsigned long rate_new, rate_old;
\r
787 DVFS_ERR("%s is not clk\n", __func__);
\r
790 dvfs_clk = clk_get_dvfs_info(clk);
\r
792 if (!dvfs_clk || dvfs_clk->vd->regulator == NULL) {
\r
793 DVFS_ERR("dvfs(%s) is not register regulator\n", dvfs_clk->name);
\r
797 /* need round rate */
\r
798 rate_new = clk_round_rate_nolock(clk, rate_hz);
\r
799 DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu)\n", dvfs_clk->name, rate_hz, rate_new);
\r
801 rate_old = clk_get_rate(clk);
\r
802 /* find the clk corresponding voltage */
\r
803 if (0 != dvfs_clk_get_ref_volt(dvfs_clk, rate_new / 1000, &clk_fv)) {
\r
804 DVFS_ERR("dvfs(%s) rate %luhz is larger,not support\n", dvfs_clk->name, rate_hz);
\r
808 volt_old = dvfs_clk->vd->cur_volt;
\r
809 volt_new = clk_fv.index;
\r
810 if (flag_arm_set_volt_err) {
\r
811 /* It means the last time set voltage error */
\r
812 flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);
\r
813 if (flag_set_volt_correct <= 0) {
\r
814 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt error %d!!! stop scaling\n",
\r
815 __func__, dvfs_clk->name, volt_new, volt_old,
\r
816 rate_new, rate_old, flag_set_volt_correct);
\r
820 flag_arm_set_volt_err = 0;
\r
821 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload arm_volt! arm_volt_correct = %d\n",
\r
822 __func__, dvfs_clk->name, volt_new, volt_old,
\r
823 rate_new, rate_old, flag_set_volt_correct);
\r
825 /* Reset vd's voltage */
\r
826 dvfs_clk->vd->cur_volt = flag_set_volt_correct;
\r
827 volt_old = dvfs_clk->vd->cur_volt;
\r
830 /* if up the voltage */
\r
831 if (volt_old < volt_new) {
\r
832 if (dvfs_clk->vd->regulator) {
\r
833 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
\r
835 flag_arm_set_volt_err = 1;
\r
836 DVFS_ERR("%s %s set voltage up err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
\r
837 __func__, dvfs_clk->name, ret, rate_new, rate_old,
\r
838 volt_new, volt_old);
\r
843 DVFS_ERR("%s up volt dvfs_clk->vd->regulator == NULL\n", __func__);
\r
847 dvfs_clk->vd->cur_volt = volt_new;
\r
848 udelay(get_volt_up_delay(volt_new, volt_old));
\r
849 DVFS_DBG("%s %s set voltage OK up ret = %d, Vnew = %d(was %d), Rnew = %lu(was %lu)\n",
\r
850 __func__, dvfs_clk->name, ret, volt_new, volt_old, rate_new, rate_old);
\r
853 /* depend voltage domain set up*/
\r
854 if (0 != dvfs_set_depend_pre(dvfs_clk, rate_old, rate_new)) {
\r
855 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), set depend pre voltage err, stop scaling\n",
\r
856 __func__, dvfs_clk->name, volt_new, volt_old,
\r
857 rate_new, rate_old);
\r
861 if (dvfs_clk->clk_dvfs_target) {
\r
862 ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);
\r
864 ret = clk_set_rate_locked(clk, rate_new);
\r
868 DVFS_ERR("set rate err\n");
\r
871 dvfs_clk->set_freq = rate_new / 1000;
\r
873 DVFS_DBG("dvfs %s set rate %lu ok\n", dvfs_clk->name, clk_get_rate(clk));
\r
875 /* depend voltage domain set down*/
\r
876 if (0 != dvfs_set_depend_post(dvfs_clk, rate_old, rate_new)) {
\r
877 DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), set depend post voltage err, stop scaling\n",
\r
878 __func__, dvfs_clk->name, volt_new, volt_old,
\r
879 rate_new, rate_old);
\r
883 /* if down the voltage */
\r
884 if (volt_old > volt_new) {
\r
885 if (dvfs_clk->vd->regulator) {
\r
886 ret = dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new);
\r
888 flag_arm_set_volt_err = 1;
\r
889 DVFS_ERR("%s %s set voltage down err ret = %d, Rnew = %lu(was %lu)Hz, Vnew = %d(was %d)mV\n",
\r
890 __func__, dvfs_clk->name, ret, rate_new, rate_old,
\r
891 volt_new, volt_old);
\r
896 DVFS_ERR("%s down volt dvfs_clk->vd->regulator == NULL\n", __func__);
\r
900 dvfs_clk->vd->cur_volt = volt_new;
\r
901 DVFS_DBG("dvfs %s set volt ok dn\n", dvfs_clk->name);
\r
910 /*****************************init**************************/
\r
912 * rate must be raising sequence
\r
914 static struct cpufreq_frequency_table cpu_dvfs_table[] = {
\r
915 // {.frequency = 48 * DVFS_KHZ, .index = 920*DVFS_MV},
\r
916 // {.frequency = 126 * DVFS_KHZ, .index = 970 * DVFS_MV},
\r
917 // {.frequency = 252 * DVFS_KHZ, .index = 1040 * DVFS_MV},
\r
918 // {.frequency = 504 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
919 {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
920 // {.frequency = 1008 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
921 {.frequency = CPUFREQ_TABLE_END},
\r
924 static struct cpufreq_frequency_table ddr_dvfs_table[] = {
\r
925 // {.frequency = 100 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
926 {.frequency = 200 * DVFS_KHZ, .index = 1000 * DVFS_MV},
\r
927 {.frequency = 300 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
928 {.frequency = 400 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
929 {.frequency = 500 * DVFS_KHZ, .index = 1150 * DVFS_MV},
\r
930 {.frequency = 600 * DVFS_KHZ, .index = 1200 * DVFS_MV},
\r
931 {.frequency = CPUFREQ_TABLE_END},
\r
934 static struct cpufreq_frequency_table gpu_dvfs_table[] = {
\r
935 {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},
\r
936 {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
937 {.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
938 {.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},
\r
939 {.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},
\r
940 {.frequency = CPUFREQ_TABLE_END},
\r
943 static struct cpufreq_frequency_table peri_aclk_dvfs_table[] = {
\r
944 {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},
\r
945 {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},
\r
946 {.frequency = 300 * DVFS_KHZ, .index = 1070 * DVFS_MV},
\r
947 {.frequency = 500 * DVFS_KHZ, .index = 1100 * DVFS_MV},
\r
948 {.frequency = CPUFREQ_TABLE_END},
\r
951 static struct cpufreq_frequency_table dep_cpu2core_table[] = {
\r
952 // {.frequency = 252 * DVFS_KHZ, .index = 1025 * DVFS_MV},
\r
953 // {.frequency = 504 * DVFS_KHZ, .index = 1025 * DVFS_MV},
\r
954 {.frequency = 816 * DVFS_KHZ, .index = 1050 * DVFS_MV},//logic 1.050V
\r
955 // {.frequency = 1008 * DVFS_KHZ,.index = 1050 * DVFS_MV},
\r
956 // {.frequency = 1200 * DVFS_KHZ,.index = 1050 * DVFS_MV},
\r
957 // {.frequency = 1272 * DVFS_KHZ,.index = 1050 * DVFS_MV},//logic 1.050V
\r
958 // {.frequency = 1416 * DVFS_KHZ,.index = 1100 * DVFS_MV},//logic 1.100V
\r
959 // {.frequency = 1512 * DVFS_KHZ,.index = 1125 * DVFS_MV},//logic 1.125V
\r
960 // {.frequency = 1608 * DVFS_KHZ,.index = 1175 * DVFS_MV},//logic 1.175V
\r
961 {.frequency = CPUFREQ_TABLE_END},
\r
964 static struct vd_node vd_cpu = {
\r
966 .regulator_name = "vdd_cpu",
\r
967 .vd_dvfs_target = dvfs_target_cpu,
\r
970 static struct vd_node vd_core = {
\r
972 .regulator_name = "vdd_core",
\r
973 .vd_dvfs_target = dvfs_target_core,
\r
976 static struct vd_node vd_rtc = {
\r
978 .regulator_name = "vdd_rtc",
\r
979 .vd_dvfs_target = NULL,
\r
982 static struct vd_node *rk30_vds[] = {&vd_cpu, &vd_core, &vd_rtc};
\r
984 static struct pd_node pd_a9_0 = {
\r
988 static struct pd_node pd_a9_1 = {
\r
992 static struct pd_node pd_debug = {
\r
993 .name = "pd_debug",
\r
996 static struct pd_node pd_scu = {
\r
1000 static struct pd_node pd_video = {
\r
1001 .name = "pd_video",
\r
1004 static struct pd_node pd_vio = {
\r
1008 static struct pd_node pd_gpu = {
\r
1012 static struct pd_node pd_peri = {
\r
1013 .name = "pd_peri",
\r
1016 static struct pd_node pd_cpu = {
\r
1020 static struct pd_node pd_alive = {
\r
1021 .name = "pd_alive",
\r
1024 static struct pd_node pd_rtc = {
\r
1028 #define LOOKUP_PD(_ppd) \
\r
1032 static struct pd_node_lookup rk30_pds[] = {
\r
1033 LOOKUP_PD(&pd_a9_0),
\r
1034 LOOKUP_PD(&pd_a9_1),
\r
1035 LOOKUP_PD(&pd_debug),
\r
1036 LOOKUP_PD(&pd_scu),
\r
1037 LOOKUP_PD(&pd_video),
\r
1038 LOOKUP_PD(&pd_vio),
\r
1039 LOOKUP_PD(&pd_gpu),
\r
1040 LOOKUP_PD(&pd_peri),
\r
1041 LOOKUP_PD(&pd_cpu),
\r
1042 LOOKUP_PD(&pd_alive),
\r
1043 LOOKUP_PD(&pd_rtc),
\r
1046 #define CLK_PDS(_ppd) \
\r
1051 static struct pds_list cpu_pds[] = {
\r
1052 CLK_PDS(&pd_a9_0),
\r
1053 CLK_PDS(&pd_a9_1),
\r
1057 static struct pds_list ddr_pds[] = {
\r
1062 static struct pds_list gpu_pds[] = {
\r
1067 static struct pds_list aclk_periph_pds[] = {
\r
1068 CLK_PDS(&pd_peri),
\r
1072 #define RK_CLKS(_clk_name, _ppds, _dvfs_table, _dvfs_nb) \
\r
1074 .name = _clk_name, \
\r
1076 .dvfs_table = _dvfs_table, \
\r
1077 .dvfs_nb = _dvfs_nb, \
\r
1080 static struct clk_node rk30_clks[] = {
\r
1081 RK_CLKS("cpu", cpu_pds, cpu_dvfs_table, &rk_dvfs_clk_notifier),
\r
1082 RK_CLKS("ddr", ddr_pds, ddr_dvfs_table, &rk_dvfs_clk_notifier),
\r
1083 RK_CLKS("gpu", gpu_pds, gpu_dvfs_table, &rk_dvfs_clk_notifier),
\r
1084 RK_CLKS("aclk_periph", aclk_periph_pds, peri_aclk_dvfs_table, &rk_dvfs_clk_notifier),
\r
1087 #define RK_DEPPENDS(_clk_name, _pvd, _dep_table) \
\r
1089 .clk_name = _clk_name, \
\r
1091 .dep_table = _dep_table, \
\r
1094 static struct depend_lookup rk30_depends[] = {
\r
1095 RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),
\r
1098 int rk30_dvfs_init(void)
\r
1101 for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {
\r
1102 rk_regist_vd(rk30_vds[i]);
\r
1104 for (i = 0; i < ARRAY_SIZE(rk30_pds); i++) {
\r
1105 rk_regist_pd(&rk30_pds[i]);
\r
1107 for (i = 0; i < ARRAY_SIZE(rk30_clks); i++) {
\r
1108 rk_regist_clk(&rk30_clks[i]);
\r
1110 for (i = 0; i < ARRAY_SIZE(rk30_depends); i++) {
\r
1111 rk_regist_depends(&rk30_depends[i]);
\r
1113 #ifdef DVFS_DUMP_TREE
\r
1119 #ifdef DVFS_DUMP_TREE
\r
1121 * dump_dbg_map() : Draw all informations of dvfs while debug
\r
1123 static void dump_dbg_map(void)
\r
1126 struct vd_node *vd;
\r
1127 struct pd_node *pd, *clkparent;
\r
1128 struct clk_list *child;
\r
1129 struct clk_node *dvfs_clk;
\r
1130 struct depend_list *depend;
\r
1132 DVFS_LOG("-------------DVFS DEBUG-----------\n\n\n");
\r
1133 DVFS_LOG("RK30 DVFS TREE:\n");
\r
1134 list_for_each_entry(vd, &rk_dvfs_tree, node) {
\r
1135 DVFS_LOG("|\n|- voltage domain:%s\n", vd->name);
\r
1136 DVFS_LOG("|- current voltage:%d\n", vd->cur_volt);
\r
1137 list_for_each_entry(depend, &vd->req_volt_list, node2vd) {
\r
1138 DVFS_LOG("|- request voltage:%d, clk:%s\n", depend->req_volt, depend->dvfs_clk->name);
\r
1141 list_for_each_entry(pd, &vd->pd_list, node) {
\r
1142 DVFS_LOG("| |\n| |- power domain:%s, status = %s, current volt = %d\n",
\r
1143 pd->name, (pd->pd_status == PD_ON) ? "ON" : "OFF", pd->cur_volt);
\r
1145 list_for_each_entry(child, &pd->clk_list, node) {
\r
1146 dvfs_clk = child->dvfs_clk;
\r
1147 DVFS_LOG("| | |\n| | |- clock: %s current: rate %d, volt = %d, enable_dvfs = %s\n",
\r
1148 dvfs_clk->name, dvfs_clk->set_freq, dvfs_clk->set_volt,
\r
1149 dvfs_clk->enable_dvfs == 0 ? "DISABLE" : "ENABLE");
\r
1150 for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {
\r
1151 clkparent = dvfs_clk->pds[i].pd;
\r
1152 DVFS_LOG("| | | |- clock parents: %s, vd_parent = %s\n",
\r
1153 clkparent->name, clkparent->vd->name);
\r
1156 for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {
\r
1157 DVFS_LOG("| | | |- freq = %d, volt = %d\n",
\r
1158 dvfs_clk->dvfs_table[i].frequency,
\r
1159 dvfs_clk->dvfs_table[i].index);
\r
1163 list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {
\r
1164 DVFS_LOG("| | | | |- DEPEND VD: %s\n", depend->dep_vd->name);
\r
1165 for (i = 0; (depend->dep_table[i].frequency != CPUFREQ_TABLE_END); i++) {
\r
1166 DVFS_LOG("| | | | |- freq = %d, req_volt = %d\n",
\r
1167 depend->dep_table[i].frequency,
\r
1168 depend->dep_table[i].index);
\r
1175 DVFS_LOG("-------------DVFS DEBUG END------------\n");
\r