4 #include <linux/device.h>
5 #include <linux/platform_device.h>
7 #include <linux/types.h>
8 #include <linux/timer.h>
9 #include <linux/notifier.h>
10 #include <asm/setup.h>
11 #include <plat/board.h>
12 #include <mach/sram.h>
13 #include <linux/i2c-gpio.h>
16 void __init rk30_map_common_io(void);
17 void __init rk30_init_irq(void);
18 void __init rk30_map_io(void);
20 void __init rk30_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
21 void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags);
23 #ifdef CONFIG_RK30_PWM_REGULATOR
24 void rk30_pwm_suspend_voltage_set(void);
25 void rk30_pwm_resume_voltage_set(void);
26 void __sramfunc rk30_pwm_logic_suspend_voltage(void);
27 void __sramfunc rk30_pwm_logic_resume_voltage(void);
30 extern struct sys_timer rk30_timer;
33 periph_pll_1485mhz = 148500000,
34 periph_pll_297mhz = 297000000,
35 periph_pll_300mhz = 300000000,
36 periph_pll_594mhz = 594000000,
37 periph_pll_1188mhz = 1188000000, /* for box*/
40 codec_pll_360mhz = 360000000, /* for HDMI */
41 codec_pll_408mhz = 408000000,
42 codec_pll_456mhz = 456000000,
43 codec_pll_504mhz = 504000000,
44 codec_pll_552mhz = 552000000, /* for HDMI */
45 codec_pll_600mhz = 600000000,
46 codec_pll_742_5khz = 742500000,
47 codec_pll_768mhz = 768000000,
48 codec_pll_798mhz = 798000000,
49 codec_pll_1188mhz = 1188000000,
50 codec_pll_1200mhz = 1200000000,
54 #define CLK_FLG_EXT_27MHZ (1<<0)
56 #define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
57 #define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
58 #define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
59 #define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
61 #define CLK_FLG_UART_1_3M (1<<5)
62 #define CLK_CPU_HPCLK_11 (1<<6)
65 #ifdef CONFIG_RK29_VMAC
67 #define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
68 #define periph_pll_default periph_pll_300mhz
69 #define codec_pll_default codec_pll_1188mhz
74 #define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
76 #if (RK30_CLOCKS_DEFAULT_FLAGS&CLK_FLG_UART_1_3M)
77 #define codec_pll_default codec_pll_768mhz
80 #ifdef CONFIG_ARCH_RK3066B
81 #define codec_pll_default codec_pll_798mhz
83 #define codec_pll_default codec_pll_1200mhz
88 #define periph_pll_default periph_pll_297mhz