2 * arch/arm/mach-rk29/iomux.c
4 *Copyright (C) 2010 ROCKCHIP, Inc.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <asm/system.h>
20 #include <linux/spinlock.h>
23 #include <mach/iomux.h>
27 static struct mux_config rk30_muxs[] = {
29 * description mux mode mux mux
30 * reg offset inter mode
33 MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 2, 0, DEFAULT)
34 MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 2, 0, DEFAULT)
35 MUX_CFG(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A, 10, 2, 0, DEFAULT)
36 MUX_CFG(GPIO0A4_PWM1_NAME, GPIO0A, 8, 2, 0, DEFAULT)
37 MUX_CFG(GPIO0A3_PWM0_NAME, GPIO0A, 6, 2, 0, DEFAULT)
38 MUX_CFG(GPIO0A2_HDMII2CSDA_NAME, GPIO0A, 4, 2, 0, DEFAULT)
39 MUX_CFG(GPIO0A1_HDMII2CSCL_NAME, GPIO0A, 2, 2, 0, DEFAULT)
40 MUX_CFG(GPIO0A0_HDMIHOTPLUGIN_NAME, GPIO0A, 0, 2, 0, DEFAULT)
43 MUX_CFG(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B, 14, 2, 0, DEFAULT)
44 MUX_CFG(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B, 12, 2, 0, DEFAULT)
45 MUX_CFG(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B, 10, 2, 0, DEFAULT)
46 MUX_CFG(GPIO0B4_I2S8CHSDO0_NAME, GPIO0B, 8, 2, 0, DEFAULT)
47 MUX_CFG(GPIO0B3_I2S8CHLRCKTX_NAME, GPIO0B, 6, 2, 0, DEFAULT)
48 MUX_CFG(GPIO0B2_I2S8CHLRCKRX_NAME, GPIO0B, 4, 2, 0, DEFAULT)
49 MUX_CFG(GPIO0B1_I2S8CHSCLK_NAME, GPIO0B, 2, 2, 0, DEFAULT)
50 MUX_CFG(GPIO0B0_I2S8CHCLK_NAME, GPIO0B, 0, 2, 0, DEFAULT)
53 MUX_CFG(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C, 14, 2, 0, DEFAULT)
54 MUX_CFG(GPIO0C6_TRACECLK_SMCADDR2_NAME, GPIO0C, 12, 2, 0, DEFAULT)
55 MUX_CFG(GPIO0C5_I2S12CHSDO_NAME, GPIO0C, 10, 2, 0, DEFAULT)
56 MUX_CFG(GPIO0C4_I2S12CHSDI_NAME, GPIO0C, 8, 2, 0, DEFAULT)
57 MUX_CFG(GPIO0C3_I2S12CHLRCKTX_NAME, GPIO0C, 6, 2, 0, DEFAULT)
58 MUX_CFG(GPIO0C2_I2S8CHLRCKRX_NAME, GPIO0C, 4, 2, 0, DEFAULT)
59 MUX_CFG(GPIO0C1_I2S12CHSCLK_NAME, GPIO0C, 2, 2, 0, DEFAULT)
60 MUX_CFG(GPIO0C0_I2S12CHCLK_NAME, GPIO0C, 0, 2, 0, DEFAULT)
63 MUX_CFG(GPIO0D7_PWM3_NAME, GPIO0D, 14, 2, 0, DEFAULT)
64 MUX_CFG(GPIO0D6_PWM2_NAME, GPIO0D, 12, 2, 0, DEFAULT)
65 MUX_CFG(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D, 10, 2, 0, DEFAULT)
66 MUX_CFG(GPIO0D4_I2S12CHSDI_SMCADDR0_NAME, GPIO0D, 8, 2, 0, DEFAULT)
67 MUX_CFG(GPIO0D3_I2S12CHLRCKTX_SMCADVN_NAME, GPIO0D, 6, 2, 0, DEFAULT)
68 MUX_CFG(GPIO0D2_I2S12CHLRCKRX_SMCOEN_NAME, GPIO0D, 4, 2, 0, DEFAULT)
69 MUX_CFG(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME, GPIO0D, 2, 2, 0, DEFAULT)
70 MUX_CFG(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D, 0, 2, 0, DEFAULT)
73 MUX_CFG(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A, 14, 2, 0, DEFAULT)
74 MUX_CFG(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A, 12, 2, 0, DEFAULT)
75 MUX_CFG(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A, 10, 2, 0, DEFAULT)
76 MUX_CFG(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A, 8, 2, 0, DEFAULT)
77 MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 2, 0, DEFAULT)
78 MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 2, 0, DEFAULT)
79 MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 2, 0, DEFAULT)
80 MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 2, 0, DEFAULT)
83 MUX_CFG(GPIO1B7_CIFDATA11_NAME, GPIO1B, 14, 2, 0, DEFAULT)
84 MUX_CFG(GPIO1B6_CIFDATA10_NAME, GPIO1B, 12, 2, 0, DEFAULT)
85 MUX_CFG(GPIO1B5_CIF0DATA1_NAME, GPIO1B, 10, 2, 0, DEFAULT)
86 MUX_CFG(GPIO1B4_CIF0DATA0_NAME, GPIO1B, 8, 2, 0, DEFAULT)
87 MUX_CFG(GPIO1B3_CIF0CLKOUT_NAME, GPIO1B, 6, 2, 0, DEFAULT)
88 MUX_CFG(GPIO1B2_SPDIFTX_NAME, GPIO1B, 4, 2, 0, DEFAULT)
89 MUX_CFG(GPIO1B1_UART2SOUT_NAME, GPIO1B, 2, 2, 0, DEFAULT)
90 MUX_CFG(GPIO1B0_UART2SIN_NAME, GPIO1B, 0, 2, 0, DEFAULT)
93 MUX_CFG(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C, 14, 2, 0, DEFAULT)
94 MUX_CFG(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C, 12, 2, 0, DEFAULT)
95 MUX_CFG(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C, 10, 2, 0, DEFAULT)
96 MUX_CFG(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C, 8, 2, 0, DEFAULT)
97 MUX_CFG(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C, 6, 2, 0, DEFAULT)
98 MUX_CFG(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C, 4, 2, 0, DEFAULT)
99 MUX_CFG(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C, 2, 2, 0, DEFAULT)
100 MUX_CFG(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C, 0, 2, 0, DEFAULT)
103 MUX_CFG(GPIO1D7_CIF1CLKOUT_NAME, GPIO1D, 14, 2, 0, DEFAULT)
104 MUX_CFG(GPIO1D6_CIF1DATA11_NAME, GPIO1D, 12, 2, 0, DEFAULT)
105 MUX_CFG(GPIO1D5_CIF1DATA10_NAME, GPIO1D, 10, 2, 0, DEFAULT)
106 MUX_CFG(GPIO1D4_CIF1DATA1_NAME, GPIO1D, 8, 2, 0, DEFAULT)
107 MUX_CFG(GPIO1D3_CIF1DATA0_NAME, GPIO1D, 6, 2, 0, DEFAULT)
108 MUX_CFG(GPIO1D2_CIF1CLKIN_NAME, GPIO1D, 4, 2, 0, DEFAULT)
109 MUX_CFG(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D, 2, 2, 0, DEFAULT)
110 MUX_CFG(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D, 0, 2, 0, DEFAULT)
113 MUX_CFG(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME, GPIO2A, 14, 2, 0, DEFAULT)
114 MUX_CFG(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME, GPIO2A, 12, 2, 0, DEFAULT)
115 MUX_CFG(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME, GPIO2A, 10, 2, 0, DEFAULT)
116 MUX_CFG(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME, GPIO2A, 8, 2, 0, DEFAULT)
117 MUX_CFG(GPIO2A3_LCDCDATA3_SMCADDR7_NAME, GPIO2A, 6, 2, 0, DEFAULT)
118 MUX_CFG(GPIO2A2_LCDCDATA2_SMCADDR6_NAME, GPIO2A, 4, 2, 0, DEFAULT)
119 MUX_CFG(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME, GPIO2A, 2, 2, 0, DEFAULT)
120 MUX_CFG(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME, GPIO2A, 0, 2, 0, DEFAULT)
123 MUX_CFG(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B, 14, 2, 0, DEFAULT)
124 MUX_CFG(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B, 12, 2, 0, DEFAULT)
125 MUX_CFG(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME, GPIO2B, 10, 2, 0, DEFAULT)
126 MUX_CFG(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME, GPIO2B, 8, 2, 0, DEFAULT)
127 MUX_CFG(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME, GPIO2B, 6, 2, 0, DEFAULT)
128 MUX_CFG(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME, GPIO2B, 4, 2, 0, DEFAULT)
129 MUX_CFG(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME, GPIO2B, 2, 2, 0, DEFAULT)
130 MUX_CFG(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME, GPIO2B, 0, 2, 0, DEFAULT)
133 MUX_CFG(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME, GPIO2C, 14, 2, 0, DEFAULT)
134 MUX_CFG(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME, GPIO2C, 12, 2, 0, DEFAULT)
135 MUX_CFG(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME, GPIO2C, 10, 2, 0, DEFAULT)
136 MUX_CFG(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME, GPIO2C, 8, 2, 0, DEFAULT)
137 MUX_CFG(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME, GPIO2C, 6, 2, 0, DEFAULT)
138 MUX_CFG(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C, 4, 2, 0, DEFAULT)
139 MUX_CFG(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C, 2, 2, 0, DEFAULT)
140 MUX_CFG(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C, 0, 2, 0, DEFAULT)
143 MUX_CFG(GPIO2D7_I2C1SCL_NAME, GPIO2D, 14, 2, 0, DEFAULT)
144 MUX_CFG(GPIO2D6_I2C1SDA_NAME, GPIO2D, 12, 2, 0, DEFAULT)
145 MUX_CFG(GPIO2D5_I2C0SCL_NAME, GPIO2D, 10, 2, 0, DEFAULT)
146 MUX_CFG(GPIO2D4_I2C0SDA_NAME, GPIO2D, 8, 2, 0, DEFAULT)
147 MUX_CFG(GPIO2D3_LCDC1VSYNC_NAME, GPIO2D, 6, 2, 0, DEFAULT)
148 MUX_CFG(GPIO2D2_LCDC1HSYNC_NAME, GPIO2D, 4, 2, 0, DEFAULT)
149 MUX_CFG(GPIO2D1_LCDC1DEN_SMCCSN1_NAME, GPIO2D, 2, 2, 0, DEFAULT)
150 MUX_CFG(GPIO2D0_LCDC1DCLK_NAME, GPIO2D, 0, 2, 0, DEFAULT)
153 MUX_CFG(GPIO3A7_SDMMC0WRITEPRT_NAME, GPIO3A, 14, 2, 0, DEFAULT)
154 MUX_CFG(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A, 12, 2, 0, DEFAULT)
155 MUX_CFG(GPIO4A5_I2C4SCL_NAME, GPIO3A, 10, 2, 0, DEFAULT)
156 MUX_CFG(GPIO3A4_I2C4SDA_NAME, GPIO3A, 8, 2, 0, DEFAULT)
157 MUX_CFG(GPIO3A3_I2C3SCL_NAME, GPIO3A, 6, 2, 0, DEFAULT)
158 MUX_CFG(GPIO3A2_I2C3SDA_NAME, GPIO3A, 4, 2, 0, DEFAULT)
159 MUX_CFG(GPIO3A1_I2C2SCL_NAME, GPIO3A, 2, 2, 0, DEFAULT)
160 MUX_CFG(GPIO3A0_I2C2SDA_NAME, GPIO3A, 0, 2, 0, DEFAULT)
163 MUX_CFG(GPIO3B7_SDMMC0WRITEPRT_NAME, GPIO3B, 14, 2, 0, DEFAULT)
164 MUX_CFG(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B, 12, 2, 0, DEFAULT)
165 MUX_CFG(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B, 10, 2, 0, DEFAULT)
166 MUX_CFG(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B, 8, 2, 0, DEFAULT)
167 MUX_CFG(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B, 6, 2, 0, DEFAULT)
168 MUX_CFG(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B, 4, 2, 0, DEFAULT)
169 MUX_CFG(GPIO3B1_SDMMC0CMD_NAME, GPIO3B, 2, 2, 0, DEFAULT)
170 MUX_CFG(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B, 0, 2, 0, DEFAULT)
173 MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C, 14, 2, 0, DEFAULT)
174 MUX_CFG(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C, 12, 2, 0, DEFAULT)
175 MUX_CFG(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C, 10, 2, 0, DEFAULT)
176 MUX_CFG(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C, 8, 2, 0, DEFAULT)
177 MUX_CFG(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C, 6, 2, 0, DEFAULT)
178 MUX_CFG(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C, 4, 2, 0, DEFAULT)
179 MUX_CFG(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C, 2, 2, 0, DEFAULT)
180 MUX_CFG(GPIO3C0_SMMC1CMD_NAME, GPIO3C, 0, 2, 0, DEFAULT)
183 MUX_CFG(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME, GPIO3D, 14, 2, 0, DEFAULT)
184 MUX_CFG(GPIO3D6_UART3RTSN_NAME, GPIO3D, 12, 2, 0, DEFAULT)
185 MUX_CFG(GPIO3D5_UART3CTSN_NAME, GPIO3D, 10, 2, 0, DEFAULT)
186 MUX_CFG(GPIO3D4_UART3SOUT_NAME, GPIO3D, 8, 2, 0, DEFAULT)
187 MUX_CFG(GPIO3D3_UART3SIN_NAME, GPIO3D, 6, 2, 0, DEFAULT)
188 MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 2, 0, DEFAULT)
189 MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D, 2, 2, 0, DEFAULT)
190 MUX_CFG(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D, 0, 2, 0, DEFAULT)
193 MUX_CFG(GPIO4A7_FLASHDATA15_NAME, GPIO4A, 14, 2, 0, DEFAULT)
194 MUX_CFG(GPIO4A6_FLASHDATA14_NAME, GPIO4A, 12, 2, 0, DEFAULT)
195 MUX_CFG(GPIO4A5_FLASHDATA13_NAME, GPIO4A, 10, 2, 0, DEFAULT)
196 MUX_CFG(GPIO4A4_FLASHDATA12_NAME, GPIO4A, 8, 2, 0, DEFAULT)
197 MUX_CFG(GPIO4A3_FLASHDATA11_NAME, GPIO4A, 6, 2, 0, DEFAULT)
198 MUX_CFG(GPIO4A2_FLASHDATA10_NAME, GPIO4A, 4, 2, 0, DEFAULT)
199 MUX_CFG(GPIO4A1_FLASHDATA9_NAME, GPIO4A, 2, 2, 0, DEFAULT)
200 MUX_CFG(GPIO4A0_FLASHDATA8_NAME, GPIO4A, 0, 2, 0, DEFAULT)
203 MUX_CFG(GPIO4B7_SPI0CSN1_NAME, GPIO4B, 14, 2, 0, DEFAULT)
204 MUX_CFG(GPIO4B6_FLASHCSN7_NAME, GPIO4B, 12, 2, 0, DEFAULT)
205 MUX_CFG(GPIO4B5_FLASHCSN6_NAME, GPIO4B, 10, 2, 0, DEFAULT)
206 MUX_CFG(GPIO4B4_FLASHCSN5_NAME, GPIO4B, 8, 2, 0, DEFAULT)
207 MUX_CFG(GPIO4B3_FLASHCSN4_NAME, GPIO4B, 6, 2, 0, DEFAULT)
208 MUX_CFG(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO4B, 4, 2, 0, DEFAULT)
209 MUX_CFG(GPIO4B1_FLASHCSN2_EMMCCMD_NAME, GPIO4B, 2, 2, 0, DEFAULT)
210 MUX_CFG(GPIO4B0_FLASHCSN1_NAME, GPIO4B, 0, 2, 0, DEFAULT)
213 MUX_CFG(GPIO4C7_SMCDATA7_TRACEDATA7_NAME, GPIO4C, 14, 2, 0, DEFAULT)
214 MUX_CFG(GPIO4C6_SMCDATA6_TRACEDATA6_NAME, GPIO4C, 12, 2, 0, DEFAULT)
215 MUX_CFG(GPIO4C5_SMCDATA5_TRACEDATA5_NAME, GPIO4C, 10, 2, 0, DEFAULT)
216 MUX_CFG(GPIO4C4_SMCDATA4_TRACEDATA4_NAME, GPIO4C, 8, 2, 0, DEFAULT)
217 MUX_CFG(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C, 6, 2, 0, DEFAULT)
218 MUX_CFG(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C, 4, 2, 0, DEFAULT)
219 MUX_CFG(GPIO4C1_SMCDATA1_TRACEDATA1_NAME, GPIO4C, 2, 2, 0, DEFAULT)
220 MUX_CFG(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C, 0, 2, 0, DEFAULT)
223 MUX_CFG(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, GPIO4D, 14, 2, 0, DEFAULT)
224 MUX_CFG(GPIO4D6_SMCDATA14_TRACEDATA14_NAME, GPIO4D, 12, 2, 0, DEFAULT)
225 MUX_CFG(GPIO4D5_SMCDATA13_TRACEDATA13_NAME, GPIO4D, 10, 2, 0, DEFAULT)
226 MUX_CFG(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D, 8, 2, 0, DEFAULT)
227 MUX_CFG(GPIO4D3_SMCDATA11_TRACEDATA11_NAME, GPIO4D, 6, 2, 0, DEFAULT)
228 MUX_CFG(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D, 4, 2, 0, DEFAULT)
229 MUX_CFG(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D, 2, 2, 0, DEFAULT)
230 MUX_CFG(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D, 0, 2, 0, DEFAULT)
233 MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 2, 0, DEFAULT)
238 void rk30_mux_set(struct mux_config *cfg)
243 mask = ((1<<(cfg->interleave))-1)<<cfg->offset;
244 regValue = readl(cfg->mux_reg);
246 regValue |=(cfg->mode<<cfg->offset);
248 printk("%s::reg=0x%p,Value=0x%x,mask=0x%x\n",__FUNCTION__,cfg->mux_reg,regValue,mask);
250 writel(regValue,cfg->mux_reg);
255 int rk30_iomux_init(void)
258 printk("%s\n",__func__);
259 for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
261 if(rk30_muxs[i].flags != DEFAULT)
262 rk30_mux_set(&rk30_muxs[i]);
265 #ifdef CONFIG_UART0_RK30
266 rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME, GPIO1A_UART0_SOUT);
267 rk30_mux_api_set(GPIO1A0_UART0SIN_NAME, GPIO1A_UART0_SIN);
268 #ifdef CONFIG_UART0_CTS_RTS_RK30
269 rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME, GPIO1A_UART0_RTS_N);
270 rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME, GPIO1A_UART0_CTS_N);
273 #ifdef CONFIG_UART1_RK30
275 rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A_UART1_SOUT);
276 rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A_UART1_SIN);
277 #ifdef CONFIG_UART1_CTS_RTS_RK30
278 rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A_UART1_RTS_N);
279 rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A_UART1_CTS_N);
283 #ifdef CONFIG_UART2_RK30
284 rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME, GPIO1B_UART2_SOUT);
285 rk30_mux_api_set(GPIO1B0_UART2SIN_NAME, GPIO1B_UART2_SIN);
287 #ifdef CONFIG_UART3_RK30
288 rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME, GPIO3D_UART3_SOUT);
289 rk30_mux_api_set(GPIO3D3_UART3SIN_NAME, GPIO3D_UART3_SIN);
290 #ifdef CONFIG_UART3_CTS_RTS_RK30
291 rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME, GPIO3D_UART3_RTS_N);
292 rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME, GPIO3D_UART3_CTS_N);
295 #ifdef CONFIG_SPIM0_RK30
297 rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A_SPI0_CLK);
298 rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A_SPI0_CSN0);
299 rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A_SPI0_TXD);
300 rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A_SPI0_RXD);
302 #ifdef CONFIG_SPIM1_RK30
303 //rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME, GPIO2C_SPI1_CSN1);
304 rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME, GPIO2C_SPI1_RXD);
305 rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME, GPIO2C_SPI1_TXD);
306 rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME, GPIO2C_SPI1_CSN0);
307 rk30_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME, GPIO2C_SPI1_CLK);
309 #ifdef CONFIG_RK30_VMAC
310 rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C_RMII_CLKOUT);
311 rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C_RMII_TX_EN);
312 rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C_RMII_TXD1);
313 rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C_RMII_TXD0);
314 rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C_RMII_RX_ERR);
315 rk30_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C_RMII_CRS_DVALID);
316 rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C_RMII_RXD1);
317 rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C_RMII_RXD0);
319 rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D_MII_MDCLK);
320 rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D_MII_MD);
325 EXPORT_SYMBOL(rk30_iomux_init);
327 *config iomux : input iomux name and iomux flags
329 void rk30_mux_api_set(char *name, unsigned int mode)
335 for(i=0;i<ARRAY_SIZE(rk30_muxs);i++)
337 if (!strcmp(rk30_muxs[i].name, name))
339 rk30_muxs[i].premode = rk30_muxs[i].mode;
340 rk30_muxs[i].mode = mode;
341 rk30_mux_set(&rk30_muxs[i]);
346 EXPORT_SYMBOL(rk30_mux_api_set);