arch/arm/mach-rk3026/common.c

   1 #include <linux/kernel.h>
   2 #include <linux/interrupt.h>
   3 #include <linux/irq.h>
   4 #include <linux/io.h>
   5
   6 #include <asm/pgtable-hwdef.h>
   7 #include <asm/hardware/gic.h>
   8 #include <asm/mach/arch.h>
   9 #include <asm/hardware/cache-l2x0.h>
  10
  11 #include <plat/sram.h>
  12 #include <mach/board.h>
  13 #include <mach/gpio.h>
  14 #include <mach/iomux.h>
  15 #include <mach/fiq.h>
  16 #include <mach/loader.h>
  17 #include <mach/ddr.h>
  18 #include <mach/cpu.h>
  19 #include <mach/cpu_axi.h>
  20 #include <mach/debug_uart.h>
  21
  22 static void __init cpu_axi_init(void)
  23 {
  24         CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU0);
  25         CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1R);
  26         CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1W);
  27         CPU_AXI_SET_QOS_PRIORITY(0, 0, PERI);
  28         CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC0);
  29         CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC1);
  30         CPU_AXI_SET_QOS_PRIORITY(2, 1, GPU);
  31
  32         writel_relaxed(0x3f, RK30_CPU_AXI_BUS_BASE + 0x0014);   // memory scheduler read latency
  33         dsb();
  34 }
  35
  36 #define L2_LY_SP_OFF (0)
  37 #define L2_LY_SP_MSK (0x7)
  38
  39 #define L2_LY_RD_OFF (4)
  40 #define L2_LY_RD_MSK (0x7)
  41
  42 #define L2_LY_WR_OFF (8)
  43 #define L2_LY_WR_MSK (0x7)
  44 #define L2_LY_SET(ly,off) (((ly)-1)<<(off))
  45
  46 #define L2_LATENCY(setup_cycles, read_cycles, write_cycles) \
  47         L2_LY_SET(setup_cycles, L2_LY_SP_OFF) | \
  48         L2_LY_SET(read_cycles, L2_LY_RD_OFF) | \
  49         L2_LY_SET(write_cycles, L2_LY_WR_OFF)
  50
  51 static void __init l2_cache_init(void)
  52 {
  53 #ifdef CONFIG_CACHE_L2X0
  54         u32 aux_ctrl, aux_ctrl_mask;
  55
  56         writel_relaxed(L2_LATENCY(1, 1, 1), RK30_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
  57         writel_relaxed(L2_LATENCY(2, 3, 1), RK30_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
  58
  59         /* L2X0 Prefetch Control */
  60         writel_relaxed(0x70000003, RK30_L2C_BASE + L2X0_PREFETCH_CTRL);
  61
  62         /* L2X0 Power Control */
  63         writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK30_L2C_BASE + L2X0_POWER_CTRL);
  64
  65         /* force 16-way, 16KB way-size on RK3026 */
  66         aux_ctrl = (
  67                         (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
  68                         (0x1 << 25) |           // Round-robin cache replacement policy
  69                         (0x1 << 0) |            // Full Line of Zero Enable
  70                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
  71                         (0x1 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 16KB way-size
  72                         (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  73                         (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  74                         (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
  75
  76         aux_ctrl_mask = ~(
  77                         (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
  78                         (0x1 << 25) |           // Cache replacement policy
  79                         (0x1 << 0) |            // Full Line of Zero Enable
  80                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
  81                         (0x7 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
  82                         (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  83                         (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  84                         (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
  85
  86         l2x0_init(RK30_L2C_BASE, aux_ctrl, aux_ctrl_mask);
  87 #endif
  88 }
  89
  90 static int boot_mode;
  91
  92 static void __init boot_mode_init(void)
  93 {
  94         u32 boot_flag = readl_relaxed(RK30_GRF_BASE + GRF_OS_REG4);
  95         boot_mode = readl_relaxed(RK30_GRF_BASE + GRF_OS_REG5);
  96
  97         if (boot_flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
  98                 boot_mode = BOOT_MODE_RECOVERY;
  99         }
 100         if (boot_mode || ((boot_flag & 0xff) && ((boot_flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
 101                 printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(boot_mode), boot_mode, boot_flag_name(boot_flag), boot_flag);
 102 #ifdef CONFIG_RK29_WATCHDOG
 103         writel_relaxed(BOOT_MODE_WATCHDOG, RK30_GRF_BASE + GRF_OS_REG5);
 104 #endif
 105 }
 106
 107 int board_boot_mode(void)
 108 {
 109         return boot_mode;
 110 }
 111 EXPORT_SYMBOL(board_boot_mode);
 112
 113 void __init rk2928_init_irq(void)
 114 {
 115         gic_init(0, IRQ_LOCALTIMER, GIC_DIST_BASE, GIC_CPU_BASE);
 116 #ifdef CONFIG_FIQ
 117         rk_fiq_init();
 118 #endif
 119         rk30_gpio_init();
 120         soc_gpio_init();
 121 }
 122
 123 static unsigned int __initdata ddr_freq = DDR_FREQ;
 124 static int __init ddr_freq_setup(char *str)
 125 {
 126         get_option(&str, &ddr_freq);
 127         return 0;
 128 }
 129 early_param("ddr_freq", ddr_freq_setup);
 130
 131 static void usb_uart_init(void)
 132 {
 133 #ifdef DEBUG_UART_BASE
 134         writel_relaxed(0x34000000, RK2928_GRF_BASE + GRF_UOC1_CON0);
 135 #ifdef CONFIG_RK_USB_UART
 136         writel_relaxed(0x34000000, RK30_GRF_BASE + GRF_UOC1_CON0);
 137
 138         if((readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1<<10)))//detect id
 139         {
 140                 if(!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1<<7)))//detect vbus
 141                 {
 142                         writel_relaxed(0x007f0055, RK30_GRF_BASE + GRF_UOC0_CON0);
 143                         writel_relaxed(0x34003000, RK30_GRF_BASE + GRF_UOC1_CON0);
 144                 }
 145                 else
 146                 {
 147                         writel_relaxed(0x34000000, RK30_GRF_BASE + GRF_UOC1_CON0);
 148                 }
 149         }
 150
 151 #endif // end of CONFIG_RK_USB_UART
 152     writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
 153     writel_relaxed(0x07, DEBUG_UART_BASE + 0x88);
 154     writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
 155     writel_relaxed(0x83, DEBUG_UART_BASE + 0x0c);
 156     writel_relaxed(0x0d, DEBUG_UART_BASE + 0x00);
 157     writel_relaxed(0x00, DEBUG_UART_BASE + 0x04);
 158     writel_relaxed(0x03, DEBUG_UART_BASE + 0x0c);
 159 #endif //end of DEBUG_UART_BASE
 160 }
 161
 162 void __init rk2928_map_io(void)
 163 {
 164         rk2928_map_common_io();
 165         usb_uart_init();
 166         rk29_setup_early_printk();
 167         cpu_axi_init();
 168         rk29_sram_init();
 169         board_clock_init();
 170         l2_cache_init();
 171         ddr_init(DDR_TYPE, ddr_freq);
 172         iomux_init();
 173         boot_mode_init();
 174 }
 175
 176 static __init u32 get_ddr_size(void)
 177 {
 178         u32 size;
 179         u32 v[1], a[1];
 180         u32 pgtbl = PAGE_OFFSET + TEXT_OFFSET - 0x4000;
 181         u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;
 182
 183         a[0] = pgtbl + (((u32)RK30_GRF_BASE >> 20) << 2);
 184         v[0] = readl_relaxed(a[0]);
 185         writel_relaxed(flag | ((RK30_GRF_PHYS >> 20) << 20), a[0]);
 186
 187         size = ddr_get_cap();
 188
 189         writel_relaxed(v[0], a[0]);
 190
 191         return size;
 192 }
 193
 194 void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags,
 195                         char **cmdline, struct meminfo *mi)
 196 {
 197         mi->nr_banks = 1;
 198         mi->bank[0].start = PLAT_PHYS_OFFSET;
 199         mi->bank[0].size = get_ddr_size();
 200 }
 201