arch/arm/mach-rk3188/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <plat/efuse.h>
  25 #include <mach/cru.h>
  26 #include <mach/iomux.h>
  27 #include <mach/clock.h>
  28 #include <mach/pmu.h>
  29 #include <mach/dvfs.h>
  30 #include <mach/ddr.h>
  31 #include <mach/cpu.h>
  32
  33 #define MHZ                     (1000UL * 1000UL)
  34 #define KHZ                     (1000UL)
  35 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  36 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
  37 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  38 void rk30_clk_dump_regs(void);
  39 static int flag_uboot_display = 0;
  40 //flags bit
  41 //has extern 27mhz
  42 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  43 //max i2s rate
  44 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  45 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  46 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  47 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  48 //uart 1m\3m
  49 #define CLK_FLG_UART_1_3M                       (1<<5)
  50
  51 #define ARCH_RK31
  52
  53 struct apll_clk_set {
  54         unsigned long   rate;
  55         u32     pllcon0;
  56         u32     pllcon1;
  57         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  58         u32     rst_dly;//us
  59         u32     clksel0;
  60         u32     clksel1;
  61         unsigned long   lpj;
  62 };
  63 struct pll_clk_set {
  64         unsigned long   rate;
  65         u32     pllcon0;
  66         u32     pllcon1;
  67         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  68         unsigned long   rst_dly;//us
  69 };
  70
  71 #define SET_PLL_DATA(_pll_id,_table) \
  72 {\
  73         .id=(_pll_id),\
  74         .table=(_table),\
  75 }
  76
  77
  78 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  79 { \
  80         .rate   = (_mhz) * KHZ, \
  81         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  82         .pllcon1 = PLL_CLKF_SET(nf),\
  83         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  84         .rst_dly=((nr*500)/24+1),\
  85 }
  86
  87
  88 #define _APLL_SET_LPJ(_mhz) \
  89         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  90
  91
  92 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  93                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  94 { \
  95         .rate   = _mhz * MHZ, \
  96         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  97         .pllcon1 = PLL_CLKF_SET(nf),\
  98         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  99         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
 100         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
 101         _APLL_SET_LPJ(_mhz),\
 102         .rst_dly=((nr*500)/24+1),\
 103 }
 104
 105 #define CRU_DIV_SET(mask,shift,max) \
 106         .div_mask=(mask),\
 107 .div_shift=(shift),\
 108 .div_max=(max)
 109
 110
 111 #define CRU_SRC_SET(mask,shift ) \
 112         .src_mask=(mask),\
 113 .src_shift=(shift)
 114
 115 #define CRU_PARENTS_SET(parents_array) \
 116         .parents=(parents_array),\
 117 .parents_num=ARRAY_SIZE((parents_array))
 118
 119 #define CRU_GATE_MODE_SET(_func,_IDX) \
 120         .mode=_func,\
 121 .gate_idx=(_IDX)
 122
 123 struct clk_src_sel {
 124         struct clk      *parent;
 125         u8      value;//crt bit
 126         u8      flag;
 127         //selgate
 128 };
 129
 130 #define GATE_CLK(NAME,PARENT,ID) \
 131         static struct clk clk_##NAME = { \
 132                 .name           = #NAME, \
 133                 .parent         = &PARENT, \
 134                 .mode           = gate_mode, \
 135                 .gate_idx       = CLK_GATE_##ID, \
 136         }
 137 #ifdef RK30_CLK_OFFBOARD_TEST
 138 u32 TEST_GRF_REG[0x240];
 139 u32 TEST_CRU_REG[0x240];
 140 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 141
 142 u32 cru_writel_is_pr(u32 offset)
 143 {
 144         return (offset == 0x4000);
 145 }
 146 void cru_writel(u32 v, u32 offset)
 147 {
 148
 149         u32 mask_v = v >> 16;
 150         TEST_CRU_REG[offset/4] &= (~mask_v);
 151
 152         v &= (mask_v);
 153
 154         TEST_CRU_REG[offset/4] |= v;
 155         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 156
 157         if(cru_writel_is_pr(offset)) {
 158                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 159
 160         }
 161
 162 }
 163 void cru_writel_i2s(u32 v, u32 offset)
 164 {
 165         TEST_CRU_REG[offset/4] = v;
 166 }
 167 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 168
 169 #define regfile_readl(offset)   (0xffffffff)
 170 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 171 void rk30_clkdev_add(struct clk_lookup *cl);
 172 #else
 173 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 174 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 175 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 176 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 177
 178 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 179 #endif
 180
 181 //#define DEBUG
 182 #ifdef DEBUG
 183 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 184 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 185 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
 186 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
 187 #else
 188 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 189 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 190 #endif
 191 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 192 #define CLKDATA_WARNING(fmt, args...) printk("CLKDATA_WANING:\t"fmt, ##args)
 193
 194
 195 #define get_cru_bits(con,mask,shift)\
 196         ((cru_readl((con)) >> (shift)) & (mask))
 197
 198 #define set_cru_bits_w_msk(val,mask,shift,con)\
 199         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 200
 201
 202 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 203                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 204
 205
 206 static u32 rk30_clock_flags = 0;
 207 static struct clk codec_pll_clk;
 208 static struct clk general_pll_clk;
 209 static struct clk arm_pll_clk;
 210 static unsigned long lpj_gpll;
 211 static unsigned int __initdata armclk = 504 * MHZ;
 212
 213
 214 /************************clk recalc div rate*********************************/
 215
 216 //for free div
 217 static unsigned long clksel_recalc_div(struct clk *clk)
 218 {
 219         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 220
 221         unsigned long rate = clk->parent->rate / div;
 222         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 223         return rate;
 224 }
 225
 226 //for div 1 2 4 2^n
 227 static unsigned long clksel_recalc_shift(struct clk *clk)
 228 {
 229         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 230         unsigned long rate = clk->parent->rate >> shift;
 231         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 232         return rate;
 233 }
 234
 235
 236 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 237 {
 238         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 239         unsigned long rate = clk->parent->rate >> shift;
 240         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 241         return rate;
 242 }
 243
 244 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 245 {
 246         unsigned long rate = clk->parent->rate;
 247         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 248         return rate;
 249 }
 250 /********************************set div rate***********************************/
 251
 252 //for free div
 253 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 254 {
 255         u32 div;
 256         for (div = 0; div < clk->div_max; div++) {
 257                 u32 new_rate = clk->parent->rate / (div + 1);
 258                 if (new_rate <= rate) {
 259                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 260                         //clk->rate = new_rate;
 261                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 262                                         clk->name, rate, div + 1);
 263                         return 0;
 264                 }
 265         }
 266         return -ENOENT;
 267 }
 268
 269 //for div 1 2 4 2^n
 270 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 271 {
 272         u32 shift;
 273         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 274                 u32 new_rate = clk->parent->rate >> shift;
 275                 if (new_rate <= rate) {
 276                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 277                         clk->rate = new_rate;
 278                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 279                                         clk->name, rate, shift);
 280                         return 0;
 281                 }
 282         }
 283         return -ENOENT;
 284 }
 285
 286 //for div 2 4 2^n
 287 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 288 {
 289         u32 shift;
 290
 291         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 292                 u32 new_rate = clk->parent->rate >> shift;
 293                 if (new_rate <= rate) {
 294                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 295                         clk->rate = new_rate;
 296                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 297                                         clk->name, rate, shift);
 298                         return 0;
 299                 }
 300         }
 301         return -ENOENT;
 302 }
 303
 304 //for div 1 2 4 2*n
 305 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 306 {
 307         u32 div = 0, new_rate = 0;
 308         for (div = 1; div < clk->div_max; div++) {
 309                 if (div >= 3 && div % 2 != 0)
 310                         continue;
 311                 new_rate = clk->parent->rate / div;
 312                 if (new_rate <= rate) {
 313                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 314                         clk->rate = new_rate;
 315                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 316                                         __func__, clk->name, rate, div);
 317                         return 0;
 318                 }
 319         }
 320         return -ENOENT;
 321 }
 322 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 323 {
 324         u32 div;
 325         unsigned long new_rate;
 326         for (div = 0; div < div_max; div++) {
 327                 new_rate = rate / (div + 1);
 328                 if (new_rate <= rate_out) {
 329                         return div + 1;
 330                 }
 331         }
 332         return div_max ? div_max : 1;
 333 }
 334 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 335 {
 336         u32 div;
 337         unsigned long new_rate;
 338         for (div = 1; div < div_max; div += 2) {
 339                 new_rate = rate / (div + 1);
 340                 if (new_rate <= rate_out) {
 341                         return div + 1;
 342                 }
 343         }
 344         return div_max ? div_max : 1;
 345 }
 346 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 347         u32 div[2] = {0, 0};
 348         unsigned long new_rate[2] = {0, 0};
 349         u32 i;
 350
 351         if(clk->rate == rate)
 352                 return clk->parent;
 353         for(i = 0; i < 2; i++) {
 354                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 355                 new_rate[i] = clk->parents[i]->rate / div[i];
 356                 if(new_rate[i] == rate) {
 357                         *div_out = div[i];
 358                         return clk->parents[i];
 359                 }
 360         }
 361         if(new_rate[0] < new_rate[1])
 362                 i = 1;
 363         else
 364                 i = 0;
 365         *div_out = div[i];
 366         return clk->parents[i];
 367 }
 368 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 369         u32 div[2] = {0, 0};
 370         unsigned long new_rate[2] = {0, 0};
 371         u32 i;
 372
 373         if(clk->rate == rate)
 374                 return clk->parent;
 375         for(i = 0; i < 2; i++) {
 376                 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 377                 new_rate[i] = clk->parents[i]->rate / div[i];
 378                 if(new_rate[i] == rate) {
 379                         *div_out = div[i];
 380                         return clk->parents[i];
 381                 }
 382         }
 383         if(new_rate[0] < new_rate[1])
 384                 i = 1;
 385         else
 386                 i = 0;
 387         *div_out = div[i];
 388         return clk->parents[i];
 389 }
 390
 391 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 392 {
 393         struct clk *p_clk;
 394         u32 div, old_div;
 395         int ret = 0;
 396         if(clk->rate == rate)
 397                 return 0;
 398         p_clk = get_freediv_parents_div(clk, rate, &div);
 399
 400         if(!p_clk)
 401                 return -ENOENT;
 402
 403         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 404         if (clk->parent != p_clk) {
 405                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 406
 407                 if(div > old_div) {
 408                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 409                 }
 410                 ret = clk_set_parent_nolock(clk, p_clk);
 411                 if(ret) {
 412                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 413                         return -ENOENT;
 414                 }
 415         }
 416         //set div
 417         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 418         return 0;
 419 }
 420 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 421 {
 422         struct clk *p_clk;
 423         u32 div, old_div;
 424         int ret = 0;
 425         if(clk->rate == rate)
 426                 return 0;
 427         p_clk = get_evendiv_parents_div(clk, rate, &div);
 428
 429         if(!p_clk)
 430                 return -ENOENT;
 431
 432         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 433         if (clk->parent != p_clk) {
 434                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 435
 436                 if(div > old_div) {
 437                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 438                 }
 439                 ret = clk_set_parent_nolock(clk, p_clk);
 440                 if(ret) {
 441                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 442                         return -ENOENT;
 443                 }
 444         }
 445         //set div
 446         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 447         return 0;
 448 }
 449
 450 //rate==div rate //hdmi
 451 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 452 {
 453         struct clk *p_clk;
 454         u32 div, old_div;
 455         int ret;
 456         p_clk = get_freediv_parents_div(clk, rate, &div);
 457
 458         if(!p_clk)
 459                 return -ENOENT;
 460
 461         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 462                 return -ENOENT;
 463
 464         if (clk->parent != p_clk) {
 465                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 466                                 clk->div_shift, clk->div_mask) + 1;
 467                 if(div > old_div) {
 468                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 469                 }
 470                 ret = clk_set_parent_nolock(clk, p_clk);
 471                 if (ret) {
 472                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 473                         return ret;
 474                 }
 475         }
 476         //set div
 477         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 478         return 0;
 479 }
 480
 481 /***************************round********************************/
 482
 483 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 484 {
 485         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 486 }
 487
 488 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 489 {
 490         u32 div;
 491         struct clk *p_clk;
 492         if(clk->rate == rate)
 493                 return clk->rate;
 494         p_clk = get_freediv_parents_div(clk, rate, &div);
 495         if(!p_clk)
 496                 return 0;
 497         return p_clk->rate / div;
 498 }
 499
 500 /**************************************others seting************************************/
 501
 502 static struct clk *clksel_get_parent(struct clk *clk) {
 503         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 504 }
 505 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 506 {
 507         u32 i;
 508         if (unlikely(!clk->parents))
 509                 return -EINVAL;
 510         for (i = 0; (i < clk->parents_num); i++) {
 511                 if (clk->parents[i] != parent)
 512                         continue;
 513                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 514                 return 0;
 515         }
 516         return -EINVAL;
 517 }
 518
 519 static int gate_mode(struct clk *clk, int on)
 520 {
 521         int idx = clk->gate_idx;
 522         if (idx >= CLK_GATE_MAX)
 523                 return -EINVAL;
 524         if(on) {
 525                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 526                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 527                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 528         } else {
 529                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 530                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 531                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 532         }
 533         return 0;
 534 }
 535 /*****************************frac set******************************************/
 536
 537 static unsigned long clksel_recalc_frac(struct clk *clk)
 538 {
 539         unsigned long rate;
 540         u64 rate64;
 541         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 542         if (r == 0) // FPGA ?
 543                 return clk->parent->rate;
 544         numerator = r >> 16;
 545         denominator = r & 0xFFFF;
 546         rate64 = (u64)clk->parent->rate * numerator;
 547         do_div(rate64, denominator);
 548         rate = rate64;
 549         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 550         return rate;
 551 }
 552
 553 static u32 clk_gcd(u32 numerator, u32 denominator)
 554 {
 555         u32 a, b;
 556
 557         if (!numerator || !denominator)
 558                 return 0;
 559         if (numerator > denominator) {
 560                 a = numerator;
 561                 b = denominator;
 562         } else {
 563                 a = denominator;
 564                 b = numerator;
 565         }
 566         while (b != 0) {
 567                 int r = b;
 568                 b = a % b;
 569                 a = r;
 570         }
 571
 572         return a;
 573 }
 574
 575 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 576                 u32 *numerator, u32 *denominator)
 577 {
 578         u32 gcd_vl;
 579         gcd_vl = clk_gcd(rate, rate_out);
 580         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 581
 582         if (!gcd_vl) {
 583                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 584                 return -ENOENT;
 585         }
 586
 587         *numerator = rate_out / gcd_vl;
 588         *denominator = rate / gcd_vl;
 589
 590         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 591                         *numerator, *denominator, *denominator / *numerator);
 592
 593         if (*numerator > 0xffff || *denominator > 0xffff ||
 594                         (*denominator / (*numerator)) < 20) {
 595                 CLKDATA_ERR("can't get a available nume and deno\n");
 596                 return -ENOENT;
 597         }
 598
 599         return 0;
 600
 601 }
 602 /* *********************pll **************************/
 603
 604 #define rk30_clock_udelay(a) udelay(a);
 605
 606 /*********************pll lock status**********************************/
 607 //#define GRF_SOC_CON0       0x15c
 608 static void pll_wait_lock(int pll_idx)
 609 {
 610         u32 pll_state[4] = {1, 0, 2, 3};
 611         u32 bit = 0x20u << pll_state[pll_idx];
 612         int delay = 24000000;
 613         while (delay > 0) {
 614                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 615                         break;
 616                 delay--;
 617         }
 618         if (delay == 0) {
 619                 CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
 620                                 cru_readl(PLL_CONS(pll_idx, 0)),
 621                                 cru_readl(PLL_CONS(pll_idx, 1)),
 622                                 cru_readl(PLL_CONS(pll_idx, 2)),
 623                                 cru_readl(PLL_CONS(pll_idx, 3)));
 624
 625                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 626                 while(1);
 627         }
 628 }
 629
 630
 631
 632 /***************************pll function**********************************/
 633 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 634 {
 635         unsigned long rate;
 636
 637         if (PLLS_IN_NORM(pll_id)) {
 638                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 639                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 640
 641
 642                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 643
 644                 /*
 645                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 646                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 647                    */
 648
 649
 650                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 651                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 652                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 653
 654                 do_div(rate64, PLL_NR(pll_con0));
 655                 do_div(rate64, PLL_NO(pll_con0));
 656
 657                 rate = rate64;
 658                 /*
 659                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 660                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 661                    */
 662         } else {
 663                 rate = parent_rate;
 664                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 665         }
 666         return rate;
 667 }
 668 static unsigned long plls_clk_recalc(struct clk *clk)
 669 {
 670         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 671 }
 672 static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 673 {
 674         unsigned long rate;
 675
 676         if (PLLS_IN_NORM(pll_id)) {
 677                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 678                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 679
 680                 u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
 681
 682                 do_div(rate64, PLUS_PLL_NR(pll_con0));
 683                 do_div(rate64, PLUS_PLL_NO(pll_con0));
 684
 685                 rate = rate64;
 686         } else {
 687                 rate = parent_rate;
 688                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 689         }
 690         return rate;
 691 }
 692 static unsigned long plus_plls_clk_recalc(struct clk *clk)
 693 {
 694         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 695         return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
 696 }
 697
 698 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 699 {
 700         //enter slowmode
 701         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 702         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 703         dsb();
 704         dsb();
 705         dsb();
 706         dsb();
 707         dsb();
 708         dsb();
 709         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 710         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 711
 712         rk30_clock_udelay(1);
 713         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 714
 715         pll_wait_lock(pll_id);
 716
 717         //return form slow
 718         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 719
 720         /*
 721            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 722            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 723            */
 724
 725         return 0;
 726 }
 727
 728 static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 729 {
 730         //enter slowmode
 731         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 732
 733         //enter rest
 734         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
 735         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 736         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 737         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
 738         rk30_clock_udelay(5);
 739
 740         //return form rest
 741         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
 742
 743         //wating lock state
 744         rk30_clock_udelay(clk_set->rst_dly);
 745         pll_wait_lock(pll_id);
 746
 747         //return form slow
 748         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 749
 750         return 0;
 751 }
 752
 753 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 754 {
 755         struct _pll_data *pll_data = c->pll;
 756         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 757
 758         while(clk_set->rate) {
 759                 if (clk_set->rate == rate) {
 760                         break;
 761                 }
 762                 clk_set++;
 763         }
 764         if(clk_set->rate == rate) {
 765                 pll_clk_set_rate(clk_set, pll_data->id);
 766                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 767         } else {
 768                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 769                 return -1;
 770         }
 771         return 0;
 772 }
 773
 774 static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
 775 {
 776         struct _pll_data *pll_data = c->pll;
 777         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 778         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 779
 780         while(clk_set->rate) {
 781                 if (clk_set->rate == rate) {
 782                         break;
 783                 }
 784                 clk_set++;
 785         }
 786         if(clk_set->rate == rate) {
 787                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 788                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 789         } else {
 790                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 791                 return -1;
 792         }
 793         return 0;
 794 }
 795 #define PLL_FREF_MIN (183*KHZ)
 796 #define PLL_FREF_MAX (1500*MHZ)
 797
 798 #define PLL_FVCO_MIN (300*MHZ)
 799 #define PLL_FVCO_MAX (1500*MHZ)
 800
 801 #define PLL_FOUT_MIN (18750*KHZ)
 802 #define PLL_FOUT_MAX (1500*MHZ)
 803
 804 #define PLL_NF_MAX (65536)
 805 #define PLL_NR_MAX (64)
 806 #define PLL_NO_MAX (64)
 807
 808 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 809 {
 810         u32 nr, nf, no, nonr;
 811         u32 n;
 812         u32 YFfenzi;
 813         u32 YFfenmu;
 814         unsigned long fref, fvco, fout;
 815         u32 gcd_val = 0;
 816
 817         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 818         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 819                 return 0;
 820         gcd_val = clk_gcd(fin_hz, fout_hz);
 821         YFfenzi = fout_hz / gcd_val;
 822         YFfenmu = fin_hz / gcd_val;
 823
 824         for(n = 1;; n++) {
 825                 nf = YFfenzi * n;
 826                 nonr = YFfenmu * n;
 827                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 828                         break;
 829                 for(no = 1; no <= PLL_NO_MAX; no++) {
 830                         if(!(no == 1 || !(no % 2)))
 831                                 continue;
 832
 833                         if(nonr % no)
 834                                 continue;
 835                         nr = nonr / no;
 836
 837                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 838                                 continue;
 839
 840                         fref = fin_hz / nr;
 841                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 842                                 continue;
 843
 844                         fvco = (fin_hz / nr) * nf;
 845                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 846                                 continue;
 847                         fout = fvco / no;
 848                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 849                                 continue;
 850                         *clk_nr = nr;
 851                         *clk_no = no;
 852                         *clk_nf = nf;
 853                         return 1;
 854
 855                 }
 856
 857         }
 858         return 0;
 859 }
 860
 861 static int pll_clk_mode(struct clk *clk, int on)
 862 {
 863         u8 pll_id = clk->pll->id;
 864         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 865         u32 dly = (nr * 500) / 24 + 1;
 866         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 867         if (on) {
 868                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 869                 rk30_clock_udelay(dly);
 870                 pll_wait_lock(pll_id);
 871                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 872         } else {
 873                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 874                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 875         }
 876         return 0;
 877 }
 878
 879 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 880 {
 881         struct _pll_data *pll_data = c->pll;
 882         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 883         struct pll_clk_set temp_clk_set;
 884         u32 clk_nr, clk_nf, clk_no;
 885
 886         if(rate == 24 * MHZ) {
 887                 cru_writel(PLL_MODE_SLOW(pll_data->id), CRU_MODE_CON);
 888                 cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll_data->id, 3));
 889                 return 0;
 890         }
 891         while(clk_set->rate) {
 892                 if (clk_set->rate == rate) {
 893                         break;
 894                 }
 895                 clk_set++;
 896         }
 897         if(clk_set->rate == rate) {
 898                 CLKDATA_DBG("cpll get a rate\n");
 899                 pll_clk_set_rate(clk_set, pll_data->id);
 900
 901         } else {
 902                 CLKDATA_DBG("cpll get auto calc a rate\n");
 903                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 904                         pr_err("cpll auto set rate error\n");
 905                         return -ENOENT;
 906                 }
 907                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 908                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 909                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 910                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 911                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 912
 913         }
 914         return 0;
 915 }
 916 static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
 917 {
 918         struct _pll_data *pll_data = c->pll;
 919         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 920         struct pll_clk_set temp_clk_set;
 921         u32 clk_nr, clk_nf, clk_no;
 922         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 923
 924         while(clk_set->rate) {
 925                 if (clk_set->rate == rate) {
 926                         break;
 927                 }
 928                 clk_set++;
 929         }
 930         if(clk_set->rate == rate) {
 931                 CLKDATA_DBG("cpll get a rate\n");
 932                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 933
 934         } else {
 935                 CLKDATA_DBG("cpll get auto calc a rate\n");
 936                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 937                         pr_err("cpll auto set rate error\n");
 938                         return -ENOENT;
 939                 }
 940                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 941                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 942                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 943                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 944                 plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
 945
 946         }
 947         return 0;
 948 }
 949
 950
 951 /* ******************fixed input clk ***********************************************/
 952 static struct clk xin24m = {
 953         .name           = "xin24m",
 954         .rate           = 24 * MHZ,
 955         .flags          = RATE_FIXED,
 956 };
 957
 958 static struct clk clk_12m = {
 959         .name           = "clk_12m",
 960         .parent         = &xin24m,
 961         .rate           = 12 * MHZ,
 962         .flags          = RATE_FIXED,
 963 };
 964
 965 /************************************pll func***************************/
 966 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 967                 struct apll_clk_set *tables) {
 968         const struct apll_clk_set *ps, *pt;
 969
 970         /* find the arm_pll we want. */
 971         ps = pt = tables;
 972         while (pt->rate) {
 973                 if (pt->rate == rate) {
 974                         ps = pt;
 975                         break;
 976                 }
 977                 // we are sorted, and ps->rate > pt->rate.
 978                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 979                         ps = pt;
 980                 if (pt->rate < rate)
 981                         break;
 982                 pt++;
 983         }
 984         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 985         return ps;
 986 }
 987 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 988 {
 989         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 990 }
 991 #if 1
 992 struct arm_clks_div_set {
 993         u32 rate;
 994         u32     clksel0;
 995         u32     clksel1;
 996 };
 997
 998 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 999 { \
1000         .rate    =_mhz,\
1001         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
1002         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
1003         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
1004         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
1005         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
1006 }
1007 struct arm_clks_div_set arm_clk_div_tlb[] = {
1008         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
1009         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
1010         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
1011         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
1012         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
1013         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
1014         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
1015 };
1016 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
1017         int i = 0;
1018         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
1019                 if(arm_clk_div_tlb[i].rate >= rate)
1020                         return &arm_clk_div_tlb[i];
1021         }
1022         return NULL;
1023 }
1024
1025 #endif
1026
1027 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1028 {
1029         unsigned long flags;
1030         const struct apll_clk_set *ps;
1031         u32 pll_id = clk->pll->id;
1032         u32 temp_div;
1033         u32 old_aclk_div = 0, new_aclk_div;
1034
1035         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1036
1037         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1038         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1039
1040         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1041                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1042
1043         if(general_pll_clk.rate > clk->rate) {
1044                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1045         } else {
1046                 temp_div = 1;
1047         }
1048
1049         // ungating cpu gpll path
1050         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1051         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1052
1053         local_irq_save(flags);
1054         //div arm clk for gpll
1055
1056         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1057         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1058
1059         loops_per_jiffy = lpj_gpll / temp_div;
1060         smp_wmb();
1061
1062         /*if core src don't select gpll ,apll neet to enter slow mode */
1063         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1064
1065
1066         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
1067         dsb();
1068         dsb();
1069         dsb();
1070         dsb();
1071         dsb();
1072         dsb();
1073         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1074         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1075
1076         rk30_clock_udelay(1);
1077         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
1078
1079         pll_wait_lock(pll_id);
1080
1081         //return form slow
1082         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1083         //reparent to apll
1084
1085         if(new_aclk_div>=old_aclk_div) {
1086                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1087                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1088         }
1089
1090         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1091         if(old_aclk_div>new_aclk_div) {
1092                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1093                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1094         }
1095
1096         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1097
1098         loops_per_jiffy = ps->lpj;
1099         smp_wmb();
1100
1101         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1102
1103         local_irq_restore(flags);
1104
1105         //gate gpll path
1106         // FIXME
1107         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1108         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1109
1110         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1111                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1112                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1113                         cru_readl(CRU_CLKSELS_CON(1)));
1114         return 0;
1115 }
1116
1117 static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1118 {
1119         unsigned long flags;
1120         const struct apll_clk_set *ps;
1121         u32 pll_id = clk->pll->id;
1122         u32 temp_div;
1123         u32 old_aclk_div = 0, new_aclk_div;
1124         DVFS_DBG("%s: for rk3188 plus\n", __func__);
1125
1126         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1127
1128         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1129         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1130
1131         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1132                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1133
1134         if(general_pll_clk.rate > clk->rate) {
1135                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1136         } else {
1137                 temp_div = 1;
1138         }
1139
1140         // ungating cpu gpll path
1141         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1142         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1143
1144         local_irq_save(flags);
1145         //div arm clk for gpll
1146
1147         cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1148         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1149
1150         loops_per_jiffy = lpj_gpll / temp_div;
1151         smp_wmb();
1152
1153         /*if core src don't select gpll ,apll neet to enter slow mode */
1154         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1155
1156         //enter rest
1157         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
1158         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1159         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1160         cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
1161         rk30_clock_udelay(5);
1162
1163         //return form rest
1164         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
1165
1166         //wating lock state
1167         rk30_clock_udelay(ps->rst_dly);
1168         pll_wait_lock(pll_id);
1169
1170         if(new_aclk_div>=old_aclk_div) {
1171                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1172                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1173         }
1174
1175         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1176         if(old_aclk_div>new_aclk_div) {
1177                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1178                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1179         }
1180
1181         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1182
1183         loops_per_jiffy = ps->lpj;
1184         smp_wmb();
1185
1186         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1187
1188         local_irq_restore(flags);
1189
1190         //gate gpll path
1191         // FIXME
1192         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1193         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1194
1195         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1196                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1197                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1198                         cru_readl(CRU_CLKSELS_CON(1)));
1199         return 0;
1200 }
1201
1202 /************************************pll clocks***************************/
1203
1204 static const struct apll_clk_set apll_clks[] = {
1205         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1206         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1207         _APLL_SET_CLKS(2208, 1, 92, 1, 8,       81, 81, 21, 41, 21),
1208         _APLL_SET_CLKS(2184, 1, 91, 1, 8,       81, 81, 21, 41, 21),
1209         _APLL_SET_CLKS(2160, 1, 90, 1, 8,       81, 81, 21, 41, 21),
1210         _APLL_SET_CLKS(2136, 1, 89, 1, 8,       81, 81, 21, 41, 21),
1211         _APLL_SET_CLKS(2112, 1, 88, 1, 8,       81, 81, 21, 41, 21),
1212         _APLL_SET_CLKS(2088, 1, 87, 1, 8,       81, 81, 21, 41, 21),
1213         _APLL_SET_CLKS(2064, 1, 86, 1, 8,       81, 81, 21, 41, 21),
1214         _APLL_SET_CLKS(2040, 1, 85, 1, 8,       81, 81, 21, 41, 21),
1215         _APLL_SET_CLKS(2016, 1, 84, 1, 8,       81, 81, 21, 41, 21),
1216         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1217         _APLL_SET_CLKS(1968, 1, 82, 1, 8,       81, 81, 21, 41, 21),
1218         _APLL_SET_CLKS(1944, 1, 81, 1, 8,       81, 81, 21, 41, 21),
1219         _APLL_SET_CLKS(1920, 1, 80, 1, 8,       81, 81, 21, 41, 21),
1220         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1221         _APLL_SET_CLKS(1872, 1, 78, 1, 8,       81, 81, 21, 41, 21),
1222         _APLL_SET_CLKS(1848, 1, 77, 1, 8,       81, 81, 21, 41, 21),
1223         _APLL_SET_CLKS(1824, 1, 76, 1, 8,       81, 81, 21, 41, 21),
1224         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1225         _APLL_SET_CLKS(1776, 1, 74, 1, 8,       81, 81, 21, 41, 21),
1226         _APLL_SET_CLKS(1752, 1, 73, 1, 8,       81, 81, 21, 41, 21),
1227         _APLL_SET_CLKS(1728, 1, 72, 1, 8,       81, 81, 21, 41, 21),
1228         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1229         _APLL_SET_CLKS(1680, 1, 70, 1, 8,       41, 41, 21, 41, 21),
1230         _APLL_SET_CLKS(1656, 1, 69, 1, 8,       41, 41, 21, 41, 21),
1231         _APLL_SET_CLKS(1632, 1, 68, 1, 8,       41, 41, 21, 41, 21),
1232         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1233         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1234         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1235         _APLL_SET_CLKS(1488, 1, 62, 1, 8,       41, 41, 21, 41, 21),
1236         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1237         _APLL_SET_CLKS(1440, 1, 60, 1, 8,       41, 41, 21, 41, 21),
1238         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1239         _APLL_SET_CLKS(1392, 1, 58, 1, 8,       41, 41, 21, 41, 21),
1240         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1241         _APLL_SET_CLKS(1344, 1, 56, 1, 8,       41, 41, 21, 41, 21),
1242         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1243         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1244         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1245         _APLL_SET_CLKS(1248, 1, 52, 1, 8,       41, 41, 21, 41, 21),
1246         _APLL_SET_CLKS(1224, 1, 51, 1, 8,       41, 41, 21, 41, 21),
1247         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1248         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1249         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1250         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1251         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1252         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1253         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1254         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1255         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1256         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1257         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1258         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1259         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1260         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1261         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1262         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1263         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1264         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1265         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1266
1267 };
1268 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1269 static struct clk arm_pll_clk = {
1270         .name           = "arm_pll",
1271         .parent         = &xin24m,
1272         .mode           = pll_clk_mode,
1273         .recalc         = plls_clk_recalc,
1274         .set_rate       = arm_pll_clk_set_rate,
1275         .round_rate     = arm_pll_clk_round_rate,
1276         .pll            = &apll_data,
1277 };
1278
1279 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1280 {
1281         /* do nothing here */
1282         return 0;
1283 }
1284 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1285 static struct clk ddr_pll_clk = {
1286         .name           = "ddr_pll",
1287         .parent         = &xin24m,
1288         .recalc         = plls_clk_recalc,
1289         .set_rate       = ddr_pll_clk_set_rate,
1290         .pll            = &dpll_data,
1291 };
1292
1293 static const struct pll_clk_set cpll_clks[] = {
1294         _PLL_SET_CLKS(360000, 1,  60,   4),
1295         _PLL_SET_CLKS(408000, 1,  68,   4),
1296         _PLL_SET_CLKS(456000, 1,  76,   4),
1297         _PLL_SET_CLKS(504000, 1,  84,   4),
1298         _PLL_SET_CLKS(552000, 1,  46,   2),
1299         _PLL_SET_CLKS(594000, 2,  198,  4),
1300         _PLL_SET_CLKS(600000, 1,  50,   2),
1301         _PLL_SET_CLKS(742500, 8,  495,  2),
1302         _PLL_SET_CLKS(768000, 1,  64,   2),
1303         _PLL_SET_CLKS(798000, 2,  133,  2),
1304         _PLL_SET_CLKS(1188000, 2, 99,   1),
1305         _PLL_SET_CLKS(     0, 4,  133,  1),
1306 };
1307 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1308 static struct clk codec_pll_clk = {
1309         .name           = "codec_pll",
1310         .parent         = &xin24m,
1311         .mode           = pll_clk_mode,
1312         .recalc         = plls_clk_recalc,
1313         .set_rate       = cpll_clk_set_rate,
1314         .pll            = &cpll_data,
1315 };
1316
1317 static const struct pll_clk_set gpll_clks[] = {
1318         _PLL_SET_CLKS(148500,   2,      99,     8),
1319         _PLL_SET_CLKS(297000,   2,      198,    8),
1320         _PLL_SET_CLKS(300000,   1,      50,     4),
1321         _PLL_SET_CLKS(384000,   2,      128,    4),
1322         _PLL_SET_CLKS(594000,   2,      198,    4),
1323         _PLL_SET_CLKS(768000,   1,      64,     2),
1324         _PLL_SET_CLKS(891000,   8,      594,    2),
1325         _PLL_SET_CLKS(1188000,  2,      99,     1),
1326         _PLL_SET_CLKS(1200000,  1,      50,     1),
1327         _PLL_SET_CLKS(0,        0,       0,     0),
1328 };
1329 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1330 static struct clk general_pll_clk = {
1331         .name           = "general_pll",
1332         .parent         = &xin24m,
1333         .recalc         = plls_clk_recalc,
1334         .set_rate       = gpll_clk_set_rate,
1335         .pll            = &gpll_data
1336 };
1337 /********************************clocks***********************************/
1338 //GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1339 static struct clk clk_ddr_gpll_path = {
1340         .name           = "ddr_gpll_path",
1341         .parent         = &general_pll_clk,
1342         .recalc         = clksel_recalc_parent_rate,
1343         .gate_idx       = CLK_GATE_DDR_GPLL,
1344         .mode           = gate_mode,
1345 };
1346
1347 /* core and cpu setting */
1348 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1349 {
1350         CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1351         return 0;
1352 }
1353
1354 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1355 {
1356         CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1357         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1358 }
1359 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1360 {
1361         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1362         unsigned long rate = 0;
1363         clk->parent = clk->get_parent(clk);
1364         rate = clk->parent->recalc(clk->parent) >> shift;
1365         CLKDATA_DBG("%s new clock rate is %lu (shift %u), parent=%s, rate=%lu\n",
1366                         clk->name, rate, shift, clk->parent->name, clk->parent->rate);
1367         return rate;
1368 }
1369 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1370 static struct clk clk_ddr = {
1371         .name           = "ddr",
1372         .parent         = &ddr_pll_clk,
1373         .get_parent     = clksel_get_parent,
1374         .set_parent     = clksel_set_parent,
1375         .recalc         = ddr_clk_recalc_rate,
1376         .set_rate       = ddr_clk_set_rate,
1377         .round_rate     = ddr_clk_round_rate,
1378         .gate_idx       = CLK_GATE_DDRPHY,
1379         .clksel_con     = CRU_CLKSELS_CON(26),
1380         CRU_DIV_SET(0x3, 0, 4),
1381         CRU_SRC_SET(1, 8),
1382         CRU_PARENTS_SET(clk_ddr_parents),
1383 };
1384 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1385 {
1386         int ret;
1387
1388         ret = clk_set_rate_nolock(c->parent, rate);
1389         if (ret) {
1390                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1391                 return ret;
1392         }
1393         //set arm pll div 1
1394         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1395         return 0;
1396 }
1397 static unsigned long clk_core_get_rate(struct clk *c)
1398 {
1399         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1400         //c->parent->rate=c->parent->recalc(c->parent);
1401         return c->parent->rate / div;
1402 }
1403 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1404 {
1405         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1406         return clk_round_rate_nolock(clk->parent, rate) / div;
1407 }
1408
1409 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1410 {
1411
1412         u32 temp_div;
1413         struct clk *old_prt;
1414
1415         if(clk->parent == new_prt)
1416                 return 0;
1417         if (unlikely(!clk->parents))
1418                 return -EINVAL;
1419         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1420         //arm
1421         old_prt = clk->parent;
1422
1423         if(clk->parents[0] == new_prt) {
1424                 new_prt->set_rate(new_prt, 300 * MHZ);
1425                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1426         } else if(clk->parents[1] == new_prt) {
1427
1428                 if(new_prt->rate > old_prt->rate) {
1429                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1430                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1431                 }
1432                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1433                 new_prt->set_rate(new_prt, 300 * MHZ);
1434         } else
1435                 return -1;
1436
1437
1438         return 0;
1439
1440 }
1441
1442 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1443 {
1444         u32 temp_div;
1445         u32 old_aclk_div = 0, new_aclk_div;
1446         struct arm_clks_div_set *temp_clk_div;
1447         unsigned long arm_gpll_rate, arm_gpll_lpj;
1448         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1449         arm_gpll_rate = c->parent->rate / temp_div;
1450
1451         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1452         if(!temp_clk_div)
1453                 temp_clk_div = &arm_clk_div_tlb[4];
1454
1455         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1456         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1457         if(c->rate >= rate) {
1458                 arm_gpll_lpj = lpj_gpll / temp_div;
1459                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1460         }
1461
1462         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1463         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1464                         CRU_CLKSELS_CON(0));
1465         if((c->rate < rate)) {
1466                 arm_gpll_lpj = lpj_gpll / temp_div;
1467                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1468         }
1469         return 0;
1470 }
1471 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1472 {
1473         return c->parent->rate;
1474 }
1475 static struct clk clk_core_gpll_path = {
1476         .name           = "cpu_gpll_path",
1477         .parent         = &general_pll_clk,
1478         .recalc         = arm_core_gpll_clk_get_rate,
1479         .set_rate       = core_gpll_clk_set_rate,
1480         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1481 };
1482
1483
1484 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1485
1486 static struct clk clk_core = {
1487         .name           = "core",
1488         .parent         = &arm_pll_clk,
1489         .set_rate       = clk_core_set_rate,
1490         .recalc         = clk_core_get_rate,
1491         .round_rate     = core_clk_round_rate,
1492         .set_parent     = core_clksel_set_parent,
1493         .clksel_con     = CRU_CLKSELS_CON(0),
1494         CRU_DIV_SET(0x1f, 9, 32),
1495         CRU_SRC_SET(1, 8),
1496         CRU_PARENTS_SET(clk_core_parents),
1497 };
1498 GATE_CLK(l2c, clk_core, CLK_L2C);
1499 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1500 static unsigned long aclk_recalc(struct clk *clk)
1501 {
1502         unsigned long rate;
1503         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1504
1505         BUG_ON(div > 5);
1506         if (div >= 5)
1507                 div = 8;
1508         rate = clk->parent->rate / div;
1509         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1510
1511         return rate;
1512 };
1513 static struct clk core_periph = {
1514         .name           = "core_periph",
1515         .parent         = &clk_core,
1516         .gate_idx       = CLK_GATE_CORE_PERIPH,
1517         .recalc         = clksel_recalc_shift_2,
1518         .clksel_con     = CRU_CLKSELS_CON(0),
1519         CRU_DIV_SET(0x3, 6, 16),
1520 };
1521 static struct clk aclk_core = {
1522         .name           = "aclk_core",
1523         .parent         = &clk_core,
1524         .gate_idx       = CLK_GATE_ACLK_CORE,
1525         .recalc         = aclk_recalc,
1526         .clksel_con     = CRU_CLKSELS_CON(1),
1527         CRU_DIV_SET(0x7, 3, 8),
1528 };
1529
1530 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1531 static struct clk clk_cpu_div = {
1532         .name           = "cpu_div",
1533         .parent         = &arm_pll_clk,
1534         .set_rate       = clksel_set_rate_freediv,
1535         .recalc         = clksel_recalc_div,
1536         .clksel_con     = CRU_CLKSELS_CON(0),
1537         CRU_DIV_SET(0x1f, 0, 32),
1538         CRU_SRC_SET(1, 5),
1539         CRU_PARENTS_SET(clk_cpu_div_parents),
1540 };
1541
1542 static struct clk aclk_cpu = {
1543         .name           = "aclk_cpu",
1544         .parent         = &clk_cpu_div,
1545         .gate_idx       = CLK_GATE_ACLK_CPU,
1546 };
1547
1548 static struct clk hclk_cpu = {
1549         .name           = "hclk_cpu",
1550         .parent         = &aclk_cpu,
1551         .gate_idx       = CLK_GATE_HCLK_CPU,
1552         .recalc         = clksel_recalc_shift,
1553         .set_rate       = clksel_set_rate_shift,
1554         .clksel_con     = CRU_CLKSELS_CON(1),
1555         CRU_DIV_SET(0x3, 8, 4),
1556
1557 };
1558
1559 static struct clk pclk_cpu = {
1560         .name           = "pclk_cpu",
1561         .parent         = &aclk_cpu,
1562         .gate_idx       = CLK_GATE_PCLK_CPU,
1563         .recalc         = clksel_recalc_shift,
1564         .set_rate       = clksel_set_rate_shift,
1565         .clksel_con     = CRU_CLKSELS_CON(1),
1566         CRU_DIV_SET(0x3, 12, 8),
1567 };
1568
1569 static struct clk ahb2apb_cpu = {
1570         .name           = "ahb2apb",
1571         .parent         = &hclk_cpu,
1572         .recalc         = clksel_recalc_shift,
1573         .set_rate       = clksel_set_rate_shift,
1574         .clksel_con     = CRU_CLKSELS_CON(1),
1575         CRU_DIV_SET(0x3, 14, 4),
1576 };
1577
1578
1579 static struct clk atclk_cpu = {
1580         .name           = "atclk_cpu",
1581         .parent         = &pclk_cpu,
1582         .gate_idx       = CLK_GATE_ATCLK_CPU,
1583 };
1584
1585 /* GPU setting */
1586 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1587 {
1588         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1589         return clkset_rate_freediv_autosel_parents(clk, max_rate);
1590 };
1591
1592 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1593
1594 static struct clk aclk_gpu = {
1595         .name           = "aclk_gpu",
1596         .mode           = gate_mode,
1597         .recalc         = clksel_recalc_div,
1598         .round_rate     = clk_freediv_round_autosel_parents_rate,
1599         .set_rate       = clkset_rate_freediv_autosel_parents,
1600         .clksel_con     = CRU_CLKSELS_CON(34),
1601         .gate_idx       = CLK_GATE_ACLK_GPU,
1602         CRU_DIV_SET(0x1f, 0, 32),
1603         CRU_SRC_SET(0x1, 7),
1604         CRU_PARENTS_SET(aclk_gpu_parents),
1605 };
1606
1607 /* vcodec setting */
1608 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1609 {
1610         unsigned long rate = clk->parent->rate / 4;
1611         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1612         return rate;
1613 }
1614
1615 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1616
1617 static struct clk aclk_vepu = {
1618         .name           = "aclk_vepu",
1619         .parent         = &codec_pll_clk,
1620         .mode           = gate_mode,
1621         .recalc         = clksel_recalc_div,
1622         .set_rate       = clkset_rate_freediv_autosel_parents,
1623         .clksel_con     = CRU_CLKSELS_CON(32),
1624         .gate_idx       = CLK_GATE_ACLK_VEPU,
1625         CRU_DIV_SET(0x1f, 0, 32),
1626         CRU_SRC_SET(0x1, 7),
1627         CRU_PARENTS_SET(aclk_vepu_parents),
1628 };
1629
1630 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1631
1632 static struct clk aclk_vdpu = {
1633         .name           = "aclk_vdpu",
1634         .mode           = gate_mode,
1635         .recalc         = clksel_recalc_div,
1636         .set_rate       = clkset_rate_freediv_autosel_parents,
1637         .clksel_con     = CRU_CLKSELS_CON(32),
1638         .gate_idx       = CLK_GATE_ACLK_VDPU,
1639         CRU_DIV_SET(0x1f, 8, 32),
1640         CRU_SRC_SET(0x1, 15),
1641         CRU_PARENTS_SET(aclk_vdpu_parents),
1642 };
1643 static struct clk hclk_vepu = {
1644         .name           = "hclk_vepu",
1645         .parent         = &aclk_vepu,
1646         .mode           = gate_mode,
1647         .recalc         = clksel_recalc_vpu_hclk,
1648         .gate_idx       = CLK_GATE_HCLK_VEPU,
1649 };
1650
1651 static struct clk hclk_vdpu = {
1652         .name           = "hclk_vdpu",
1653         .parent         = &aclk_vdpu,
1654         .mode           = gate_mode,
1655         .recalc         = clksel_recalc_vpu_hclk,
1656         .gate_idx       = CLK_GATE_HCLK_VDPU,
1657 };
1658
1659 /* aclk lcdc setting */
1660 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1661
1662 static struct clk aclk_lcdc0_pre = {
1663         .name           = "aclk_lcdc0_pre",
1664         .parent         = &codec_pll_clk,
1665         .mode           = gate_mode,
1666         .recalc         = clksel_recalc_div,
1667         .set_rate       = clkset_rate_freediv_autosel_parents,
1668         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1669         .clksel_con     = CRU_CLKSELS_CON(31),
1670         CRU_DIV_SET(0x1f, 0, 32),
1671         CRU_SRC_SET(0x1, 7),
1672         CRU_PARENTS_SET(aclk_lcdc0_parents),
1673 };
1674
1675 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1676
1677 static struct clk aclk_lcdc1_pre = {
1678         .name           = "aclk_lcdc1_pre",
1679         .parent         = &codec_pll_clk,
1680         .mode           = gate_mode,
1681         .recalc         = clksel_recalc_div,
1682         .set_rate       = clkset_rate_freediv_autosel_parents,
1683         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1684         .clksel_con     = CRU_CLKSELS_CON(31),
1685         CRU_DIV_SET(0x1f, 8, 32),
1686         CRU_SRC_SET(0x1, 15),
1687         CRU_PARENTS_SET(aclk_lcdc1_parents),
1688 };
1689
1690 /* aclk/hclk/pclk periph setting */
1691 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1692
1693 static struct clk aclk_periph = {
1694         .name           = "aclk_periph",
1695         .parent         = &general_pll_clk,
1696         .mode           = gate_mode,
1697         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1698         .recalc         = clksel_recalc_div,
1699         .set_rate       = clksel_set_rate_freediv,
1700         .clksel_con     = CRU_CLKSELS_CON(10),
1701         CRU_DIV_SET(0x1f, 0, 32),
1702         CRU_SRC_SET(1, 15),
1703         CRU_PARENTS_SET(aclk_periph_parents),
1704 };
1705 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1706
1707 static struct clk pclk_periph = {
1708         .name           = "pclk_periph",
1709         .parent         = &aclk_periph,
1710         .mode           = gate_mode,
1711         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1712         .recalc         = clksel_recalc_shift,
1713         .set_rate       = clksel_set_rate_shift,
1714         .clksel_con     = CRU_CLKSELS_CON(10),
1715         CRU_DIV_SET(0x3, 12, 8),
1716 };
1717
1718 static struct clk hclk_periph = {
1719         .name           = "hclk_periph",
1720         .parent         = &aclk_periph,
1721         .mode           = gate_mode,
1722         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1723         .recalc         = clksel_recalc_shift,
1724         .set_rate       = clksel_set_rate_shift,
1725         .clksel_con     = CRU_CLKSELS_CON(10),
1726         CRU_DIV_SET(0x3, 8, 4),
1727 };
1728 /* dclk lcdc setting */
1729 // FIXME
1730 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1731 {
1732         u32 div, old_div;
1733         int i;
1734         unsigned long new_rate;
1735         int ret = 0;
1736
1737         if(clk->rate == rate)
1738                 return 0;
1739         for(i = 0; i < 2; i++) {
1740                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1741                 new_rate = clk->parents[i]->rate / div;
1742                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1743                         break;
1744                 }
1745         }
1746         if(i >= 2) {
1747                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1748                 return -1;
1749         }
1750
1751         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1752
1753         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1754                         clk->div_shift, clk->div_mask) + 1;
1755         if(div > old_div)
1756                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1757
1758         if(clk->parents[i] != clk->parent) {
1759                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1760         }
1761
1762         if (ret) {
1763                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1764                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1765                 return ret;
1766         }
1767         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1768         return 0;
1769 }
1770
1771 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1772 {
1773         if (rate == 27 * MHZ)
1774                 return clkset_rate_freediv_autosel_parents(clk, rate);
1775         else
1776                 return clkset_rate_evendiv_autosel_parents(clk, rate);
1777
1778 #if 0
1779         int ret = 0;
1780         struct clk *parent;
1781         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1782                 parent = clk->parents[1];
1783                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1784         } else {
1785                 parent = clk->parents[0];
1786         }
1787         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1788         //clk->name,rate,parent->name,clk->parent->name);
1789
1790         if(parent != clk->parents[1]) {
1791                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1792                 if (ret) {
1793                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1794                         return ret;
1795                 }
1796         }
1797         if (clk->parent != parent) {
1798                 ret = clk_set_parent_nolock(clk, parent);
1799                 if (ret) {
1800                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1801                         return ret;
1802                 }
1803         }
1804         return ret;
1805 #endif
1806 }
1807
1808 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1809 static struct clk dclk_lcdc0 = {
1810         .name           = "dclk_lcdc0",
1811         .mode           = gate_mode,
1812         .set_rate       = dclk_lcdc_set_rate,
1813         .recalc         = clksel_recalc_div,
1814         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1815         .clksel_con     = CRU_CLKSELS_CON(27),
1816         CRU_SRC_SET(0x1, 0),
1817         CRU_DIV_SET(0xff, 8, 256),
1818         CRU_PARENTS_SET(dclk_lcdc0_parents),
1819 };
1820
1821 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1822 static struct clk dclk_lcdc1 = {
1823         .name           = "dclk_lcdc1",
1824         .mode           = gate_mode,
1825         .set_rate       = dclk_lcdc_set_rate,
1826         .recalc         = clksel_recalc_div,
1827         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1828         .clksel_con     = CRU_CLKSELS_CON(28),
1829         CRU_SRC_SET(0x1, 0),
1830         CRU_DIV_SET(0xff, 8, 256),
1831         CRU_PARENTS_SET(dclk_lcdc1_parents),
1832 };
1833
1834 /* cif setting */
1835 // FIXME
1836 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1837 static struct clk cif_out_pll = {
1838         .name           = "cif_out_pll",
1839         .parent         = &general_pll_clk,
1840         .clksel_con     = CRU_CLKSELS_CON(29),
1841         CRU_SRC_SET(0x1, 0),
1842         CRU_PARENTS_SET(cifout_sel_pll_parents),
1843 };
1844
1845 static struct clk cif0_out_div = {
1846         .name           = "cif0_out_div",
1847         .parent         = &cif_out_pll,
1848         .mode           = gate_mode,
1849         .recalc         = clksel_recalc_div,
1850         .set_rate       = clksel_set_rate_freediv,
1851         .gate_idx       = CLK_GATE_CIF0_OUT,
1852         .clksel_con     = CRU_CLKSELS_CON(29),
1853         CRU_DIV_SET(0x1f, 1, 32),
1854 };
1855
1856 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1857 {
1858         int ret = 0;
1859         struct clk *parent;
1860
1861         if (rate == 24 * MHZ) {
1862                 parent = clk->parents[1];
1863         } else {
1864                 parent = clk->parents[0];
1865                 ret = clk_set_rate_nolock(parent, rate);
1866                 if (ret)
1867                         return ret;
1868         }
1869         if (clk->parent != parent)
1870                 ret = clk_set_parent_nolock(clk, parent);
1871
1872         return ret;
1873 }
1874
1875 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1876 static struct clk cif0_out = {
1877         .name           = "cif0_out",
1878         .parent         = &cif0_out_div,
1879         .set_rate       = cif_out_set_rate,
1880         .clksel_con     = CRU_CLKSELS_CON(29),
1881         CRU_SRC_SET(0x1, 7),
1882         CRU_PARENTS_SET(cif0_out_parents),
1883 };
1884
1885 static struct clk pclkin_cif0 = {
1886         .name           = "pclkin_cif0",
1887         .mode           = gate_mode,
1888         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1889 };
1890
1891 static struct clk inv_cif0 = {
1892         .name           = "inv_cif0",
1893         .parent         = &pclkin_cif0,
1894 };
1895
1896 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1897 static struct clk cif0_in = {
1898         .name           = "cif0_in",
1899         .parent         = &pclkin_cif0,
1900         .clksel_con     = CRU_CLKSELS_CON(30),
1901         CRU_SRC_SET(0x1, 8),
1902         CRU_PARENTS_SET(cif0_in_parents),
1903 };
1904
1905 /* i2s/spdif setting */
1906 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1907 static struct clk clk_i2s_pll = {
1908         .name           = "i2s_pll",
1909         .parent         = &general_pll_clk,
1910         .clksel_con     = CRU_CLKSELS_CON(2),
1911         CRU_SRC_SET(0x1, 15),
1912         CRU_PARENTS_SET(clk_i2s_div_parents),
1913 };
1914
1915 static struct clk clk_i2s0_div = {
1916         .name           = "i2s0_div",
1917         .parent         = &clk_i2s_pll,
1918         .mode           = gate_mode,
1919         .recalc         = clksel_recalc_div,
1920         .set_rate       = clksel_set_rate_freediv,
1921         .round_rate     = clksel_freediv_round_rate,
1922         .gate_idx       = CLK_GATE_I2S0_SRC,
1923         .clksel_con     = CRU_CLKSELS_CON(3),
1924         CRU_DIV_SET(0x7f, 0, 64),
1925 };
1926
1927 static struct clk clk_spdif_div = {
1928         .name           = "spdif_div",
1929         .parent         = &clk_i2s_pll,
1930         .recalc         = clksel_recalc_div,
1931         .set_rate       = clksel_set_rate_freediv,
1932         .round_rate     = clksel_freediv_round_rate,
1933         .mode           = gate_mode,
1934         .gate_idx       = CLK_GATE_SPDIF_SRC,
1935         .clksel_con     = CRU_CLKSELS_CON(5),
1936         CRU_DIV_SET(0x7f, 0, 64),
1937 };
1938 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1939 {
1940         u32 numerator, denominator;
1941         int i = 10;
1942         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1943         //clk->parent->parent
1944         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1945                                 &numerator, &denominator) == 0) {
1946                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1947
1948                 while (i--) {
1949                         cru_writel_frac((numerator - 1) << 16 | denominator, clk->clksel_con);
1950                         mdelay(1);
1951                         cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1952                         mdelay(1);
1953                 }
1954                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1955         } else {
1956                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1957                 return -ENOENT;
1958         }
1959         return 0;
1960 }
1961
1962 static struct clk clk_i2s0_frac_div = {
1963         .name           = "i2s0_frac_div",
1964         .parent         = &clk_i2s0_div,
1965         .mode           = gate_mode,
1966         .gate_idx       = CLK_GATE_I2S0_FRAC,
1967         .recalc         = clksel_recalc_frac,
1968         .set_rate       = clk_i2s_fracdiv_set_rate,
1969         .clksel_con     = CRU_CLKSELS_CON(7),
1970 };
1971
1972 static struct clk clk_spdif_frac_div = {
1973         .name           = "spdif_frac_div",
1974         .parent         = &clk_spdif_div,
1975         .mode           = gate_mode,
1976         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1977         .recalc         = clksel_recalc_frac,
1978         .set_rate       = clk_i2s_fracdiv_set_rate,
1979         .clksel_con     = CRU_CLKSELS_CON(9),
1980 };
1981
1982 #define I2S_SRC_DIV     (0x0)
1983 #define I2S_SRC_FRAC    (0x1)
1984 #define I2S_SRC_12M     (0x2)
1985
1986 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1987 {
1988         int ret = -EINVAL;
1989         struct clk *parent;
1990
1991         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1992                 parent = clk->parents[I2S_SRC_12M];
1993         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1994                 parent = clk->parents[I2S_SRC_DIV];
1995         } else {
1996                 parent = clk->parents[I2S_SRC_FRAC];
1997         }
1998
1999         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2000                         clk->name, rate, parent->name, clk->parent->name);
2001
2002         if(parent != clk->parents[I2S_SRC_12M]) {
2003                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
2004                 if (ret) {
2005                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2006                         return ret;
2007                 }
2008         }
2009
2010         if (clk->parent != parent) {
2011                 ret = clk_set_parent_nolock(clk, parent);
2012                 if (ret) {
2013                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2014                         return ret;
2015                 }
2016         }
2017
2018         return ret;
2019 };
2020
2021 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
2022
2023 static struct clk clk_i2s0 = {
2024         .name           = "i2s0",
2025         .set_rate       = i2s_set_rate,
2026         .clksel_con     = CRU_CLKSELS_CON(3),
2027         CRU_SRC_SET(0x3, 8),
2028         CRU_PARENTS_SET(clk_i2s0_parents),
2029 };
2030
2031 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
2032
2033 static struct clk clk_spdif = {
2034         .name           = "spdif",
2035         .parent         = &clk_spdif_frac_div,
2036         .set_rate       = i2s_set_rate,
2037         .clksel_con = CRU_CLKSELS_CON(5),
2038         CRU_SRC_SET(0x3, 8),
2039         CRU_PARENTS_SET(clk_spdif_parents),
2040 };
2041
2042 /* otgphy setting */
2043 GATE_CLK(otgphy0, xin24m, OTGPHY0);
2044 GATE_CLK(otgphy1, xin24m, OTGPHY1);
2045
2046 static struct clk clk_otgphy0_480m = {
2047         .name           = "otgphy0_480m",
2048         .parent         = &clk_otgphy0,
2049 };
2050 static struct clk clk_otgphy1_480m = {
2051         .name           = "otgphy1_480m",
2052         .parent         = &clk_otgphy1,
2053 };
2054
2055 /* hsicphy setting */
2056 #ifdef ARCH_RK31
2057 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
2058 static struct clk clk_hsicphy_480m = {
2059         .name           = "hsicphy_480m",
2060         .parent         = &clk_otgphy0_480m,
2061         .clksel_con      = CRU_CLKSELS_CON(30),
2062         CRU_SRC_SET(0x3, 0),
2063         CRU_PARENTS_SET(clk_hsicphy_parents),
2064 };
2065 static struct clk clk_hsicphy_12m = {
2066         .name           = "hsicphy_12m",
2067         .parent         = &clk_hsicphy_480m,
2068         .clksel_con     = CRU_CLKSELS_CON(11),
2069         CRU_DIV_SET(0x3f, 8, 64),
2070 };
2071 #endif
2072
2073 /* mac and rmii setting */
2074 // FIXME
2075 static struct clk rmii_clkin = {
2076         .name           = "rmii_clkin",
2077 };
2078 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
2079 static struct clk clk_mac_pll_div = {
2080         .name           = "mac_pll_div",
2081         .parent         = &general_pll_clk,
2082         .mode           = gate_mode,
2083         .gate_idx       = CLK_GATE_MAC_SRC,
2084         .recalc         = clksel_recalc_div,
2085         .set_rate       = clksel_set_rate_freediv,
2086         .clksel_con     = CRU_CLKSELS_CON(21),
2087         CRU_DIV_SET(0x1f, 8, 32),
2088         CRU_SRC_SET(0x1, 0),
2089         CRU_PARENTS_SET(clk_mac_ref_div_parents),
2090 };
2091
2092 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
2093 {
2094         if(clk->parent == clk->parents[1]) {
2095                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
2096                 return -ENOENT;
2097         } else if(clk->parent == clk->parents[0]) {
2098                 return clk_set_rate_nolock(clk->parents[0], rate);
2099         }
2100         return -ENOENT;
2101 }
2102
2103 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
2104
2105 static struct clk clk_mac_ref = {
2106         .name           = "mac_ref",
2107         .parent         = &clk_mac_pll_div,
2108         .set_rate       = clksel_mac_ref_set_rate,
2109         .clksel_con     = CRU_CLKSELS_CON(21),
2110         CRU_SRC_SET(0x1, 4),
2111         CRU_PARENTS_SET(clk_mac_ref_parents),
2112 };
2113
2114 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
2115 {
2116         return clk_set_parent_nolock(clk->parent, parent);
2117 }
2118
2119 static struct clk clk_mii_tx = {
2120         .name           = "mii_tx",
2121         .parent         = &clk_mac_ref,
2122         //.set_parent   = clk_set_mii_tx_parent,
2123         .mode           = gate_mode,
2124         .gate_idx       = CLK_GATE_MAC_LBTEST,
2125 };
2126
2127 /* hsadc and saradc */
2128 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
2129 static struct clk clk_hsadc_pll_div = {
2130         .name           = "hsadc_pll_div",
2131         .parent         = &general_pll_clk,
2132         .mode           = gate_mode,
2133         .gate_idx       = CLK_GATE_HSADC_SRC,
2134         .recalc         = clksel_recalc_div,
2135         .round_rate     = clk_freediv_round_autosel_parents_rate,
2136         .set_rate       = clkset_rate_freediv_autosel_parents,
2137         //.round_rate   = clksel_freediv_round_rate,
2138         //.set_rate     = clksel_set_rate_freediv,
2139         .clksel_con = CRU_CLKSELS_CON(22),
2140         CRU_DIV_SET(0xff, 8, 256),
2141         CRU_SRC_SET(0x1, 0),
2142         CRU_PARENTS_SET(clk_hsadc_pll_parents),
2143 };
2144 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2145 {
2146         u32 numerator, denominator;
2147         //        clk_hsadc_pll_div->gpll/cpll
2148         //clk->parent->parent
2149         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2150                                 &numerator, &denominator) == 0) {
2151                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2152
2153                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2154
2155                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2156         } else {
2157                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2158                 return -ENOENT;
2159         }
2160         return 0;
2161 }
2162 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2163 {
2164         u32 numerator, denominator;
2165         u32 i, ret = 0;
2166         //        clk_hsadc_pll_div->gpll/cpll
2167         //clk->parent->parent
2168         for(i = 0; i < 2; i++) {
2169                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2170                                         &numerator, &denominator) == 0)
2171                         break;
2172         }
2173         if(i >= 2)
2174                 return -ENOENT;
2175
2176         if(clk->parent->parent != clk->parent->parents[i])
2177                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2178         if(ret == 0) {
2179                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2180
2181                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2182
2183                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2184         } else {
2185                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2186                 return -ENOENT;
2187         }
2188         return 0;
2189 }
2190
2191 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2192 {
2193         u32 numerator, denominator;
2194
2195         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2196         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2197                                 &numerator, &denominator) == 0)
2198                 return rate;
2199
2200         return 0;
2201 }
2202 static struct clk clk_hsadc_frac_div = {
2203         .name           = "hsadc_frac_div",
2204         .parent         = &clk_hsadc_pll_div,
2205         .mode           = gate_mode,
2206         .recalc         = clksel_recalc_frac,
2207         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2208         .round_rate     = clk_hsadc_fracdiv_round_rate,
2209         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
2210         .clksel_con     = CRU_CLKSELS_CON(23),
2211 };
2212
2213 #define HSADC_SRC_DIV 0x0
2214 #define HSADC_SRC_FRAC 0x1
2215 #define HSADC_SRC_EXT 0x2
2216 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2217 {
2218         int ret = -EINVAL;
2219         struct clk *parent;
2220
2221         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2222                 CLKDATA_DBG("hsadc clk is form ext\n");
2223                 return 0;
2224         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2225                 parent = clk->parents[HSADC_SRC_DIV];
2226         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2227                 parent = clk->parents[HSADC_SRC_FRAC];
2228         } else
2229                 parent = clk->parents[HSADC_SRC_DIV];
2230
2231         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2232                         clk->name, rate, parent->name, clk->parent->name);
2233
2234         ret = clk_set_rate_nolock(parent, rate);
2235         if (ret) {
2236                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2237                 return ret;
2238         }
2239         if (clk->parent != parent) {
2240                 ret = clk_set_parent_nolock(clk, parent);
2241                 if (ret) {
2242                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2243                         return ret;
2244                 }
2245         }
2246         return ret;
2247 }
2248
2249 static struct clk clk_hsadc_ext = {
2250         .name           = "hsadc_ext",
2251 };
2252
2253 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2254 static struct clk clk_hsadc_out = {
2255         .name           = "hsadc_out",
2256         .parent         = &clk_hsadc_pll_div,
2257         .set_rate       = clk_hsadc_set_rate,
2258         .clksel_con     = CRU_CLKSELS_CON(22),
2259         CRU_SRC_SET(0x3, 4),
2260         CRU_PARENTS_SET(clk_hsadc_out_parents),
2261 };
2262 static struct clk clk_hsadc_out_inv = {
2263         .name           = "hsadc_out_inv",
2264         .parent         = &clk_hsadc_out,
2265 };
2266
2267 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2268 static struct clk clk_hsadc = {
2269         .name           = "hsadc",
2270         .parent         = &clk_hsadc_out,
2271         .clksel_con     = CRU_CLKSELS_CON(22),
2272         CRU_SRC_SET(0x1, 7),
2273         CRU_PARENTS_SET(clk_hsadc_parents),
2274 };
2275
2276 static struct clk clk_saradc = {
2277         .name           = "saradc",
2278         .parent         = &xin24m,
2279         .mode           = gate_mode,
2280         .recalc         = clksel_recalc_div,
2281         .set_rate       = clksel_set_rate_freediv,
2282         .gate_idx       = CLK_GATE_SARADC_SRC,
2283         .clksel_con     = CRU_CLKSELS_CON(24),
2284         CRU_DIV_SET(0xff, 8, 256),
2285 };
2286
2287 /* smc setting */
2288 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2289 static struct clk clkn_smc = {
2290         .name           = "smc_inv",
2291         .parent         = &clk_smc,
2292 };
2293
2294 /* spi setting */
2295 static struct clk clk_spi0 = {
2296         .name           = "spi0",
2297         .parent         = &pclk_periph,
2298         .mode           = gate_mode,
2299         .recalc         = clksel_recalc_div,
2300         .set_rate       = clksel_set_rate_freediv,
2301         .gate_idx       = CLK_GATE_SPI0_SRC,
2302         .clksel_con     = CRU_CLKSELS_CON(25),
2303         CRU_DIV_SET(0x7f, 0, 128),
2304 };
2305
2306 static struct clk clk_spi1 = {
2307         .name           = "spi1",
2308         .parent         = &pclk_periph,
2309         .mode           = gate_mode,
2310         .recalc         = clksel_recalc_div,
2311         .set_rate       = clksel_set_rate_freediv,
2312         .gate_idx       = CLK_GATE_SPI1_SRC,
2313         .clksel_con     = CRU_CLKSELS_CON(25),
2314         CRU_DIV_SET(0x7f, 8, 128),
2315 };
2316
2317 /* sdmmc/sdio/emmc setting */
2318 static struct clk clk_sdmmc = {
2319         .name           = "sdmmc",
2320         .parent         = &hclk_periph,
2321         .mode           = gate_mode,
2322         .recalc         = clksel_recalc_div,
2323         .set_rate       = clksel_set_rate_even,
2324         .gate_idx       = CLK_GATE_MMC0_SRC,
2325         .clksel_con     = CRU_CLKSELS_CON(11),
2326         CRU_DIV_SET(0x3f, 0, 64),
2327 };
2328
2329 static struct clk clk_sdio = {
2330         .name           = "sdio",
2331         .parent         = &hclk_periph,
2332         .mode           = gate_mode,
2333         .recalc         = clksel_recalc_div,
2334         .set_rate       = clksel_set_rate_even,
2335         .gate_idx       = CLK_GATE_SDIO_SRC,
2336         .clksel_con     = CRU_CLKSELS_CON(12),
2337         CRU_DIV_SET(0x3f, 0, 64),
2338
2339 };
2340
2341 static struct clk clk_emmc = {
2342         .name           = "emmc",
2343         .parent         = &hclk_periph,
2344         .mode           = gate_mode,
2345         .recalc         = clksel_recalc_div,
2346         .set_rate       = clksel_set_rate_even,
2347         .gate_idx       = CLK_GATE_EMMC_SRC,
2348         .clksel_con     = CRU_CLKSELS_CON(12),
2349         CRU_DIV_SET(0x3f, 8, 64),
2350 };
2351
2352 /* uart setting */
2353 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2354 static struct clk clk_uart_pll = {
2355         .name           = "uart_pll",
2356         .parent         = &general_pll_clk,
2357         .clksel_con     = CRU_CLKSELS_CON(12),
2358         CRU_SRC_SET(0x1, 15),
2359         CRU_PARENTS_SET(clk_uart_src_parents),
2360 };
2361 static struct clk clk_uart0_div = {
2362         .name           = "uart0_div",
2363         .parent         = &clk_uart_pll,
2364         .mode           = gate_mode,
2365         .gate_idx       = CLK_GATE_UART0_SRC,
2366         .recalc         = clksel_recalc_div,
2367         .set_rate       = clksel_set_rate_freediv,
2368         .round_rate     = clksel_freediv_round_rate,
2369         .clksel_con     = CRU_CLKSELS_CON(13),
2370         CRU_DIV_SET(0x7f, 0, 64),
2371 };
2372 static struct clk clk_uart1_div = {
2373         .name           = "uart1_div",
2374         .parent         = &clk_uart_pll,
2375         .mode           = gate_mode,
2376         .gate_idx       = CLK_GATE_UART1_SRC,
2377         .recalc         = clksel_recalc_div,
2378         .round_rate     = clksel_freediv_round_rate,
2379         .set_rate       = clksel_set_rate_freediv,
2380         .clksel_con     = CRU_CLKSELS_CON(14),
2381         CRU_DIV_SET(0x7f, 0, 64),
2382 };
2383
2384 static struct clk clk_uart2_div = {
2385         .name           = "uart2_div",
2386         .parent         = &clk_uart_pll,
2387         .mode           = gate_mode,
2388         .gate_idx       = CLK_GATE_UART2_SRC,
2389         .recalc         = clksel_recalc_div,
2390         .round_rate     = clksel_freediv_round_rate,
2391         .set_rate       = clksel_set_rate_freediv,
2392         .clksel_con     = CRU_CLKSELS_CON(15),
2393         CRU_DIV_SET(0x7f, 0, 64),
2394 };
2395
2396 static struct clk clk_uart3_div = {
2397         .name           = "uart3_div",
2398         .parent         = &clk_uart_pll,
2399         .mode           = gate_mode,
2400         .gate_idx       = CLK_GATE_UART3_SRC,
2401         .recalc         = clksel_recalc_div,
2402         .round_rate     = clksel_freediv_round_rate,
2403         .set_rate       = clksel_set_rate_freediv,
2404         .clksel_con     = CRU_CLKSELS_CON(16),
2405         CRU_DIV_SET(0x7f, 0, 64),
2406 };
2407 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2408 {
2409         u32 numerator, denominator;
2410         //clk_uart0_div->clk_uart_pll->gpll/cpll
2411         //clk->parent->parent
2412         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2413                                 &numerator, &denominator) == 0) {
2414                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2415
2416                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2417
2418                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2419         } else {
2420                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2421                 return -ENOENT;
2422         }
2423         return 0;
2424 }
2425
2426 static struct clk clk_uart0_frac_div = {
2427         .name           = "uart0_frac_div",
2428         .parent         = &clk_uart0_div,
2429         .mode           = gate_mode,
2430         .recalc         = clksel_recalc_frac,
2431         .set_rate       = clk_uart_fracdiv_set_rate,
2432         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2433         .clksel_con     = CRU_CLKSELS_CON(17),
2434 };
2435 static struct clk clk_uart1_frac_div = {
2436         .name           = "uart1_frac_div",
2437         .parent         = &clk_uart1_div,
2438         .mode           = gate_mode,
2439         .recalc         = clksel_recalc_frac,
2440         .set_rate       = clk_uart_fracdiv_set_rate,
2441         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2442         .clksel_con     = CRU_CLKSELS_CON(18),
2443 };
2444 static struct clk clk_uart2_frac_div = {
2445         .name           = "uart2_frac_div",
2446         .mode           = gate_mode,
2447         .parent         = &clk_uart2_div,
2448         .recalc         = clksel_recalc_frac,
2449         .set_rate       = clk_uart_fracdiv_set_rate,
2450         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2451         .clksel_con     = CRU_CLKSELS_CON(19),
2452 };
2453 static struct clk clk_uart3_frac_div = {
2454         .name           = "uart3_frac_div",
2455         .parent         = &clk_uart3_div,
2456         .mode           = gate_mode,
2457         .recalc         = clksel_recalc_frac,
2458         .set_rate       = clk_uart_fracdiv_set_rate,
2459         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2460         .clksel_con     = CRU_CLKSELS_CON(20),
2461 };
2462
2463 #define UART_SRC_DIV 0
2464 #define UART_SRC_FRAC 1
2465 #define UART_SRC_24M 2
2466
2467 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2468 {
2469         int ret = 0;
2470         struct clk *parent;
2471
2472         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2473                 parent = clk->parents[UART_SRC_24M];
2474         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2475                 parent = clk->parents[UART_SRC_DIV];
2476         } else {
2477                 parent = clk->parents[UART_SRC_FRAC];
2478         }
2479
2480         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2481                         clk->name, rate, parent->name, clk->parent->name);
2482
2483         if(parent != clk->parents[UART_SRC_24M]) {
2484                 ret = clk_set_rate_nolock(parent, rate);
2485                 if (ret) {
2486                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2487                         return ret;
2488                 }
2489         }
2490
2491         if (clk->parent != parent) {
2492                 ret = clk_set_parent_nolock(clk, parent);
2493                 if (ret) {
2494                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2495                         return ret;
2496                 }
2497         }
2498
2499         return ret;
2500 }
2501
2502 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2503 static struct clk clk_uart0 = {
2504         .name           = "uart0",
2505         .set_rate       = clk_uart_set_rate,
2506         .clksel_con     = CRU_CLKSELS_CON(13),
2507         CRU_SRC_SET(0x3, 8),
2508         CRU_PARENTS_SET(clk_uart0_parents),
2509 };
2510
2511 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2512 static struct clk clk_uart1 = {
2513         .name           = "uart1",
2514         .set_rate       = clk_uart_set_rate,
2515         .clksel_con     = CRU_CLKSELS_CON(14),
2516         CRU_SRC_SET(0x3, 8),
2517         CRU_PARENTS_SET(clk_uart1_parents),
2518 };
2519
2520 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2521 static struct clk clk_uart2 = {
2522         .name           = "uart2",
2523         .set_rate       = clk_uart_set_rate,
2524         .clksel_con     = CRU_CLKSELS_CON(15),
2525         CRU_SRC_SET(0x3, 8),
2526         CRU_PARENTS_SET(clk_uart2_parents),
2527 };
2528 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2529 static struct clk clk_uart3 = {
2530         .name           = "uart3",
2531         .set_rate       = clk_uart_set_rate,
2532         .clksel_con     = CRU_CLKSELS_CON(16),
2533         CRU_SRC_SET(0x3, 8),
2534         CRU_PARENTS_SET(clk_uart3_parents),
2535 };
2536
2537 /* timer setting */
2538 GATE_CLK(timer0, xin24m, TIMER0);
2539 GATE_CLK(timer1, xin24m, TIMER1);
2540 GATE_CLK(timer2, xin24m, TIMER2);
2541 GATE_CLK(timer3, xin24m, TIMER3);
2542 GATE_CLK(timer4, xin24m, TIMER4);
2543 GATE_CLK(timer5, xin24m, TIMER5);
2544 GATE_CLK(timer6, xin24m, TIMER6);
2545
2546 /*********************power domain*******************************/
2547 #if 1
2548 #ifdef RK30_CLK_OFFBOARD_TEST
2549 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2550 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2551 #else
2552 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2553 #define _pmu_set_power_domain pmu_set_power_domain
2554 #endif
2555
2556 static int pd_video_mode(struct clk *clk, int on)
2557 {
2558         u32 gate[3];
2559         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2560         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2561         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2562         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2563         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2564         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2565         pmu_set_power_domain(PD_VIDEO, on);
2566         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2567         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2568         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2569         return 0;
2570 }
2571
2572 static struct clk pd_video = {
2573         .name   = "pd_video",
2574         .flags  = IS_PD,
2575         .mode   = pd_video_mode,
2576         .gate_idx       = PD_VIDEO,
2577 };
2578 static int pd_display_mode(struct clk *clk, int on)
2579 {
2580         u32 gate[10];
2581         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2582         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2583         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2584         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2585         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2586         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2587         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2588         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2589         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2590         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2591         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2592         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2593         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2594         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2595         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2596         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2597         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2598         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2599         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2600         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2601         pmu_set_power_domain(PD_VIO, on);
2602         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2603         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2604         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2605         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2606         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2607         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2608         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2609         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2610         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2611         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2612         return 0;
2613 }
2614
2615 static struct clk pd_display = {
2616         .name   = "pd_vio",
2617         .flags  = IS_PD,
2618         .mode   = pd_display_mode,
2619         .gate_idx       = PD_VIO,
2620 };
2621 static struct clk pd_lcdc0 = {
2622         .parent = &pd_display,
2623         .name   = "pd_lcdc0",
2624 };
2625 static struct clk pd_lcdc1 = {
2626         .parent = &pd_display,
2627         .name   = "pd_lcdc1",
2628 };
2629 static struct clk pd_cif0 = {
2630         .parent = &pd_display,
2631         .name   = "pd_cif0",
2632 };
2633 static struct clk pd_rga = {
2634         .parent = &pd_display,
2635         .name   = "pd_rga",
2636 };
2637 static struct clk pd_ipp = {
2638         .parent = &pd_display,
2639         .name   = "pd_ipp",
2640 };
2641 static struct clk pd_hdmi = {
2642         .parent = &pd_display,
2643         .name   = "pd_hdmi",
2644 };
2645
2646
2647 static int pd_gpu_mode(struct clk *clk, int on)
2648 {
2649         u32 gate[3];
2650         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2651         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2652         pmu_set_power_domain(PD_GPU, on);
2653         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2654         return 0;
2655 }
2656
2657 static struct clk pd_gpu = {
2658         .name   = "pd_gpu",
2659         .flags  = IS_PD,
2660         .mode   = pd_gpu_mode,
2661         .gate_idx       = PD_GPU,
2662 };
2663
2664 static int pm_off_mode(struct clk *clk, int on)
2665 {
2666         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2667         return 0;
2668 }
2669 static struct clk pd_peri = {
2670         .name   = "pd_peri",
2671         .flags  = IS_PD,
2672         .mode   = pm_off_mode,
2673         .gate_idx       = PD_PERI,
2674 };
2675
2676
2677 #define PD_CLK(name) \
2678 {\
2679         .dev_id = NULL,\
2680         .con_id = #name,\
2681         .clk = &name,\
2682 }
2683
2684 #endif
2685 /************************rk30 fixed div clock****************************************/
2686
2687 /*************************aclk_cpu***********************/
2688
2689 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2690 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2691 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2692
2693 /*************************hclk_cpu***********************/
2694
2695 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2696 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2697 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2698 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2699 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2700 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2701 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2702 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2703 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2704 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2705 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2706 GATE_CLK(hclk_imem0,    hclk_cpu,       HCLK_IMEM0);
2707 GATE_CLK(hclk_imem1,    hclk_cpu,       HCLK_IMEM1);
2708
2709 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2710 GATE_CLK(pclk_uart0,    ahb2apb_cpu, PCLK_UART0);
2711 GATE_CLK(pclk_uart1,    ahb2apb_cpu, PCLK_UART1);
2712 /*************************pclk_cpu***********************/
2713 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2714 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2715 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2716 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2717 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2718 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2719 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2720 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2721 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2722 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2723 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2724 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2725 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2726 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2727 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2728
2729 /*************************aclk_periph***********************/
2730
2731 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2732 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2733 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2734 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2735 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2736 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2737
2738 /*************************hclk_periph***********************/
2739 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2740 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2741 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2742 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2743 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2744 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2745 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2746 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2747 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2748 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2749 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2750 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2751 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2752 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2753 /*************************pclk_periph***********************/
2754 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2755 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2756 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2757 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2758 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2759 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2760 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2761 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2762 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2763 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2764 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2765 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2766 /*************************aclk_lcdc0***********************/
2767
2768 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2769 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2770 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2771 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2772
2773 /*************************aclk_lcdc0***********************/
2774
2775 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2776 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2777 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2778
2779
2780 #if 1
2781 #define CLK(dev, con, ck) \
2782 {\
2783         .dev_id = dev,\
2784         .con_id = con,\
2785         .clk = ck,\
2786 }
2787
2788
2789 #define CLK1(name) \
2790 {\
2791         .dev_id = NULL,\
2792         .con_id = #name,\
2793         .clk = &clk_##name,\
2794 }
2795
2796 #endif
2797
2798 static struct clk_lookup clks[] = {
2799         CLK(NULL, "xin24m", &xin24m),
2800         //CLK(NULL, "xin27m", &xin27m),
2801         CLK(NULL, "xin12m", &clk_12m),
2802         CLK(NULL, "arm_pll", &arm_pll_clk),
2803         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2804         CLK(NULL, "codec_pll", &codec_pll_clk),
2805         CLK(NULL, "general_pll", &general_pll_clk),
2806
2807         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2808         CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2809
2810         CLK(NULL, "ddr", &clk_ddr),
2811         CLK(NULL, "cpu", &clk_core),
2812         CLK1(l2c),
2813         CLK1(core_dbg),
2814         CLK("smp_twd", NULL, &core_periph),
2815         CLK(NULL, "aclk_core", &aclk_core),
2816
2817         CLK(NULL, "logic", &clk_cpu_div),
2818         CLK(NULL, "aclk_cpu", &aclk_cpu),
2819         CLK(NULL, "pclk_cpu", &pclk_cpu),
2820         CLK(NULL, "atclk_cpu", &atclk_cpu),
2821         CLK(NULL, "hclk_cpu", &hclk_cpu),
2822         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2823
2824         CLK(NULL, "gpu",        &aclk_gpu),
2825
2826         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2827         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2828         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2829         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2830
2831         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2832         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2833
2834         CLK(NULL, "aclk_periph", &aclk_periph),
2835         CLK(NULL, "pclk_periph", &pclk_periph),
2836         CLK(NULL, "hclk_periph", &hclk_periph),
2837
2838         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2839         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2840
2841         CLK(NULL, "cif_out_pll", &cif_out_pll),
2842         CLK(NULL, "cif0_out_div", &cif0_out_div),
2843         CLK(NULL, "cif0_out", &cif0_out),
2844
2845         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2846         CLK(NULL, "inv_cif0", &inv_cif0),
2847         CLK(NULL, "cif0_in", &cif0_in),
2848
2849         CLK1(i2s_pll),
2850         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2851         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2852         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2853
2854         // actually no i2s1
2855         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2856         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2857         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2858
2859
2860         CLK1(spdif_div),
2861         CLK1(spdif_frac_div),
2862         CLK1(spdif),
2863
2864         CLK1(otgphy0),
2865         CLK1(otgphy1),
2866         CLK1(otgphy0_480m),
2867         CLK1(otgphy1_480m),
2868         CLK1(hsicphy_480m),
2869         CLK1(hsicphy_12m),
2870
2871         CLK(NULL, "rmii_clkin", &rmii_clkin),
2872         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2873         CLK1(mac_ref),
2874         CLK1(mii_tx),
2875
2876         CLK1(hsadc_pll_div),
2877         CLK1(hsadc_frac_div),
2878         CLK1(hsadc_ext),
2879         CLK1(hsadc_out),
2880         CLK1(hsadc_out_inv),
2881         CLK1(hsadc),
2882
2883         CLK1(saradc),
2884
2885         CLK1(smc),
2886         CLK(NULL, "smc_inv",    &clkn_smc),
2887
2888         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2889         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2890
2891         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2892         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2893         CLK1(emmc),
2894
2895         CLK1(uart_pll),
2896         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2897         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2898         CLK("rk_serial.0", "uart", &clk_uart0),
2899         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2900         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2901         CLK("rk_serial.1", "uart", &clk_uart1),
2902         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2903         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2904         CLK("rk_serial.2", "uart", &clk_uart2),
2905         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2906         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2907         CLK("rk_serial.3", "uart", &clk_uart3),
2908
2909         CLK1(timer0),
2910         CLK1(timer1),
2911         CLK1(timer2),
2912         CLK1(timer3),
2913         CLK1(timer4),
2914         CLK1(timer5),
2915         CLK1(timer6),
2916
2917         /*************************aclk_cpu***********************/
2918         CLK1(dma1),
2919         CLK1(intmem),
2920         CLK1(aclk_strc_sys),
2921
2922         /*************************hclk_cpu***********************/
2923         CLK1(rom),
2924         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2925         // actually no i2s1
2926         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2927         CLK1(hclk_spdif),
2928         CLK1(hclk_cpubus),
2929         CLK1(hclk_ahb2apb),
2930         CLK1(hclk_vio_bus),
2931         CLK1(hclk_lcdc0),
2932         CLK1(hclk_lcdc1),
2933         CLK1(hclk_cif0),
2934         CLK1(hclk_ipp),
2935         CLK1(hclk_rga),
2936         CLK1(hclk_imem0),
2937         CLK1(hclk_imem1),
2938
2939         /*************************pclk_cpu***********************/
2940         CLK1(pwm01),
2941         CLK1(pclk_timer0),
2942         CLK1(pclk_timer2),
2943         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2944         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2945         CLK1(gpio0),
2946         CLK1(gpio1),
2947         CLK1(gpio2),
2948         CLK1(efuse),
2949         CLK1(tzpc),
2950         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2951         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2952         CLK1(pclk_ddrupctl),
2953         CLK1(pclk_ddrpubl),
2954         CLK1(dbg),
2955         CLK1(grf),
2956         CLK1(pmu),
2957
2958         /*************************aclk_periph***********************/
2959         CLK1(dma2),
2960         CLK1(aclk_smc),
2961         CLK1(aclk_gps),
2962         CLK1(aclk_peri_niu),
2963         CLK1(aclk_cpu_peri),
2964         CLK1(aclk_peri_axi_matrix),
2965
2966         /*************************hclk_periph***********************/
2967         CLK1(hclk_peri_axi_matrix),
2968         CLK1(hclk_peri_ahb_arbi),
2969         CLK1(hclk_emem_peri),
2970         CLK1(hclk_mac),
2971         CLK1(nandc),
2972         CLK1(hclk_usb_peri),
2973         CLK1(hclk_otg0),
2974         CLK1(hclk_otg1),
2975         CLK1(hclk_hsic),
2976         CLK1(hclk_hsadc),
2977         CLK1(hclk_pidfilter),
2978         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2979         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2980         CLK1(hclk_emmc),
2981
2982         /*************************pclk_periph***********************/
2983         CLK1(pclk_peri_axi_matrix),
2984         CLK1(pwm23),
2985         CLK1(wdt),
2986         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2987         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2988         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2989         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2990         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2991         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2992         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2993         CLK1(gpio3),
2994         CLK1(pclk_saradc),
2995
2996         /*************************aclk_lcdc0***********************/
2997         CLK1(aclk_vio0),
2998         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2999         CLK1(aclk_cif0),
3000         CLK1(aclk_ipp),
3001
3002         /*************************aclk_lcdc1***********************/
3003         CLK1(aclk_vio1),
3004         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
3005         CLK1(aclk_rga),
3006         /************************power domain**********************/
3007
3008         PD_CLK(pd_peri),
3009         PD_CLK(pd_display),
3010         PD_CLK(pd_lcdc0),
3011         PD_CLK(pd_lcdc1),
3012         PD_CLK(pd_cif0),
3013         //PD_CLK(pd_cif1),
3014         PD_CLK(pd_rga),
3015         PD_CLK(pd_ipp),
3016         //PD_CLK(pd_video),
3017         PD_CLK(pd_gpu),
3018         //PD_CLK(pd_dbg),
3019 };
3020 static void __init rk30_init_enable_clocks(void)
3021 {
3022         #if 0
3023         //clk_enable_nolock(&xin24m);
3024         //clk_enable_nolock(&clk_12m);
3025         //clk_enable_nolock(&arm_pll_clk);
3026         //clk_enable_nolock(&ddr_pll_clk);
3027         //clk_enable_nolock(&codec_pll_clk);
3028         //clk_enable_nolock(&general_pll_clk);
3029         #endif
3030         clk_enable_nolock(&clk_ddr);
3031         //clk_enable_nolock(&clk_core);
3032         clk_enable_nolock(&clk_cpu_div);
3033         clk_enable_nolock(&clk_core_gpll_path);
3034         clk_enable_nolock(&clk_ddr_gpll_path);
3035         clk_enable_nolock(&clk_l2c);
3036         clk_enable_nolock(&clk_core_dbg);
3037         clk_enable_nolock(&core_periph);
3038         clk_enable_nolock(&aclk_core);
3039         //clk_enable_nolock(&aclk_cpu);
3040         //clk_enable_nolock(&pclk_cpu);
3041         clk_enable_nolock(&atclk_cpu);
3042         //clk_enable_nolock(&hclk_cpu);
3043         clk_enable_nolock(&ahb2apb_cpu);
3044         if (flag_uboot_display) {
3045                 clk_enable_nolock(&dclk_lcdc0);
3046                 clk_enable_nolock(&dclk_lcdc1);
3047                 clk_enable_nolock(&clk_hclk_lcdc0);
3048                 clk_enable_nolock(&clk_hclk_lcdc1);
3049                 clk_enable_nolock(&clk_aclk_lcdc0);
3050                 clk_enable_nolock(&clk_aclk_lcdc1);
3051                 clk_enable_nolock(&aclk_lcdc0_pre);
3052                 clk_enable_nolock(&aclk_lcdc1_pre);
3053                 clk_enable_nolock(&pd_lcdc0);
3054                 clk_enable_nolock(&pd_lcdc1);
3055         }
3056         #if 0
3057          clk_enable_nolock(&clk_gpu);
3058          clk_enable_nolock(&aclk_gpu);
3059          clk_enable_nolock(&aclk_gpu_slv);
3060          clk_enable_nolock(&aclk_gpu_mst);
3061
3062          clk_enable_nolock(&aclk_vepu);
3063          clk_enable_nolock(&hclk_vepu);
3064          clk_enable_nolock(&aclk_vdpu);
3065          clk_enable_nolock(&hclk_vdpu);
3066
3067
3068          clk_enable_nolock(&aclk_periph);
3069         clk_enable_nolock(&pclk_periph);
3070         clk_enable_nolock(&hclk_periph);
3071         #endif
3072         #if 0
3073          clk_enable_nolock(&cif_out_pll);
3074          clk_enable_nolock(&cif0_out_div);
3075
3076          clk_enable_nolock(&cif0_out);
3077          clk_enable_nolock(&pclkin_cif0);
3078          clk_enable_nolock(&inv_cif0);
3079          clk_enable_nolock(&cif0_in);
3080
3081          clk_enable_nolock(&clk_i2s_pll);
3082          clk_enable_nolock(&clk_i2s0_div);
3083          clk_enable_nolock(&clk_i2s0_frac_div);
3084          clk_enable_nolock(&clk_i2s0);
3085
3086           actually no i2s1
3087          clk_enable_nolock(&clk_i2s0_div);
3088          clk_enable_nolock(&clk_i2s0_frac_div);
3089          clk_enable_nolock(&clk_i2s0);
3090
3091         clk_enable_nolock(&clk_spdif_div);
3092         clk_enable_nolock(&clk_spdif_frac_div);
3093         clk_enable_nolock(&clk_spdif);
3094         #endif
3095         #if 0
3096         clk_enable_nolock(&clk_otgphy0);
3097         clk_enable_nolock(&clk_otgphy1);
3098         clk_enable_nolock(&clk_otgphy0_480m);
3099         clk_enable_nolock(&clk_otgphy1_480m);
3100         clk_enable_nolock(&clk_hsicphy_480m);
3101         clk_enable_nolock(&clk_hsicphy_12m);
3102         #endif
3103
3104         #if 0
3105         clk_enable_nolock(&rmii_clkin);
3106         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
3107         clk_enable_nolock(&clk_mac_ref);
3108         clk_enable_nolock(&clk_mii_tx);
3109         #endif
3110
3111         #if 0
3112         clk_enable_nolock(&clk_hsadc_pll_div);
3113         clk_enable_nolock(&clk_hsadc_frac_div);
3114         clk_enable_nolock(&clk_hsadc_ext);
3115         clk_enable_nolock(&clk_hsadc_out);
3116         clk_enable_nolock(&clk_hsadc_out_inv);
3117         clk_enable_nolock(&clk_hsadc);
3118
3119         clk_enable_nolock(&clk_saradc);
3120         #endif
3121         /*
3122         clk_enable_nolock(&clk_smc);
3123         clk_enable_nolock(&clkn_smc);
3124         */
3125         /*
3126         clk_enable_nolock(&clk_spi0);
3127         clk_enable_nolock(&clk_spi1);
3128         */
3129         /*
3130         clk_enable_nolock(&clk_sdmmc);
3131         clk_enable_nolock(&clk_sdio);
3132         clk_enable_nolock(&clk_emmc);
3133         */
3134         #if 0
3135         clk_enable_nolock(&clk_uart_pll);
3136         clk_enable_nolock(&clk_uart0_div);
3137         clk_enable_nolock(&clk_uart0_frac_div);
3138         clk_enable_nolock(&clk_uart0);
3139         clk_enable_nolock(&clk_uart1_div);
3140         clk_enable_nolock(&clk_uart1_frac_div);
3141         clk_enable_nolock(&clk_uart1);
3142         clk_enable_nolock(&clk_uart2_div);
3143         clk_enable_nolock(&clk_uart2_frac_div);
3144         clk_enable_nolock(&clk_uart2);
3145         clk_enable_nolock(&clk_uart3_div);
3146         clk_enable_nolock(&clk_uart3_frac_div);
3147         clk_enable_nolock(&clk_uart3);
3148         #endif
3149         #if CONFIG_RK_DEBUG_UART == 0
3150                 clk_enable_nolock(&clk_uart0);
3151                 clk_enable_nolock(&clk_pclk_uart0);
3152         #elif CONFIG_RK_DEBUG_UART == 1
3153                 clk_enable_nolock(&clk_uart1);
3154                 clk_enable_nolock(&clk_pclk_uart1);
3155
3156         #elif CONFIG_RK_DEBUG_UART == 2
3157                 clk_enable_nolock(&clk_uart2);
3158                 clk_enable_nolock(&clk_pclk_uart2);
3159
3160         #elif CONFIG_RK_DEBUG_UART == 3
3161                 clk_enable_nolock(&clk_uart3);
3162                 clk_enable_nolock(&clk_pclk_uart3);
3163
3164         #endif
3165         #if 0
3166         clk_enable_nolock(&clk_timer0);
3167         clk_enable_nolock(&clk_timer1);
3168         clk_enable_nolock(&clk_timer2);
3169         #endif
3170
3171         /*************************aclk_cpu***********************/
3172         clk_enable_nolock(&clk_dma1);
3173         clk_enable_nolock(&clk_intmem);
3174         clk_enable_nolock(&clk_aclk_strc_sys);
3175
3176         /*************************hclk_cpu***********************/
3177         clk_enable_nolock(&clk_rom);
3178         #if 0
3179         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3180         // actually no i2s1
3181         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3182         clk_enable_nolock(&clk_hclk_spdif);
3183         #endif
3184         clk_enable_nolock(&clk_hclk_cpubus);
3185         clk_enable_nolock(&clk_hclk_ahb2apb);
3186         clk_enable_nolock(&clk_hclk_vio_bus);
3187         #if 0
3188         clk_enable_nolock(&clk_hclk_cif0);
3189         clk_enable_nolock(&clk_hclk_ipp);
3190         clk_enable_nolock(&clk_hclk_rga);
3191         #endif
3192         clk_enable_nolock(&clk_hclk_imem0);
3193         clk_enable_nolock(&clk_hclk_imem1);
3194
3195         /*************************pclk_cpu***********************/
3196         #if 0
3197         clk_enable_nolock(&clk_pwm01);
3198         clk_enable_nolock(&clk_pclk_timer0);
3199         clk_enable_nolock(&clk_pclk_timer1);
3200         clk_enable_nolock(&clk_pclk_timer2);
3201         clk_enable_nolock(&clk_i2c0);
3202         clk_enable_nolock(&clk_i2c1);
3203         clk_enable_nolock(&clk_gpio0);
3204         clk_enable_nolock(&clk_gpio1);
3205         clk_enable_nolock(&clk_gpio2);
3206         clk_enable_nolock(&clk_efuse);
3207         #endif
3208         clk_enable_nolock(&clk_tzpc);
3209         //clk_enable_nolock(&clk_pclk_uart0);
3210         //clk_enable_nolock(&clk_pclk_uart1);
3211         clk_enable_nolock(&clk_pclk_ddrupctl);
3212         clk_enable_nolock(&clk_pclk_ddrpubl);
3213         clk_enable_nolock(&clk_dbg);
3214         clk_enable_nolock(&clk_grf);
3215         clk_enable_nolock(&clk_pmu);
3216
3217         /*************************aclk_periph***********************/
3218         clk_enable_nolock(&clk_dma2);
3219         clk_enable_nolock(&clk_aclk_smc);
3220         clk_enable_nolock(&clk_aclk_peri_niu);
3221         clk_enable_nolock(&clk_aclk_cpu_peri);
3222         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3223
3224         /*************************hclk_periph***********************/
3225         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3226         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3227         clk_enable_nolock(&clk_hclk_emem_peri);
3228         //clk_enable_nolock(&clk_hclk_mac);
3229         clk_enable_nolock(&clk_nandc);
3230         clk_enable_nolock(&clk_hclk_usb_peri);
3231         #if 0
3232         clk_enable_nolock(&clk_hclk_otg0);
3233         clk_enable_nolock(&clk_hclk_otg1);
3234         clk_enable_nolock(&clk_hclk_hsic);
3235         clk_enable_nolock(&clk_hclk_gps);
3236         clk_enable_nolock(&clk_hclk_hsadc);
3237         clk_enable_nolock(&clk_hclk_pidfilter);
3238         clk_enable_nolock(&clk_hclk_sdmmc);
3239         clk_enable_nolock(&clk_hclk_sdio);
3240         clk_enable_nolock(&clk_hclk_emmc);
3241         #endif
3242
3243         /*************************pclk_periph***********************/
3244         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3245         #if 0
3246         clk_enable_nolock(&clk_pwm23);
3247         clk_enable_nolock(&clk_wdt);
3248         clk_enable_nolock(&clk_pclk_spi0);
3249         clk_enable_nolock(&clk_pclk_spi1);
3250         clk_enable_nolock(&clk_pclk_uart2);
3251         clk_enable_nolock(&clk_pclk_uart3);
3252         #endif
3253         #if 0
3254         clk_enable_nolock(&clk_i2c2);
3255         clk_enable_nolock(&clk_i2c3);
3256         clk_enable_nolock(&clk_i2c4);
3257         clk_enable_nolock(&clk_gpio3);
3258         clk_enable_nolock(&clk_pclk_saradc);
3259         #endif
3260         /*************************aclk_lcdc0***********************/
3261 #if 1
3262         //clk_enable_nolock(&clk_aclk_vio0);
3263         //clk_enable_nolock(&clk_aclk_cif0);
3264         //clk_enable_nolock(&clk_aclk_ipp);
3265 #endif
3266         /*************************aclk_lcdc1***********************/
3267 #if 1
3268         //clk_enable_nolock(&clk_aclk_vio1);
3269         //clk_enable_nolock(&clk_aclk_rga);
3270 #endif
3271         /************************power domain**********************/
3272
3273 }
3274 static void periph_clk_set_init(void)
3275 {
3276         unsigned long aclk_p, hclk_p, pclk_p;
3277         unsigned long ppll_rate = general_pll_clk.rate;
3278         //aclk 148.5
3279
3280         /* general pll */
3281         switch (ppll_rate) {
3282                 case 148500 * KHZ:
3283                         aclk_p = 148500 * KHZ;
3284                         hclk_p = aclk_p >> 1;
3285                         pclk_p = aclk_p >> 2;
3286                         break;
3287                 case 297 * MHZ:
3288                         aclk_p = ppll_rate >> 1;
3289                         hclk_p = aclk_p >> 0;
3290                         pclk_p = aclk_p >> 1;
3291                         break;
3292                 case 300 * MHZ:
3293                         aclk_p = ppll_rate >> 1;
3294                         hclk_p = aclk_p >> 0;
3295                         pclk_p = aclk_p >> 1;
3296                         break;
3297                 case 384 * MHZ:
3298                         aclk_p = ppll_rate >> 1;
3299                         hclk_p = aclk_p >> 1;
3300                         pclk_p = aclk_p >> 2;
3301                         break;
3302                 case 594 * MHZ:
3303                         aclk_p = ppll_rate >> 2;
3304                         hclk_p = aclk_p >> 0;
3305                         pclk_p = aclk_p >> 1;
3306                         break;
3307                 case 768 * MHZ:
3308                         aclk_p = ppll_rate >> 2;
3309                         hclk_p = aclk_p >> 1;
3310                         pclk_p = aclk_p >> 2;
3311                         break;
3312                 case 891 * MHZ:
3313                         aclk_p = ppll_rate / 6;
3314                         hclk_p = aclk_p >> 0;
3315                         pclk_p = aclk_p >> 1;
3316                         break;
3317                 case 1188 * MHZ:
3318                         aclk_p = ppll_rate >> 3;
3319                         hclk_p = aclk_p >> 0;
3320                         pclk_p = aclk_p >> 1;
3321                         break;
3322
3323                 default:
3324                         aclk_p = 150 * MHZ;
3325                         hclk_p = 150 * MHZ;
3326                         pclk_p = 75 * MHZ;
3327                         break;
3328         }
3329         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3330         clk_set_rate_nolock(&aclk_periph, aclk_p);
3331         clk_set_rate_nolock(&hclk_periph, hclk_p);
3332         clk_set_rate_nolock(&pclk_periph, pclk_p);
3333 }
3334
3335 static void cpu_axi_init(void)
3336 {
3337         unsigned long cpu_div_rate = 0, aclk_cpu_rate = 0, hclk_cpu_rate = 0,
3338                       pclk_cpu_rate = 0, ahb2apb_cpu_rate = 0;
3339         unsigned long gpll_rate = general_pll_clk.rate;
3340
3341         switch (gpll_rate) {
3342                 case 297 * MHZ:
3343                         cpu_div_rate = gpll_rate;
3344                         aclk_cpu_rate = cpu_div_rate >> 0;
3345                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3346                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3347                         break;
3348
3349                 case 384 * MHZ:
3350                         cpu_div_rate = gpll_rate >> 1;
3351                         aclk_cpu_rate = cpu_div_rate >> 0;
3352                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3353                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3354                         break;
3355
3356                 case 594 * MHZ:
3357                         cpu_div_rate = gpll_rate >> 1;
3358                         aclk_cpu_rate = cpu_div_rate >> 0;
3359                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3360                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3361                         break;
3362
3363                 case 768 * MHZ:
3364                         cpu_div_rate = gpll_rate >> 2;
3365                         aclk_cpu_rate = cpu_div_rate >> 0;
3366                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3367                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3368                         break;
3369
3370                 case 891 * MHZ:
3371                         cpu_div_rate = gpll_rate / 3;
3372                         aclk_cpu_rate = cpu_div_rate >> 0;
3373                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3374                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3375                         break;
3376
3377                 case 1188 * MHZ:
3378                         cpu_div_rate = gpll_rate >> 2;
3379                         aclk_cpu_rate = cpu_div_rate >> 0;
3380                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3381                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3382                         break;
3383
3384                 default:
3385                         aclk_cpu_rate = 150 * MHZ;
3386                         hclk_cpu_rate = 150 * MHZ;
3387                         pclk_cpu_rate = 75 * MHZ;
3388                         break;
3389         }
3390         ahb2apb_cpu_rate = pclk_cpu_rate;
3391
3392         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3393         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3394         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3395         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3396         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3397         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3398 }
3399
3400 void rk30_clock_common_i2s_init(void)
3401 {
3402         unsigned long i2s_rate;
3403         //20 times
3404         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3405                 i2s_rate = 49152000;
3406         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3407                 i2s_rate = 24576000;
3408         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3409                 i2s_rate = 22579000;
3410         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3411                 i2s_rate = 12288000;
3412         } else {
3413                 i2s_rate = 49152000;
3414         }
3415
3416         /*
3417          * Priority setting i2s under cpll to fix i2s frac div do not effect, let
3418          * axi_cpu's pll different with i2s's
3419          * */
3420         if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3421                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3422         } else if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3423                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3424         } else {
3425                 if(general_pll_clk.rate > codec_pll_clk.rate)
3426                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3427                 else
3428                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3429         }
3430 }
3431 void rk30_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
3432 {
3433         struct clk *p_clk;
3434         unsigned long rate;
3435         if(!(gpll_clk->rate%(48*MHZ)))
3436         {
3437                 p_clk=gpll_clk;
3438                 rate=48*MHZ;
3439         }
3440         else if(!(cpll_clk->rate%(48*MHZ)))
3441         {
3442                 p_clk=cpll_clk;
3443                 rate=48*MHZ;
3444         }
3445         else if(!(gpll_clk->rate%(49500*KHZ)))
3446         {
3447                 p_clk=gpll_clk;
3448                 rate=(49500*KHZ);
3449         }
3450         else if(!(cpll_clk->rate%(49500*KHZ)))
3451         {
3452                 p_clk=cpll_clk;
3453                 rate=(49500*KHZ);
3454         }
3455         else
3456         {
3457                 if(cpll_clk->rate>gpll_clk->rate)
3458                 {
3459                         p_clk=cpll_clk;
3460                 }
3461                 else
3462                 {
3463                         p_clk=gpll_clk;
3464                 }
3465                 rate=50*MHZ;
3466         }
3467         clk_set_parent_nolock(&clk_uart_pll, p_clk);
3468         clk_set_rate_nolock(&clk_uart0_div,rate);
3469         clk_set_rate_nolock(&clk_uart1_div,rate);
3470         clk_set_rate_nolock(&clk_uart2_div,rate);
3471         clk_set_rate_nolock(&clk_uart3_div,rate);
3472 }
3473
3474 static void inline clock_set_div(struct clk *clk,u32 div)
3475 {
3476         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3477 }
3478
3479 static void inline clock_set_max_div(struct clk *clk)
3480 {
3481         set_cru_bits_w_msk(clk->div_max - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3482 }
3483
3484 static void div_clk_for_pll_init(void)
3485 {
3486         clock_set_max_div(&clk_cpu_div);
3487         clock_set_max_div(&aclk_vdpu);
3488         clock_set_max_div(&aclk_vepu);
3489         clock_set_max_div(&aclk_gpu);
3490         if (!flag_uboot_display) {
3491                 clock_set_max_div(&aclk_lcdc0_pre);
3492                 clock_set_max_div(&aclk_lcdc1_pre);
3493                 clock_set_max_div(&dclk_lcdc0);
3494                 clock_set_max_div(&dclk_lcdc1);
3495         }
3496         clock_set_max_div(&aclk_periph);
3497         clock_set_max_div(&cif0_out_div);
3498         clock_set_max_div(&clk_i2s0_div);
3499         clock_set_max_div(&clk_spdif_div);
3500         clock_set_max_div(&clk_uart0_div);
3501         clock_set_max_div(&clk_uart1_div);
3502         clock_set_max_div(&clk_uart2_div);
3503         clock_set_max_div(&clk_uart3_div);
3504         clock_set_max_div(&clk_hsicphy_12m);
3505         clock_set_max_div(&clk_hsadc_pll_div);
3506         clock_set_max_div(&clk_saradc);
3507 }
3508
3509 static u8 pll_flag = 0;
3510
3511 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3512 {
3513         //general
3514         if (!flag_uboot_display)
3515                 clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3516         lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
3517
3518         //code pll
3519         if (!flag_uboot_display)
3520                 clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3521
3522         cpu_axi_init();
3523         clk_set_rate_nolock(&clk_core, 816 * MHZ);
3524         //periph clk
3525         periph_clk_set_init();
3526
3527         //i2s
3528         rk30_clock_common_i2s_init();
3529
3530         // spi
3531         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3532         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3533
3534         // uart
3535         rk30_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
3536
3537         //mac
3538         if(!(gpll_rate % (50 * MHZ))) {
3539                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3540
3541         } else if((!(ddr_pll_clk.rate % (50 * MHZ))) && (ddr_pll_clk.rate != 24 * MHZ) && ((pll_flag & 0x2) == 0)) {
3542                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3543
3544         } else {
3545                 CLKDATA_DBG("mac can't get 50mhz, set to gpll\n");
3546                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3547         }
3548
3549         //hsadc
3550         //auto pll sel
3551         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3552
3553         if (!flag_uboot_display) {
3554                 //lcdc0 lcd auto sel pll
3555                 clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3556                 clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3557
3558                 //axi lcdc auto sel
3559                 clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3560                 clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3561                 clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3562                 clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3563         }
3564         //cif
3565         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3566
3567         //axi vepu auto sel
3568         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3569         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3570
3571         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3572         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3573         //gpu auto sel
3574         clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
3575         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3576
3577         clk_set_rate_nolock(&clk_uart0, 48000000);
3578         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3579         clk_set_rate_nolock(&clk_sdio, 24750000);
3580 }
3581
3582 static struct clk def_ops_clk = {
3583         .get_parent = clksel_get_parent,
3584         .set_parent = clksel_set_parent,
3585 };
3586
3587 #ifdef CONFIG_PROC_FS
3588 struct clk_dump_ops dump_ops;
3589 #endif
3590 void rk_dump_clock_info(void);
3591 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3592 {
3593         struct clk_lookup *lk;
3594
3595         if (soc_is_rk3188plus()) {
3596                 arm_pll_clk.recalc = plus_plls_clk_recalc;
3597                 ddr_pll_clk.recalc = plus_plls_clk_recalc;
3598                 codec_pll_clk.recalc = plus_plls_clk_recalc;
3599                 general_pll_clk.recalc = plus_plls_clk_recalc;
3600
3601                 arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
3602                 codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
3603                 general_pll_clk.set_rate = plus_gpll_clk_set_rate;
3604         }
3605
3606         rk_efuse_init();
3607         pll_flag = rk_pll_flag();
3608         printk("CLKDATA_MSG: pll_flag = 0x%02x\n", pll_flag);
3609
3610         if (0 != pll_flag) {
3611                 CLKDATA_DBG("CPLL=%lu, GPLL=%lu;CPLL CAN NOT LOCK, SET CPLL BY PASS, USE GPLL REPLACE CPLL\n",
3612                                 cpll, gpll);
3613                 codec_pll_clk.mode = NULL;
3614                 cpll = 24 * MHZ;
3615                 gpll = 891 * MHZ;
3616         }
3617
3618         clk_register_dump_ops(&dump_ops);
3619         clk_register_default_ops_clk(&def_ops_clk);
3620         rk30_clock_flags = flags;
3621         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3622 #ifdef RK30_CLK_OFFBOARD_TEST
3623                 rk30_clkdev_add(lk);
3624 #else
3625                 clkdev_add(lk);
3626 #endif
3627                 clk_register(lk->clk);
3628         }
3629
3630         div_clk_for_pll_init();
3631         clk_recalculate_root_clocks_nolock();
3632
3633         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3634
3635         /*
3636          * Only enable those clocks we will need, let the drivers
3637          * enable other clocks as necessary
3638          */
3639
3640         rk30_init_enable_clocks();
3641 #if 0
3642         // print loader config
3643         CLKDATA_DBG("%s clks register dbg start\n", __func__);
3644         rk_dump_clock_info();
3645         rk30_clk_dump_regs();
3646
3647         CLKDATA_DBG("%s clks register dbg end\n", __func__);
3648 #endif
3649         /*
3650          * Disable any unused clocks left on by the bootloader
3651          */
3652         //clk_disable_unused();
3653         rk30_clock_common_init(gpll, cpll);
3654         preset_lpj = loops_per_jiffy;
3655
3656
3657         //gpio6_b7
3658         //regfile_writel(0xc0004000,0x10c);
3659         //cru_writel(0x07000000,CRU_MISC_CON);
3660
3661 }
3662 extern int rk3188_dvfs_init(void);
3663
3664 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3665 {
3666         CLKDATA_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
3667                         gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3668         _rk30_clock_data_init(gpll, cpll, flags);
3669         rk3188_dvfs_init();
3670 }
3671 #define STR_UBOOT_DISPLAY       "fastboot"
3672 static int __init bootloader_setup(char *str)
3673 {
3674         if (0 == strncmp(str, STR_UBOOT_DISPLAY, strlen(STR_UBOOT_DISPLAY))) {
3675                 printk("CLKDATA_MSG: get uboot display\n");
3676                 flag_uboot_display = 1;
3677         }
3678         return 0;
3679 }
3680 early_param("androidboot.bootloader", bootloader_setup);
3681
3682 int support_uboot_display(void)
3683 {
3684         return flag_uboot_display;
3685 }
3686 /*
3687  * You can override arm_clk rate with armclk= cmdline option.
3688  */
3689 static int __init armclk_setup(char *str)
3690 {
3691         get_option(&str, &armclk);
3692
3693         if (!armclk)
3694                 return 0;
3695         if (armclk < 10000)
3696                 armclk *= MHZ;
3697         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3698         return 0;
3699 }
3700 #ifndef RK30_CLK_OFFBOARD_TEST
3701 early_param("armclk", armclk_setup);
3702 #endif
3703
3704
3705 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3706 {
3707         struct clk *ck;
3708         int i;
3709         unsigned long rate = clk->rate;
3710         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3711         for (i = 0; i < deep; i++)
3712                 printk("    ");
3713
3714         printk("%-11s ", clk->name);
3715 #ifndef RK30_CLK_OFFBOARD_TEST
3716         if (clk->flags & IS_PD) {
3717                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3718         }
3719 #endif
3720         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3721                 int idx = clk->gate_idx;
3722                 u32 v;
3723                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3724                 printk("%s ", v ? "off" : "on ");
3725         }
3726
3727         if (clk->pll) {
3728                 u32 pll_mode;
3729                 u32 pll_id = clk->pll->id;
3730                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3731                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3732                         printk("slow   ");
3733                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3734                         printk("normal ");
3735                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3736                         printk("deep   ");
3737
3738                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3739                         printk("bypass ");
3740         } else if(clk == &clk_ddr) {
3741                 rate = clk->recalc(clk);
3742         }
3743
3744         if (rate >= MHZ) {
3745                 if (rate % MHZ)
3746                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3747                 else
3748                         printk("%ld MHz", rate / MHZ);
3749         } else if (rate >= KHZ) {
3750                 if (rate % KHZ)
3751                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3752                 else
3753                         printk("%ld KHz", rate / KHZ);
3754         } else {
3755                 printk("%ld Hz", rate);
3756         }
3757
3758         printk(" usecount = %d", clk->usecount);
3759
3760         if (clk->parent)
3761                 printk(" parent = %s", clk->parent->name);
3762
3763         printk("\n");
3764
3765         list_for_each_entry(ck, root_clocks, node) {
3766                 if (ck->parent == clk)
3767                         rk_dump_clock(ck, deep + 1, root_clocks);
3768         }
3769 }
3770
3771 #if 1
3772 struct list_head *get_rk_clocks_head(void);
3773
3774 void rk_dump_clock_info(void)
3775 {
3776         struct clk* clk;
3777         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3778                 if (!clk->parent)
3779                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3780         }
3781 }
3782 #endif
3783
3784 #ifdef CONFIG_PROC_FS
3785
3786 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3787 {
3788         struct clk *ck;
3789         int i;
3790         unsigned long rate = clk->rate;
3791         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3792         for (i = 0; i < deep; i++)
3793                 seq_printf(s, "    ");
3794
3795         seq_printf(s, "%-11s ", clk->name);
3796 #ifndef RK30_CLK_OFFBOARD_TEST
3797         if (clk->flags & IS_PD) {
3798                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3799         }
3800 #endif
3801         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3802                 int idx = clk->gate_idx;
3803                 u32 v;
3804                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3805                 seq_printf(s, "%s ", v ? "off" : "on ");
3806         }
3807
3808         if (clk->pll) {
3809                 u32 pll_mode;
3810                 u32 pll_id = clk->pll->id;
3811                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3812                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3813                         seq_printf(s, "slow   ");
3814                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3815                         seq_printf(s, "normal ");
3816                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3817                         seq_printf(s, "deep   ");
3818
3819                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3820                         seq_printf(s, "bypass ");
3821         } else if(clk == &clk_ddr) {
3822                 rate = clk->recalc(clk);
3823         }
3824
3825         if (rate >= MHZ) {
3826                 if (rate % MHZ)
3827                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3828                 else
3829                         seq_printf(s, "%ld MHz", rate / MHZ);
3830         } else if (rate >= KHZ) {
3831                 if (rate % KHZ)
3832                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3833                 else
3834                         seq_printf(s, "%ld KHz", rate / KHZ);
3835         } else {
3836                 seq_printf(s, "%ld Hz", rate);
3837         }
3838
3839         seq_printf(s, " usecount = %d", clk->usecount);
3840
3841         if (clk->parent)
3842                 seq_printf(s, " parent = %s", clk->parent->name);
3843
3844         if (clk->last_set_rate != 0)
3845                 seq_printf(s, " [set %lu Hz]", clk->last_set_rate);
3846
3847         seq_printf(s, "\n");
3848
3849         list_for_each_entry(ck, root_clocks, node) {
3850                 if (ck->parent == clk)
3851                         dump_clock(s, ck, deep + 1, root_clocks);
3852         }
3853 }
3854
3855 static void dump_regs(struct seq_file *s)
3856 {
3857         int i = 0;
3858         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3859         seq_printf(s, "\nPLLRegisters:\n");
3860         for(i = 0; i < END_PLL_ID; i++) {
3861                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3862                                 cru_readl(PLL_CONS(i, 0)),
3863                                 cru_readl(PLL_CONS(i, 1)),
3864                                 cru_readl(PLL_CONS(i, 2)),
3865                                 cru_readl(PLL_CONS(i, 3))
3866                           );
3867         }
3868         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3869
3870         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3871                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3872         }
3873         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3874                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3875         }
3876         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3877         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3878
3879         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3880                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3881         }
3882         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3883         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3884
3885 }
3886
3887 void rk30_clk_dump_regs(void)
3888 {
3889         int i = 0;
3890         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3891         printk("\nPLLRegisters:\n");
3892         for(i = 0; i < END_PLL_ID; i++) {
3893                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3894                                 cru_readl(PLL_CONS(i, 0)),
3895                                 cru_readl(PLL_CONS(i, 1)),
3896                                 cru_readl(PLL_CONS(i, 2)),
3897                                 cru_readl(PLL_CONS(i, 3))
3898                       );
3899         }
3900         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3901
3902         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3903                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3904         }
3905         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3906                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3907         }
3908         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3909         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3910
3911         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3912                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3913         }
3914         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3915         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3916
3917 }
3918
3919
3920 #ifdef CONFIG_PROC_FS
3921 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3922 struct clk_dump_ops dump_ops = {
3923         .dump_clk = dump_clock,
3924         .dump_regs = dump_regs,
3925 };
3926 #endif
3927
3928
3929 #endif /* CONFIG_PROC_FS */
3930
3931
3932
3933
3934 #ifdef RK30_CLK_OFFBOARD_TEST
3935 struct clk *test_get_parent(struct clk *clk) {
3936         return clk->parent;
3937 }
3938
3939 void i2s_test(void)
3940 {
3941         struct clk *i2s_clk = &clk_i2s0;
3942
3943         clk_enable_nolock(i2s_clk);
3944
3945         clk_set_rate_nolock(i2s_clk, 12288000);
3946         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3947         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3948         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3949         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3950         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3951
3952 }
3953
3954 void uart_test(void)
3955 {
3956         struct clk *uart_clk = &clk_uart0;
3957
3958         clk_enable_nolock(uart_clk);
3959
3960         clk_set_rate_nolock(uart_clk, 12288000);
3961         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3962         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3963         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3964         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3965         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3966
3967 }
3968 void hsadc_test(void)
3969 {
3970         struct clk *hsadc_clk = &clk_hsadc;
3971
3972         printk("******************hsadc_test**********************\n");
3973         clk_enable_nolock(hsadc_clk);
3974
3975         clk_set_rate_nolock(hsadc_clk, 12288000);
3976         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3977
3978
3979         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3980         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3981
3982         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3983
3984         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3985
3986         printk("******************hsadc out clock**********************\n");
3987
3988         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3989         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3990         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3991         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3992
3993
3994
3995 }
3996
3997 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3998 {
3999         //arm
4000         printk("*********arm_pll_clk***********\n");
4001         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
4002
4003         printk("*********set clk_core parent***********\n");
4004         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
4005         clk_set_rate_nolock(&clk_core, 504 * MHZ);
4006
4007         //general
4008         printk("*********general_pll_clk***********\n");
4009         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
4010
4011         //code pll
4012         printk("*********codec_pll_clk***********\n");
4013         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
4014
4015
4016         printk("*********periph_clk_set_init***********\n");
4017         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
4018         periph_clk_set_init();
4019
4020 #if 0 //
4021         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
4022 #else
4023         printk("*********clk i2s***********\n");
4024         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
4025         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
4026         i2s_test();
4027 #endif
4028         // spi
4029         clk_enable_nolock(&clk_spi0);
4030         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
4031         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
4032         //saradc
4033         clk_enable_nolock(&clk_saradc);
4034         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
4035         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
4036         //sdio
4037         clk_enable_nolock(&clk_sdio);
4038         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
4039         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
4040         // uart
4041         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
4042         uart_test();
4043         //mac
4044         printk("*********mac***********\n");
4045
4046         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
4047         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
4048
4049         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
4050         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
4051         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
4052
4053         printk("*********mac mii set***********\n");
4054         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
4055         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
4056         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
4057         //hsadc
4058         printk("*********hsadc 1***********\n");
4059         //auto pll
4060         hsadc_test();
4061         //lcdc
4062         clk_enable_nolock(&dclk_lcdc0);
4063
4064         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
4065         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
4066
4067         //cif
4068         clk_enable_nolock(&cif0_out);
4069
4070         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
4071         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
4072
4073         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
4074         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4075
4076         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
4077         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4078         //cif_in
4079         clk_enable_nolock(&cif0_in);
4080         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
4081         //axi lcdc
4082         clk_enable_nolock(&aclk_lcdc0);
4083         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
4084         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
4085         //axi vepu
4086         clk_enable_nolock(&aclk_vepu);
4087         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4088         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
4089
4090         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
4091         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
4092
4093         printk("test end\n");
4094
4095         /* arm pll
4096            clk_set_rate_nolock(&arm_pll_clk, armclk);
4097            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
4098            */
4099         //
4100         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
4101         //
4102         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4103         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
4104
4105 }
4106
4107
4108
4109
4110
4111 static LIST_HEAD(rk30_clocks);
4112 static DEFINE_MUTEX(rk30_clocks_mutex);
4113
4114 static inline int __rk30clk_get(struct clk *clk)
4115 {
4116         return 1;
4117 }
4118 void rk30_clkdev_add(struct clk_lookup *cl)
4119 {
4120         mutex_lock(&rk30_clocks_mutex);
4121         list_add_tail(&cl->node, &rk30_clocks);
4122         mutex_unlock(&rk30_clocks_mutex);
4123 }
4124 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
4125         struct clk_lookup *p, *cl = NULL;
4126         int match, best = 0;
4127
4128         list_for_each_entry(p, &rk30_clocks, node) {
4129                 match = 0;
4130                 if (p->dev_id) {
4131                         if (!dev_id || strcmp(p->dev_id, dev_id))
4132                                 continue;
4133                         match += 2;
4134                 }
4135                 if (p->con_id) {
4136                         if (!con_id || strcmp(p->con_id, con_id))
4137                                 continue;
4138                         match += 1;
4139                 }
4140
4141                 if (match > best) {
4142                         cl = p;
4143                         if (match != 3)
4144                                 best = match;
4145                         else
4146                                 break;
4147                 }
4148         }
4149         return cl;
4150 }
4151
4152 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
4153         struct clk_lookup *cl;
4154
4155         mutex_lock(&rk30_clocks_mutex);
4156         cl = rk30_clk_find(dev_id, con_id);
4157         if (cl && !__rk30clk_get(cl->clk))
4158                 cl = NULL;
4159         mutex_unlock(&rk30_clocks_mutex);
4160
4161         return cl ? cl->clk : ERR_PTR(-ENOENT);
4162 }
4163 //EXPORT_SYMBOL(rk30_clk_get_sys);
4164
4165 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
4166         const char *dev_id = dev ? dev_name(dev) : NULL;
4167         return rk30_clk_get_sys(dev_id, con_id);
4168 }
4169 //EXPORT_SYMBOL(rk30_clk_get);
4170
4171
4172 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
4173
4174 void rk30_clocks_test(void)
4175 {
4176         struct clk *test_gpll;
4177         test_gpll = rk30_clk_get(NULL, "general_pll");
4178         if(test_gpll) {
4179                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
4180                 printk("gpll rate=%lu\n", test_gpll->rate);
4181         }
4182         //while(1);
4183 }
4184
4185 void __init rk30_clock_init_test(void)
4186 {
4187
4188         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
4189         //while(1);
4190 }
4191
4192
4193 #endif
4194
4195