arch/arm/mach-rk3188/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include <mach/clock.h>
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29 #include <mach/ddr.h>
  30
  31 #define MHZ                     (1000UL * 1000UL)
  32 #define KHZ                     (1000UL)
  33 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  34 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
  35 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  36 void rk30_clk_dump_regs(void);
  37
  38 //flags bit
  39 //has extern 27mhz
  40 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  41 //max i2s rate
  42 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  43 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  44 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  45 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  46 //uart 1m\3m
  47 #define CLK_FLG_UART_1_3M                       (1<<5)
  48
  49 #define ARCH_RK31
  50
  51 struct apll_clk_set {
  52         unsigned long   rate;
  53         u32     pllcon0;
  54         u32     pllcon1;
  55         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  56         u32     rst_dly;//us
  57         u32     clksel0;
  58         u32     clksel1;
  59         unsigned long   lpj;
  60 };
  61 struct pll_clk_set {
  62         unsigned long   rate;
  63         u32     pllcon0;
  64         u32     pllcon1;
  65         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  66         unsigned long   rst_dly;//us
  67 };
  68
  69 #define SET_PLL_DATA(_pll_id,_table) \
  70 {\
  71         .id=(_pll_id),\
  72         .table=(_table),\
  73 }
  74
  75
  76 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  77 { \
  78         .rate   = (_mhz) * KHZ, \
  79         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  80         .pllcon1 = PLL_CLKF_SET(nf),\
  81         .rst_dly=((nr*500)/24+1),\
  82 }
  83
  84
  85 #define _APLL_SET_LPJ(_mhz) \
  86         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  87
  88
  89 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  90                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  91 { \
  92         .rate   = _mhz * MHZ, \
  93         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  94         .pllcon1 = PLL_CLKF_SET(nf),\
  95         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
  96         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
  97         _APLL_SET_LPJ(_mhz),\
  98         .rst_dly=((nr*500)/24+1),\
  99 }
 100
 101 #define CRU_DIV_SET(mask,shift,max) \
 102         .div_mask=(mask),\
 103 .div_shift=(shift),\
 104 .div_max=(max)
 105
 106
 107 #define CRU_SRC_SET(mask,shift ) \
 108         .src_mask=(mask),\
 109 .src_shift=(shift)
 110
 111 #define CRU_PARENTS_SET(parents_array) \
 112         .parents=(parents_array),\
 113 .parents_num=ARRAY_SIZE((parents_array))
 114
 115 #define CRU_GATE_MODE_SET(_func,_IDX) \
 116         .mode=_func,\
 117 .gate_idx=(_IDX)
 118
 119 struct clk_src_sel {
 120         struct clk      *parent;
 121         u8      value;//crt bit
 122         u8      flag;
 123         //selgate
 124 };
 125
 126 #define GATE_CLK(NAME,PARENT,ID) \
 127         static struct clk clk_##NAME = { \
 128                 .name           = #NAME, \
 129                 .parent         = &PARENT, \
 130                 .mode           = gate_mode, \
 131                 .gate_idx       = CLK_GATE_##ID, \
 132         }
 133 #ifdef RK30_CLK_OFFBOARD_TEST
 134 u32 TEST_GRF_REG[0x240];
 135 u32 TEST_CRU_REG[0x240];
 136 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 137
 138 u32 cru_writel_is_pr(u32 offset)
 139 {
 140         return (offset == 0x4000);
 141 }
 142 void cru_writel(u32 v, u32 offset)
 143 {
 144
 145         u32 mask_v = v >> 16;
 146         TEST_CRU_REG[offset/4] &= (~mask_v);
 147
 148         v &= (mask_v);
 149
 150         TEST_CRU_REG[offset/4] |= v;
 151         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 152
 153         if(cru_writel_is_pr(offset)) {
 154                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 155
 156         }
 157
 158 }
 159 void cru_writel_i2s(u32 v, u32 offset)
 160 {
 161         TEST_CRU_REG[offset/4] = v;
 162 }
 163 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 164
 165 #define regfile_readl(offset)   (0xffffffff)
 166 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 167 void rk30_clkdev_add(struct clk_lookup *cl);
 168 #else
 169 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 170 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 171 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 172 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 173
 174 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 175 #endif
 176
 177 //#define DEBUG
 178 #ifdef DEBUG
 179 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 180 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 181 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
 182 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
 183 #else
 184 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 185 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 186 #endif
 187 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 188 #define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
 189
 190
 191 #define get_cru_bits(con,mask,shift)\
 192         ((cru_readl((con)) >> (shift)) & (mask))
 193
 194 #define set_cru_bits_w_msk(val,mask,shift,con)\
 195         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 196
 197
 198 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 199                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 200
 201
 202 static u32 rk30_clock_flags = 0;
 203 static struct clk codec_pll_clk;
 204 static struct clk general_pll_clk;
 205 static struct clk arm_pll_clk;
 206 static unsigned long lpj_gpll;
 207 static unsigned int __initdata armclk = 504 * MHZ;
 208
 209
 210 /************************clk recalc div rate*********************************/
 211
 212 //for free div
 213 static unsigned long clksel_recalc_div(struct clk *clk)
 214 {
 215         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 216
 217         unsigned long rate = clk->parent->rate / div;
 218         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 219         return rate;
 220 }
 221
 222 //for div 1 2 4 2^n
 223 static unsigned long clksel_recalc_shift(struct clk *clk)
 224 {
 225         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 226         unsigned long rate = clk->parent->rate >> shift;
 227         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 228         return rate;
 229 }
 230
 231
 232 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 233 {
 234         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 235         unsigned long rate = clk->parent->rate >> shift;
 236         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 237         return rate;
 238 }
 239
 240 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 241 {
 242         unsigned long rate = clk->parent->rate;
 243         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 244         return rate;
 245 }
 246 /********************************set div rate***********************************/
 247
 248 //for free div
 249 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 250 {
 251         u32 div;
 252         for (div = 0; div < clk->div_max; div++) {
 253                 u32 new_rate = clk->parent->rate / (div + 1);
 254                 if (new_rate <= rate) {
 255                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 256                         //clk->rate = new_rate;
 257                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 258                                         clk->name, rate, div + 1);
 259                         return 0;
 260                 }
 261         }
 262         return -ENOENT;
 263 }
 264
 265 //for div 1 2 4 2^n
 266 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 267 {
 268         u32 shift;
 269         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 270                 u32 new_rate = clk->parent->rate >> shift;
 271                 if (new_rate <= rate) {
 272                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 273                         clk->rate = new_rate;
 274                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 275                                         clk->name, rate, shift);
 276                         return 0;
 277                 }
 278         }
 279         return -ENOENT;
 280 }
 281
 282 //for div 2 4 2^n
 283 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 284 {
 285         u32 shift;
 286
 287         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 288                 u32 new_rate = clk->parent->rate >> shift;
 289                 if (new_rate <= rate) {
 290                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 291                         clk->rate = new_rate;
 292                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 293                                         clk->name, rate, shift);
 294                         return 0;
 295                 }
 296         }
 297         return -ENOENT;
 298 }
 299
 300 //for div 1 2 4 2*n
 301 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 302 {
 303         u32 div;
 304         for (div = 2; div < clk->div_max; div += 2) {
 305                 u32 new_rate = clk->parent->rate / div;
 306                 if (new_rate <= rate) {
 307                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 308                         clk->rate = new_rate;
 309                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 310                                         __func__, clk->name, rate, div);
 311                         return 0;
 312                 }
 313         }
 314         return -ENOENT;
 315 }
 316 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 317 {
 318         u32 div;
 319         unsigned long new_rate;
 320         for (div = 0; div < div_max; div++) {
 321                 new_rate = rate / (div + 1);
 322                 if (new_rate <= rate_out) {
 323                         return div + 1;
 324                 }
 325         }
 326         return div_max ? div_max : 1;
 327 }
 328 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 329 {
 330         u32 div;
 331         unsigned long new_rate;
 332         for (div = 1; div < div_max; div += 2) {
 333                 new_rate = rate / (div + 1);
 334                 if (new_rate <= rate_out) {
 335                         return div + 1;
 336                 }
 337         }
 338         return div_max ? div_max : 1;
 339 }
 340 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 341         u32 div[2] = {0, 0};
 342         unsigned long new_rate[2] = {0, 0};
 343         u32 i;
 344
 345         if(clk->rate == rate)
 346                 return clk->parent;
 347         for(i = 0; i < 2; i++) {
 348                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 349                 new_rate[i] = clk->parents[i]->rate / div[i];
 350                 if(new_rate[i] == rate) {
 351                         *div_out = div[i];
 352                         return clk->parents[i];
 353                 }
 354         }
 355         if(new_rate[0] < new_rate[1])
 356                 i = 1;
 357         else
 358                 i = 0;
 359         *div_out = div[i];
 360         return clk->parents[i];
 361 }
 362 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 363         u32 div[2] = {0, 0};
 364         unsigned long new_rate[2] = {0, 0};
 365         u32 i;
 366
 367         if(clk->rate == rate)
 368                 return clk->parent;
 369         for(i = 0; i < 2; i++) {
 370                 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 371                 new_rate[i] = clk->parents[i]->rate / div[i];
 372                 if(new_rate[i] == rate) {
 373                         *div_out = div[i];
 374                         return clk->parents[i];
 375                 }
 376         }
 377         if(new_rate[0] < new_rate[1])
 378                 i = 1;
 379         else
 380                 i = 0;
 381         *div_out = div[i];
 382         return clk->parents[i];
 383 }
 384
 385 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 386 {
 387         struct clk *p_clk;
 388         u32 div, old_div;
 389         int ret = 0;
 390         if(clk->rate == rate)
 391                 return 0;
 392         p_clk = get_freediv_parents_div(clk, rate, &div);
 393
 394         if(!p_clk)
 395                 return -ENOENT;
 396
 397         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 398         if (clk->parent != p_clk) {
 399                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 400
 401                 if(div > old_div) {
 402                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 403                 }
 404                 ret = clk_set_parent_nolock(clk, p_clk);
 405                 if(ret) {
 406                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 407                         return -ENOENT;
 408                 }
 409         }
 410         //set div
 411         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 412         return 0;
 413 }
 414 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 415 {
 416         struct clk *p_clk;
 417         u32 div, old_div;
 418         int ret = 0;
 419         if(clk->rate == rate)
 420                 return 0;
 421         p_clk = get_evendiv_parents_div(clk, rate, &div);
 422
 423         if(!p_clk)
 424                 return -ENOENT;
 425
 426         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 427         if (clk->parent != p_clk) {
 428                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 429
 430                 if(div > old_div) {
 431                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 432                 }
 433                 ret = clk_set_parent_nolock(clk, p_clk);
 434                 if(ret) {
 435                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 436                         return -ENOENT;
 437                 }
 438         }
 439         //set div
 440         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 441         return 0;
 442 }
 443
 444 //rate==div rate //hdmi
 445 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 446 {
 447         struct clk *p_clk;
 448         u32 div, old_div;
 449         int ret;
 450         p_clk = get_freediv_parents_div(clk, rate, &div);
 451
 452         if(!p_clk)
 453                 return -ENOENT;
 454
 455         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 456                 return -ENOENT;
 457
 458         if (clk->parent != p_clk) {
 459                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 460                                 clk->div_shift, clk->div_mask) + 1;
 461                 if(div > old_div) {
 462                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 463                 }
 464                 ret = clk_set_parent_nolock(clk, p_clk);
 465                 if (ret) {
 466                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 467                         return ret;
 468                 }
 469         }
 470         //set div
 471         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 472         return 0;
 473 }
 474
 475 /***************************round********************************/
 476
 477 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 478 {
 479         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 480 }
 481
 482 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 483 {
 484         u32 div;
 485         struct clk *p_clk;
 486         if(clk->rate == rate)
 487                 return clk->rate;
 488         p_clk = get_freediv_parents_div(clk, rate, &div);
 489         if(!p_clk)
 490                 return 0;
 491         return p_clk->rate / div;
 492 }
 493
 494 /**************************************others seting************************************/
 495
 496 static struct clk *clksel_get_parent(struct clk *clk) {
 497         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 498 }
 499 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 500 {
 501         u32 i;
 502         if (unlikely(!clk->parents))
 503                 return -EINVAL;
 504         for (i = 0; (i < clk->parents_num); i++) {
 505                 if (clk->parents[i] != parent)
 506                         continue;
 507                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 508                 return 0;
 509         }
 510         return -EINVAL;
 511 }
 512
 513 static int gate_mode(struct clk *clk, int on)
 514 {
 515         int idx = clk->gate_idx;
 516         if (idx >= CLK_GATE_MAX)
 517                 return -EINVAL;
 518         if(on) {
 519                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 520                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 521                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 522         } else {
 523                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 524                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 525                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 526         }
 527         return 0;
 528 }
 529 /*****************************frac set******************************************/
 530
 531 static unsigned long clksel_recalc_frac(struct clk *clk)
 532 {
 533         unsigned long rate;
 534         u64 rate64;
 535         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 536         if (r == 0) // FPGA ?
 537                 return clk->parent->rate;
 538         numerator = r >> 16;
 539         denominator = r & 0xFFFF;
 540         rate64 = (u64)clk->parent->rate * numerator;
 541         do_div(rate64, denominator);
 542         rate = rate64;
 543         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 544         return rate;
 545 }
 546
 547 static u32 clk_gcd(u32 numerator, u32 denominator)
 548 {
 549         u32 a, b;
 550
 551         if (!numerator || !denominator)
 552                 return 0;
 553         if (numerator > denominator) {
 554                 a = numerator;
 555                 b = denominator;
 556         } else {
 557                 a = denominator;
 558                 b = numerator;
 559         }
 560         while (b != 0) {
 561                 int r = b;
 562                 b = a % b;
 563                 a = r;
 564         }
 565
 566         return a;
 567 }
 568
 569 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 570                 u32 *numerator, u32 *denominator)
 571 {
 572         u32 gcd_vl;
 573         gcd_vl = clk_gcd(rate, rate_out);
 574         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 575
 576         if (!gcd_vl) {
 577                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 578                 return -ENOENT;
 579         }
 580
 581         *numerator = rate_out / gcd_vl;
 582         *denominator = rate / gcd_vl;
 583
 584         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 585                         *numerator, *denominator, *denominator / *numerator);
 586
 587         if (*numerator > 0xffff || *denominator > 0xffff ||
 588                         (*denominator / (*numerator)) < 20) {
 589                 CLKDATA_ERR("can't get a available nume and deno\n");
 590                 return -ENOENT;
 591         }
 592
 593         return 0;
 594
 595 }
 596 /* *********************pll **************************/
 597
 598 #define rk30_clock_udelay(a) udelay(a);
 599
 600 /*********************pll lock status**********************************/
 601 //#define GRF_SOC_CON0       0x15c
 602 static void pll_wait_lock(int pll_idx)
 603 {
 604         u32 pll_state[4] = {1, 0, 2, 3};
 605         u32 bit = 0x20u << pll_state[pll_idx];
 606         int delay = 24000000;
 607         while (delay > 0) {
 608                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 609                         break;
 610                 delay--;
 611         }
 612         if (delay == 0) {
 613                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 614                 while(1);
 615         }
 616 }
 617
 618
 619
 620 /***************************pll function**********************************/
 621 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 622 {
 623         unsigned long rate;
 624
 625         if (PLLS_IN_NORM(pll_id)) {
 626                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 627                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 628
 629
 630                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 631
 632                 /*
 633                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 634                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 635                    */
 636
 637
 638                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 639                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 640                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 641
 642                 do_div(rate64, PLL_NR(pll_con0));
 643                 do_div(rate64, PLL_NO(pll_con0));
 644
 645                 rate = rate64;
 646                 /*
 647                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 648                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 649                    */
 650         } else {
 651                 rate = parent_rate;
 652                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 653         }
 654         return rate;
 655 }
 656 static unsigned long plls_clk_recalc(struct clk *clk)
 657 {
 658         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 659 }
 660
 661 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 662 {
 663         //enter slowmode
 664         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 665         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 666         dsb();
 667         dsb();
 668         dsb();
 669         dsb();
 670         dsb();
 671         dsb();
 672         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 673         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 674
 675         rk30_clock_udelay(1);
 676         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 677
 678         pll_wait_lock(pll_id);
 679
 680         //return form slow
 681         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 682
 683         /*
 684            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 685            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 686            */
 687
 688         return 0;
 689 }
 690 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 691 {
 692         struct _pll_data *pll_data = c->pll;
 693         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 694
 695         while(clk_set->rate) {
 696                 if (clk_set->rate == rate) {
 697                         break;
 698                 }
 699                 clk_set++;
 700         }
 701         if(clk_set->rate == rate) {
 702                 pll_clk_set_rate(clk_set, pll_data->id);
 703                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 704         } else {
 705                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 706                 return -1;
 707         }
 708         return 0;
 709 }
 710
 711 #define PLL_FREF_MIN (183*KHZ)
 712 #define PLL_FREF_MAX (1500*MHZ)
 713
 714 #define PLL_FVCO_MIN (300*MHZ)
 715 #define PLL_FVCO_MAX (1500*MHZ)
 716
 717 #define PLL_FOUT_MIN (18750*KHZ)
 718 #define PLL_FOUT_MAX (1500*MHZ)
 719
 720 #define PLL_NF_MAX (65536)
 721 #define PLL_NR_MAX (64)
 722 #define PLL_NO_MAX (64)
 723
 724 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 725 {
 726         u32 nr, nf, no, nonr;
 727         u32 n;
 728         u32 YFfenzi;
 729         u32 YFfenmu;
 730         unsigned long fref, fvco, fout;
 731         u32 gcd_val = 0;
 732
 733         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 734         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 735                 return 0;
 736         gcd_val = clk_gcd(fin_hz, fout_hz);
 737         YFfenzi = fout_hz / gcd_val;
 738         YFfenmu = fin_hz / gcd_val;
 739
 740         for(n = 1;; n++) {
 741                 nf = YFfenzi * n;
 742                 nonr = YFfenmu * n;
 743                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 744                         break;
 745                 for(no = 1; no <= PLL_NO_MAX; no++) {
 746                         if(!(no == 1 || !(no % 2)))
 747                                 continue;
 748
 749                         if(nonr % no)
 750                                 continue;
 751                         nr = nonr / no;
 752
 753                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 754                                 continue;
 755
 756                         fref = fin_hz / nr;
 757                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 758                                 continue;
 759
 760                         fvco = (fin_hz / nr) * nf;
 761                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 762                                 continue;
 763                         fout = fvco / no;
 764                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 765                                 continue;
 766                         *clk_nr = nr;
 767                         *clk_no = no;
 768                         *clk_nf = nf;
 769                         return 1;
 770
 771                 }
 772
 773         }
 774         return 0;
 775 }
 776
 777 static int pll_clk_mode(struct clk *clk, int on)
 778 {
 779         u8 pll_id = clk->pll->id;
 780         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 781         u32 dly = (nr * 500) / 24 + 1;
 782         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 783         if (on) {
 784                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 785                 rk30_clock_udelay(dly);
 786                 pll_wait_lock(pll_id);
 787                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 788         } else {
 789                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 790                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 791         }
 792         return 0;
 793 }
 794
 795 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 796 {
 797         struct _pll_data *pll_data = c->pll;
 798         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 799         struct pll_clk_set temp_clk_set;
 800         u32 clk_nr, clk_nf, clk_no;
 801
 802
 803         while(clk_set->rate) {
 804                 if (clk_set->rate == rate) {
 805                         break;
 806                 }
 807                 clk_set++;
 808         }
 809         if(clk_set->rate == rate) {
 810                 CLKDATA_DBG("cpll get a rate\n");
 811                 pll_clk_set_rate(clk_set, pll_data->id);
 812
 813         } else {
 814                 CLKDATA_DBG("cpll get auto calc a rate\n");
 815                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 816                         pr_err("cpll auto set rate error\n");
 817                         return -ENOENT;
 818                 }
 819                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 820                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 821                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 822                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 823                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 824
 825         }
 826         return 0;
 827 }
 828
 829
 830 /* ******************fixed input clk ***********************************************/
 831 static struct clk xin24m = {
 832         .name           = "xin24m",
 833         .rate           = 24 * MHZ,
 834         .flags          = RATE_FIXED,
 835 };
 836
 837 static struct clk clk_12m = {
 838         .name           = "clk_12m",
 839         .parent         = &xin24m,
 840         .rate           = 12 * MHZ,
 841         .flags          = RATE_FIXED,
 842 };
 843
 844 /************************************pll func***************************/
 845 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 846                 struct apll_clk_set *tables) {
 847         const struct apll_clk_set *ps, *pt;
 848
 849         /* find the arm_pll we want. */
 850         ps = pt = tables;
 851         while (pt->rate) {
 852                 if (pt->rate == rate) {
 853                         ps = pt;
 854                         break;
 855                 }
 856                 // we are sorted, and ps->rate > pt->rate.
 857                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 858                         ps = pt;
 859                 if (pt->rate < rate)
 860                         break;
 861                 pt++;
 862         }
 863         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 864         return ps;
 865 }
 866 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 867 {
 868         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 869 }
 870 #if 1
 871 struct arm_clks_div_set {
 872         u32 rate;
 873         u32     clksel0;
 874         u32     clksel1;
 875 };
 876
 877 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 878 { \
 879         .rate    =_mhz,\
 880         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 881         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 882         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 883         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 884         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 885 }
 886 struct arm_clks_div_set arm_clk_div_tlb[] = {
 887         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 888         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 889         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 890         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 891         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
 892         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
 893         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
 894 };
 895 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
 896         int i = 0;
 897         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
 898                 if(arm_clk_div_tlb[i].rate >= rate)
 899                         return &arm_clk_div_tlb[i];
 900         }
 901         return NULL;
 902 }
 903
 904 #endif
 905
 906 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 907 {
 908         unsigned long flags;
 909         const struct apll_clk_set *ps;
 910         u32 pll_id = clk->pll->id;
 911         u32 temp_div;
 912         u32 old_aclk_div = 0, new_aclk_div;
 913
 914         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
 915
 916         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
 917         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
 918
 919         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
 920                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
 921
 922         if(general_pll_clk.rate > clk->rate) {
 923                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
 924         } else {
 925                 temp_div = 1;
 926         }
 927
 928         // ungating cpu gpll path
 929         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
 930         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 931
 932         local_irq_save(flags);
 933         //div arm clk for gpll
 934
 935         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
 936         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
 937
 938         loops_per_jiffy = lpj_gpll / temp_div;
 939         smp_wmb();
 940
 941         /*if core src don't select gpll ,apll neet to enter slow mode */
 942         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 943
 944
 945         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 946         dsb();
 947         dsb();
 948         dsb();
 949         dsb();
 950         dsb();
 951         dsb();
 952         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
 953         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
 954
 955         rk30_clock_udelay(1);
 956         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 957
 958         pll_wait_lock(pll_id);
 959
 960         //return form slow
 961         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 962         //reparent to apll
 963
 964         if(new_aclk_div>=old_aclk_div) {
 965                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 966                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 967         }
 968
 969         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
 970         if(old_aclk_div>new_aclk_div) {
 971                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 972                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 973         }
 974
 975         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
 976
 977         loops_per_jiffy = ps->lpj;
 978         smp_wmb();
 979
 980         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
 981
 982         local_irq_restore(flags);
 983
 984         //gate gpll path
 985         // FIXME
 986         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
 987         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 988
 989         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
 990                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
 991                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
 992                         cru_readl(CRU_CLKSELS_CON(1)));
 993         return 0;
 994 }
 995
 996
 997 /************************************pll clocks***************************/
 998
 999 static const struct apll_clk_set apll_clks[] = {
1000         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1001         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1002         _APLL_SET_CLKS(2208, 1, 92, 1, 8,       81, 81, 21, 41, 21),
1003         _APLL_SET_CLKS(2184, 1, 91, 1, 8,       81, 81, 21, 41, 21),
1004         _APLL_SET_CLKS(2160, 1, 90, 1, 8,       81, 81, 21, 41, 21),
1005         _APLL_SET_CLKS(2136, 1, 89, 1, 8,       81, 81, 21, 41, 21),
1006         _APLL_SET_CLKS(2112, 1, 88, 1, 8,       81, 81, 21, 41, 21),
1007         _APLL_SET_CLKS(2088, 1, 87, 1, 8,       81, 81, 21, 41, 21),
1008         _APLL_SET_CLKS(2064, 1, 86, 1, 8,       81, 81, 21, 41, 21),
1009         _APLL_SET_CLKS(2040, 1, 85, 1, 8,       81, 81, 21, 41, 21),
1010         _APLL_SET_CLKS(2016, 1, 84, 1, 8,       81, 81, 21, 41, 21),
1011         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1012         _APLL_SET_CLKS(1968, 1, 82, 1, 8,       81, 81, 21, 41, 21),
1013         _APLL_SET_CLKS(1944, 1, 81, 1, 8,       81, 81, 21, 41, 21),
1014         _APLL_SET_CLKS(1920, 1, 80, 1, 8,       81, 81, 21, 41, 21),
1015         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1016         _APLL_SET_CLKS(1872, 1, 78, 1, 8,       81, 81, 21, 41, 21),
1017         _APLL_SET_CLKS(1848, 1, 77, 1, 8,       81, 81, 21, 41, 21),
1018         _APLL_SET_CLKS(1824, 1, 76, 1, 8,       81, 81, 21, 41, 21),
1019         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1020         _APLL_SET_CLKS(1776, 1, 74, 1, 8,       81, 81, 21, 41, 21),
1021         _APLL_SET_CLKS(1752, 1, 73, 1, 8,       81, 81, 21, 41, 21),
1022         _APLL_SET_CLKS(1728, 1, 72, 1, 8,       81, 81, 21, 41, 21),
1023         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1024         _APLL_SET_CLKS(1680, 1, 70, 1, 8,       41, 41, 21, 41, 21),
1025         _APLL_SET_CLKS(1656, 1, 69, 1, 8,       41, 41, 21, 41, 21),
1026         _APLL_SET_CLKS(1632, 1, 68, 1, 8,       41, 41, 21, 41, 21),
1027         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1028         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1029         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1030         _APLL_SET_CLKS(1488, 1, 62, 1, 8,       41, 41, 21, 41, 21),
1031         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1032         _APLL_SET_CLKS(1440, 1, 60, 1, 8,       41, 41, 21, 41, 21),
1033         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1034         _APLL_SET_CLKS(1392, 1, 58, 1, 8,       41, 41, 21, 41, 21),
1035         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1036         _APLL_SET_CLKS(1344, 1, 56, 1, 8,       41, 41, 21, 41, 21),
1037         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1038         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1039         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1040         _APLL_SET_CLKS(1248, 1, 52, 1, 8,       41, 41, 21, 41, 21),
1041         _APLL_SET_CLKS(1224, 1, 51, 1, 8,       41, 41, 21, 41, 21),
1042         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1043         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1044         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1045         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1046         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1047         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1048         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1049         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1050         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1051         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1052         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1053         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1054         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1055         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1056         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1057         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1058         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1059         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1060         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1061
1062 };
1063 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1064 static struct clk arm_pll_clk = {
1065         .name           = "arm_pll",
1066         .parent         = &xin24m,
1067         .mode           = pll_clk_mode,
1068         .recalc         = plls_clk_recalc,
1069         .set_rate       = arm_pll_clk_set_rate,
1070         .round_rate     = arm_pll_clk_round_rate,
1071         .pll            = &apll_data,
1072 };
1073
1074 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1075 {
1076         /* do nothing here */
1077         return 0;
1078 }
1079 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1080 static struct clk ddr_pll_clk = {
1081         .name           = "ddr_pll",
1082         .parent         = &xin24m,
1083         .recalc         = plls_clk_recalc,
1084         .set_rate       = ddr_pll_clk_set_rate,
1085         .pll            = &dpll_data,
1086 };
1087
1088 static const struct pll_clk_set cpll_clks[] = {
1089         _PLL_SET_CLKS(360000, 1,  60,   4),
1090         _PLL_SET_CLKS(408000, 1,  68,   4),
1091         _PLL_SET_CLKS(456000, 1,  76,   4),
1092         _PLL_SET_CLKS(504000, 1,  84,   4),
1093         _PLL_SET_CLKS(552000, 1,  46,   2),
1094         _PLL_SET_CLKS(600000, 1,  50,   2),
1095         _PLL_SET_CLKS(742500, 8,  495,  2),
1096         _PLL_SET_CLKS(768000, 1,  64,   2),
1097         _PLL_SET_CLKS(798000, 2,  133,  2),
1098         _PLL_SET_CLKS(1188000, 2, 99,   1),
1099         _PLL_SET_CLKS(     0, 4,  133,  1),
1100 };
1101 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1102 static struct clk codec_pll_clk = {
1103         .name           = "codec_pll",
1104         .parent         = &xin24m,
1105         .mode           = pll_clk_mode,
1106         .recalc         = plls_clk_recalc,
1107         .set_rate       = cpll_clk_set_rate,
1108         .pll            = &cpll_data,
1109 };
1110
1111 static const struct pll_clk_set gpll_clks[] = {
1112         _PLL_SET_CLKS(148500,   2,      99,     8),
1113         _PLL_SET_CLKS(297000,   2,      198,    8),
1114         _PLL_SET_CLKS(300000,   1,      50,     4),
1115         _PLL_SET_CLKS(594000,   2,      198,    4),
1116         _PLL_SET_CLKS(1188000,  2,      99,     1),
1117         _PLL_SET_CLKS(1200000,  1,      50,     1),
1118         _PLL_SET_CLKS(0,        0,       0,     0),
1119 };
1120 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1121 static struct clk general_pll_clk = {
1122         .name           = "general_pll",
1123         .parent         = &xin24m,
1124         .recalc         = plls_clk_recalc,
1125         .set_rate       = gpll_clk_set_rate,
1126         .pll            = &gpll_data
1127 };
1128 /********************************clocks***********************************/
1129 GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1130
1131 /* core and cpu setting */
1132 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1133 {
1134         CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1135         return 0;
1136 }
1137
1138 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1139 {
1140         CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1141         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1142 }
1143 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1144 {
1145         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1146         unsigned long rate = clk->parent->recalc(clk->parent) >> shift;
1147         //CLKDATA_DBG("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1148         return rate;
1149 }
1150 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1151 static struct clk clk_ddr = {
1152         .name           = "ddr",
1153         .parent         = &ddr_pll_clk,
1154         .recalc         = ddr_clk_recalc_rate,
1155         .set_rate       = ddr_clk_set_rate,
1156         .round_rate     = ddr_clk_round_rate,
1157         .gate_idx       = CLK_GATE_DDRPHY,
1158         .clksel_con     = CRU_CLKSELS_CON(26),
1159         CRU_DIV_SET(0x3, 0, 4),
1160         CRU_SRC_SET(1, 8),
1161         CRU_PARENTS_SET(clk_ddr_parents),
1162 };
1163 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1164 {
1165         int ret;
1166
1167         ret = clk_set_rate_nolock(c->parent, rate);
1168         if (ret) {
1169                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1170                 return ret;
1171         }
1172         //set arm pll div 1
1173         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1174         return 0;
1175 }
1176 static unsigned long clk_core_get_rate(struct clk *c)
1177 {
1178         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1179         //c->parent->rate=c->parent->recalc(c->parent);
1180         return c->parent->rate / div;
1181 }
1182 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1183 {
1184         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1185         return clk_round_rate_nolock(clk->parent, rate) / div;
1186 }
1187
1188 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1189 {
1190
1191         u32 temp_div;
1192         struct clk *old_prt;
1193
1194         if(clk->parent == new_prt)
1195                 return 0;
1196         if (unlikely(!clk->parents))
1197                 return -EINVAL;
1198         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1199         //arm
1200         old_prt = clk->parent;
1201
1202         if(clk->parents[0] == new_prt) {
1203                 new_prt->set_rate(new_prt, 300 * MHZ);
1204                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1205         } else if(clk->parents[1] == new_prt) {
1206
1207                 if(new_prt->rate > old_prt->rate) {
1208                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1209                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1210                 }
1211                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1212                 new_prt->set_rate(new_prt, 300 * MHZ);
1213         } else
1214                 return -1;
1215
1216
1217         return 0;
1218
1219 }
1220
1221 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1222 {
1223         u32 temp_div;
1224         u32 old_aclk_div = 0, new_aclk_div;
1225         struct arm_clks_div_set *temp_clk_div;
1226         unsigned long arm_gpll_rate, arm_gpll_lpj;
1227         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1228         arm_gpll_rate = c->parent->rate / temp_div;
1229
1230         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1231         if(!temp_clk_div)
1232                 temp_clk_div = &arm_clk_div_tlb[4];
1233
1234         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1235         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1236         if(c->rate >= rate) {
1237                 arm_gpll_lpj = lpj_gpll / temp_div;
1238                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1239         }
1240
1241         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1242         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1243                         CRU_CLKSELS_CON(0));
1244         if((c->rate < rate)) {
1245                 arm_gpll_lpj = lpj_gpll / temp_div;
1246                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1247         }
1248         return 0;
1249 }
1250 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1251 {
1252         return c->parent->rate;
1253 }
1254 static struct clk clk_core_gpll_path = {
1255         .name           = "cpu_gpll_path",
1256         .parent         = &general_pll_clk,
1257         .recalc         = arm_core_gpll_clk_get_rate,
1258         .set_rate       = core_gpll_clk_set_rate,
1259         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1260 };
1261
1262
1263 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1264
1265 static struct clk clk_core = {
1266         .name           = "core",
1267         .parent         = &arm_pll_clk,
1268         .set_rate       = clk_core_set_rate,
1269         .recalc         = clk_core_get_rate,
1270         .round_rate     = core_clk_round_rate,
1271         .set_parent     = core_clksel_set_parent,
1272         .clksel_con     = CRU_CLKSELS_CON(0),
1273         CRU_DIV_SET(0x1f, 9, 32),
1274         CRU_SRC_SET(1, 8),
1275         CRU_PARENTS_SET(clk_core_parents),
1276 };
1277 GATE_CLK(l2c, clk_core, CLK_L2C);
1278 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1279 static unsigned long aclk_recalc(struct clk *clk)
1280 {
1281         unsigned long rate;
1282         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1283
1284         BUG_ON(div > 5);
1285         if (div >= 5)
1286                 div = 8;
1287         rate = clk->parent->rate / div;
1288         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1289
1290         return rate;
1291 };
1292 static struct clk core_periph = {
1293         .name           = "core_periph",
1294         .parent         = &clk_core,
1295         .gate_idx       = CLK_GATE_CORE_PERIPH,
1296         .recalc         = clksel_recalc_shift_2,
1297         .clksel_con     = CRU_CLKSELS_CON(0),
1298         CRU_DIV_SET(0x3, 6, 16),
1299 };
1300 static struct clk aclk_core = {
1301         .name           = "aclk_core",
1302         .parent         = &clk_core,
1303         .gate_idx       = CLK_GATE_ACLK_CORE,
1304         .recalc         = aclk_recalc,
1305         .clksel_con     = CRU_CLKSELS_CON(1),
1306         CRU_DIV_SET(0x7, 3, 8),
1307 };
1308
1309 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1310 static struct clk clk_cpu_div = {
1311         .name           = "cpu_div",
1312         .parent         = &arm_pll_clk,
1313         .set_rate       = clksel_set_rate_freediv,
1314         .recalc         = clksel_recalc_div,
1315         .clksel_con     = CRU_CLKSELS_CON(0),
1316         CRU_DIV_SET(0x1f, 0, 32),
1317         CRU_SRC_SET(1, 5),
1318         CRU_PARENTS_SET(clk_cpu_div_parents),
1319 };
1320
1321 static struct clk aclk_cpu = {
1322         .name           = "aclk_cpu",
1323         .parent         = &clk_cpu_div,
1324         .gate_idx       = CLK_GATE_ACLK_CPU,
1325 };
1326
1327 static struct clk hclk_cpu = {
1328         .name           = "hclk_cpu",
1329         .parent         = &aclk_cpu,
1330         .gate_idx       = CLK_GATE_HCLK_CPU,
1331         .recalc         = clksel_recalc_shift,
1332         .set_rate       = clksel_set_rate_shift,
1333         .clksel_con     = CRU_CLKSELS_CON(1),
1334         CRU_DIV_SET(0x3, 8, 4),
1335
1336 };
1337
1338 static struct clk pclk_cpu = {
1339         .name           = "pclk_cpu",
1340         .parent         = &aclk_cpu,
1341         .gate_idx       = CLK_GATE_PCLK_CPU,
1342         .recalc         = clksel_recalc_shift,
1343         .set_rate       = clksel_set_rate_shift,
1344         .clksel_con     = CRU_CLKSELS_CON(1),
1345         CRU_DIV_SET(0x3, 12, 8),
1346 };
1347
1348 static struct clk ahb2apb_cpu = {
1349         .name           = "ahb2apb",
1350         .parent         = &hclk_cpu,
1351         .recalc         = clksel_recalc_shift,
1352         .set_rate       = clksel_set_rate_shift,
1353         .clksel_con     = CRU_CLKSELS_CON(1),
1354         CRU_DIV_SET(0x3, 14, 4),
1355 };
1356
1357
1358 static struct clk atclk_cpu = {
1359         .name           = "atclk_cpu",
1360         .parent         = &pclk_cpu,
1361         .gate_idx       = CLK_GATE_ATCLK_CPU,
1362 };
1363
1364 /* GPU setting */
1365 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1366 {
1367         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1368         return clkset_rate_freediv_autosel_parents(clk, max_rate);
1369 };
1370
1371 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1372
1373 static struct clk aclk_gpu = {
1374         .name           = "aclk_gpu",
1375         .mode           = gate_mode,
1376         .recalc         = clksel_recalc_div,
1377         .round_rate     = clk_freediv_round_autosel_parents_rate,
1378         .set_rate       = clkset_rate_freediv_autosel_parents,
1379         .clksel_con     = CRU_CLKSELS_CON(34),
1380         .gate_idx       = CLK_GATE_ACLK_GPU,
1381         CRU_DIV_SET(0x1f, 0, 32),
1382         CRU_SRC_SET(0x1, 7),
1383         CRU_PARENTS_SET(aclk_gpu_parents),
1384 };
1385
1386 /* vcodec setting */
1387 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1388 {
1389         unsigned long rate = clk->parent->rate / 4;
1390         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1391         return rate;
1392 }
1393
1394 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1395
1396 static struct clk aclk_vepu = {
1397         .name           = "aclk_vepu",
1398         .parent         = &codec_pll_clk,
1399         .mode           = gate_mode,
1400         .recalc         = clksel_recalc_div,
1401         .set_rate       = clkset_rate_freediv_autosel_parents,
1402         .clksel_con     = CRU_CLKSELS_CON(32),
1403         .gate_idx       = CLK_GATE_ACLK_VEPU,
1404         CRU_DIV_SET(0x1f, 0, 32),
1405         CRU_SRC_SET(0x1, 7),
1406         CRU_PARENTS_SET(aclk_vepu_parents),
1407 };
1408
1409 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1410
1411 static struct clk aclk_vdpu = {
1412         .name           = "aclk_vdpu",
1413         .mode           = gate_mode,
1414         .recalc         = clksel_recalc_div,
1415         .set_rate       = clkset_rate_freediv_autosel_parents,
1416         .clksel_con     = CRU_CLKSELS_CON(32),
1417         .gate_idx       = CLK_GATE_ACLK_VDPU,
1418         CRU_DIV_SET(0x1f, 8, 32),
1419         CRU_SRC_SET(0x1, 15),
1420         CRU_PARENTS_SET(aclk_vdpu_parents),
1421 };
1422 static struct clk hclk_vepu = {
1423         .name           = "hclk_vepu",
1424         .parent         = &aclk_vepu,
1425         .mode           = gate_mode,
1426         .recalc         = clksel_recalc_vpu_hclk,
1427         .gate_idx       = CLK_GATE_HCLK_VEPU,
1428 };
1429
1430 static struct clk hclk_vdpu = {
1431         .name           = "hclk_vdpu",
1432         .parent         = &aclk_vdpu,
1433         .mode           = gate_mode,
1434         .recalc         = clksel_recalc_vpu_hclk,
1435         .gate_idx       = CLK_GATE_HCLK_VDPU,
1436 };
1437
1438 /* aclk lcdc setting */
1439 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1440
1441 static struct clk aclk_lcdc0_pre = {
1442         .name           = "aclk_lcdc0_pre",
1443         .parent         = &codec_pll_clk,
1444         .mode           = gate_mode,
1445         .recalc         = clksel_recalc_div,
1446         .set_rate       = clkset_rate_freediv_autosel_parents,
1447         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1448         .clksel_con     = CRU_CLKSELS_CON(31),
1449         CRU_DIV_SET(0x1f, 0, 32),
1450         CRU_SRC_SET(0x1, 7),
1451         CRU_PARENTS_SET(aclk_lcdc0_parents),
1452 };
1453
1454 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1455
1456 static struct clk aclk_lcdc1_pre = {
1457         .name           = "aclk_lcdc1_pre",
1458         .parent         = &codec_pll_clk,
1459         .mode           = gate_mode,
1460         .recalc         = clksel_recalc_div,
1461         .set_rate       = clkset_rate_freediv_autosel_parents,
1462         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1463         .clksel_con     = CRU_CLKSELS_CON(31),
1464         CRU_DIV_SET(0x1f, 8, 32),
1465         CRU_SRC_SET(0x1, 15),
1466         CRU_PARENTS_SET(aclk_lcdc1_parents),
1467 };
1468
1469 /* aclk/hclk/pclk periph setting */
1470 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1471
1472 static struct clk aclk_periph = {
1473         .name           = "aclk_periph",
1474         .parent         = &general_pll_clk,
1475         .mode           = gate_mode,
1476         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1477         .recalc         = clksel_recalc_div,
1478         .set_rate       = clksel_set_rate_freediv,
1479         .clksel_con     = CRU_CLKSELS_CON(10),
1480         CRU_DIV_SET(0x1f, 0, 32),
1481         CRU_SRC_SET(1, 15),
1482         CRU_PARENTS_SET(aclk_periph_parents),
1483 };
1484 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1485
1486 static struct clk pclk_periph = {
1487         .name           = "pclk_periph",
1488         .parent         = &aclk_periph,
1489         .mode           = gate_mode,
1490         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1491         .recalc         = clksel_recalc_shift,
1492         .set_rate       = clksel_set_rate_shift,
1493         .clksel_con     = CRU_CLKSELS_CON(10),
1494         CRU_DIV_SET(0x3, 12, 8),
1495 };
1496
1497 static struct clk hclk_periph = {
1498         .name           = "hclk_periph",
1499         .parent         = &aclk_periph,
1500         .mode           = gate_mode,
1501         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1502         .recalc         = clksel_recalc_shift,
1503         .set_rate       = clksel_set_rate_shift,
1504         .clksel_con     = CRU_CLKSELS_CON(10),
1505         CRU_DIV_SET(0x3, 8, 4),
1506 };
1507 /* dclk lcdc setting */
1508 // FIXME
1509 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1510 {
1511         u32 div, old_div;
1512         int i;
1513         unsigned long new_rate;
1514         int ret = 0;
1515
1516         if(clk->rate == rate)
1517                 return 0;
1518         for(i = 0; i < 2; i++) {
1519                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1520                 new_rate = clk->parents[i]->rate / div;
1521                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1522                         break;
1523                 }
1524         }
1525         if(i >= 2) {
1526                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1527                 return -1;
1528         }
1529
1530         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1531
1532         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1533                         clk->div_shift, clk->div_mask) + 1;
1534         if(div > old_div)
1535                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1536
1537         if(clk->parents[i] != clk->parent) {
1538                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1539         }
1540
1541         if (ret) {
1542                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1543                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1544                 return ret;
1545         }
1546         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1547         return 0;
1548 }
1549
1550 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1551 {
1552         if (rate == 27 * MHZ)
1553                 return clkset_rate_freediv_autosel_parents(clk, rate);
1554         else
1555                 return clkset_rate_evendiv_autosel_parents(clk, rate);
1556
1557 #if 0
1558         int ret = 0;
1559         struct clk *parent;
1560         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1561                 parent = clk->parents[1];
1562                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1563         } else {
1564                 parent = clk->parents[0];
1565         }
1566         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1567         //clk->name,rate,parent->name,clk->parent->name);
1568
1569         if(parent != clk->parents[1]) {
1570                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1571                 if (ret) {
1572                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1573                         return ret;
1574                 }
1575         }
1576         if (clk->parent != parent) {
1577                 ret = clk_set_parent_nolock(clk, parent);
1578                 if (ret) {
1579                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1580                         return ret;
1581                 }
1582         }
1583         return ret;
1584 #endif
1585 }
1586
1587 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1588 static struct clk dclk_lcdc0 = {
1589         .name           = "dclk_lcdc0",
1590         .mode           = gate_mode,
1591         .set_rate       = dclk_lcdc_set_rate,
1592         .recalc         = clksel_recalc_div,
1593         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1594         .clksel_con     = CRU_CLKSELS_CON(27),
1595         CRU_SRC_SET(0x1, 0),
1596         CRU_DIV_SET(0xff, 8, 256),
1597         CRU_PARENTS_SET(dclk_lcdc0_parents),
1598 };
1599
1600 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1601 static struct clk dclk_lcdc1 = {
1602         .name           = "dclk_lcdc1",
1603         .mode           = gate_mode,
1604         .set_rate       = dclk_lcdc_set_rate,
1605         .recalc         = clksel_recalc_div,
1606         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1607         .clksel_con     = CRU_CLKSELS_CON(28),
1608         CRU_SRC_SET(0x1, 0),
1609         CRU_DIV_SET(0xff, 8, 256),
1610         CRU_PARENTS_SET(dclk_lcdc1_parents),
1611 };
1612
1613 /* cif setting */
1614 // FIXME
1615 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1616 static struct clk cif_out_pll = {
1617         .name           = "cif_out_pll",
1618         .parent         = &general_pll_clk,
1619         .clksel_con     = CRU_CLKSELS_CON(29),
1620         CRU_SRC_SET(0x1, 0),
1621         CRU_PARENTS_SET(cifout_sel_pll_parents),
1622 };
1623
1624 static struct clk cif0_out_div = {
1625         .name           = "cif0_out_div",
1626         .parent         = &cif_out_pll,
1627         .mode           = gate_mode,
1628         .recalc         = clksel_recalc_div,
1629         .set_rate       = clksel_set_rate_freediv,
1630         .gate_idx       = CLK_GATE_CIF0_OUT,
1631         .clksel_con     = CRU_CLKSELS_CON(29),
1632         CRU_DIV_SET(0x1f, 1, 32),
1633 };
1634
1635 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1636 {
1637         int ret = 0;
1638         struct clk *parent;
1639
1640         if (rate == 24 * MHZ) {
1641                 parent = clk->parents[1];
1642         } else {
1643                 parent = clk->parents[0];
1644                 ret = clk_set_rate_nolock(parent, rate);
1645                 if (ret)
1646                         return ret;
1647         }
1648         if (clk->parent != parent)
1649                 ret = clk_set_parent_nolock(clk, parent);
1650
1651         return ret;
1652 }
1653
1654 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1655 static struct clk cif0_out = {
1656         .name           = "cif0_out",
1657         .parent         = &cif0_out_div,
1658         .set_rate       = cif_out_set_rate,
1659         .clksel_con     = CRU_CLKSELS_CON(29),
1660         CRU_SRC_SET(0x1, 7),
1661         CRU_PARENTS_SET(cif0_out_parents),
1662 };
1663
1664 static struct clk pclkin_cif0 = {
1665         .name           = "pclkin_cif0",
1666         .mode           = gate_mode,
1667         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1668 };
1669
1670 static struct clk inv_cif0 = {
1671         .name           = "inv_cif0",
1672         .parent         = &pclkin_cif0,
1673 };
1674
1675 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1676 static struct clk cif0_in = {
1677         .name           = "cif0_in",
1678         .parent         = &pclkin_cif0,
1679         .clksel_con     = CRU_CLKSELS_CON(30),
1680         CRU_SRC_SET(0x1, 8),
1681         CRU_PARENTS_SET(cif0_in_parents),
1682 };
1683
1684 /* i2s/spdif setting */
1685 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1686 static struct clk clk_i2s_pll = {
1687         .name           = "i2s_pll",
1688         .parent         = &general_pll_clk,
1689         .clksel_con     = CRU_CLKSELS_CON(2),
1690         CRU_SRC_SET(0x1, 15),
1691         CRU_PARENTS_SET(clk_i2s_div_parents),
1692 };
1693
1694 static struct clk clk_i2s0_div = {
1695         .name           = "i2s0_div",
1696         .parent         = &clk_i2s_pll,
1697         .mode           = gate_mode,
1698         .recalc         = clksel_recalc_div,
1699         .set_rate       = clksel_set_rate_freediv,
1700         .round_rate     = clksel_freediv_round_rate,
1701         .gate_idx       = CLK_GATE_I2S0_SRC,
1702         .clksel_con     = CRU_CLKSELS_CON(3),
1703         CRU_DIV_SET(0x7f, 0, 64),
1704 };
1705
1706 static struct clk clk_spdif_div = {
1707         .name           = "spdif_div",
1708         .parent         = &clk_i2s_pll,
1709         .recalc         = clksel_recalc_div,
1710         .set_rate       = clksel_set_rate_freediv,
1711         .round_rate     = clksel_freediv_round_rate,
1712         .mode           = gate_mode,
1713         .gate_idx       = CLK_GATE_SPDIF_SRC,
1714         .clksel_con     = CRU_CLKSELS_CON(5),
1715         CRU_DIV_SET(0x7f, 0, 64),
1716 };
1717 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1718 {
1719         u32 numerator, denominator;
1720         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1721         //clk->parent->parent
1722         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1723                                 &numerator, &denominator) == 0) {
1724                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1725                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1726                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1727         } else {
1728                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1729                 return -ENOENT;
1730         }
1731         return 0;
1732 }
1733
1734 static struct clk clk_i2s0_frac_div = {
1735         .name           = "i2s0_frac_div",
1736         .parent         = &clk_i2s0_div,
1737         .mode           = gate_mode,
1738         .gate_idx       = CLK_GATE_I2S0_FRAC,
1739         .recalc         = clksel_recalc_frac,
1740         .set_rate       = clk_i2s_fracdiv_set_rate,
1741         .clksel_con     = CRU_CLKSELS_CON(7),
1742 };
1743
1744 static struct clk clk_spdif_frac_div = {
1745         .name           = "spdif_frac_div",
1746         .parent         = &clk_spdif_div,
1747         .mode           = gate_mode,
1748         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1749         .recalc         = clksel_recalc_frac,
1750         .set_rate       = clk_i2s_fracdiv_set_rate,
1751         .clksel_con     = CRU_CLKSELS_CON(9),
1752 };
1753
1754 #define I2S_SRC_DIV     (0x0)
1755 #define I2S_SRC_FRAC    (0x1)
1756 #define I2S_SRC_12M     (0x2)
1757
1758 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1759 {
1760         int ret = -EINVAL;
1761         struct clk *parent;
1762
1763         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1764                 parent = clk->parents[I2S_SRC_12M];
1765         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1766                 parent = clk->parents[I2S_SRC_DIV];
1767         } else {
1768                 parent = clk->parents[I2S_SRC_FRAC];
1769         }
1770
1771         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1772                         clk->name, rate, parent->name, clk->parent->name);
1773
1774         if(parent != clk->parents[I2S_SRC_12M]) {
1775                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1776                 if (ret) {
1777                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1778                         return ret;
1779                 }
1780         }
1781
1782         if (clk->parent != parent) {
1783                 ret = clk_set_parent_nolock(clk, parent);
1784                 if (ret) {
1785                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1786                         return ret;
1787                 }
1788         }
1789
1790         return ret;
1791 };
1792
1793 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
1794
1795 static struct clk clk_i2s0 = {
1796         .name           = "i2s0",
1797         .set_rate       = i2s_set_rate,
1798         .clksel_con     = CRU_CLKSELS_CON(3),
1799         CRU_SRC_SET(0x3, 8),
1800         CRU_PARENTS_SET(clk_i2s0_parents),
1801 };
1802
1803 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
1804
1805 static struct clk clk_spdif = {
1806         .name           = "spdif",
1807         .parent         = &clk_spdif_frac_div,
1808         .set_rate       = i2s_set_rate,
1809         .clksel_con = CRU_CLKSELS_CON(5),
1810         CRU_SRC_SET(0x3, 8),
1811         CRU_PARENTS_SET(clk_spdif_parents),
1812 };
1813
1814 /* otgphy setting */
1815 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1816 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1817
1818 static struct clk clk_otgphy0_480m = {
1819         .name           = "otgphy0_480m",
1820         .parent         = &clk_otgphy0,
1821 };
1822 static struct clk clk_otgphy1_480m = {
1823         .name           = "otgphy1_480m",
1824         .parent         = &clk_otgphy1,
1825 };
1826
1827 /* hsicphy setting */
1828 #ifdef ARCH_RK31
1829 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
1830 static struct clk clk_hsicphy_480m = {
1831         .name           = "hsicphy_480m",
1832         .parent         = &clk_otgphy0_480m,
1833         .clksel_con      = CRU_CLKSELS_CON(30),
1834         CRU_SRC_SET(0x3, 0),
1835         CRU_PARENTS_SET(clk_hsicphy_parents),
1836 };
1837 static struct clk clk_hsicphy_12m = {
1838         .name           = "hsicphy_12m",
1839         .parent         = &clk_hsicphy_480m,
1840         .clksel_con     = CRU_CLKSELS_CON(11),
1841         CRU_DIV_SET(0x3f, 8, 64),
1842 };
1843 #endif
1844
1845 /* mac and rmii setting */
1846 // FIXME
1847 static struct clk rmii_clkin = {
1848         .name           = "rmii_clkin",
1849 };
1850 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
1851 static struct clk clk_mac_pll_div = {
1852         .name           = "mac_pll_div",
1853         .parent         = &general_pll_clk,
1854         .mode           = gate_mode,
1855         .gate_idx       = CLK_GATE_MAC_SRC,
1856         .recalc         = clksel_recalc_div,
1857         .set_rate       = clksel_set_rate_freediv,
1858         .clksel_con     = CRU_CLKSELS_CON(21),
1859         CRU_DIV_SET(0x1f, 8, 32),
1860         CRU_SRC_SET(0x1, 0),
1861         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1862 };
1863
1864 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1865 {
1866         if(clk->parent == clk->parents[1]) {
1867                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1868                 return -ENOENT;
1869         } else if(clk->parent == clk->parents[0]) {
1870                 return clk_set_rate_nolock(clk->parents[0], rate);
1871         }
1872         return -ENOENT;
1873 }
1874
1875 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
1876
1877 static struct clk clk_mac_ref = {
1878         .name           = "mac_ref",
1879         .parent         = &clk_mac_pll_div,
1880         .set_rate       = clksel_mac_ref_set_rate,
1881         .clksel_con     = CRU_CLKSELS_CON(21),
1882         CRU_SRC_SET(0x1, 4),
1883         CRU_PARENTS_SET(clk_mac_ref_parents),
1884 };
1885
1886 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1887 {
1888         return clk_set_parent_nolock(clk->parent, parent);
1889 }
1890
1891 static struct clk clk_mii_tx = {
1892         .name           = "mii_tx",
1893         .parent         = &clk_mac_ref,
1894         //.set_parent   = clk_set_mii_tx_parent,
1895         .mode           = gate_mode,
1896         .gate_idx       = CLK_GATE_MAC_LBTEST,
1897 };
1898
1899 /* hsadc and saradc */
1900 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
1901 static struct clk clk_hsadc_pll_div = {
1902         .name           = "hsadc_pll_div",
1903         .parent         = &general_pll_clk,
1904         .mode           = gate_mode,
1905         .gate_idx       = CLK_GATE_HSADC_SRC,
1906         .recalc         = clksel_recalc_div,
1907         .round_rate     = clk_freediv_round_autosel_parents_rate,
1908         .set_rate       = clkset_rate_freediv_autosel_parents,
1909         //.round_rate   = clksel_freediv_round_rate,
1910         //.set_rate     = clksel_set_rate_freediv,
1911         .clksel_con = CRU_CLKSELS_CON(22),
1912         CRU_DIV_SET(0xff, 8, 256),
1913         CRU_SRC_SET(0x1, 0),
1914         CRU_PARENTS_SET(clk_hsadc_pll_parents),
1915 };
1916 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
1917 {
1918         u32 numerator, denominator;
1919         //        clk_hsadc_pll_div->gpll/cpll
1920         //clk->parent->parent
1921         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1922                                 &numerator, &denominator) == 0) {
1923                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1924
1925                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1926
1927                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1928         } else {
1929                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1930                 return -ENOENT;
1931         }
1932         return 0;
1933 }
1934 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
1935 {
1936         u32 numerator, denominator;
1937         u32 i, ret = 0;
1938         //        clk_hsadc_pll_div->gpll/cpll
1939         //clk->parent->parent
1940         for(i = 0; i < 2; i++) {
1941                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
1942                                         &numerator, &denominator) == 0)
1943                         break;
1944         }
1945         if(i >= 2)
1946                 return -ENOENT;
1947
1948         if(clk->parent->parent != clk->parent->parents[i])
1949                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
1950         if(ret == 0) {
1951                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
1952
1953                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1954
1955                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
1956         } else {
1957                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1958                 return -ENOENT;
1959         }
1960         return 0;
1961 }
1962
1963 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
1964 {
1965         u32 numerator, denominator;
1966
1967         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
1968         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1969                                 &numerator, &denominator) == 0)
1970                 return rate;
1971
1972         return 0;
1973 }
1974 static struct clk clk_hsadc_frac_div = {
1975         .name           = "hsadc_frac_div",
1976         .parent         = &clk_hsadc_pll_div,
1977         .mode           = gate_mode,
1978         .recalc         = clksel_recalc_frac,
1979         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
1980         .round_rate     = clk_hsadc_fracdiv_round_rate,
1981         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
1982         .clksel_con     = CRU_CLKSELS_CON(23),
1983 };
1984
1985 #define HSADC_SRC_DIV 0x0
1986 #define HSADC_SRC_FRAC 0x1
1987 #define HSADC_SRC_EXT 0x2
1988 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
1989 {
1990         int ret = -EINVAL;
1991         struct clk *parent;
1992
1993         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
1994                 CLKDATA_DBG("hsadc clk is form ext\n");
1995                 return 0;
1996         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
1997                 parent = clk->parents[HSADC_SRC_DIV];
1998         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
1999                 parent = clk->parents[HSADC_SRC_FRAC];
2000         } else
2001                 parent = clk->parents[HSADC_SRC_DIV];
2002
2003         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2004                         clk->name, rate, parent->name, clk->parent->name);
2005
2006         ret = clk_set_rate_nolock(parent, rate);
2007         if (ret) {
2008                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2009                 return ret;
2010         }
2011         if (clk->parent != parent) {
2012                 ret = clk_set_parent_nolock(clk, parent);
2013                 if (ret) {
2014                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2015                         return ret;
2016                 }
2017         }
2018         return ret;
2019 }
2020
2021 static struct clk clk_hsadc_ext = {
2022         .name           = "hsadc_ext",
2023 };
2024
2025 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2026 static struct clk clk_hsadc_out = {
2027         .name           = "hsadc_out",
2028         .parent         = &clk_hsadc_pll_div,
2029         .set_rate       = clk_hsadc_set_rate,
2030         .clksel_con     = CRU_CLKSELS_CON(22),
2031         CRU_SRC_SET(0x3, 4),
2032         CRU_PARENTS_SET(clk_hsadc_out_parents),
2033 };
2034 static struct clk clk_hsadc_out_inv = {
2035         .name           = "hsadc_out_inv",
2036         .parent         = &clk_hsadc_out,
2037 };
2038
2039 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2040 static struct clk clk_hsadc = {
2041         .name           = "hsadc",
2042         .parent         = &clk_hsadc_out,
2043         .clksel_con     = CRU_CLKSELS_CON(22),
2044         CRU_SRC_SET(0x1, 7),
2045         CRU_PARENTS_SET(clk_hsadc_parents),
2046 };
2047
2048 static struct clk clk_saradc = {
2049         .name           = "saradc",
2050         .parent         = &xin24m,
2051         .mode           = gate_mode,
2052         .recalc         = clksel_recalc_div,
2053         .set_rate       = clksel_set_rate_freediv,
2054         .gate_idx       = CLK_GATE_SARADC_SRC,
2055         .clksel_con     = CRU_CLKSELS_CON(24),
2056         CRU_DIV_SET(0xff, 8, 256),
2057 };
2058
2059 /* smc setting */
2060 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2061 static struct clk clkn_smc = {
2062         .name           = "smc_inv",
2063         .parent         = &clk_smc,
2064 };
2065
2066 /* spi setting */
2067 static struct clk clk_spi0 = {
2068         .name           = "spi0",
2069         .parent         = &pclk_periph,
2070         .mode           = gate_mode,
2071         .recalc         = clksel_recalc_div,
2072         .set_rate       = clksel_set_rate_freediv,
2073         .gate_idx       = CLK_GATE_SPI0_SRC,
2074         .clksel_con     = CRU_CLKSELS_CON(25),
2075         CRU_DIV_SET(0x7f, 0, 128),
2076 };
2077
2078 static struct clk clk_spi1 = {
2079         .name           = "spi1",
2080         .parent         = &pclk_periph,
2081         .mode           = gate_mode,
2082         .recalc         = clksel_recalc_div,
2083         .set_rate       = clksel_set_rate_freediv,
2084         .gate_idx       = CLK_GATE_SPI1_SRC,
2085         .clksel_con     = CRU_CLKSELS_CON(25),
2086         CRU_DIV_SET(0x7f, 8, 128),
2087 };
2088
2089 /* sdmmc/sdio/emmc setting */
2090 static struct clk clk_sdmmc = {
2091         .name           = "sdmmc",
2092         .parent         = &hclk_periph,
2093         .mode           = gate_mode,
2094         .recalc         = clksel_recalc_div,
2095         .set_rate       = clksel_set_rate_even,
2096         .gate_idx       = CLK_GATE_MMC0_SRC,
2097         .clksel_con     = CRU_CLKSELS_CON(11),
2098         CRU_DIV_SET(0x3f, 0, 64),
2099 };
2100
2101 static struct clk clk_sdio = {
2102         .name           = "sdio",
2103         .parent         = &hclk_periph,
2104         .mode           = gate_mode,
2105         .recalc         = clksel_recalc_div,
2106         .set_rate       = clksel_set_rate_even,
2107         .gate_idx       = CLK_GATE_SDIO_SRC,
2108         .clksel_con     = CRU_CLKSELS_CON(12),
2109         CRU_DIV_SET(0x3f, 0, 64),
2110
2111 };
2112
2113 static struct clk clk_emmc = {
2114         .name           = "emmc",
2115         .parent         = &hclk_periph,
2116         .mode           = gate_mode,
2117         .recalc         = clksel_recalc_div,
2118         .set_rate       = clksel_set_rate_freediv,
2119         .gate_idx       = CLK_GATE_EMMC_SRC,
2120         .clksel_con     = CRU_CLKSELS_CON(12),
2121         CRU_DIV_SET(0x3f, 8, 64),
2122 };
2123
2124 /* uart setting */
2125 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2126 static struct clk clk_uart_pll = {
2127         .name           = "uart_pll",
2128         .parent         = &general_pll_clk,
2129         .clksel_con     = CRU_CLKSELS_CON(12),
2130         CRU_SRC_SET(0x1, 15),
2131         CRU_PARENTS_SET(clk_uart_src_parents),
2132 };
2133 static struct clk clk_uart0_div = {
2134         .name           = "uart0_div",
2135         .parent         = &clk_uart_pll,
2136         .mode           = gate_mode,
2137         .gate_idx       = CLK_GATE_UART0_SRC,
2138         .recalc         = clksel_recalc_div,
2139         .set_rate       = clksel_set_rate_freediv,
2140         .round_rate     = clksel_freediv_round_rate,
2141         .clksel_con     = CRU_CLKSELS_CON(13),
2142         CRU_DIV_SET(0x7f, 0, 64),
2143 };
2144 static struct clk clk_uart1_div = {
2145         .name           = "uart1_div",
2146         .parent         = &clk_uart_pll,
2147         .mode           = gate_mode,
2148         .gate_idx       = CLK_GATE_UART1_SRC,
2149         .recalc         = clksel_recalc_div,
2150         .round_rate     = clksel_freediv_round_rate,
2151         .set_rate       = clksel_set_rate_freediv,
2152         .clksel_con     = CRU_CLKSELS_CON(14),
2153         CRU_DIV_SET(0x7f, 0, 64),
2154 };
2155
2156 static struct clk clk_uart2_div = {
2157         .name           = "uart2_div",
2158         .parent         = &clk_uart_pll,
2159         .mode           = gate_mode,
2160         .gate_idx       = CLK_GATE_UART2_SRC,
2161         .recalc         = clksel_recalc_div,
2162         .round_rate     = clksel_freediv_round_rate,
2163         .set_rate       = clksel_set_rate_freediv,
2164         .clksel_con     = CRU_CLKSELS_CON(15),
2165         CRU_DIV_SET(0x7f, 0, 64),
2166 };
2167
2168 static struct clk clk_uart3_div = {
2169         .name           = "uart3_div",
2170         .parent         = &clk_uart_pll,
2171         .mode           = gate_mode,
2172         .gate_idx       = CLK_GATE_UART3_SRC,
2173         .recalc         = clksel_recalc_div,
2174         .round_rate     = clksel_freediv_round_rate,
2175         .set_rate       = clksel_set_rate_freediv,
2176         .clksel_con     = CRU_CLKSELS_CON(16),
2177         CRU_DIV_SET(0x7f, 0, 64),
2178 };
2179 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2180 {
2181         u32 numerator, denominator;
2182         //clk_uart0_div->clk_uart_pll->gpll/cpll
2183         //clk->parent->parent
2184         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2185                                 &numerator, &denominator) == 0) {
2186                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2187
2188                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2189
2190                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2191         } else {
2192                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2193                 return -ENOENT;
2194         }
2195         return 0;
2196 }
2197
2198 static struct clk clk_uart0_frac_div = {
2199         .name           = "uart0_frac_div",
2200         .parent         = &clk_uart0_div,
2201         .mode           = gate_mode,
2202         .recalc         = clksel_recalc_frac,
2203         .set_rate       = clk_uart_fracdiv_set_rate,
2204         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2205         .clksel_con     = CRU_CLKSELS_CON(17),
2206 };
2207 static struct clk clk_uart1_frac_div = {
2208         .name           = "uart1_frac_div",
2209         .parent         = &clk_uart1_div,
2210         .mode           = gate_mode,
2211         .recalc         = clksel_recalc_frac,
2212         .set_rate       = clk_uart_fracdiv_set_rate,
2213         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2214         .clksel_con     = CRU_CLKSELS_CON(18),
2215 };
2216 static struct clk clk_uart2_frac_div = {
2217         .name           = "uart2_frac_div",
2218         .mode           = gate_mode,
2219         .parent         = &clk_uart2_div,
2220         .recalc         = clksel_recalc_frac,
2221         .set_rate       = clk_uart_fracdiv_set_rate,
2222         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2223         .clksel_con     = CRU_CLKSELS_CON(19),
2224 };
2225 static struct clk clk_uart3_frac_div = {
2226         .name           = "uart3_frac_div",
2227         .parent         = &clk_uart3_div,
2228         .mode           = gate_mode,
2229         .recalc         = clksel_recalc_frac,
2230         .set_rate       = clk_uart_fracdiv_set_rate,
2231         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2232         .clksel_con     = CRU_CLKSELS_CON(20),
2233 };
2234
2235 #define UART_SRC_DIV 0
2236 #define UART_SRC_FRAC 1
2237 #define UART_SRC_24M 2
2238
2239 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2240 {
2241         int ret = 0;
2242         struct clk *parent;
2243
2244         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2245                 parent = clk->parents[UART_SRC_24M];
2246         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2247                 parent = clk->parents[UART_SRC_DIV];
2248         } else {
2249                 parent = clk->parents[UART_SRC_FRAC];
2250         }
2251
2252         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2253                         clk->name, rate, parent->name, clk->parent->name);
2254
2255         if(parent != clk->parents[UART_SRC_24M]) {
2256                 ret = clk_set_rate_nolock(parent, rate);
2257                 if (ret) {
2258                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2259                         return ret;
2260                 }
2261         }
2262
2263         if (clk->parent != parent) {
2264                 ret = clk_set_parent_nolock(clk, parent);
2265                 if (ret) {
2266                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2267                         return ret;
2268                 }
2269         }
2270
2271         return ret;
2272 }
2273
2274 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2275 static struct clk clk_uart0 = {
2276         .name           = "uart0",
2277         .set_rate       = clk_uart_set_rate,
2278         .clksel_con     = CRU_CLKSELS_CON(13),
2279         CRU_SRC_SET(0x3, 8),
2280         CRU_PARENTS_SET(clk_uart0_parents),
2281 };
2282
2283 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2284 static struct clk clk_uart1 = {
2285         .name           = "uart1",
2286         .set_rate       = clk_uart_set_rate,
2287         .clksel_con     = CRU_CLKSELS_CON(14),
2288         CRU_SRC_SET(0x3, 8),
2289         CRU_PARENTS_SET(clk_uart1_parents),
2290 };
2291
2292 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2293 static struct clk clk_uart2 = {
2294         .name           = "uart2",
2295         .set_rate       = clk_uart_set_rate,
2296         .clksel_con     = CRU_CLKSELS_CON(15),
2297         CRU_SRC_SET(0x3, 8),
2298         CRU_PARENTS_SET(clk_uart2_parents),
2299 };
2300 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2301 static struct clk clk_uart3 = {
2302         .name           = "uart3",
2303         .set_rate       = clk_uart_set_rate,
2304         .clksel_con     = CRU_CLKSELS_CON(16),
2305         CRU_SRC_SET(0x3, 8),
2306         CRU_PARENTS_SET(clk_uart3_parents),
2307 };
2308
2309 /* timer setting */
2310 GATE_CLK(timer0, xin24m, TIMER0);
2311 GATE_CLK(timer1, xin24m, TIMER1);
2312 GATE_CLK(timer2, xin24m, TIMER2);
2313 GATE_CLK(timer3, xin24m, TIMER3);
2314 GATE_CLK(timer4, xin24m, TIMER4);
2315 GATE_CLK(timer5, xin24m, TIMER5);
2316 GATE_CLK(timer6, xin24m, TIMER6);
2317
2318 /*********************power domain*******************************/
2319 #if 1
2320 #ifdef RK30_CLK_OFFBOARD_TEST
2321 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2322 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2323 #else
2324 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2325 #define _pmu_set_power_domain pmu_set_power_domain
2326 #endif
2327
2328 static int pd_video_mode(struct clk *clk, int on)
2329 {
2330         u32 gate[3];
2331         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2332         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2333         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2334         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2335         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2336         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2337         pmu_set_power_domain(PD_VIDEO, on);
2338         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2339         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2340         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2341         return 0;
2342 }
2343
2344 static struct clk pd_video = {
2345         .name   = "pd_video",
2346         .flags  = IS_PD,
2347         .mode   = pd_video_mode,
2348         .gate_idx       = PD_VIDEO,
2349 };
2350 static int pd_display_mode(struct clk *clk, int on)
2351 {
2352         u32 gate[10];
2353         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2354         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2355         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2356         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2357         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2358         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2359         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2360         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2361         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2362         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2363         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2364         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2365         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2366         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2367         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2368         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2369         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2370         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2371         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2372         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2373         pmu_set_power_domain(PD_VIO, on);
2374         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2375         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2376         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2377         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2378         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2379         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2380         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2381         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2382         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2383         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2384         return 0;
2385 }
2386
2387 static struct clk pd_display = {
2388         .name   = "pd_vio",
2389         .flags  = IS_PD,
2390         .mode   = pd_display_mode,
2391         .gate_idx       = PD_VIO,
2392 };
2393 static struct clk pd_lcdc0 = {
2394         .parent = &pd_display,
2395         .name   = "pd_lcdc0",
2396 };
2397 static struct clk pd_lcdc1 = {
2398         .parent = &pd_display,
2399         .name   = "pd_lcdc1",
2400 };
2401 static struct clk pd_cif0 = {
2402         .parent = &pd_display,
2403         .name   = "pd_cif0",
2404 };
2405 static struct clk pd_rga = {
2406         .parent = &pd_display,
2407         .name   = "pd_rga",
2408 };
2409 static struct clk pd_ipp = {
2410         .parent = &pd_display,
2411         .name   = "pd_ipp",
2412 };
2413 static struct clk pd_hdmi = {
2414         .parent = &pd_display,
2415         .name   = "pd_hdmi",
2416 };
2417
2418
2419 static int pd_gpu_mode(struct clk *clk, int on)
2420 {
2421         u32 gate[3];
2422         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2423         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2424         pmu_set_power_domain(PD_GPU, on);
2425         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2426         return 0;
2427 }
2428
2429 static struct clk pd_gpu = {
2430         .name   = "pd_gpu",
2431         .flags  = IS_PD,
2432         .mode   = pd_gpu_mode,
2433         .gate_idx       = PD_GPU,
2434 };
2435
2436 static int pm_off_mode(struct clk *clk, int on)
2437 {
2438         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2439         return 0;
2440 }
2441 static struct clk pd_peri = {
2442         .name   = "pd_peri",
2443         .flags  = IS_PD,
2444         .mode   = pm_off_mode,
2445         .gate_idx       = PD_PERI,
2446 };
2447
2448
2449 #define PD_CLK(name) \
2450 {\
2451         .dev_id = NULL,\
2452         .con_id = #name,\
2453         .clk = &name,\
2454 }
2455
2456 #endif
2457 /************************rk30 fixed div clock****************************************/
2458
2459 /*************************aclk_cpu***********************/
2460
2461 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2462 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2463 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2464
2465 /*************************hclk_cpu***********************/
2466
2467 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2468 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2469 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2470 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2471 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2472 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2473 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2474 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2475 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2476 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2477 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2478 GATE_CLK(hclk_imem0,    hclk_cpu,       HCLK_IMEM0);
2479 GATE_CLK(hclk_imem1,    hclk_cpu,       HCLK_IMEM1);
2480
2481 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2482 GATE_CLK(pclk_uart0,    ahb2apb_cpu, PCLK_UART0);
2483 GATE_CLK(pclk_uart1,    ahb2apb_cpu, PCLK_UART1);
2484 /*************************pclk_cpu***********************/
2485 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2486 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2487 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2488 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2489 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2490 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2491 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2492 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2493 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2494 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2495 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2496 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2497 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2498 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2499 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2500
2501 /*************************aclk_periph***********************/
2502
2503 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2504 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2505 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2506 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2507 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2508 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2509
2510 /*************************hclk_periph***********************/
2511 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2512 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2513 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2514 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2515 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2516 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2517 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2518 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2519 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2520 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2521 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2522 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2523 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2524 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2525 /*************************pclk_periph***********************/
2526 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2527 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2528 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2529 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2530 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2531 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2532 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2533 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2534 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2535 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2536 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2537 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2538 /*************************aclk_lcdc0***********************/
2539
2540 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2541 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2542 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2543 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2544
2545 /*************************aclk_lcdc0***********************/
2546
2547 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2548 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2549 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2550
2551
2552 #if 1
2553 #define CLK(dev, con, ck) \
2554 {\
2555         .dev_id = dev,\
2556         .con_id = con,\
2557         .clk = ck,\
2558 }
2559
2560
2561 #define CLK1(name) \
2562 {\
2563         .dev_id = NULL,\
2564         .con_id = #name,\
2565         .clk = &clk_##name,\
2566 }
2567
2568 #endif
2569
2570 static struct clk_lookup clks[] = {
2571         CLK(NULL, "xin24m", &xin24m),
2572         //CLK(NULL, "xin27m", &xin27m),
2573         CLK(NULL, "xin12m", &clk_12m),
2574         CLK(NULL, "arm_pll", &arm_pll_clk),
2575         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2576         CLK(NULL, "codec_pll", &codec_pll_clk),
2577         CLK(NULL, "general_pll", &general_pll_clk),
2578
2579         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2580         CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2581
2582         CLK(NULL, "ddr", &clk_ddr),
2583         CLK(NULL, "cpu", &clk_core),
2584         CLK1(l2c),
2585         CLK1(core_dbg),
2586         CLK("smp_twd", NULL, &core_periph),
2587         CLK(NULL, "aclk_core", &aclk_core),
2588
2589         CLK(NULL, "logic", &clk_cpu_div),
2590         CLK(NULL, "aclk_cpu", &aclk_cpu),
2591         CLK(NULL, "pclk_cpu", &pclk_cpu),
2592         CLK(NULL, "atclk_cpu", &atclk_cpu),
2593         CLK(NULL, "hclk_cpu", &hclk_cpu),
2594         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2595
2596         CLK(NULL, "gpu",        &aclk_gpu),
2597
2598         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2599         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2600         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2601         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2602
2603         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2604         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2605
2606         CLK(NULL, "aclk_periph", &aclk_periph),
2607         CLK(NULL, "pclk_periph", &pclk_periph),
2608         CLK(NULL, "hclk_periph", &hclk_periph),
2609
2610         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2611         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2612
2613         CLK(NULL, "cif_out_pll", &cif_out_pll),
2614         CLK(NULL, "cif0_out_div", &cif0_out_div),
2615         CLK(NULL, "cif0_out", &cif0_out),
2616
2617         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2618         CLK(NULL, "inv_cif0", &inv_cif0),
2619         CLK(NULL, "cif0_in", &cif0_in),
2620
2621         CLK1(i2s_pll),
2622         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2623         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2624         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2625
2626         // actually no i2s1
2627         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2628         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2629         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2630
2631
2632         CLK1(spdif_div),
2633         CLK1(spdif_frac_div),
2634         CLK1(spdif),
2635
2636         CLK1(otgphy0),
2637         CLK1(otgphy1),
2638         CLK1(otgphy0_480m),
2639         CLK1(otgphy1_480m),
2640         CLK1(hsicphy_480m),
2641         CLK1(hsicphy_12m),
2642
2643         CLK(NULL, "rmii_clkin", &rmii_clkin),
2644         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2645         CLK1(mac_ref),
2646         CLK1(mii_tx),
2647
2648         CLK1(hsadc_pll_div),
2649         CLK1(hsadc_frac_div),
2650         CLK1(hsadc_ext),
2651         CLK1(hsadc_out),
2652         CLK1(hsadc_out_inv),
2653         CLK1(hsadc),
2654
2655         CLK1(saradc),
2656
2657         CLK1(smc),
2658         CLK(NULL, "smc_inv",    &clkn_smc),
2659
2660         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2661         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2662
2663         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2664         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2665         CLK1(emmc),
2666
2667         CLK1(uart_pll),
2668         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2669         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2670         CLK("rk_serial.0", "uart", &clk_uart0),
2671         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2672         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2673         CLK("rk_serial.1", "uart", &clk_uart1),
2674         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2675         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2676         CLK("rk_serial.2", "uart", &clk_uart2),
2677         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2678         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2679         CLK("rk_serial.3", "uart", &clk_uart3),
2680
2681         CLK1(timer0),
2682         CLK1(timer1),
2683         CLK1(timer2),
2684         CLK1(timer3),
2685         CLK1(timer4),
2686         CLK1(timer5),
2687         CLK1(timer6),
2688
2689         /*************************aclk_cpu***********************/
2690         CLK1(dma1),
2691         CLK1(intmem),
2692         CLK1(aclk_strc_sys),
2693
2694         /*************************hclk_cpu***********************/
2695         CLK1(rom),
2696         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2697         // actually no i2s1
2698         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2699         CLK1(hclk_spdif),
2700         CLK1(hclk_cpubus),
2701         CLK1(hclk_ahb2apb),
2702         CLK1(hclk_vio_bus),
2703         CLK1(hclk_lcdc0),
2704         CLK1(hclk_lcdc1),
2705         CLK1(hclk_cif0),
2706         CLK1(hclk_ipp),
2707         CLK1(hclk_rga),
2708         CLK1(hclk_imem0),
2709         CLK1(hclk_imem1),
2710
2711         /*************************pclk_cpu***********************/
2712         CLK1(pwm01),
2713         CLK1(pclk_timer0),
2714         CLK1(pclk_timer2),
2715         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2716         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2717         CLK1(gpio0),
2718         CLK1(gpio1),
2719         CLK1(gpio2),
2720         CLK1(efuse),
2721         CLK1(tzpc),
2722         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2723         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2724         CLK1(pclk_ddrupctl),
2725         CLK1(pclk_ddrpubl),
2726         CLK1(dbg),
2727         CLK1(grf),
2728         CLK1(pmu),
2729
2730         /*************************aclk_periph***********************/
2731         CLK1(dma2),
2732         CLK1(aclk_smc),
2733         CLK1(aclk_gps),
2734         CLK1(aclk_peri_niu),
2735         CLK1(aclk_cpu_peri),
2736         CLK1(aclk_peri_axi_matrix),
2737
2738         /*************************hclk_periph***********************/
2739         CLK1(hclk_peri_axi_matrix),
2740         CLK1(hclk_peri_ahb_arbi),
2741         CLK1(hclk_emem_peri),
2742         CLK1(hclk_mac),
2743         CLK1(nandc),
2744         CLK1(hclk_usb_peri),
2745         CLK1(hclk_otg0),
2746         CLK1(hclk_otg1),
2747         CLK1(hclk_hsic),
2748         CLK1(hclk_hsadc),
2749         CLK1(hclk_pidfilter),
2750         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2751         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2752         CLK1(hclk_emmc),
2753
2754         /*************************pclk_periph***********************/
2755         CLK1(pclk_peri_axi_matrix),
2756         CLK1(pwm23),
2757         CLK1(wdt),
2758         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2759         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2760         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2761         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2762         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2763         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2764         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2765         CLK1(gpio3),
2766         CLK1(pclk_saradc),
2767
2768         /*************************aclk_lcdc0***********************/
2769         CLK1(aclk_vio0),
2770         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2771         CLK1(aclk_cif0),
2772         CLK1(aclk_ipp),
2773
2774         /*************************aclk_lcdc1***********************/
2775         CLK1(aclk_vio1),
2776         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2777         CLK1(aclk_rga),
2778         /************************power domain**********************/
2779
2780         PD_CLK(pd_peri),
2781         PD_CLK(pd_display),
2782         PD_CLK(pd_lcdc0),
2783         PD_CLK(pd_lcdc1),
2784         PD_CLK(pd_cif0),
2785         //PD_CLK(pd_cif1),
2786         PD_CLK(pd_rga),
2787         PD_CLK(pd_ipp),
2788         //PD_CLK(pd_video),
2789         PD_CLK(pd_gpu),
2790         //PD_CLK(pd_dbg),
2791 };
2792 static void __init rk30_init_enable_clocks(void)
2793 {
2794         #if 0
2795         //clk_enable_nolock(&xin24m);
2796         //clk_enable_nolock(&clk_12m);
2797         //clk_enable_nolock(&arm_pll_clk);
2798         //clk_enable_nolock(&ddr_pll_clk);
2799         //clk_enable_nolock(&codec_pll_clk);
2800         //clk_enable_nolock(&general_pll_clk);
2801         #endif
2802         clk_enable_nolock(&clk_ddr);
2803         //clk_enable_nolock(&clk_core);
2804         clk_enable_nolock(&clk_cpu_div);
2805         clk_enable_nolock(&clk_core_gpll_path);
2806         clk_enable_nolock(&clk_l2c);
2807         clk_enable_nolock(&clk_core_dbg);
2808         clk_enable_nolock(&core_periph);
2809         clk_enable_nolock(&aclk_core);
2810         //clk_enable_nolock(&aclk_cpu);
2811         //clk_enable_nolock(&pclk_cpu);
2812         clk_enable_nolock(&atclk_cpu);
2813         //clk_enable_nolock(&hclk_cpu);
2814         clk_enable_nolock(&ahb2apb_cpu);
2815         #if 0
2816          clk_enable_nolock(&clk_gpu);
2817          clk_enable_nolock(&aclk_gpu);
2818          clk_enable_nolock(&aclk_gpu_slv);
2819          clk_enable_nolock(&aclk_gpu_mst);
2820
2821          clk_enable_nolock(&aclk_vepu);
2822          clk_enable_nolock(&hclk_vepu);
2823          clk_enable_nolock(&aclk_vdpu);
2824          clk_enable_nolock(&hclk_vdpu);
2825
2826          clk_enable_nolock(&aclk_lcdc0_pre);
2827          clk_enable_nolock(&aclk_lcdc1_pre);
2828
2829          clk_enable_nolock(&aclk_periph);
2830         clk_enable_nolock(&pclk_periph);
2831         clk_enable_nolock(&hclk_periph);
2832         #endif
2833         #if 0
2834          clk_enable_nolock(&dclk_lcdc0);
2835          clk_enable_nolock(&dclk_lcdc1);
2836
2837          clk_enable_nolock(&cif_out_pll);
2838          clk_enable_nolock(&cif0_out_div);
2839
2840          clk_enable_nolock(&cif0_out);
2841          clk_enable_nolock(&pclkin_cif0);
2842          clk_enable_nolock(&inv_cif0);
2843          clk_enable_nolock(&cif0_in);
2844
2845          clk_enable_nolock(&clk_i2s_pll);
2846          clk_enable_nolock(&clk_i2s0_div);
2847          clk_enable_nolock(&clk_i2s0_frac_div);
2848          clk_enable_nolock(&clk_i2s0);
2849
2850           actually no i2s1
2851          clk_enable_nolock(&clk_i2s0_div);
2852          clk_enable_nolock(&clk_i2s0_frac_div);
2853          clk_enable_nolock(&clk_i2s0);
2854
2855         clk_enable_nolock(&clk_spdif_div);
2856         clk_enable_nolock(&clk_spdif_frac_div);
2857         clk_enable_nolock(&clk_spdif);
2858         #endif
2859         #if 0
2860         clk_enable_nolock(&clk_otgphy0);
2861         clk_enable_nolock(&clk_otgphy1);
2862         clk_enable_nolock(&clk_otgphy0_480m);
2863         clk_enable_nolock(&clk_otgphy1_480m);
2864         clk_enable_nolock(&clk_hsicphy_480m);
2865         clk_enable_nolock(&clk_hsicphy_12m);
2866         #endif
2867
2868         #if 0
2869         clk_enable_nolock(&rmii_clkin);
2870         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
2871         clk_enable_nolock(&clk_mac_ref);
2872         clk_enable_nolock(&clk_mii_tx);
2873         #endif
2874
2875         #if 0
2876         clk_enable_nolock(&clk_hsadc_pll_div);
2877         clk_enable_nolock(&clk_hsadc_frac_div);
2878         clk_enable_nolock(&clk_hsadc_ext);
2879         clk_enable_nolock(&clk_hsadc_out);
2880         clk_enable_nolock(&clk_hsadc_out_inv);
2881         clk_enable_nolock(&clk_hsadc);
2882
2883         clk_enable_nolock(&clk_saradc);
2884         #endif
2885         /*
2886         clk_enable_nolock(&clk_smc);
2887         clk_enable_nolock(&clkn_smc);
2888         */
2889         /*
2890         clk_enable_nolock(&clk_spi0);
2891         clk_enable_nolock(&clk_spi1);
2892         */
2893         /*
2894         clk_enable_nolock(&clk_sdmmc);
2895         clk_enable_nolock(&clk_sdio);
2896         clk_enable_nolock(&clk_emmc);
2897         */
2898         #if 0
2899         clk_enable_nolock(&clk_uart_pll);
2900         clk_enable_nolock(&clk_uart0_div);
2901         clk_enable_nolock(&clk_uart0_frac_div);
2902         clk_enable_nolock(&clk_uart0);
2903         clk_enable_nolock(&clk_uart1_div);
2904         clk_enable_nolock(&clk_uart1_frac_div);
2905         clk_enable_nolock(&clk_uart1);
2906         clk_enable_nolock(&clk_uart2_div);
2907         clk_enable_nolock(&clk_uart2_frac_div);
2908         clk_enable_nolock(&clk_uart2);
2909         clk_enable_nolock(&clk_uart3_div);
2910         clk_enable_nolock(&clk_uart3_frac_div);
2911         clk_enable_nolock(&clk_uart3);
2912         #endif
2913         #if CONFIG_RK_DEBUG_UART == 0
2914                 clk_enable_nolock(&clk_uart0);
2915                 clk_enable_nolock(&clk_pclk_uart0);
2916         #elif CONFIG_RK_DEBUG_UART == 1
2917                 clk_enable_nolock(&clk_uart1);
2918                 clk_enable_nolock(&clk_pclk_uart1);
2919
2920         #elif CONFIG_RK_DEBUG_UART == 2
2921                 clk_enable_nolock(&clk_uart2);
2922                 clk_enable_nolock(&clk_pclk_uart2);
2923
2924         #elif CONFIG_RK_DEBUG_UART == 3
2925                 clk_enable_nolock(&clk_uart3);
2926                 clk_enable_nolock(&clk_pclk_uart3);
2927
2928         #endif
2929         #if 0
2930         clk_enable_nolock(&clk_timer0);
2931         clk_enable_nolock(&clk_timer1);
2932         clk_enable_nolock(&clk_timer2);
2933         #endif
2934
2935         /*************************aclk_cpu***********************/
2936         clk_enable_nolock(&clk_dma1);
2937         clk_enable_nolock(&clk_intmem);
2938         clk_enable_nolock(&clk_aclk_strc_sys);
2939
2940         /*************************hclk_cpu***********************/
2941         clk_enable_nolock(&clk_rom);
2942         #if 0
2943         clk_enable_nolock(&clk_hclk_i2s0_2ch);
2944         // actually no i2s1
2945         clk_enable_nolock(&clk_hclk_i2s0_2ch);
2946         clk_enable_nolock(&clk_hclk_spdif);
2947         #endif
2948         clk_enable_nolock(&clk_hclk_cpubus);
2949         clk_enable_nolock(&clk_hclk_ahb2apb);
2950         clk_enable_nolock(&clk_hclk_vio_bus);
2951         #if 0
2952         clk_enable_nolock(&clk_hclk_lcdc0);
2953         clk_enable_nolock(&clk_hclk_lcdc1);
2954         clk_enable_nolock(&clk_hclk_cif0);
2955         clk_enable_nolock(&clk_hclk_ipp);
2956         clk_enable_nolock(&clk_hclk_rga);
2957         #endif
2958         clk_enable_nolock(&clk_hclk_imem0);
2959         clk_enable_nolock(&clk_hclk_imem1);
2960
2961         /*************************pclk_cpu***********************/
2962         #if 0
2963         clk_enable_nolock(&clk_pwm01);
2964         clk_enable_nolock(&clk_pclk_timer0);
2965         clk_enable_nolock(&clk_pclk_timer1);
2966         clk_enable_nolock(&clk_pclk_timer2);
2967         clk_enable_nolock(&clk_i2c0);
2968         clk_enable_nolock(&clk_i2c1);
2969         clk_enable_nolock(&clk_gpio0);
2970         clk_enable_nolock(&clk_gpio1);
2971         clk_enable_nolock(&clk_gpio2);
2972         clk_enable_nolock(&clk_efuse);
2973         #endif
2974         clk_enable_nolock(&clk_tzpc);
2975         //clk_enable_nolock(&clk_pclk_uart0);
2976         //clk_enable_nolock(&clk_pclk_uart1);
2977         clk_enable_nolock(&clk_pclk_ddrupctl);
2978         clk_enable_nolock(&clk_pclk_ddrpubl);
2979         clk_enable_nolock(&clk_dbg);
2980         clk_enable_nolock(&clk_grf);
2981         clk_enable_nolock(&clk_pmu);
2982
2983         /*************************aclk_periph***********************/
2984         clk_enable_nolock(&clk_dma2);
2985         clk_enable_nolock(&clk_aclk_smc);
2986         clk_enable_nolock(&clk_aclk_peri_niu);
2987         clk_enable_nolock(&clk_aclk_cpu_peri);
2988         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
2989
2990         /*************************hclk_periph***********************/
2991         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
2992         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
2993         clk_enable_nolock(&clk_hclk_emem_peri);
2994         //clk_enable_nolock(&clk_hclk_mac);
2995         clk_enable_nolock(&clk_nandc);
2996         clk_enable_nolock(&clk_hclk_usb_peri);
2997         #if 0
2998         clk_enable_nolock(&clk_hclk_otg0);
2999         clk_enable_nolock(&clk_hclk_otg1);
3000         clk_enable_nolock(&clk_hclk_hsic);
3001         clk_enable_nolock(&clk_hclk_gps);
3002         clk_enable_nolock(&clk_hclk_hsadc);
3003         clk_enable_nolock(&clk_hclk_pidfilter);
3004         clk_enable_nolock(&clk_hclk_sdmmc);
3005         clk_enable_nolock(&clk_hclk_sdio);
3006         clk_enable_nolock(&clk_hclk_emmc);
3007         #endif
3008
3009         /*************************pclk_periph***********************/
3010         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3011         #if 0
3012         clk_enable_nolock(&clk_pwm23);
3013         clk_enable_nolock(&clk_wdt);
3014         clk_enable_nolock(&clk_pclk_spi0);
3015         clk_enable_nolock(&clk_pclk_spi1);
3016         clk_enable_nolock(&clk_pclk_uart2);
3017         clk_enable_nolock(&clk_pclk_uart3);
3018         #endif
3019         #if 0
3020         clk_enable_nolock(&clk_i2c2);
3021         clk_enable_nolock(&clk_i2c3);
3022         clk_enable_nolock(&clk_i2c4);
3023         clk_enable_nolock(&clk_gpio3);
3024         clk_enable_nolock(&clk_pclk_saradc);
3025         #endif
3026         /*************************aclk_lcdc0***********************/
3027 #if 1
3028         //clk_enable_nolock(&clk_aclk_vio0);
3029         //clk_enable_nolock(&clk_aclk_lcdc0);
3030         //clk_enable_nolock(&clk_aclk_cif0);
3031         //clk_enable_nolock(&clk_aclk_ipp);
3032 #endif
3033         /*************************aclk_lcdc1***********************/
3034 #if 1
3035         //clk_enable_nolock(&clk_aclk_vio1);
3036         //clk_enable_nolock(&clk_aclk_lcdc1);
3037         //clk_enable_nolock(&clk_aclk_rga);
3038 #endif
3039         /************************power domain**********************/
3040
3041 }
3042 static void periph_clk_set_init(void)
3043 {
3044         unsigned long aclk_p, hclk_p, pclk_p;
3045         unsigned long ppll_rate = general_pll_clk.rate;
3046         //aclk 148.5
3047
3048         /* general pll */
3049         switch (ppll_rate) {
3050                 case 148500* KHZ:
3051                         aclk_p = 148500 * KHZ;
3052                         hclk_p = aclk_p >> 1;
3053                         pclk_p = aclk_p >> 2;
3054                         break;
3055                 case 1188*MHZ:
3056                         aclk_p = aclk_p >> 3; // 0
3057                         hclk_p = aclk_p >> 1;
3058                         pclk_p = aclk_p >> 2;
3059
3060                 case 297 * MHZ:
3061                         aclk_p = ppll_rate >> 1;
3062                         hclk_p = aclk_p >> 0;
3063                         pclk_p = aclk_p >> 1;
3064                         break;
3065
3066                 case 300 * MHZ:
3067                         aclk_p = ppll_rate >> 1;
3068                         hclk_p = aclk_p >> 0;
3069                         pclk_p = aclk_p >> 1;
3070                         break;
3071                 case 594 * MHZ:
3072                         aclk_p = ppll_rate >> 2;
3073                         hclk_p = aclk_p >> 0;
3074                         pclk_p = aclk_p >> 1;
3075                         break;
3076                 default:
3077                         aclk_p = 150 * MHZ;
3078                         hclk_p = 150 * MHZ;
3079                         pclk_p = 75 * MHZ;
3080                         break;
3081         }
3082         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3083         clk_set_rate_nolock(&aclk_periph, aclk_p);
3084         clk_set_rate_nolock(&hclk_periph, hclk_p);
3085         clk_set_rate_nolock(&pclk_periph, pclk_p);
3086 }
3087
3088 static void cpu_axi_init(void)
3089 {
3090         unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3091         unsigned long gpll_rate = general_pll_clk.rate;
3092
3093         switch (gpll_rate) {
3094                 case 297 * MHZ:
3095                         cpu_div_rate = gpll_rate;
3096                         aclk_cpu_rate = cpu_div_rate >> 0;
3097                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3098                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3099                         break;
3100
3101                 case 594 * MHZ:
3102                         cpu_div_rate = gpll_rate >> 1;
3103                         aclk_cpu_rate = cpu_div_rate >> 0;
3104                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3105                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3106                         break;
3107                 default:
3108                         aclk_cpu_rate = 150 * MHZ;
3109                         hclk_cpu_rate = 150 * MHZ;
3110                         pclk_cpu_rate = 75 * MHZ;
3111                         break;
3112         }
3113         ahb2apb_cpu_rate = pclk_cpu_rate;
3114
3115         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3116         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3117         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3118         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3119         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3120         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3121 }
3122
3123 void rk30_clock_common_i2s_init(void)
3124 {
3125         unsigned long i2s_rate;
3126         //20 times
3127         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3128                 i2s_rate = 49152000;
3129         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3130                 i2s_rate = 24576000;
3131         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3132                 i2s_rate = 22579000;
3133         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3134                 i2s_rate = 12288000;
3135         } else {
3136                 i2s_rate = 49152000;
3137         }
3138
3139         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3140                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3141         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3142                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3143         } else {
3144                 if(general_pll_clk.rate > codec_pll_clk.rate)
3145                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3146                 else
3147                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3148         }
3149 }
3150
3151 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3152 {
3153
3154         //general
3155         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3156         //code pll
3157         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3158
3159         cpu_axi_init();
3160         clk_set_rate_nolock(&clk_core, 816 * MHZ);
3161         //periph clk
3162         periph_clk_set_init();
3163
3164         //i2s
3165         rk30_clock_common_i2s_init();
3166
3167         // spi
3168         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3169         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3170
3171         // uart
3172         if(rk30_clock_flags & CLK_FLG_UART_1_3M)
3173                 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3174         else
3175                 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3176         //mac
3177         if(!(gpll_rate % (50 * MHZ)))
3178                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3179         else if(!(ddr_pll_clk.rate % (50 * MHZ)))
3180                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3181         else
3182                 CLKDATA_ERR("mac can't get 50mhz\n");
3183
3184         //hsadc
3185         //auto pll sel
3186         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3187
3188         //lcdc0 lcd auto sel pll
3189         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3190         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3191
3192         //cif
3193         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3194
3195         //axi lcdc auto sel
3196         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3197         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3198         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3199         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3200
3201         //axi vepu auto sel
3202         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3203         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3204
3205         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3206         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3207         //gpu auto sel
3208         clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
3209         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3210
3211         clk_set_rate_nolock(&clk_uart0, 49500000);
3212         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3213         clk_set_rate_nolock(&clk_sdio, 24750000);
3214
3215 }
3216
3217 static struct clk def_ops_clk = {
3218         .get_parent = clksel_get_parent,
3219         .set_parent = clksel_set_parent,
3220 };
3221
3222 #ifdef CONFIG_PROC_FS
3223 struct clk_dump_ops dump_ops;
3224 #endif
3225 void rk_dump_clock_info(void);
3226
3227 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3228 {
3229         struct clk_lookup *lk;
3230
3231         clk_register_dump_ops(&dump_ops);
3232         clk_register_default_ops_clk(&def_ops_clk);
3233         rk30_clock_flags = flags;
3234         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3235 #ifdef RK30_CLK_OFFBOARD_TEST
3236                 rk30_clkdev_add(lk);
3237 #else
3238                 clkdev_add(lk);
3239 #endif
3240                 clk_register(lk->clk);
3241         }
3242         clk_recalculate_root_clocks_nolock();
3243
3244         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3245
3246         /*
3247          * Only enable those clocks we will need, let the drivers
3248          * enable other clocks as necessary
3249          */
3250         rk30_init_enable_clocks();
3251 #if 0
3252         // print loader config
3253         CLKDATA_DBG("%s clks register dbg start\n", __func__);
3254         rk_dump_clock_info();
3255         rk30_clk_dump_regs();
3256
3257         CLKDATA_DBG("%s clks register dbg end\n", __func__);
3258 #endif
3259         /*
3260          * Disable any unused clocks left on by the bootloader
3261          */
3262         //clk_disable_unused();
3263         rk30_clock_common_init(gpll, cpll);
3264         preset_lpj = loops_per_jiffy;
3265
3266         //gpio6_b7
3267         //regfile_writel(0xc0004000,0x10c);
3268         //cru_writel(0x07000000,CRU_MISC_CON);
3269
3270 }
3271 extern int rk3188_dvfs_init(void);
3272
3273 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3274 {
3275         printk("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n", gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3276         _rk30_clock_data_init(gpll, cpll, flags);
3277         rk3188_dvfs_init();
3278 }
3279
3280 /*
3281  * You can override arm_clk rate with armclk= cmdline option.
3282  */
3283 static int __init armclk_setup(char *str)
3284 {
3285         get_option(&str, &armclk);
3286
3287         if (!armclk)
3288                 return 0;
3289         if (armclk < 10000)
3290                 armclk *= MHZ;
3291         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3292         return 0;
3293 }
3294 #ifndef RK30_CLK_OFFBOARD_TEST
3295 early_param("armclk", armclk_setup);
3296 #endif
3297
3298
3299 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3300 {
3301         struct clk *ck;
3302         int i;
3303         unsigned long rate = clk->rate;
3304         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3305         for (i = 0; i < deep; i++)
3306                 printk("    ");
3307
3308         printk("%-11s ", clk->name);
3309 #ifndef RK30_CLK_OFFBOARD_TEST
3310         if (clk->flags & IS_PD) {
3311                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3312         }
3313 #endif
3314         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3315                 int idx = clk->gate_idx;
3316                 u32 v;
3317                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3318                 printk("%s ", v ? "off" : "on ");
3319         }
3320
3321         if (clk->pll) {
3322                 u32 pll_mode;
3323                 u32 pll_id = clk->pll->id;
3324                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3325                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3326                         printk("slow   ");
3327                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3328                         printk("normal ");
3329                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3330                         printk("deep   ");
3331
3332                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3333                         printk("bypass ");
3334         } else if(clk == &clk_ddr) {
3335                 rate = clk->recalc(clk);
3336         }
3337
3338         if (rate >= MHZ) {
3339                 if (rate % MHZ)
3340                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3341                 else
3342                         printk("%ld MHz", rate / MHZ);
3343         } else if (rate >= KHZ) {
3344                 if (rate % KHZ)
3345                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3346                 else
3347                         printk("%ld KHz", rate / KHZ);
3348         } else {
3349                 printk("%ld Hz", rate);
3350         }
3351
3352         printk(" usecount = %d", clk->usecount);
3353
3354         if (clk->parent)
3355                 printk(" parent = %s", clk->parent->name);
3356
3357         printk("\n");
3358
3359         list_for_each_entry(ck, root_clocks, node) {
3360                 if (ck->parent == clk)
3361                         rk_dump_clock(ck, deep + 1, root_clocks);
3362         }
3363 }
3364
3365 #if 1
3366 struct list_head *get_rk_clocks_head(void);
3367
3368 void rk_dump_clock_info(void)
3369 {
3370         struct clk* clk;
3371         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3372                 if (!clk->parent)
3373                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3374         }
3375 }
3376 #endif
3377
3378 #ifdef CONFIG_PROC_FS
3379
3380 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3381 {
3382         struct clk *ck;
3383         int i;
3384         unsigned long rate = clk->rate;
3385         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3386         for (i = 0; i < deep; i++)
3387                 seq_printf(s, "    ");
3388
3389         seq_printf(s, "%-11s ", clk->name);
3390 #ifndef RK30_CLK_OFFBOARD_TEST
3391         if (clk->flags & IS_PD) {
3392                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3393         }
3394 #endif
3395         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3396                 int idx = clk->gate_idx;
3397                 u32 v;
3398                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3399                 seq_printf(s, "%s ", v ? "off" : "on ");
3400         }
3401
3402         if (clk->pll) {
3403                 u32 pll_mode;
3404                 u32 pll_id = clk->pll->id;
3405                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3406                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3407                         seq_printf(s, "slow   ");
3408                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3409                         seq_printf(s, "normal ");
3410                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3411                         seq_printf(s, "deep   ");
3412
3413                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3414                         seq_printf(s, "bypass ");
3415         } else if(clk == &clk_ddr) {
3416                 rate = clk->recalc(clk);
3417         }
3418
3419         if (rate >= MHZ) {
3420                 if (rate % MHZ)
3421                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3422                 else
3423                         seq_printf(s, "%ld MHz", rate / MHZ);
3424         } else if (rate >= KHZ) {
3425                 if (rate % KHZ)
3426                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3427                 else
3428                         seq_printf(s, "%ld KHz", rate / KHZ);
3429         } else {
3430                 seq_printf(s, "%ld Hz", rate);
3431         }
3432
3433         seq_printf(s, " usecount = %d", clk->usecount);
3434
3435         if (clk->parent)
3436                 seq_printf(s, " parent = %s", clk->parent->name);
3437
3438         seq_printf(s, "\n");
3439
3440         list_for_each_entry(ck, root_clocks, node) {
3441                 if (ck->parent == clk)
3442                         dump_clock(s, ck, deep + 1, root_clocks);
3443         }
3444 }
3445
3446 static void dump_regs(struct seq_file *s)
3447 {
3448         int i = 0;
3449         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3450         seq_printf(s, "\nPLLRegisters:\n");
3451         for(i = 0; i < END_PLL_ID; i++) {
3452                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3453                                 cru_readl(PLL_CONS(i, 0)),
3454                                 cru_readl(PLL_CONS(i, 1)),
3455                                 cru_readl(PLL_CONS(i, 2)),
3456                                 cru_readl(PLL_CONS(i, 3))
3457                           );
3458         }
3459         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3460
3461         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3462                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3463         }
3464         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3465                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3466         }
3467         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3468         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3469
3470         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3471                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3472         }
3473         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3474         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3475
3476 }
3477
3478 void rk30_clk_dump_regs(void)
3479 {
3480         int i = 0;
3481         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3482         printk("\nPLLRegisters:\n");
3483         for(i = 0; i < END_PLL_ID; i++) {
3484                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3485                                 cru_readl(PLL_CONS(i, 0)),
3486                                 cru_readl(PLL_CONS(i, 1)),
3487                                 cru_readl(PLL_CONS(i, 2)),
3488                                 cru_readl(PLL_CONS(i, 3))
3489                       );
3490         }
3491         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3492
3493         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3494                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3495         }
3496         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3497                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3498         }
3499         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3500         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3501
3502         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3503                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3504         }
3505         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3506         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3507
3508 }
3509
3510
3511 #ifdef CONFIG_PROC_FS
3512 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3513 struct clk_dump_ops dump_ops = {
3514         .dump_clk = dump_clock,
3515         .dump_regs = dump_regs,
3516 };
3517 #endif
3518
3519
3520 #endif /* CONFIG_PROC_FS */
3521
3522
3523
3524
3525 #ifdef RK30_CLK_OFFBOARD_TEST
3526 struct clk *test_get_parent(struct clk *clk) {
3527         return clk->parent;
3528 }
3529
3530 void i2s_test(void)
3531 {
3532         struct clk *i2s_clk = &clk_i2s0;
3533
3534         clk_enable_nolock(i2s_clk);
3535
3536         clk_set_rate_nolock(i2s_clk, 12288000);
3537         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3538         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3539         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3540         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3541         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3542
3543 }
3544
3545 void uart_test(void)
3546 {
3547         struct clk *uart_clk = &clk_uart0;
3548
3549         clk_enable_nolock(uart_clk);
3550
3551         clk_set_rate_nolock(uart_clk, 12288000);
3552         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3553         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3554         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3555         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3556         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3557
3558 }
3559 void hsadc_test(void)
3560 {
3561         struct clk *hsadc_clk = &clk_hsadc;
3562
3563         printk("******************hsadc_test**********************\n");
3564         clk_enable_nolock(hsadc_clk);
3565
3566         clk_set_rate_nolock(hsadc_clk, 12288000);
3567         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3568
3569
3570         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3571         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3572
3573         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3574
3575         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3576
3577         printk("******************hsadc out clock**********************\n");
3578
3579         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3580         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3581         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3582         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3583
3584
3585
3586 }
3587
3588 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3589 {
3590         //arm
3591         printk("*********arm_pll_clk***********\n");
3592         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3593
3594         printk("*********set clk_core parent***********\n");
3595         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3596         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3597
3598         //general
3599         printk("*********general_pll_clk***********\n");
3600         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3601
3602         //code pll
3603         printk("*********codec_pll_clk***********\n");
3604         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3605
3606
3607         printk("*********periph_clk_set_init***********\n");
3608         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3609         periph_clk_set_init();
3610
3611 #if 0 //
3612         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3613 #else
3614         printk("*********clk i2s***********\n");
3615         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3616         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3617         i2s_test();
3618 #endif
3619         // spi
3620         clk_enable_nolock(&clk_spi0);
3621         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3622         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3623         //saradc
3624         clk_enable_nolock(&clk_saradc);
3625         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3626         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3627         //sdio
3628         clk_enable_nolock(&clk_sdio);
3629         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3630         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3631         // uart
3632         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3633         uart_test();
3634         //mac
3635         printk("*********mac***********\n");
3636
3637         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3638         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3639
3640         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3641         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3642         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3643
3644         printk("*********mac mii set***********\n");
3645         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3646         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3647         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3648         //hsadc
3649         printk("*********hsadc 1***********\n");
3650         //auto pll
3651         hsadc_test();
3652         //lcdc
3653         clk_enable_nolock(&dclk_lcdc0);
3654
3655         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
3656         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
3657
3658         //cif
3659         clk_enable_nolock(&cif0_out);
3660
3661         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3662         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
3663
3664         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
3665         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3666
3667         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
3668         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3669         //cif_in
3670         clk_enable_nolock(&cif0_in);
3671         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
3672         //axi lcdc
3673         clk_enable_nolock(&aclk_lcdc0);
3674         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
3675         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
3676         //axi vepu
3677         clk_enable_nolock(&aclk_vepu);
3678         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3679         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
3680
3681         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
3682         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
3683
3684         printk("test end\n");
3685
3686         /* arm pll
3687            clk_set_rate_nolock(&arm_pll_clk, armclk);
3688            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
3689            */
3690         //
3691         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3692         //
3693         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3694         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3695
3696 }
3697
3698
3699
3700
3701
3702 static LIST_HEAD(rk30_clocks);
3703 static DEFINE_MUTEX(rk30_clocks_mutex);
3704
3705 static inline int __rk30clk_get(struct clk *clk)
3706 {
3707         return 1;
3708 }
3709 void rk30_clkdev_add(struct clk_lookup *cl)
3710 {
3711         mutex_lock(&rk30_clocks_mutex);
3712         list_add_tail(&cl->node, &rk30_clocks);
3713         mutex_unlock(&rk30_clocks_mutex);
3714 }
3715 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
3716         struct clk_lookup *p, *cl = NULL;
3717         int match, best = 0;
3718
3719         list_for_each_entry(p, &rk30_clocks, node) {
3720                 match = 0;
3721                 if (p->dev_id) {
3722                         if (!dev_id || strcmp(p->dev_id, dev_id))
3723                                 continue;
3724                         match += 2;
3725                 }
3726                 if (p->con_id) {
3727                         if (!con_id || strcmp(p->con_id, con_id))
3728                                 continue;
3729                         match += 1;
3730                 }
3731
3732                 if (match > best) {
3733                         cl = p;
3734                         if (match != 3)
3735                                 best = match;
3736                         else
3737                                 break;
3738                 }
3739         }
3740         return cl;
3741 }
3742
3743 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
3744         struct clk_lookup *cl;
3745
3746         mutex_lock(&rk30_clocks_mutex);
3747         cl = rk30_clk_find(dev_id, con_id);
3748         if (cl && !__rk30clk_get(cl->clk))
3749                 cl = NULL;
3750         mutex_unlock(&rk30_clocks_mutex);
3751
3752         return cl ? cl->clk : ERR_PTR(-ENOENT);
3753 }
3754 //EXPORT_SYMBOL(rk30_clk_get_sys);
3755
3756 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
3757         const char *dev_id = dev ? dev_name(dev) : NULL;
3758         return rk30_clk_get_sys(dev_id, con_id);
3759 }
3760 //EXPORT_SYMBOL(rk30_clk_get);
3761
3762
3763 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3764
3765 void rk30_clocks_test(void)
3766 {
3767         struct clk *test_gpll;
3768         test_gpll = rk30_clk_get(NULL, "general_pll");
3769         if(test_gpll) {
3770                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
3771                 printk("gpll rate=%lu\n", test_gpll->rate);
3772         }
3773         //while(1);
3774 }
3775
3776 void __init rk30_clock_init_test(void)
3777 {
3778
3779         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
3780         //while(1);
3781 }
3782
3783
3784 #endif
3785
3786