arch/arm/mach-rk3188/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <plat/efuse.h>
  25 #include <mach/cru.h>
  26 #include <mach/iomux.h>
  27 #include <mach/clock.h>
  28 #include <mach/pmu.h>
  29 #include <mach/dvfs.h>
  30 #include <mach/ddr.h>
  31 #include <mach/cpu.h>
  32
  33 #define MHZ                     (1000UL * 1000UL)
  34 #define KHZ                     (1000UL)
  35 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  36 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
  37 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  38 void rk30_clk_dump_regs(void);
  39
  40 //flags bit
  41 //has extern 27mhz
  42 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  43 //max i2s rate
  44 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  45 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  46 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  47 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  48 //uart 1m\3m
  49 #define CLK_FLG_UART_1_3M                       (1<<5)
  50
  51 #define ARCH_RK31
  52
  53 struct apll_clk_set {
  54         unsigned long   rate;
  55         u32     pllcon0;
  56         u32     pllcon1;
  57         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  58         u32     rst_dly;//us
  59         u32     clksel0;
  60         u32     clksel1;
  61         unsigned long   lpj;
  62 };
  63 struct pll_clk_set {
  64         unsigned long   rate;
  65         u32     pllcon0;
  66         u32     pllcon1;
  67         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  68         unsigned long   rst_dly;//us
  69 };
  70
  71 #define SET_PLL_DATA(_pll_id,_table) \
  72 {\
  73         .id=(_pll_id),\
  74         .table=(_table),\
  75 }
  76
  77
  78 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  79 { \
  80         .rate   = (_mhz) * KHZ, \
  81         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  82         .pllcon1 = PLL_CLKF_SET(nf),\
  83         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  84         .rst_dly=((nr*500)/24+1),\
  85 }
  86
  87
  88 #define _APLL_SET_LPJ(_mhz) \
  89         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  90
  91
  92 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  93                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  94 { \
  95         .rate   = _mhz * MHZ, \
  96         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  97         .pllcon1 = PLL_CLKF_SET(nf),\
  98         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  99         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
 100         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
 101         _APLL_SET_LPJ(_mhz),\
 102         .rst_dly=((nr*500)/24+1),\
 103 }
 104
 105 #define CRU_DIV_SET(mask,shift,max) \
 106         .div_mask=(mask),\
 107 .div_shift=(shift),\
 108 .div_max=(max)
 109
 110
 111 #define CRU_SRC_SET(mask,shift ) \
 112         .src_mask=(mask),\
 113 .src_shift=(shift)
 114
 115 #define CRU_PARENTS_SET(parents_array) \
 116         .parents=(parents_array),\
 117 .parents_num=ARRAY_SIZE((parents_array))
 118
 119 #define CRU_GATE_MODE_SET(_func,_IDX) \
 120         .mode=_func,\
 121 .gate_idx=(_IDX)
 122
 123 struct clk_src_sel {
 124         struct clk      *parent;
 125         u8      value;//crt bit
 126         u8      flag;
 127         //selgate
 128 };
 129
 130 #define GATE_CLK(NAME,PARENT,ID) \
 131         static struct clk clk_##NAME = { \
 132                 .name           = #NAME, \
 133                 .parent         = &PARENT, \
 134                 .mode           = gate_mode, \
 135                 .gate_idx       = CLK_GATE_##ID, \
 136         }
 137 #ifdef RK30_CLK_OFFBOARD_TEST
 138 u32 TEST_GRF_REG[0x240];
 139 u32 TEST_CRU_REG[0x240];
 140 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 141
 142 u32 cru_writel_is_pr(u32 offset)
 143 {
 144         return (offset == 0x4000);
 145 }
 146 void cru_writel(u32 v, u32 offset)
 147 {
 148
 149         u32 mask_v = v >> 16;
 150         TEST_CRU_REG[offset/4] &= (~mask_v);
 151
 152         v &= (mask_v);
 153
 154         TEST_CRU_REG[offset/4] |= v;
 155         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 156
 157         if(cru_writel_is_pr(offset)) {
 158                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 159
 160         }
 161
 162 }
 163 void cru_writel_i2s(u32 v, u32 offset)
 164 {
 165         TEST_CRU_REG[offset/4] = v;
 166 }
 167 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 168
 169 #define regfile_readl(offset)   (0xffffffff)
 170 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 171 void rk30_clkdev_add(struct clk_lookup *cl);
 172 #else
 173 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 174 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 175 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 176 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 177
 178 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 179 #endif
 180
 181 //#define DEBUG
 182 #ifdef DEBUG
 183 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 184 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 185 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
 186 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
 187 #else
 188 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 189 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 190 #endif
 191 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 192 #define CLKDATA_WARNING(fmt, args...) printk("CLKDATA_WANING:\t"fmt, ##args)
 193
 194
 195 #define get_cru_bits(con,mask,shift)\
 196         ((cru_readl((con)) >> (shift)) & (mask))
 197
 198 #define set_cru_bits_w_msk(val,mask,shift,con)\
 199         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 200
 201
 202 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 203                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 204
 205
 206 static u32 rk30_clock_flags = 0;
 207 static struct clk codec_pll_clk;
 208 static struct clk general_pll_clk;
 209 static struct clk arm_pll_clk;
 210 static unsigned long lpj_gpll;
 211 static unsigned int __initdata armclk = 504 * MHZ;
 212
 213
 214 /************************clk recalc div rate*********************************/
 215
 216 //for free div
 217 static unsigned long clksel_recalc_div(struct clk *clk)
 218 {
 219         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 220
 221         unsigned long rate = clk->parent->rate / div;
 222         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 223         return rate;
 224 }
 225
 226 //for div 1 2 4 2^n
 227 static unsigned long clksel_recalc_shift(struct clk *clk)
 228 {
 229         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 230         unsigned long rate = clk->parent->rate >> shift;
 231         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 232         return rate;
 233 }
 234
 235
 236 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 237 {
 238         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 239         unsigned long rate = clk->parent->rate >> shift;
 240         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 241         return rate;
 242 }
 243
 244 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 245 {
 246         unsigned long rate = clk->parent->rate;
 247         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 248         return rate;
 249 }
 250 /********************************set div rate***********************************/
 251
 252 //for free div
 253 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 254 {
 255         u32 div;
 256         for (div = 0; div < clk->div_max; div++) {
 257                 u32 new_rate = clk->parent->rate / (div + 1);
 258                 if (new_rate <= rate) {
 259                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 260                         //clk->rate = new_rate;
 261                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 262                                         clk->name, rate, div + 1);
 263                         return 0;
 264                 }
 265         }
 266         return -ENOENT;
 267 }
 268
 269 //for div 1 2 4 2^n
 270 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 271 {
 272         u32 shift;
 273         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 274                 u32 new_rate = clk->parent->rate >> shift;
 275                 if (new_rate <= rate) {
 276                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 277                         clk->rate = new_rate;
 278                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 279                                         clk->name, rate, shift);
 280                         return 0;
 281                 }
 282         }
 283         return -ENOENT;
 284 }
 285
 286 //for div 2 4 2^n
 287 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 288 {
 289         u32 shift;
 290
 291         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 292                 u32 new_rate = clk->parent->rate >> shift;
 293                 if (new_rate <= rate) {
 294                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 295                         clk->rate = new_rate;
 296                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 297                                         clk->name, rate, shift);
 298                         return 0;
 299                 }
 300         }
 301         return -ENOENT;
 302 }
 303
 304 //for div 1 2 4 2*n
 305 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 306 {
 307         u32 div;
 308         for (div = 2; div < clk->div_max; div += 2) {
 309                 u32 new_rate = clk->parent->rate / div;
 310                 if (new_rate <= rate) {
 311                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 312                         clk->rate = new_rate;
 313                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 314                                         __func__, clk->name, rate, div);
 315                         return 0;
 316                 }
 317         }
 318         return -ENOENT;
 319 }
 320 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 321 {
 322         u32 div;
 323         unsigned long new_rate;
 324         for (div = 0; div < div_max; div++) {
 325                 new_rate = rate / (div + 1);
 326                 if (new_rate <= rate_out) {
 327                         return div + 1;
 328                 }
 329         }
 330         return div_max ? div_max : 1;
 331 }
 332 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 333 {
 334         u32 div;
 335         unsigned long new_rate;
 336         for (div = 1; div < div_max; div += 2) {
 337                 new_rate = rate / (div + 1);
 338                 if (new_rate <= rate_out) {
 339                         return div + 1;
 340                 }
 341         }
 342         return div_max ? div_max : 1;
 343 }
 344 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 345         u32 div[2] = {0, 0};
 346         unsigned long new_rate[2] = {0, 0};
 347         u32 i;
 348
 349         if(clk->rate == rate)
 350                 return clk->parent;
 351         for(i = 0; i < 2; i++) {
 352                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 353                 new_rate[i] = clk->parents[i]->rate / div[i];
 354                 if(new_rate[i] == rate) {
 355                         *div_out = div[i];
 356                         return clk->parents[i];
 357                 }
 358         }
 359         if(new_rate[0] < new_rate[1])
 360                 i = 1;
 361         else
 362                 i = 0;
 363         *div_out = div[i];
 364         return clk->parents[i];
 365 }
 366 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 367         u32 div[2] = {0, 0};
 368         unsigned long new_rate[2] = {0, 0};
 369         u32 i;
 370
 371         if(clk->rate == rate)
 372                 return clk->parent;
 373         for(i = 0; i < 2; i++) {
 374                 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 375                 new_rate[i] = clk->parents[i]->rate / div[i];
 376                 if(new_rate[i] == rate) {
 377                         *div_out = div[i];
 378                         return clk->parents[i];
 379                 }
 380         }
 381         if(new_rate[0] < new_rate[1])
 382                 i = 1;
 383         else
 384                 i = 0;
 385         *div_out = div[i];
 386         return clk->parents[i];
 387 }
 388
 389 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 390 {
 391         struct clk *p_clk;
 392         u32 div, old_div;
 393         int ret = 0;
 394         if(clk->rate == rate)
 395                 return 0;
 396         p_clk = get_freediv_parents_div(clk, rate, &div);
 397
 398         if(!p_clk)
 399                 return -ENOENT;
 400
 401         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 402         if (clk->parent != p_clk) {
 403                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 404
 405                 if(div > old_div) {
 406                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 407                 }
 408                 ret = clk_set_parent_nolock(clk, p_clk);
 409                 if(ret) {
 410                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 411                         return -ENOENT;
 412                 }
 413         }
 414         //set div
 415         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 416         return 0;
 417 }
 418 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 419 {
 420         struct clk *p_clk;
 421         u32 div, old_div;
 422         int ret = 0;
 423         if(clk->rate == rate)
 424                 return 0;
 425         p_clk = get_evendiv_parents_div(clk, rate, &div);
 426
 427         if(!p_clk)
 428                 return -ENOENT;
 429
 430         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 431         if (clk->parent != p_clk) {
 432                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 433
 434                 if(div > old_div) {
 435                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 436                 }
 437                 ret = clk_set_parent_nolock(clk, p_clk);
 438                 if(ret) {
 439                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 440                         return -ENOENT;
 441                 }
 442         }
 443         //set div
 444         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 445         return 0;
 446 }
 447
 448 //rate==div rate //hdmi
 449 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 450 {
 451         struct clk *p_clk;
 452         u32 div, old_div;
 453         int ret;
 454         p_clk = get_freediv_parents_div(clk, rate, &div);
 455
 456         if(!p_clk)
 457                 return -ENOENT;
 458
 459         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 460                 return -ENOENT;
 461
 462         if (clk->parent != p_clk) {
 463                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 464                                 clk->div_shift, clk->div_mask) + 1;
 465                 if(div > old_div) {
 466                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 467                 }
 468                 ret = clk_set_parent_nolock(clk, p_clk);
 469                 if (ret) {
 470                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 471                         return ret;
 472                 }
 473         }
 474         //set div
 475         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 476         return 0;
 477 }
 478
 479 /***************************round********************************/
 480
 481 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 482 {
 483         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 484 }
 485
 486 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 487 {
 488         u32 div;
 489         struct clk *p_clk;
 490         if(clk->rate == rate)
 491                 return clk->rate;
 492         p_clk = get_freediv_parents_div(clk, rate, &div);
 493         if(!p_clk)
 494                 return 0;
 495         return p_clk->rate / div;
 496 }
 497
 498 /**************************************others seting************************************/
 499
 500 static struct clk *clksel_get_parent(struct clk *clk) {
 501         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 502 }
 503 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 504 {
 505         u32 i;
 506         if (unlikely(!clk->parents))
 507                 return -EINVAL;
 508         for (i = 0; (i < clk->parents_num); i++) {
 509                 if (clk->parents[i] != parent)
 510                         continue;
 511                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 512                 return 0;
 513         }
 514         return -EINVAL;
 515 }
 516
 517 static int gate_mode(struct clk *clk, int on)
 518 {
 519         int idx = clk->gate_idx;
 520         if (idx >= CLK_GATE_MAX)
 521                 return -EINVAL;
 522         if(on) {
 523                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 524                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 525                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 526         } else {
 527                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 528                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 529                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 530         }
 531         return 0;
 532 }
 533 /*****************************frac set******************************************/
 534
 535 static unsigned long clksel_recalc_frac(struct clk *clk)
 536 {
 537         unsigned long rate;
 538         u64 rate64;
 539         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 540         if (r == 0) // FPGA ?
 541                 return clk->parent->rate;
 542         numerator = r >> 16;
 543         denominator = r & 0xFFFF;
 544         rate64 = (u64)clk->parent->rate * numerator;
 545         do_div(rate64, denominator);
 546         rate = rate64;
 547         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 548         return rate;
 549 }
 550
 551 static u32 clk_gcd(u32 numerator, u32 denominator)
 552 {
 553         u32 a, b;
 554
 555         if (!numerator || !denominator)
 556                 return 0;
 557         if (numerator > denominator) {
 558                 a = numerator;
 559                 b = denominator;
 560         } else {
 561                 a = denominator;
 562                 b = numerator;
 563         }
 564         while (b != 0) {
 565                 int r = b;
 566                 b = a % b;
 567                 a = r;
 568         }
 569
 570         return a;
 571 }
 572
 573 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 574                 u32 *numerator, u32 *denominator)
 575 {
 576         u32 gcd_vl;
 577         gcd_vl = clk_gcd(rate, rate_out);
 578         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 579
 580         if (!gcd_vl) {
 581                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 582                 return -ENOENT;
 583         }
 584
 585         *numerator = rate_out / gcd_vl;
 586         *denominator = rate / gcd_vl;
 587
 588         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 589                         *numerator, *denominator, *denominator / *numerator);
 590
 591         if (*numerator > 0xffff || *denominator > 0xffff ||
 592                         (*denominator / (*numerator)) < 20) {
 593                 CLKDATA_ERR("can't get a available nume and deno\n");
 594                 return -ENOENT;
 595         }
 596
 597         return 0;
 598
 599 }
 600 /* *********************pll **************************/
 601
 602 #define rk30_clock_udelay(a) udelay(a);
 603
 604 /*********************pll lock status**********************************/
 605 //#define GRF_SOC_CON0       0x15c
 606 static void pll_wait_lock(int pll_idx)
 607 {
 608         u32 pll_state[4] = {1, 0, 2, 3};
 609         u32 bit = 0x20u << pll_state[pll_idx];
 610         int delay = 24000000;
 611         while (delay > 0) {
 612                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 613                         break;
 614                 delay--;
 615         }
 616         if (delay == 0) {
 617                 CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
 618                                 cru_readl(PLL_CONS(pll_idx, 0)),
 619                                 cru_readl(PLL_CONS(pll_idx, 1)),
 620                                 cru_readl(PLL_CONS(pll_idx, 2)),
 621                                 cru_readl(PLL_CONS(pll_idx, 3)));
 622
 623                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 624                 while(1);
 625         }
 626 }
 627
 628
 629
 630 /***************************pll function**********************************/
 631 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 632 {
 633         unsigned long rate;
 634
 635         if (PLLS_IN_NORM(pll_id)) {
 636                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 637                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 638
 639
 640                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 641
 642                 /*
 643                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 644                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 645                    */
 646
 647
 648                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 649                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 650                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 651
 652                 do_div(rate64, PLL_NR(pll_con0));
 653                 do_div(rate64, PLL_NO(pll_con0));
 654
 655                 rate = rate64;
 656                 /*
 657                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 658                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 659                    */
 660         } else {
 661                 rate = parent_rate;
 662                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 663         }
 664         return rate;
 665 }
 666 static unsigned long plls_clk_recalc(struct clk *clk)
 667 {
 668         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 669 }
 670 static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 671 {
 672         unsigned long rate;
 673
 674         if (PLLS_IN_NORM(pll_id)) {
 675                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 676                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 677
 678                 u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
 679
 680                 do_div(rate64, PLUS_PLL_NR(pll_con0));
 681                 do_div(rate64, PLUS_PLL_NO(pll_con0));
 682
 683                 rate = rate64;
 684         } else {
 685                 rate = parent_rate;
 686                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 687         }
 688         return rate;
 689 }
 690 static unsigned long plus_plls_clk_recalc(struct clk *clk)
 691 {
 692         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 693         return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
 694 }
 695
 696 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 697 {
 698         //enter slowmode
 699         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 700         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 701         dsb();
 702         dsb();
 703         dsb();
 704         dsb();
 705         dsb();
 706         dsb();
 707         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 708         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 709
 710         rk30_clock_udelay(1);
 711         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 712
 713         pll_wait_lock(pll_id);
 714
 715         //return form slow
 716         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 717
 718         /*
 719            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 720            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 721            */
 722
 723         return 0;
 724 }
 725
 726 static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 727 {
 728         //enter slowmode
 729         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 730
 731         //enter rest
 732         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
 733         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 734         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 735         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
 736         rk30_clock_udelay(5);
 737
 738         //return form rest
 739         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
 740
 741         //wating lock state
 742         rk30_clock_udelay(clk_set->rst_dly);
 743         pll_wait_lock(pll_id);
 744
 745         //return form slow
 746         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 747
 748         return 0;
 749 }
 750
 751 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 752 {
 753         struct _pll_data *pll_data = c->pll;
 754         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 755
 756         while(clk_set->rate) {
 757                 if (clk_set->rate == rate) {
 758                         break;
 759                 }
 760                 clk_set++;
 761         }
 762         if(clk_set->rate == rate) {
 763                 pll_clk_set_rate(clk_set, pll_data->id);
 764                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 765         } else {
 766                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 767                 return -1;
 768         }
 769         return 0;
 770 }
 771
 772 static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
 773 {
 774         struct _pll_data *pll_data = c->pll;
 775         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 776         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 777
 778         while(clk_set->rate) {
 779                 if (clk_set->rate == rate) {
 780                         break;
 781                 }
 782                 clk_set++;
 783         }
 784         if(clk_set->rate == rate) {
 785                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 786                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 787         } else {
 788                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 789                 return -1;
 790         }
 791         return 0;
 792 }
 793 #define PLL_FREF_MIN (183*KHZ)
 794 #define PLL_FREF_MAX (1500*MHZ)
 795
 796 #define PLL_FVCO_MIN (300*MHZ)
 797 #define PLL_FVCO_MAX (1500*MHZ)
 798
 799 #define PLL_FOUT_MIN (18750*KHZ)
 800 #define PLL_FOUT_MAX (1500*MHZ)
 801
 802 #define PLL_NF_MAX (65536)
 803 #define PLL_NR_MAX (64)
 804 #define PLL_NO_MAX (64)
 805
 806 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 807 {
 808         u32 nr, nf, no, nonr;
 809         u32 n;
 810         u32 YFfenzi;
 811         u32 YFfenmu;
 812         unsigned long fref, fvco, fout;
 813         u32 gcd_val = 0;
 814
 815         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 816         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 817                 return 0;
 818         gcd_val = clk_gcd(fin_hz, fout_hz);
 819         YFfenzi = fout_hz / gcd_val;
 820         YFfenmu = fin_hz / gcd_val;
 821
 822         for(n = 1;; n++) {
 823                 nf = YFfenzi * n;
 824                 nonr = YFfenmu * n;
 825                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 826                         break;
 827                 for(no = 1; no <= PLL_NO_MAX; no++) {
 828                         if(!(no == 1 || !(no % 2)))
 829                                 continue;
 830
 831                         if(nonr % no)
 832                                 continue;
 833                         nr = nonr / no;
 834
 835                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 836                                 continue;
 837
 838                         fref = fin_hz / nr;
 839                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 840                                 continue;
 841
 842                         fvco = (fin_hz / nr) * nf;
 843                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 844                                 continue;
 845                         fout = fvco / no;
 846                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 847                                 continue;
 848                         *clk_nr = nr;
 849                         *clk_no = no;
 850                         *clk_nf = nf;
 851                         return 1;
 852
 853                 }
 854
 855         }
 856         return 0;
 857 }
 858
 859 static int pll_clk_mode(struct clk *clk, int on)
 860 {
 861         u8 pll_id = clk->pll->id;
 862         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 863         u32 dly = (nr * 500) / 24 + 1;
 864         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 865         if (on) {
 866                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 867                 rk30_clock_udelay(dly);
 868                 pll_wait_lock(pll_id);
 869                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 870         } else {
 871                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 872                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 873         }
 874         return 0;
 875 }
 876
 877 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 878 {
 879         struct _pll_data *pll_data = c->pll;
 880         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 881         struct pll_clk_set temp_clk_set;
 882         u32 clk_nr, clk_nf, clk_no;
 883
 884         if(rate == 24 * MHZ) {
 885                 cru_writel(PLL_MODE_SLOW(pll_data->id), CRU_MODE_CON);
 886                 cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll_data->id, 3));
 887                 return 0;
 888         }
 889         while(clk_set->rate) {
 890                 if (clk_set->rate == rate) {
 891                         break;
 892                 }
 893                 clk_set++;
 894         }
 895         if(clk_set->rate == rate) {
 896                 CLKDATA_DBG("cpll get a rate\n");
 897                 pll_clk_set_rate(clk_set, pll_data->id);
 898
 899         } else {
 900                 CLKDATA_DBG("cpll get auto calc a rate\n");
 901                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 902                         pr_err("cpll auto set rate error\n");
 903                         return -ENOENT;
 904                 }
 905                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 906                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 907                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 908                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 909                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 910
 911         }
 912         return 0;
 913 }
 914 static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
 915 {
 916         struct _pll_data *pll_data = c->pll;
 917         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 918         struct pll_clk_set temp_clk_set;
 919         u32 clk_nr, clk_nf, clk_no;
 920         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 921
 922         while(clk_set->rate) {
 923                 if (clk_set->rate == rate) {
 924                         break;
 925                 }
 926                 clk_set++;
 927         }
 928         if(clk_set->rate == rate) {
 929                 CLKDATA_DBG("cpll get a rate\n");
 930                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 931
 932         } else {
 933                 CLKDATA_DBG("cpll get auto calc a rate\n");
 934                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 935                         pr_err("cpll auto set rate error\n");
 936                         return -ENOENT;
 937                 }
 938                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 939                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 940                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 941                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 942                 plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
 943
 944         }
 945         return 0;
 946 }
 947
 948
 949 /* ******************fixed input clk ***********************************************/
 950 static struct clk xin24m = {
 951         .name           = "xin24m",
 952         .rate           = 24 * MHZ,
 953         .flags          = RATE_FIXED,
 954 };
 955
 956 static struct clk clk_12m = {
 957         .name           = "clk_12m",
 958         .parent         = &xin24m,
 959         .rate           = 12 * MHZ,
 960         .flags          = RATE_FIXED,
 961 };
 962
 963 /************************************pll func***************************/
 964 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 965                 struct apll_clk_set *tables) {
 966         const struct apll_clk_set *ps, *pt;
 967
 968         /* find the arm_pll we want. */
 969         ps = pt = tables;
 970         while (pt->rate) {
 971                 if (pt->rate == rate) {
 972                         ps = pt;
 973                         break;
 974                 }
 975                 // we are sorted, and ps->rate > pt->rate.
 976                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 977                         ps = pt;
 978                 if (pt->rate < rate)
 979                         break;
 980                 pt++;
 981         }
 982         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 983         return ps;
 984 }
 985 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 986 {
 987         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 988 }
 989 #if 1
 990 struct arm_clks_div_set {
 991         u32 rate;
 992         u32     clksel0;
 993         u32     clksel1;
 994 };
 995
 996 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 997 { \
 998         .rate    =_mhz,\
 999         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
1000         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
1001         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
1002         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
1003         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
1004 }
1005 struct arm_clks_div_set arm_clk_div_tlb[] = {
1006         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
1007         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
1008         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
1009         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
1010         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
1011         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
1012         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
1013 };
1014 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
1015         int i = 0;
1016         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
1017                 if(arm_clk_div_tlb[i].rate >= rate)
1018                         return &arm_clk_div_tlb[i];
1019         }
1020         return NULL;
1021 }
1022
1023 #endif
1024
1025 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1026 {
1027         unsigned long flags;
1028         const struct apll_clk_set *ps;
1029         u32 pll_id = clk->pll->id;
1030         u32 temp_div;
1031         u32 old_aclk_div = 0, new_aclk_div;
1032
1033         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1034
1035         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1036         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1037
1038         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1039                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1040
1041         if(general_pll_clk.rate > clk->rate) {
1042                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1043         } else {
1044                 temp_div = 1;
1045         }
1046
1047         // ungating cpu gpll path
1048         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1049         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1050
1051         local_irq_save(flags);
1052         //div arm clk for gpll
1053
1054         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1055         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1056
1057         loops_per_jiffy = lpj_gpll / temp_div;
1058         smp_wmb();
1059
1060         /*if core src don't select gpll ,apll neet to enter slow mode */
1061         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1062
1063
1064         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
1065         dsb();
1066         dsb();
1067         dsb();
1068         dsb();
1069         dsb();
1070         dsb();
1071         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1072         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1073
1074         rk30_clock_udelay(1);
1075         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
1076
1077         pll_wait_lock(pll_id);
1078
1079         //return form slow
1080         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1081         //reparent to apll
1082
1083         if(new_aclk_div>=old_aclk_div) {
1084                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1085                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1086         }
1087
1088         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1089         if(old_aclk_div>new_aclk_div) {
1090                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1091                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1092         }
1093
1094         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1095
1096         loops_per_jiffy = ps->lpj;
1097         smp_wmb();
1098
1099         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1100
1101         local_irq_restore(flags);
1102
1103         //gate gpll path
1104         // FIXME
1105         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1106         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1107
1108         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1109                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1110                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1111                         cru_readl(CRU_CLKSELS_CON(1)));
1112         return 0;
1113 }
1114
1115 static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1116 {
1117         unsigned long flags;
1118         const struct apll_clk_set *ps;
1119         u32 pll_id = clk->pll->id;
1120         u32 temp_div;
1121         u32 old_aclk_div = 0, new_aclk_div;
1122         DVFS_DBG("%s: for rk3188 plus\n", __func__);
1123
1124         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1125
1126         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1127         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1128
1129         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1130                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1131
1132         if(general_pll_clk.rate > clk->rate) {
1133                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1134         } else {
1135                 temp_div = 1;
1136         }
1137
1138         // ungating cpu gpll path
1139         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1140         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1141
1142         local_irq_save(flags);
1143         //div arm clk for gpll
1144
1145         cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1146         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1147
1148         loops_per_jiffy = lpj_gpll / temp_div;
1149         smp_wmb();
1150
1151         /*if core src don't select gpll ,apll neet to enter slow mode */
1152         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1153
1154         //enter rest
1155         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
1156         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1157         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1158         cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
1159         rk30_clock_udelay(5);
1160
1161         //return form rest
1162         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
1163
1164         //wating lock state
1165         rk30_clock_udelay(ps->rst_dly);
1166         pll_wait_lock(pll_id);
1167
1168         if(new_aclk_div>=old_aclk_div) {
1169                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1170                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1171         }
1172
1173         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1174         if(old_aclk_div>new_aclk_div) {
1175                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1176                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1177         }
1178
1179         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1180
1181         loops_per_jiffy = ps->lpj;
1182         smp_wmb();
1183
1184         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1185
1186         local_irq_restore(flags);
1187
1188         //gate gpll path
1189         // FIXME
1190         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1191         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1192
1193         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1194                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1195                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1196                         cru_readl(CRU_CLKSELS_CON(1)));
1197         return 0;
1198 }
1199
1200 /************************************pll clocks***************************/
1201
1202 static const struct apll_clk_set apll_clks[] = {
1203         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1204         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1205         _APLL_SET_CLKS(2208, 1, 92, 1, 8,       81, 81, 21, 41, 21),
1206         _APLL_SET_CLKS(2184, 1, 91, 1, 8,       81, 81, 21, 41, 21),
1207         _APLL_SET_CLKS(2160, 1, 90, 1, 8,       81, 81, 21, 41, 21),
1208         _APLL_SET_CLKS(2136, 1, 89, 1, 8,       81, 81, 21, 41, 21),
1209         _APLL_SET_CLKS(2112, 1, 88, 1, 8,       81, 81, 21, 41, 21),
1210         _APLL_SET_CLKS(2088, 1, 87, 1, 8,       81, 81, 21, 41, 21),
1211         _APLL_SET_CLKS(2064, 1, 86, 1, 8,       81, 81, 21, 41, 21),
1212         _APLL_SET_CLKS(2040, 1, 85, 1, 8,       81, 81, 21, 41, 21),
1213         _APLL_SET_CLKS(2016, 1, 84, 1, 8,       81, 81, 21, 41, 21),
1214         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1215         _APLL_SET_CLKS(1968, 1, 82, 1, 8,       81, 81, 21, 41, 21),
1216         _APLL_SET_CLKS(1944, 1, 81, 1, 8,       81, 81, 21, 41, 21),
1217         _APLL_SET_CLKS(1920, 1, 80, 1, 8,       81, 81, 21, 41, 21),
1218         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1219         _APLL_SET_CLKS(1872, 1, 78, 1, 8,       81, 81, 21, 41, 21),
1220         _APLL_SET_CLKS(1848, 1, 77, 1, 8,       81, 81, 21, 41, 21),
1221         _APLL_SET_CLKS(1824, 1, 76, 1, 8,       81, 81, 21, 41, 21),
1222         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1223         _APLL_SET_CLKS(1776, 1, 74, 1, 8,       81, 81, 21, 41, 21),
1224         _APLL_SET_CLKS(1752, 1, 73, 1, 8,       81, 81, 21, 41, 21),
1225         _APLL_SET_CLKS(1728, 1, 72, 1, 8,       81, 81, 21, 41, 21),
1226         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1227         _APLL_SET_CLKS(1680, 1, 70, 1, 8,       41, 41, 21, 41, 21),
1228         _APLL_SET_CLKS(1656, 1, 69, 1, 8,       41, 41, 21, 41, 21),
1229         _APLL_SET_CLKS(1632, 1, 68, 1, 8,       41, 41, 21, 41, 21),
1230         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1231         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1232         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1233         _APLL_SET_CLKS(1488, 1, 62, 1, 8,       41, 41, 21, 41, 21),
1234         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1235         _APLL_SET_CLKS(1440, 1, 60, 1, 8,       41, 41, 21, 41, 21),
1236         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1237         _APLL_SET_CLKS(1392, 1, 58, 1, 8,       41, 41, 21, 41, 21),
1238         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1239         _APLL_SET_CLKS(1344, 1, 56, 1, 8,       41, 41, 21, 41, 21),
1240         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1241         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1242         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1243         _APLL_SET_CLKS(1248, 1, 52, 1, 8,       41, 41, 21, 41, 21),
1244         _APLL_SET_CLKS(1224, 1, 51, 1, 8,       41, 41, 21, 41, 21),
1245         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1246         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1247         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1248         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1249         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1250         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1251         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1252         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1253         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1254         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1255         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1256         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1257         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1258         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1259         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1260         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1261         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1262         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1263         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1264
1265 };
1266 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1267 static struct clk arm_pll_clk = {
1268         .name           = "arm_pll",
1269         .parent         = &xin24m,
1270         .mode           = pll_clk_mode,
1271         .recalc         = plls_clk_recalc,
1272         .set_rate       = arm_pll_clk_set_rate,
1273         .round_rate     = arm_pll_clk_round_rate,
1274         .pll            = &apll_data,
1275 };
1276
1277 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1278 {
1279         /* do nothing here */
1280         return 0;
1281 }
1282 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1283 static struct clk ddr_pll_clk = {
1284         .name           = "ddr_pll",
1285         .parent         = &xin24m,
1286         .recalc         = plls_clk_recalc,
1287         .set_rate       = ddr_pll_clk_set_rate,
1288         .pll            = &dpll_data,
1289 };
1290
1291 static const struct pll_clk_set cpll_clks[] = {
1292         _PLL_SET_CLKS(360000, 1,  60,   4),
1293         _PLL_SET_CLKS(408000, 1,  68,   4),
1294         _PLL_SET_CLKS(456000, 1,  76,   4),
1295         _PLL_SET_CLKS(504000, 1,  84,   4),
1296         _PLL_SET_CLKS(552000, 1,  46,   2),
1297         _PLL_SET_CLKS(594000, 2,  198,  4),
1298         _PLL_SET_CLKS(600000, 1,  50,   2),
1299         _PLL_SET_CLKS(742500, 8,  495,  2),
1300         _PLL_SET_CLKS(768000, 1,  64,   2),
1301         _PLL_SET_CLKS(798000, 2,  133,  2),
1302         _PLL_SET_CLKS(1188000, 2, 99,   1),
1303         _PLL_SET_CLKS(     0, 4,  133,  1),
1304 };
1305 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1306 static struct clk codec_pll_clk = {
1307         .name           = "codec_pll",
1308         .parent         = &xin24m,
1309         .mode           = pll_clk_mode,
1310         .recalc         = plls_clk_recalc,
1311         .set_rate       = cpll_clk_set_rate,
1312         .pll            = &cpll_data,
1313 };
1314
1315 static const struct pll_clk_set gpll_clks[] = {
1316         _PLL_SET_CLKS(148500,   2,      99,     8),
1317         _PLL_SET_CLKS(297000,   2,      198,    8),
1318         _PLL_SET_CLKS(300000,   1,      50,     4),
1319         _PLL_SET_CLKS(384000,   2,      128,    4),
1320         _PLL_SET_CLKS(594000,   2,      198,    4),
1321         _PLL_SET_CLKS(768000,   1,      64,     2),
1322         _PLL_SET_CLKS(891000,   8,      594,    2),
1323         _PLL_SET_CLKS(1188000,  2,      99,     1),
1324         _PLL_SET_CLKS(1200000,  1,      50,     1),
1325         _PLL_SET_CLKS(0,        0,       0,     0),
1326 };
1327 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1328 static struct clk general_pll_clk = {
1329         .name           = "general_pll",
1330         .parent         = &xin24m,
1331         .recalc         = plls_clk_recalc,
1332         .set_rate       = gpll_clk_set_rate,
1333         .pll            = &gpll_data
1334 };
1335 /********************************clocks***********************************/
1336 //GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1337 static struct clk clk_ddr_gpll_path = {
1338         .name           = "ddr_gpll_path",
1339         .parent         = &general_pll_clk,
1340         .recalc         = clksel_recalc_parent_rate,
1341         .gate_idx       = CLK_GATE_DDR_GPLL,
1342         .mode           = gate_mode,
1343 };
1344
1345 /* core and cpu setting */
1346 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1347 {
1348         CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1349         return 0;
1350 }
1351
1352 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1353 {
1354         CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1355         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1356 }
1357 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1358 {
1359         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1360         unsigned long rate = 0;
1361         clk->parent = clk->get_parent(clk);
1362         rate = clk->parent->recalc(clk->parent) >> shift;
1363         CLKDATA_DBG("%s new clock rate is %lu (shift %u), parent=%s, rate=%lu\n",
1364                         clk->name, rate, shift, clk->parent->name, clk->parent->rate);
1365         return rate;
1366 }
1367 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1368 static struct clk clk_ddr = {
1369         .name           = "ddr",
1370         .parent         = &ddr_pll_clk,
1371         .get_parent     = clksel_get_parent,
1372         .set_parent     = clksel_set_parent,
1373         .recalc         = ddr_clk_recalc_rate,
1374         .set_rate       = ddr_clk_set_rate,
1375         .round_rate     = ddr_clk_round_rate,
1376         .gate_idx       = CLK_GATE_DDRPHY,
1377         .clksel_con     = CRU_CLKSELS_CON(26),
1378         CRU_DIV_SET(0x3, 0, 4),
1379         CRU_SRC_SET(1, 8),
1380         CRU_PARENTS_SET(clk_ddr_parents),
1381 };
1382 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1383 {
1384         int ret;
1385
1386         ret = clk_set_rate_nolock(c->parent, rate);
1387         if (ret) {
1388                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1389                 return ret;
1390         }
1391         //set arm pll div 1
1392         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1393         return 0;
1394 }
1395 static unsigned long clk_core_get_rate(struct clk *c)
1396 {
1397         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1398         //c->parent->rate=c->parent->recalc(c->parent);
1399         return c->parent->rate / div;
1400 }
1401 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1402 {
1403         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1404         return clk_round_rate_nolock(clk->parent, rate) / div;
1405 }
1406
1407 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1408 {
1409
1410         u32 temp_div;
1411         struct clk *old_prt;
1412
1413         if(clk->parent == new_prt)
1414                 return 0;
1415         if (unlikely(!clk->parents))
1416                 return -EINVAL;
1417         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1418         //arm
1419         old_prt = clk->parent;
1420
1421         if(clk->parents[0] == new_prt) {
1422                 new_prt->set_rate(new_prt, 300 * MHZ);
1423                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1424         } else if(clk->parents[1] == new_prt) {
1425
1426                 if(new_prt->rate > old_prt->rate) {
1427                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1428                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1429                 }
1430                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1431                 new_prt->set_rate(new_prt, 300 * MHZ);
1432         } else
1433                 return -1;
1434
1435
1436         return 0;
1437
1438 }
1439
1440 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1441 {
1442         u32 temp_div;
1443         u32 old_aclk_div = 0, new_aclk_div;
1444         struct arm_clks_div_set *temp_clk_div;
1445         unsigned long arm_gpll_rate, arm_gpll_lpj;
1446         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1447         arm_gpll_rate = c->parent->rate / temp_div;
1448
1449         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1450         if(!temp_clk_div)
1451                 temp_clk_div = &arm_clk_div_tlb[4];
1452
1453         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1454         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1455         if(c->rate >= rate) {
1456                 arm_gpll_lpj = lpj_gpll / temp_div;
1457                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1458         }
1459
1460         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1461         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1462                         CRU_CLKSELS_CON(0));
1463         if((c->rate < rate)) {
1464                 arm_gpll_lpj = lpj_gpll / temp_div;
1465                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1466         }
1467         return 0;
1468 }
1469 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1470 {
1471         return c->parent->rate;
1472 }
1473 static struct clk clk_core_gpll_path = {
1474         .name           = "cpu_gpll_path",
1475         .parent         = &general_pll_clk,
1476         .recalc         = arm_core_gpll_clk_get_rate,
1477         .set_rate       = core_gpll_clk_set_rate,
1478         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1479 };
1480
1481
1482 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1483
1484 static struct clk clk_core = {
1485         .name           = "core",
1486         .parent         = &arm_pll_clk,
1487         .set_rate       = clk_core_set_rate,
1488         .recalc         = clk_core_get_rate,
1489         .round_rate     = core_clk_round_rate,
1490         .set_parent     = core_clksel_set_parent,
1491         .clksel_con     = CRU_CLKSELS_CON(0),
1492         CRU_DIV_SET(0x1f, 9, 32),
1493         CRU_SRC_SET(1, 8),
1494         CRU_PARENTS_SET(clk_core_parents),
1495 };
1496 GATE_CLK(l2c, clk_core, CLK_L2C);
1497 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1498 static unsigned long aclk_recalc(struct clk *clk)
1499 {
1500         unsigned long rate;
1501         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1502
1503         BUG_ON(div > 5);
1504         if (div >= 5)
1505                 div = 8;
1506         rate = clk->parent->rate / div;
1507         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1508
1509         return rate;
1510 };
1511 static struct clk core_periph = {
1512         .name           = "core_periph",
1513         .parent         = &clk_core,
1514         .gate_idx       = CLK_GATE_CORE_PERIPH,
1515         .recalc         = clksel_recalc_shift_2,
1516         .clksel_con     = CRU_CLKSELS_CON(0),
1517         CRU_DIV_SET(0x3, 6, 16),
1518 };
1519 static struct clk aclk_core = {
1520         .name           = "aclk_core",
1521         .parent         = &clk_core,
1522         .gate_idx       = CLK_GATE_ACLK_CORE,
1523         .recalc         = aclk_recalc,
1524         .clksel_con     = CRU_CLKSELS_CON(1),
1525         CRU_DIV_SET(0x7, 3, 8),
1526 };
1527
1528 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1529 static struct clk clk_cpu_div = {
1530         .name           = "cpu_div",
1531         .parent         = &arm_pll_clk,
1532         .set_rate       = clksel_set_rate_freediv,
1533         .recalc         = clksel_recalc_div,
1534         .clksel_con     = CRU_CLKSELS_CON(0),
1535         CRU_DIV_SET(0x1f, 0, 32),
1536         CRU_SRC_SET(1, 5),
1537         CRU_PARENTS_SET(clk_cpu_div_parents),
1538 };
1539
1540 static struct clk aclk_cpu = {
1541         .name           = "aclk_cpu",
1542         .parent         = &clk_cpu_div,
1543         .gate_idx       = CLK_GATE_ACLK_CPU,
1544 };
1545
1546 static struct clk hclk_cpu = {
1547         .name           = "hclk_cpu",
1548         .parent         = &aclk_cpu,
1549         .gate_idx       = CLK_GATE_HCLK_CPU,
1550         .recalc         = clksel_recalc_shift,
1551         .set_rate       = clksel_set_rate_shift,
1552         .clksel_con     = CRU_CLKSELS_CON(1),
1553         CRU_DIV_SET(0x3, 8, 4),
1554
1555 };
1556
1557 static struct clk pclk_cpu = {
1558         .name           = "pclk_cpu",
1559         .parent         = &aclk_cpu,
1560         .gate_idx       = CLK_GATE_PCLK_CPU,
1561         .recalc         = clksel_recalc_shift,
1562         .set_rate       = clksel_set_rate_shift,
1563         .clksel_con     = CRU_CLKSELS_CON(1),
1564         CRU_DIV_SET(0x3, 12, 8),
1565 };
1566
1567 static struct clk ahb2apb_cpu = {
1568         .name           = "ahb2apb",
1569         .parent         = &hclk_cpu,
1570         .recalc         = clksel_recalc_shift,
1571         .set_rate       = clksel_set_rate_shift,
1572         .clksel_con     = CRU_CLKSELS_CON(1),
1573         CRU_DIV_SET(0x3, 14, 4),
1574 };
1575
1576
1577 static struct clk atclk_cpu = {
1578         .name           = "atclk_cpu",
1579         .parent         = &pclk_cpu,
1580         .gate_idx       = CLK_GATE_ATCLK_CPU,
1581 };
1582
1583 /* GPU setting */
1584 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1585 {
1586         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1587         return clkset_rate_freediv_autosel_parents(clk, max_rate);
1588 };
1589
1590 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1591
1592 static struct clk aclk_gpu = {
1593         .name           = "aclk_gpu",
1594         .mode           = gate_mode,
1595         .recalc         = clksel_recalc_div,
1596         .round_rate     = clk_freediv_round_autosel_parents_rate,
1597         .set_rate       = clkset_rate_freediv_autosel_parents,
1598         .clksel_con     = CRU_CLKSELS_CON(34),
1599         .gate_idx       = CLK_GATE_ACLK_GPU,
1600         CRU_DIV_SET(0x1f, 0, 32),
1601         CRU_SRC_SET(0x1, 7),
1602         CRU_PARENTS_SET(aclk_gpu_parents),
1603 };
1604
1605 /* vcodec setting */
1606 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1607 {
1608         unsigned long rate = clk->parent->rate / 4;
1609         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1610         return rate;
1611 }
1612
1613 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1614
1615 static struct clk aclk_vepu = {
1616         .name           = "aclk_vepu",
1617         .parent         = &codec_pll_clk,
1618         .mode           = gate_mode,
1619         .recalc         = clksel_recalc_div,
1620         .set_rate       = clkset_rate_freediv_autosel_parents,
1621         .clksel_con     = CRU_CLKSELS_CON(32),
1622         .gate_idx       = CLK_GATE_ACLK_VEPU,
1623         CRU_DIV_SET(0x1f, 0, 32),
1624         CRU_SRC_SET(0x1, 7),
1625         CRU_PARENTS_SET(aclk_vepu_parents),
1626 };
1627
1628 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1629
1630 static struct clk aclk_vdpu = {
1631         .name           = "aclk_vdpu",
1632         .mode           = gate_mode,
1633         .recalc         = clksel_recalc_div,
1634         .set_rate       = clkset_rate_freediv_autosel_parents,
1635         .clksel_con     = CRU_CLKSELS_CON(32),
1636         .gate_idx       = CLK_GATE_ACLK_VDPU,
1637         CRU_DIV_SET(0x1f, 8, 32),
1638         CRU_SRC_SET(0x1, 15),
1639         CRU_PARENTS_SET(aclk_vdpu_parents),
1640 };
1641 static struct clk hclk_vepu = {
1642         .name           = "hclk_vepu",
1643         .parent         = &aclk_vepu,
1644         .mode           = gate_mode,
1645         .recalc         = clksel_recalc_vpu_hclk,
1646         .gate_idx       = CLK_GATE_HCLK_VEPU,
1647 };
1648
1649 static struct clk hclk_vdpu = {
1650         .name           = "hclk_vdpu",
1651         .parent         = &aclk_vdpu,
1652         .mode           = gate_mode,
1653         .recalc         = clksel_recalc_vpu_hclk,
1654         .gate_idx       = CLK_GATE_HCLK_VDPU,
1655 };
1656
1657 /* aclk lcdc setting */
1658 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1659
1660 static struct clk aclk_lcdc0_pre = {
1661         .name           = "aclk_lcdc0_pre",
1662         .parent         = &codec_pll_clk,
1663         .mode           = gate_mode,
1664         .recalc         = clksel_recalc_div,
1665         .set_rate       = clkset_rate_freediv_autosel_parents,
1666         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1667         .clksel_con     = CRU_CLKSELS_CON(31),
1668         CRU_DIV_SET(0x1f, 0, 32),
1669         CRU_SRC_SET(0x1, 7),
1670         CRU_PARENTS_SET(aclk_lcdc0_parents),
1671 };
1672
1673 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1674
1675 static struct clk aclk_lcdc1_pre = {
1676         .name           = "aclk_lcdc1_pre",
1677         .parent         = &codec_pll_clk,
1678         .mode           = gate_mode,
1679         .recalc         = clksel_recalc_div,
1680         .set_rate       = clkset_rate_freediv_autosel_parents,
1681         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1682         .clksel_con     = CRU_CLKSELS_CON(31),
1683         CRU_DIV_SET(0x1f, 8, 32),
1684         CRU_SRC_SET(0x1, 15),
1685         CRU_PARENTS_SET(aclk_lcdc1_parents),
1686 };
1687
1688 /* aclk/hclk/pclk periph setting */
1689 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1690
1691 static struct clk aclk_periph = {
1692         .name           = "aclk_periph",
1693         .parent         = &general_pll_clk,
1694         .mode           = gate_mode,
1695         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1696         .recalc         = clksel_recalc_div,
1697         .set_rate       = clksel_set_rate_freediv,
1698         .clksel_con     = CRU_CLKSELS_CON(10),
1699         CRU_DIV_SET(0x1f, 0, 32),
1700         CRU_SRC_SET(1, 15),
1701         CRU_PARENTS_SET(aclk_periph_parents),
1702 };
1703 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1704
1705 static struct clk pclk_periph = {
1706         .name           = "pclk_periph",
1707         .parent         = &aclk_periph,
1708         .mode           = gate_mode,
1709         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1710         .recalc         = clksel_recalc_shift,
1711         .set_rate       = clksel_set_rate_shift,
1712         .clksel_con     = CRU_CLKSELS_CON(10),
1713         CRU_DIV_SET(0x3, 12, 8),
1714 };
1715
1716 static struct clk hclk_periph = {
1717         .name           = "hclk_periph",
1718         .parent         = &aclk_periph,
1719         .mode           = gate_mode,
1720         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1721         .recalc         = clksel_recalc_shift,
1722         .set_rate       = clksel_set_rate_shift,
1723         .clksel_con     = CRU_CLKSELS_CON(10),
1724         CRU_DIV_SET(0x3, 8, 4),
1725 };
1726 /* dclk lcdc setting */
1727 // FIXME
1728 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1729 {
1730         u32 div, old_div;
1731         int i;
1732         unsigned long new_rate;
1733         int ret = 0;
1734
1735         if(clk->rate == rate)
1736                 return 0;
1737         for(i = 0; i < 2; i++) {
1738                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1739                 new_rate = clk->parents[i]->rate / div;
1740                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1741                         break;
1742                 }
1743         }
1744         if(i >= 2) {
1745                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1746                 return -1;
1747         }
1748
1749         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1750
1751         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1752                         clk->div_shift, clk->div_mask) + 1;
1753         if(div > old_div)
1754                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1755
1756         if(clk->parents[i] != clk->parent) {
1757                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1758         }
1759
1760         if (ret) {
1761                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1762                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1763                 return ret;
1764         }
1765         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1766         return 0;
1767 }
1768
1769 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1770 {
1771         if (rate == 27 * MHZ)
1772                 return clkset_rate_freediv_autosel_parents(clk, rate);
1773         else
1774                 return clkset_rate_evendiv_autosel_parents(clk, rate);
1775
1776 #if 0
1777         int ret = 0;
1778         struct clk *parent;
1779         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1780                 parent = clk->parents[1];
1781                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1782         } else {
1783                 parent = clk->parents[0];
1784         }
1785         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1786         //clk->name,rate,parent->name,clk->parent->name);
1787
1788         if(parent != clk->parents[1]) {
1789                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1790                 if (ret) {
1791                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1792                         return ret;
1793                 }
1794         }
1795         if (clk->parent != parent) {
1796                 ret = clk_set_parent_nolock(clk, parent);
1797                 if (ret) {
1798                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1799                         return ret;
1800                 }
1801         }
1802         return ret;
1803 #endif
1804 }
1805
1806 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1807 static struct clk dclk_lcdc0 = {
1808         .name           = "dclk_lcdc0",
1809         .mode           = gate_mode,
1810         .set_rate       = dclk_lcdc_set_rate,
1811         .recalc         = clksel_recalc_div,
1812         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1813         .clksel_con     = CRU_CLKSELS_CON(27),
1814         CRU_SRC_SET(0x1, 0),
1815         CRU_DIV_SET(0xff, 8, 256),
1816         CRU_PARENTS_SET(dclk_lcdc0_parents),
1817 };
1818
1819 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1820 static struct clk dclk_lcdc1 = {
1821         .name           = "dclk_lcdc1",
1822         .mode           = gate_mode,
1823         .set_rate       = dclk_lcdc_set_rate,
1824         .recalc         = clksel_recalc_div,
1825         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1826         .clksel_con     = CRU_CLKSELS_CON(28),
1827         CRU_SRC_SET(0x1, 0),
1828         CRU_DIV_SET(0xff, 8, 256),
1829         CRU_PARENTS_SET(dclk_lcdc1_parents),
1830 };
1831
1832 /* cif setting */
1833 // FIXME
1834 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1835 static struct clk cif_out_pll = {
1836         .name           = "cif_out_pll",
1837         .parent         = &general_pll_clk,
1838         .clksel_con     = CRU_CLKSELS_CON(29),
1839         CRU_SRC_SET(0x1, 0),
1840         CRU_PARENTS_SET(cifout_sel_pll_parents),
1841 };
1842
1843 static struct clk cif0_out_div = {
1844         .name           = "cif0_out_div",
1845         .parent         = &cif_out_pll,
1846         .mode           = gate_mode,
1847         .recalc         = clksel_recalc_div,
1848         .set_rate       = clksel_set_rate_freediv,
1849         .gate_idx       = CLK_GATE_CIF0_OUT,
1850         .clksel_con     = CRU_CLKSELS_CON(29),
1851         CRU_DIV_SET(0x1f, 1, 32),
1852 };
1853
1854 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1855 {
1856         int ret = 0;
1857         struct clk *parent;
1858
1859         if (rate == 24 * MHZ) {
1860                 parent = clk->parents[1];
1861         } else {
1862                 parent = clk->parents[0];
1863                 ret = clk_set_rate_nolock(parent, rate);
1864                 if (ret)
1865                         return ret;
1866         }
1867         if (clk->parent != parent)
1868                 ret = clk_set_parent_nolock(clk, parent);
1869
1870         return ret;
1871 }
1872
1873 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1874 static struct clk cif0_out = {
1875         .name           = "cif0_out",
1876         .parent         = &cif0_out_div,
1877         .set_rate       = cif_out_set_rate,
1878         .clksel_con     = CRU_CLKSELS_CON(29),
1879         CRU_SRC_SET(0x1, 7),
1880         CRU_PARENTS_SET(cif0_out_parents),
1881 };
1882
1883 static struct clk pclkin_cif0 = {
1884         .name           = "pclkin_cif0",
1885         .mode           = gate_mode,
1886         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1887 };
1888
1889 static struct clk inv_cif0 = {
1890         .name           = "inv_cif0",
1891         .parent         = &pclkin_cif0,
1892 };
1893
1894 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1895 static struct clk cif0_in = {
1896         .name           = "cif0_in",
1897         .parent         = &pclkin_cif0,
1898         .clksel_con     = CRU_CLKSELS_CON(30),
1899         CRU_SRC_SET(0x1, 8),
1900         CRU_PARENTS_SET(cif0_in_parents),
1901 };
1902
1903 /* i2s/spdif setting */
1904 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1905 static struct clk clk_i2s_pll = {
1906         .name           = "i2s_pll",
1907         .parent         = &general_pll_clk,
1908         .clksel_con     = CRU_CLKSELS_CON(2),
1909         CRU_SRC_SET(0x1, 15),
1910         CRU_PARENTS_SET(clk_i2s_div_parents),
1911 };
1912
1913 static struct clk clk_i2s0_div = {
1914         .name           = "i2s0_div",
1915         .parent         = &clk_i2s_pll,
1916         .mode           = gate_mode,
1917         .recalc         = clksel_recalc_div,
1918         .set_rate       = clksel_set_rate_freediv,
1919         .round_rate     = clksel_freediv_round_rate,
1920         .gate_idx       = CLK_GATE_I2S0_SRC,
1921         .clksel_con     = CRU_CLKSELS_CON(3),
1922         CRU_DIV_SET(0x7f, 0, 64),
1923 };
1924
1925 static struct clk clk_spdif_div = {
1926         .name           = "spdif_div",
1927         .parent         = &clk_i2s_pll,
1928         .recalc         = clksel_recalc_div,
1929         .set_rate       = clksel_set_rate_freediv,
1930         .round_rate     = clksel_freediv_round_rate,
1931         .mode           = gate_mode,
1932         .gate_idx       = CLK_GATE_SPDIF_SRC,
1933         .clksel_con     = CRU_CLKSELS_CON(5),
1934         CRU_DIV_SET(0x7f, 0, 64),
1935 };
1936 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1937 {
1938         u32 numerator, denominator;
1939         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1940         //clk->parent->parent
1941         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1942                                 &numerator, &denominator) == 0) {
1943                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1944                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1945                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1946         } else {
1947                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1948                 return -ENOENT;
1949         }
1950         return 0;
1951 }
1952
1953 static struct clk clk_i2s0_frac_div = {
1954         .name           = "i2s0_frac_div",
1955         .parent         = &clk_i2s0_div,
1956         .mode           = gate_mode,
1957         .gate_idx       = CLK_GATE_I2S0_FRAC,
1958         .recalc         = clksel_recalc_frac,
1959         .set_rate       = clk_i2s_fracdiv_set_rate,
1960         .clksel_con     = CRU_CLKSELS_CON(7),
1961 };
1962
1963 static struct clk clk_spdif_frac_div = {
1964         .name           = "spdif_frac_div",
1965         .parent         = &clk_spdif_div,
1966         .mode           = gate_mode,
1967         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1968         .recalc         = clksel_recalc_frac,
1969         .set_rate       = clk_i2s_fracdiv_set_rate,
1970         .clksel_con     = CRU_CLKSELS_CON(9),
1971 };
1972
1973 #define I2S_SRC_DIV     (0x0)
1974 #define I2S_SRC_FRAC    (0x1)
1975 #define I2S_SRC_12M     (0x2)
1976
1977 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1978 {
1979         int ret = -EINVAL;
1980         struct clk *parent;
1981
1982         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1983                 parent = clk->parents[I2S_SRC_12M];
1984         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1985                 parent = clk->parents[I2S_SRC_DIV];
1986         } else {
1987                 parent = clk->parents[I2S_SRC_FRAC];
1988         }
1989
1990         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1991                         clk->name, rate, parent->name, clk->parent->name);
1992
1993         if(parent != clk->parents[I2S_SRC_12M]) {
1994                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1995                 if (ret) {
1996                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1997                         return ret;
1998                 }
1999         }
2000
2001         if (clk->parent != parent) {
2002                 ret = clk_set_parent_nolock(clk, parent);
2003                 if (ret) {
2004                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2005                         return ret;
2006                 }
2007         }
2008
2009         return ret;
2010 };
2011
2012 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
2013
2014 static struct clk clk_i2s0 = {
2015         .name           = "i2s0",
2016         .set_rate       = i2s_set_rate,
2017         .clksel_con     = CRU_CLKSELS_CON(3),
2018         CRU_SRC_SET(0x3, 8),
2019         CRU_PARENTS_SET(clk_i2s0_parents),
2020 };
2021
2022 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
2023
2024 static struct clk clk_spdif = {
2025         .name           = "spdif",
2026         .parent         = &clk_spdif_frac_div,
2027         .set_rate       = i2s_set_rate,
2028         .clksel_con = CRU_CLKSELS_CON(5),
2029         CRU_SRC_SET(0x3, 8),
2030         CRU_PARENTS_SET(clk_spdif_parents),
2031 };
2032
2033 /* otgphy setting */
2034 GATE_CLK(otgphy0, xin24m, OTGPHY0);
2035 GATE_CLK(otgphy1, xin24m, OTGPHY1);
2036
2037 static struct clk clk_otgphy0_480m = {
2038         .name           = "otgphy0_480m",
2039         .parent         = &clk_otgphy0,
2040 };
2041 static struct clk clk_otgphy1_480m = {
2042         .name           = "otgphy1_480m",
2043         .parent         = &clk_otgphy1,
2044 };
2045
2046 /* hsicphy setting */
2047 #ifdef ARCH_RK31
2048 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
2049 static struct clk clk_hsicphy_480m = {
2050         .name           = "hsicphy_480m",
2051         .parent         = &clk_otgphy0_480m,
2052         .clksel_con      = CRU_CLKSELS_CON(30),
2053         CRU_SRC_SET(0x3, 0),
2054         CRU_PARENTS_SET(clk_hsicphy_parents),
2055 };
2056 static struct clk clk_hsicphy_12m = {
2057         .name           = "hsicphy_12m",
2058         .parent         = &clk_hsicphy_480m,
2059         .clksel_con     = CRU_CLKSELS_CON(11),
2060         CRU_DIV_SET(0x3f, 8, 64),
2061 };
2062 #endif
2063
2064 /* mac and rmii setting */
2065 // FIXME
2066 static struct clk rmii_clkin = {
2067         .name           = "rmii_clkin",
2068 };
2069 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
2070 static struct clk clk_mac_pll_div = {
2071         .name           = "mac_pll_div",
2072         .parent         = &general_pll_clk,
2073         .mode           = gate_mode,
2074         .gate_idx       = CLK_GATE_MAC_SRC,
2075         .recalc         = clksel_recalc_div,
2076         .set_rate       = clksel_set_rate_freediv,
2077         .clksel_con     = CRU_CLKSELS_CON(21),
2078         CRU_DIV_SET(0x1f, 8, 32),
2079         CRU_SRC_SET(0x1, 0),
2080         CRU_PARENTS_SET(clk_mac_ref_div_parents),
2081 };
2082
2083 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
2084 {
2085         if(clk->parent == clk->parents[1]) {
2086                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
2087                 return -ENOENT;
2088         } else if(clk->parent == clk->parents[0]) {
2089                 return clk_set_rate_nolock(clk->parents[0], rate);
2090         }
2091         return -ENOENT;
2092 }
2093
2094 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
2095
2096 static struct clk clk_mac_ref = {
2097         .name           = "mac_ref",
2098         .parent         = &clk_mac_pll_div,
2099         .set_rate       = clksel_mac_ref_set_rate,
2100         .clksel_con     = CRU_CLKSELS_CON(21),
2101         CRU_SRC_SET(0x1, 4),
2102         CRU_PARENTS_SET(clk_mac_ref_parents),
2103 };
2104
2105 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
2106 {
2107         return clk_set_parent_nolock(clk->parent, parent);
2108 }
2109
2110 static struct clk clk_mii_tx = {
2111         .name           = "mii_tx",
2112         .parent         = &clk_mac_ref,
2113         //.set_parent   = clk_set_mii_tx_parent,
2114         .mode           = gate_mode,
2115         .gate_idx       = CLK_GATE_MAC_LBTEST,
2116 };
2117
2118 /* hsadc and saradc */
2119 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
2120 static struct clk clk_hsadc_pll_div = {
2121         .name           = "hsadc_pll_div",
2122         .parent         = &general_pll_clk,
2123         .mode           = gate_mode,
2124         .gate_idx       = CLK_GATE_HSADC_SRC,
2125         .recalc         = clksel_recalc_div,
2126         .round_rate     = clk_freediv_round_autosel_parents_rate,
2127         .set_rate       = clkset_rate_freediv_autosel_parents,
2128         //.round_rate   = clksel_freediv_round_rate,
2129         //.set_rate     = clksel_set_rate_freediv,
2130         .clksel_con = CRU_CLKSELS_CON(22),
2131         CRU_DIV_SET(0xff, 8, 256),
2132         CRU_SRC_SET(0x1, 0),
2133         CRU_PARENTS_SET(clk_hsadc_pll_parents),
2134 };
2135 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2136 {
2137         u32 numerator, denominator;
2138         //        clk_hsadc_pll_div->gpll/cpll
2139         //clk->parent->parent
2140         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2141                                 &numerator, &denominator) == 0) {
2142                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2143
2144                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2145
2146                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2147         } else {
2148                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2149                 return -ENOENT;
2150         }
2151         return 0;
2152 }
2153 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2154 {
2155         u32 numerator, denominator;
2156         u32 i, ret = 0;
2157         //        clk_hsadc_pll_div->gpll/cpll
2158         //clk->parent->parent
2159         for(i = 0; i < 2; i++) {
2160                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2161                                         &numerator, &denominator) == 0)
2162                         break;
2163         }
2164         if(i >= 2)
2165                 return -ENOENT;
2166
2167         if(clk->parent->parent != clk->parent->parents[i])
2168                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2169         if(ret == 0) {
2170                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2171
2172                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2173
2174                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2175         } else {
2176                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2177                 return -ENOENT;
2178         }
2179         return 0;
2180 }
2181
2182 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2183 {
2184         u32 numerator, denominator;
2185
2186         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2187         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2188                                 &numerator, &denominator) == 0)
2189                 return rate;
2190
2191         return 0;
2192 }
2193 static struct clk clk_hsadc_frac_div = {
2194         .name           = "hsadc_frac_div",
2195         .parent         = &clk_hsadc_pll_div,
2196         .mode           = gate_mode,
2197         .recalc         = clksel_recalc_frac,
2198         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2199         .round_rate     = clk_hsadc_fracdiv_round_rate,
2200         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
2201         .clksel_con     = CRU_CLKSELS_CON(23),
2202 };
2203
2204 #define HSADC_SRC_DIV 0x0
2205 #define HSADC_SRC_FRAC 0x1
2206 #define HSADC_SRC_EXT 0x2
2207 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2208 {
2209         int ret = -EINVAL;
2210         struct clk *parent;
2211
2212         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2213                 CLKDATA_DBG("hsadc clk is form ext\n");
2214                 return 0;
2215         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2216                 parent = clk->parents[HSADC_SRC_DIV];
2217         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2218                 parent = clk->parents[HSADC_SRC_FRAC];
2219         } else
2220                 parent = clk->parents[HSADC_SRC_DIV];
2221
2222         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2223                         clk->name, rate, parent->name, clk->parent->name);
2224
2225         ret = clk_set_rate_nolock(parent, rate);
2226         if (ret) {
2227                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2228                 return ret;
2229         }
2230         if (clk->parent != parent) {
2231                 ret = clk_set_parent_nolock(clk, parent);
2232                 if (ret) {
2233                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2234                         return ret;
2235                 }
2236         }
2237         return ret;
2238 }
2239
2240 static struct clk clk_hsadc_ext = {
2241         .name           = "hsadc_ext",
2242 };
2243
2244 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2245 static struct clk clk_hsadc_out = {
2246         .name           = "hsadc_out",
2247         .parent         = &clk_hsadc_pll_div,
2248         .set_rate       = clk_hsadc_set_rate,
2249         .clksel_con     = CRU_CLKSELS_CON(22),
2250         CRU_SRC_SET(0x3, 4),
2251         CRU_PARENTS_SET(clk_hsadc_out_parents),
2252 };
2253 static struct clk clk_hsadc_out_inv = {
2254         .name           = "hsadc_out_inv",
2255         .parent         = &clk_hsadc_out,
2256 };
2257
2258 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2259 static struct clk clk_hsadc = {
2260         .name           = "hsadc",
2261         .parent         = &clk_hsadc_out,
2262         .clksel_con     = CRU_CLKSELS_CON(22),
2263         CRU_SRC_SET(0x1, 7),
2264         CRU_PARENTS_SET(clk_hsadc_parents),
2265 };
2266
2267 static struct clk clk_saradc = {
2268         .name           = "saradc",
2269         .parent         = &xin24m,
2270         .mode           = gate_mode,
2271         .recalc         = clksel_recalc_div,
2272         .set_rate       = clksel_set_rate_freediv,
2273         .gate_idx       = CLK_GATE_SARADC_SRC,
2274         .clksel_con     = CRU_CLKSELS_CON(24),
2275         CRU_DIV_SET(0xff, 8, 256),
2276 };
2277
2278 /* smc setting */
2279 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2280 static struct clk clkn_smc = {
2281         .name           = "smc_inv",
2282         .parent         = &clk_smc,
2283 };
2284
2285 /* spi setting */
2286 static struct clk clk_spi0 = {
2287         .name           = "spi0",
2288         .parent         = &pclk_periph,
2289         .mode           = gate_mode,
2290         .recalc         = clksel_recalc_div,
2291         .set_rate       = clksel_set_rate_freediv,
2292         .gate_idx       = CLK_GATE_SPI0_SRC,
2293         .clksel_con     = CRU_CLKSELS_CON(25),
2294         CRU_DIV_SET(0x7f, 0, 128),
2295 };
2296
2297 static struct clk clk_spi1 = {
2298         .name           = "spi1",
2299         .parent         = &pclk_periph,
2300         .mode           = gate_mode,
2301         .recalc         = clksel_recalc_div,
2302         .set_rate       = clksel_set_rate_freediv,
2303         .gate_idx       = CLK_GATE_SPI1_SRC,
2304         .clksel_con     = CRU_CLKSELS_CON(25),
2305         CRU_DIV_SET(0x7f, 8, 128),
2306 };
2307
2308 /* sdmmc/sdio/emmc setting */
2309 static struct clk clk_sdmmc = {
2310         .name           = "sdmmc",
2311         .parent         = &hclk_periph,
2312         .mode           = gate_mode,
2313         .recalc         = clksel_recalc_div,
2314         .set_rate       = clksel_set_rate_even,
2315         .gate_idx       = CLK_GATE_MMC0_SRC,
2316         .clksel_con     = CRU_CLKSELS_CON(11),
2317         CRU_DIV_SET(0x3f, 0, 64),
2318 };
2319
2320 static struct clk clk_sdio = {
2321         .name           = "sdio",
2322         .parent         = &hclk_periph,
2323         .mode           = gate_mode,
2324         .recalc         = clksel_recalc_div,
2325         .set_rate       = clksel_set_rate_even,
2326         .gate_idx       = CLK_GATE_SDIO_SRC,
2327         .clksel_con     = CRU_CLKSELS_CON(12),
2328         CRU_DIV_SET(0x3f, 0, 64),
2329
2330 };
2331
2332 static struct clk clk_emmc = {
2333         .name           = "emmc",
2334         .parent         = &hclk_periph,
2335         .mode           = gate_mode,
2336         .recalc         = clksel_recalc_div,
2337         .set_rate       = clksel_set_rate_even,
2338         .gate_idx       = CLK_GATE_EMMC_SRC,
2339         .clksel_con     = CRU_CLKSELS_CON(12),
2340         CRU_DIV_SET(0x3f, 8, 64),
2341 };
2342
2343 /* uart setting */
2344 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2345 static struct clk clk_uart_pll = {
2346         .name           = "uart_pll",
2347         .parent         = &general_pll_clk,
2348         .clksel_con     = CRU_CLKSELS_CON(12),
2349         CRU_SRC_SET(0x1, 15),
2350         CRU_PARENTS_SET(clk_uart_src_parents),
2351 };
2352 static struct clk clk_uart0_div = {
2353         .name           = "uart0_div",
2354         .parent         = &clk_uart_pll,
2355         .mode           = gate_mode,
2356         .gate_idx       = CLK_GATE_UART0_SRC,
2357         .recalc         = clksel_recalc_div,
2358         .set_rate       = clksel_set_rate_freediv,
2359         .round_rate     = clksel_freediv_round_rate,
2360         .clksel_con     = CRU_CLKSELS_CON(13),
2361         CRU_DIV_SET(0x7f, 0, 64),
2362 };
2363 static struct clk clk_uart1_div = {
2364         .name           = "uart1_div",
2365         .parent         = &clk_uart_pll,
2366         .mode           = gate_mode,
2367         .gate_idx       = CLK_GATE_UART1_SRC,
2368         .recalc         = clksel_recalc_div,
2369         .round_rate     = clksel_freediv_round_rate,
2370         .set_rate       = clksel_set_rate_freediv,
2371         .clksel_con     = CRU_CLKSELS_CON(14),
2372         CRU_DIV_SET(0x7f, 0, 64),
2373 };
2374
2375 static struct clk clk_uart2_div = {
2376         .name           = "uart2_div",
2377         .parent         = &clk_uart_pll,
2378         .mode           = gate_mode,
2379         .gate_idx       = CLK_GATE_UART2_SRC,
2380         .recalc         = clksel_recalc_div,
2381         .round_rate     = clksel_freediv_round_rate,
2382         .set_rate       = clksel_set_rate_freediv,
2383         .clksel_con     = CRU_CLKSELS_CON(15),
2384         CRU_DIV_SET(0x7f, 0, 64),
2385 };
2386
2387 static struct clk clk_uart3_div = {
2388         .name           = "uart3_div",
2389         .parent         = &clk_uart_pll,
2390         .mode           = gate_mode,
2391         .gate_idx       = CLK_GATE_UART3_SRC,
2392         .recalc         = clksel_recalc_div,
2393         .round_rate     = clksel_freediv_round_rate,
2394         .set_rate       = clksel_set_rate_freediv,
2395         .clksel_con     = CRU_CLKSELS_CON(16),
2396         CRU_DIV_SET(0x7f, 0, 64),
2397 };
2398 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2399 {
2400         u32 numerator, denominator;
2401         //clk_uart0_div->clk_uart_pll->gpll/cpll
2402         //clk->parent->parent
2403         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2404                                 &numerator, &denominator) == 0) {
2405                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2406
2407                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2408
2409                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2410         } else {
2411                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2412                 return -ENOENT;
2413         }
2414         return 0;
2415 }
2416
2417 static struct clk clk_uart0_frac_div = {
2418         .name           = "uart0_frac_div",
2419         .parent         = &clk_uart0_div,
2420         .mode           = gate_mode,
2421         .recalc         = clksel_recalc_frac,
2422         .set_rate       = clk_uart_fracdiv_set_rate,
2423         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2424         .clksel_con     = CRU_CLKSELS_CON(17),
2425 };
2426 static struct clk clk_uart1_frac_div = {
2427         .name           = "uart1_frac_div",
2428         .parent         = &clk_uart1_div,
2429         .mode           = gate_mode,
2430         .recalc         = clksel_recalc_frac,
2431         .set_rate       = clk_uart_fracdiv_set_rate,
2432         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2433         .clksel_con     = CRU_CLKSELS_CON(18),
2434 };
2435 static struct clk clk_uart2_frac_div = {
2436         .name           = "uart2_frac_div",
2437         .mode           = gate_mode,
2438         .parent         = &clk_uart2_div,
2439         .recalc         = clksel_recalc_frac,
2440         .set_rate       = clk_uart_fracdiv_set_rate,
2441         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2442         .clksel_con     = CRU_CLKSELS_CON(19),
2443 };
2444 static struct clk clk_uart3_frac_div = {
2445         .name           = "uart3_frac_div",
2446         .parent         = &clk_uart3_div,
2447         .mode           = gate_mode,
2448         .recalc         = clksel_recalc_frac,
2449         .set_rate       = clk_uart_fracdiv_set_rate,
2450         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2451         .clksel_con     = CRU_CLKSELS_CON(20),
2452 };
2453
2454 #define UART_SRC_DIV 0
2455 #define UART_SRC_FRAC 1
2456 #define UART_SRC_24M 2
2457
2458 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2459 {
2460         int ret = 0;
2461         struct clk *parent;
2462
2463         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2464                 parent = clk->parents[UART_SRC_24M];
2465         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2466                 parent = clk->parents[UART_SRC_DIV];
2467         } else {
2468                 parent = clk->parents[UART_SRC_FRAC];
2469         }
2470
2471         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2472                         clk->name, rate, parent->name, clk->parent->name);
2473
2474         if(parent != clk->parents[UART_SRC_24M]) {
2475                 ret = clk_set_rate_nolock(parent, rate);
2476                 if (ret) {
2477                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2478                         return ret;
2479                 }
2480         }
2481
2482         if (clk->parent != parent) {
2483                 ret = clk_set_parent_nolock(clk, parent);
2484                 if (ret) {
2485                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2486                         return ret;
2487                 }
2488         }
2489
2490         return ret;
2491 }
2492
2493 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2494 static struct clk clk_uart0 = {
2495         .name           = "uart0",
2496         .set_rate       = clk_uart_set_rate,
2497         .clksel_con     = CRU_CLKSELS_CON(13),
2498         CRU_SRC_SET(0x3, 8),
2499         CRU_PARENTS_SET(clk_uart0_parents),
2500 };
2501
2502 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2503 static struct clk clk_uart1 = {
2504         .name           = "uart1",
2505         .set_rate       = clk_uart_set_rate,
2506         .clksel_con     = CRU_CLKSELS_CON(14),
2507         CRU_SRC_SET(0x3, 8),
2508         CRU_PARENTS_SET(clk_uart1_parents),
2509 };
2510
2511 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2512 static struct clk clk_uart2 = {
2513         .name           = "uart2",
2514         .set_rate       = clk_uart_set_rate,
2515         .clksel_con     = CRU_CLKSELS_CON(15),
2516         CRU_SRC_SET(0x3, 8),
2517         CRU_PARENTS_SET(clk_uart2_parents),
2518 };
2519 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2520 static struct clk clk_uart3 = {
2521         .name           = "uart3",
2522         .set_rate       = clk_uart_set_rate,
2523         .clksel_con     = CRU_CLKSELS_CON(16),
2524         CRU_SRC_SET(0x3, 8),
2525         CRU_PARENTS_SET(clk_uart3_parents),
2526 };
2527
2528 /* timer setting */
2529 GATE_CLK(timer0, xin24m, TIMER0);
2530 GATE_CLK(timer1, xin24m, TIMER1);
2531 GATE_CLK(timer2, xin24m, TIMER2);
2532 GATE_CLK(timer3, xin24m, TIMER3);
2533 GATE_CLK(timer4, xin24m, TIMER4);
2534 GATE_CLK(timer5, xin24m, TIMER5);
2535 GATE_CLK(timer6, xin24m, TIMER6);
2536
2537 /*********************power domain*******************************/
2538 #if 1
2539 #ifdef RK30_CLK_OFFBOARD_TEST
2540 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2541 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2542 #else
2543 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2544 #define _pmu_set_power_domain pmu_set_power_domain
2545 #endif
2546
2547 static int pd_video_mode(struct clk *clk, int on)
2548 {
2549         u32 gate[3];
2550         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2551         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2552         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2553         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2554         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2555         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2556         pmu_set_power_domain(PD_VIDEO, on);
2557         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2558         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2559         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2560         return 0;
2561 }
2562
2563 static struct clk pd_video = {
2564         .name   = "pd_video",
2565         .flags  = IS_PD,
2566         .mode   = pd_video_mode,
2567         .gate_idx       = PD_VIDEO,
2568 };
2569 static int pd_display_mode(struct clk *clk, int on)
2570 {
2571         u32 gate[10];
2572         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2573         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2574         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2575         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2576         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2577         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2578         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2579         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2580         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2581         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2582         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2583         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2584         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2585         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2586         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2587         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2588         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2589         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2590         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2591         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2592         pmu_set_power_domain(PD_VIO, on);
2593         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2594         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2595         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2596         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2597         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2598         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2599         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2600         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2601         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2602         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2603         return 0;
2604 }
2605
2606 static struct clk pd_display = {
2607         .name   = "pd_vio",
2608         .flags  = IS_PD,
2609         .mode   = pd_display_mode,
2610         .gate_idx       = PD_VIO,
2611 };
2612 static struct clk pd_lcdc0 = {
2613         .parent = &pd_display,
2614         .name   = "pd_lcdc0",
2615 };
2616 static struct clk pd_lcdc1 = {
2617         .parent = &pd_display,
2618         .name   = "pd_lcdc1",
2619 };
2620 static struct clk pd_cif0 = {
2621         .parent = &pd_display,
2622         .name   = "pd_cif0",
2623 };
2624 static struct clk pd_rga = {
2625         .parent = &pd_display,
2626         .name   = "pd_rga",
2627 };
2628 static struct clk pd_ipp = {
2629         .parent = &pd_display,
2630         .name   = "pd_ipp",
2631 };
2632 static struct clk pd_hdmi = {
2633         .parent = &pd_display,
2634         .name   = "pd_hdmi",
2635 };
2636
2637
2638 static int pd_gpu_mode(struct clk *clk, int on)
2639 {
2640         u32 gate[3];
2641         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2642         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2643         pmu_set_power_domain(PD_GPU, on);
2644         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2645         return 0;
2646 }
2647
2648 static struct clk pd_gpu = {
2649         .name   = "pd_gpu",
2650         .flags  = IS_PD,
2651         .mode   = pd_gpu_mode,
2652         .gate_idx       = PD_GPU,
2653 };
2654
2655 static int pm_off_mode(struct clk *clk, int on)
2656 {
2657         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2658         return 0;
2659 }
2660 static struct clk pd_peri = {
2661         .name   = "pd_peri",
2662         .flags  = IS_PD,
2663         .mode   = pm_off_mode,
2664         .gate_idx       = PD_PERI,
2665 };
2666
2667
2668 #define PD_CLK(name) \
2669 {\
2670         .dev_id = NULL,\
2671         .con_id = #name,\
2672         .clk = &name,\
2673 }
2674
2675 #endif
2676 /************************rk30 fixed div clock****************************************/
2677
2678 /*************************aclk_cpu***********************/
2679
2680 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2681 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2682 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2683
2684 /*************************hclk_cpu***********************/
2685
2686 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2687 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2688 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2689 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2690 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2691 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2692 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2693 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2694 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2695 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2696 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2697 GATE_CLK(hclk_imem0,    hclk_cpu,       HCLK_IMEM0);
2698 GATE_CLK(hclk_imem1,    hclk_cpu,       HCLK_IMEM1);
2699
2700 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2701 GATE_CLK(pclk_uart0,    ahb2apb_cpu, PCLK_UART0);
2702 GATE_CLK(pclk_uart1,    ahb2apb_cpu, PCLK_UART1);
2703 /*************************pclk_cpu***********************/
2704 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2705 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2706 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2707 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2708 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2709 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2710 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2711 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2712 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2713 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2714 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2715 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2716 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2717 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2718 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2719
2720 /*************************aclk_periph***********************/
2721
2722 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2723 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2724 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2725 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2726 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2727 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2728
2729 /*************************hclk_periph***********************/
2730 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2731 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2732 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2733 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2734 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2735 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2736 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2737 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2738 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2739 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2740 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2741 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2742 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2743 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2744 /*************************pclk_periph***********************/
2745 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2746 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2747 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2748 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2749 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2750 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2751 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2752 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2753 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2754 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2755 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2756 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2757 /*************************aclk_lcdc0***********************/
2758
2759 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2760 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2761 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2762 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2763
2764 /*************************aclk_lcdc0***********************/
2765
2766 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2767 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2768 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2769
2770
2771 #if 1
2772 #define CLK(dev, con, ck) \
2773 {\
2774         .dev_id = dev,\
2775         .con_id = con,\
2776         .clk = ck,\
2777 }
2778
2779
2780 #define CLK1(name) \
2781 {\
2782         .dev_id = NULL,\
2783         .con_id = #name,\
2784         .clk = &clk_##name,\
2785 }
2786
2787 #endif
2788
2789 static struct clk_lookup clks[] = {
2790         CLK(NULL, "xin24m", &xin24m),
2791         //CLK(NULL, "xin27m", &xin27m),
2792         CLK(NULL, "xin12m", &clk_12m),
2793         CLK(NULL, "arm_pll", &arm_pll_clk),
2794         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2795         CLK(NULL, "codec_pll", &codec_pll_clk),
2796         CLK(NULL, "general_pll", &general_pll_clk),
2797
2798         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2799         CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2800
2801         CLK(NULL, "ddr", &clk_ddr),
2802         CLK(NULL, "cpu", &clk_core),
2803         CLK1(l2c),
2804         CLK1(core_dbg),
2805         CLK("smp_twd", NULL, &core_periph),
2806         CLK(NULL, "aclk_core", &aclk_core),
2807
2808         CLK(NULL, "logic", &clk_cpu_div),
2809         CLK(NULL, "aclk_cpu", &aclk_cpu),
2810         CLK(NULL, "pclk_cpu", &pclk_cpu),
2811         CLK(NULL, "atclk_cpu", &atclk_cpu),
2812         CLK(NULL, "hclk_cpu", &hclk_cpu),
2813         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2814
2815         CLK(NULL, "gpu",        &aclk_gpu),
2816
2817         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2818         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2819         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2820         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2821
2822         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2823         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2824
2825         CLK(NULL, "aclk_periph", &aclk_periph),
2826         CLK(NULL, "pclk_periph", &pclk_periph),
2827         CLK(NULL, "hclk_periph", &hclk_periph),
2828
2829         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2830         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2831
2832         CLK(NULL, "cif_out_pll", &cif_out_pll),
2833         CLK(NULL, "cif0_out_div", &cif0_out_div),
2834         CLK(NULL, "cif0_out", &cif0_out),
2835
2836         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2837         CLK(NULL, "inv_cif0", &inv_cif0),
2838         CLK(NULL, "cif0_in", &cif0_in),
2839
2840         CLK1(i2s_pll),
2841         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2842         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2843         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2844
2845         // actually no i2s1
2846         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2847         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2848         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2849
2850
2851         CLK1(spdif_div),
2852         CLK1(spdif_frac_div),
2853         CLK1(spdif),
2854
2855         CLK1(otgphy0),
2856         CLK1(otgphy1),
2857         CLK1(otgphy0_480m),
2858         CLK1(otgphy1_480m),
2859         CLK1(hsicphy_480m),
2860         CLK1(hsicphy_12m),
2861
2862         CLK(NULL, "rmii_clkin", &rmii_clkin),
2863         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2864         CLK1(mac_ref),
2865         CLK1(mii_tx),
2866
2867         CLK1(hsadc_pll_div),
2868         CLK1(hsadc_frac_div),
2869         CLK1(hsadc_ext),
2870         CLK1(hsadc_out),
2871         CLK1(hsadc_out_inv),
2872         CLK1(hsadc),
2873
2874         CLK1(saradc),
2875
2876         CLK1(smc),
2877         CLK(NULL, "smc_inv",    &clkn_smc),
2878
2879         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2880         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2881
2882         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2883         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2884         CLK1(emmc),
2885
2886         CLK1(uart_pll),
2887         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2888         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2889         CLK("rk_serial.0", "uart", &clk_uart0),
2890         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2891         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2892         CLK("rk_serial.1", "uart", &clk_uart1),
2893         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2894         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2895         CLK("rk_serial.2", "uart", &clk_uart2),
2896         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2897         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2898         CLK("rk_serial.3", "uart", &clk_uart3),
2899
2900         CLK1(timer0),
2901         CLK1(timer1),
2902         CLK1(timer2),
2903         CLK1(timer3),
2904         CLK1(timer4),
2905         CLK1(timer5),
2906         CLK1(timer6),
2907
2908         /*************************aclk_cpu***********************/
2909         CLK1(dma1),
2910         CLK1(intmem),
2911         CLK1(aclk_strc_sys),
2912
2913         /*************************hclk_cpu***********************/
2914         CLK1(rom),
2915         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2916         // actually no i2s1
2917         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2918         CLK1(hclk_spdif),
2919         CLK1(hclk_cpubus),
2920         CLK1(hclk_ahb2apb),
2921         CLK1(hclk_vio_bus),
2922         CLK1(hclk_lcdc0),
2923         CLK1(hclk_lcdc1),
2924         CLK1(hclk_cif0),
2925         CLK1(hclk_ipp),
2926         CLK1(hclk_rga),
2927         CLK1(hclk_imem0),
2928         CLK1(hclk_imem1),
2929
2930         /*************************pclk_cpu***********************/
2931         CLK1(pwm01),
2932         CLK1(pclk_timer0),
2933         CLK1(pclk_timer2),
2934         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2935         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2936         CLK1(gpio0),
2937         CLK1(gpio1),
2938         CLK1(gpio2),
2939         CLK1(efuse),
2940         CLK1(tzpc),
2941         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2942         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2943         CLK1(pclk_ddrupctl),
2944         CLK1(pclk_ddrpubl),
2945         CLK1(dbg),
2946         CLK1(grf),
2947         CLK1(pmu),
2948
2949         /*************************aclk_periph***********************/
2950         CLK1(dma2),
2951         CLK1(aclk_smc),
2952         CLK1(aclk_gps),
2953         CLK1(aclk_peri_niu),
2954         CLK1(aclk_cpu_peri),
2955         CLK1(aclk_peri_axi_matrix),
2956
2957         /*************************hclk_periph***********************/
2958         CLK1(hclk_peri_axi_matrix),
2959         CLK1(hclk_peri_ahb_arbi),
2960         CLK1(hclk_emem_peri),
2961         CLK1(hclk_mac),
2962         CLK1(nandc),
2963         CLK1(hclk_usb_peri),
2964         CLK1(hclk_otg0),
2965         CLK1(hclk_otg1),
2966         CLK1(hclk_hsic),
2967         CLK1(hclk_hsadc),
2968         CLK1(hclk_pidfilter),
2969         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2970         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2971         CLK1(hclk_emmc),
2972
2973         /*************************pclk_periph***********************/
2974         CLK1(pclk_peri_axi_matrix),
2975         CLK1(pwm23),
2976         CLK1(wdt),
2977         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2978         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2979         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2980         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2981         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2982         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2983         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2984         CLK1(gpio3),
2985         CLK1(pclk_saradc),
2986
2987         /*************************aclk_lcdc0***********************/
2988         CLK1(aclk_vio0),
2989         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2990         CLK1(aclk_cif0),
2991         CLK1(aclk_ipp),
2992
2993         /*************************aclk_lcdc1***********************/
2994         CLK1(aclk_vio1),
2995         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2996         CLK1(aclk_rga),
2997         /************************power domain**********************/
2998
2999         PD_CLK(pd_peri),
3000         PD_CLK(pd_display),
3001         PD_CLK(pd_lcdc0),
3002         PD_CLK(pd_lcdc1),
3003         PD_CLK(pd_cif0),
3004         //PD_CLK(pd_cif1),
3005         PD_CLK(pd_rga),
3006         PD_CLK(pd_ipp),
3007         //PD_CLK(pd_video),
3008         PD_CLK(pd_gpu),
3009         //PD_CLK(pd_dbg),
3010 };
3011 static void __init rk30_init_enable_clocks(void)
3012 {
3013         #if 0
3014         //clk_enable_nolock(&xin24m);
3015         //clk_enable_nolock(&clk_12m);
3016         //clk_enable_nolock(&arm_pll_clk);
3017         //clk_enable_nolock(&ddr_pll_clk);
3018         //clk_enable_nolock(&codec_pll_clk);
3019         //clk_enable_nolock(&general_pll_clk);
3020         #endif
3021         clk_enable_nolock(&clk_ddr);
3022         //clk_enable_nolock(&clk_core);
3023         clk_enable_nolock(&clk_cpu_div);
3024         clk_enable_nolock(&clk_core_gpll_path);
3025         clk_enable_nolock(&clk_ddr_gpll_path);
3026         clk_enable_nolock(&clk_l2c);
3027         clk_enable_nolock(&clk_core_dbg);
3028         clk_enable_nolock(&core_periph);
3029         clk_enable_nolock(&aclk_core);
3030         //clk_enable_nolock(&aclk_cpu);
3031         //clk_enable_nolock(&pclk_cpu);
3032         clk_enable_nolock(&atclk_cpu);
3033         //clk_enable_nolock(&hclk_cpu);
3034         clk_enable_nolock(&ahb2apb_cpu);
3035         #if 0
3036          clk_enable_nolock(&clk_gpu);
3037          clk_enable_nolock(&aclk_gpu);
3038          clk_enable_nolock(&aclk_gpu_slv);
3039          clk_enable_nolock(&aclk_gpu_mst);
3040
3041          clk_enable_nolock(&aclk_vepu);
3042          clk_enable_nolock(&hclk_vepu);
3043          clk_enable_nolock(&aclk_vdpu);
3044          clk_enable_nolock(&hclk_vdpu);
3045
3046          clk_enable_nolock(&aclk_lcdc0_pre);
3047          clk_enable_nolock(&aclk_lcdc1_pre);
3048
3049          clk_enable_nolock(&aclk_periph);
3050         clk_enable_nolock(&pclk_periph);
3051         clk_enable_nolock(&hclk_periph);
3052         #endif
3053         #if 0
3054          clk_enable_nolock(&dclk_lcdc0);
3055          clk_enable_nolock(&dclk_lcdc1);
3056
3057          clk_enable_nolock(&cif_out_pll);
3058          clk_enable_nolock(&cif0_out_div);
3059
3060          clk_enable_nolock(&cif0_out);
3061          clk_enable_nolock(&pclkin_cif0);
3062          clk_enable_nolock(&inv_cif0);
3063          clk_enable_nolock(&cif0_in);
3064
3065          clk_enable_nolock(&clk_i2s_pll);
3066          clk_enable_nolock(&clk_i2s0_div);
3067          clk_enable_nolock(&clk_i2s0_frac_div);
3068          clk_enable_nolock(&clk_i2s0);
3069
3070           actually no i2s1
3071          clk_enable_nolock(&clk_i2s0_div);
3072          clk_enable_nolock(&clk_i2s0_frac_div);
3073          clk_enable_nolock(&clk_i2s0);
3074
3075         clk_enable_nolock(&clk_spdif_div);
3076         clk_enable_nolock(&clk_spdif_frac_div);
3077         clk_enable_nolock(&clk_spdif);
3078         #endif
3079         #if 0
3080         clk_enable_nolock(&clk_otgphy0);
3081         clk_enable_nolock(&clk_otgphy1);
3082         clk_enable_nolock(&clk_otgphy0_480m);
3083         clk_enable_nolock(&clk_otgphy1_480m);
3084         clk_enable_nolock(&clk_hsicphy_480m);
3085         clk_enable_nolock(&clk_hsicphy_12m);
3086         #endif
3087
3088         #if 0
3089         clk_enable_nolock(&rmii_clkin);
3090         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
3091         clk_enable_nolock(&clk_mac_ref);
3092         clk_enable_nolock(&clk_mii_tx);
3093         #endif
3094
3095         #if 0
3096         clk_enable_nolock(&clk_hsadc_pll_div);
3097         clk_enable_nolock(&clk_hsadc_frac_div);
3098         clk_enable_nolock(&clk_hsadc_ext);
3099         clk_enable_nolock(&clk_hsadc_out);
3100         clk_enable_nolock(&clk_hsadc_out_inv);
3101         clk_enable_nolock(&clk_hsadc);
3102
3103         clk_enable_nolock(&clk_saradc);
3104         #endif
3105         /*
3106         clk_enable_nolock(&clk_smc);
3107         clk_enable_nolock(&clkn_smc);
3108         */
3109         /*
3110         clk_enable_nolock(&clk_spi0);
3111         clk_enable_nolock(&clk_spi1);
3112         */
3113         /*
3114         clk_enable_nolock(&clk_sdmmc);
3115         clk_enable_nolock(&clk_sdio);
3116         clk_enable_nolock(&clk_emmc);
3117         */
3118         #if 0
3119         clk_enable_nolock(&clk_uart_pll);
3120         clk_enable_nolock(&clk_uart0_div);
3121         clk_enable_nolock(&clk_uart0_frac_div);
3122         clk_enable_nolock(&clk_uart0);
3123         clk_enable_nolock(&clk_uart1_div);
3124         clk_enable_nolock(&clk_uart1_frac_div);
3125         clk_enable_nolock(&clk_uart1);
3126         clk_enable_nolock(&clk_uart2_div);
3127         clk_enable_nolock(&clk_uart2_frac_div);
3128         clk_enable_nolock(&clk_uart2);
3129         clk_enable_nolock(&clk_uart3_div);
3130         clk_enable_nolock(&clk_uart3_frac_div);
3131         clk_enable_nolock(&clk_uart3);
3132         #endif
3133         #if CONFIG_RK_DEBUG_UART == 0
3134                 clk_enable_nolock(&clk_uart0);
3135                 clk_enable_nolock(&clk_pclk_uart0);
3136         #elif CONFIG_RK_DEBUG_UART == 1
3137                 clk_enable_nolock(&clk_uart1);
3138                 clk_enable_nolock(&clk_pclk_uart1);
3139
3140         #elif CONFIG_RK_DEBUG_UART == 2
3141                 clk_enable_nolock(&clk_uart2);
3142                 clk_enable_nolock(&clk_pclk_uart2);
3143
3144         #elif CONFIG_RK_DEBUG_UART == 3
3145                 clk_enable_nolock(&clk_uart3);
3146                 clk_enable_nolock(&clk_pclk_uart3);
3147
3148         #endif
3149         #if 0
3150         clk_enable_nolock(&clk_timer0);
3151         clk_enable_nolock(&clk_timer1);
3152         clk_enable_nolock(&clk_timer2);
3153         #endif
3154
3155         /*************************aclk_cpu***********************/
3156         clk_enable_nolock(&clk_dma1);
3157         clk_enable_nolock(&clk_intmem);
3158         clk_enable_nolock(&clk_aclk_strc_sys);
3159
3160         /*************************hclk_cpu***********************/
3161         clk_enable_nolock(&clk_rom);
3162         #if 0
3163         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3164         // actually no i2s1
3165         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3166         clk_enable_nolock(&clk_hclk_spdif);
3167         #endif
3168         clk_enable_nolock(&clk_hclk_cpubus);
3169         clk_enable_nolock(&clk_hclk_ahb2apb);
3170         clk_enable_nolock(&clk_hclk_vio_bus);
3171         #if 0
3172         clk_enable_nolock(&clk_hclk_lcdc0);
3173         clk_enable_nolock(&clk_hclk_lcdc1);
3174         clk_enable_nolock(&clk_hclk_cif0);
3175         clk_enable_nolock(&clk_hclk_ipp);
3176         clk_enable_nolock(&clk_hclk_rga);
3177         #endif
3178         clk_enable_nolock(&clk_hclk_imem0);
3179         clk_enable_nolock(&clk_hclk_imem1);
3180
3181         /*************************pclk_cpu***********************/
3182         #if 0
3183         clk_enable_nolock(&clk_pwm01);
3184         clk_enable_nolock(&clk_pclk_timer0);
3185         clk_enable_nolock(&clk_pclk_timer1);
3186         clk_enable_nolock(&clk_pclk_timer2);
3187         clk_enable_nolock(&clk_i2c0);
3188         clk_enable_nolock(&clk_i2c1);
3189         clk_enable_nolock(&clk_gpio0);
3190         clk_enable_nolock(&clk_gpio1);
3191         clk_enable_nolock(&clk_gpio2);
3192         clk_enable_nolock(&clk_efuse);
3193         #endif
3194         clk_enable_nolock(&clk_tzpc);
3195         //clk_enable_nolock(&clk_pclk_uart0);
3196         //clk_enable_nolock(&clk_pclk_uart1);
3197         clk_enable_nolock(&clk_pclk_ddrupctl);
3198         clk_enable_nolock(&clk_pclk_ddrpubl);
3199         clk_enable_nolock(&clk_dbg);
3200         clk_enable_nolock(&clk_grf);
3201         clk_enable_nolock(&clk_pmu);
3202
3203         /*************************aclk_periph***********************/
3204         clk_enable_nolock(&clk_dma2);
3205         clk_enable_nolock(&clk_aclk_smc);
3206         clk_enable_nolock(&clk_aclk_peri_niu);
3207         clk_enable_nolock(&clk_aclk_cpu_peri);
3208         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3209
3210         /*************************hclk_periph***********************/
3211         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3212         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3213         clk_enable_nolock(&clk_hclk_emem_peri);
3214         //clk_enable_nolock(&clk_hclk_mac);
3215         clk_enable_nolock(&clk_nandc);
3216         clk_enable_nolock(&clk_hclk_usb_peri);
3217         #if 0
3218         clk_enable_nolock(&clk_hclk_otg0);
3219         clk_enable_nolock(&clk_hclk_otg1);
3220         clk_enable_nolock(&clk_hclk_hsic);
3221         clk_enable_nolock(&clk_hclk_gps);
3222         clk_enable_nolock(&clk_hclk_hsadc);
3223         clk_enable_nolock(&clk_hclk_pidfilter);
3224         clk_enable_nolock(&clk_hclk_sdmmc);
3225         clk_enable_nolock(&clk_hclk_sdio);
3226         clk_enable_nolock(&clk_hclk_emmc);
3227         #endif
3228
3229         /*************************pclk_periph***********************/
3230         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3231         #if 0
3232         clk_enable_nolock(&clk_pwm23);
3233         clk_enable_nolock(&clk_wdt);
3234         clk_enable_nolock(&clk_pclk_spi0);
3235         clk_enable_nolock(&clk_pclk_spi1);
3236         clk_enable_nolock(&clk_pclk_uart2);
3237         clk_enable_nolock(&clk_pclk_uart3);
3238         #endif
3239         #if 0
3240         clk_enable_nolock(&clk_i2c2);
3241         clk_enable_nolock(&clk_i2c3);
3242         clk_enable_nolock(&clk_i2c4);
3243         clk_enable_nolock(&clk_gpio3);
3244         clk_enable_nolock(&clk_pclk_saradc);
3245         #endif
3246         /*************************aclk_lcdc0***********************/
3247 #if 1
3248         //clk_enable_nolock(&clk_aclk_vio0);
3249         //clk_enable_nolock(&clk_aclk_lcdc0);
3250         //clk_enable_nolock(&clk_aclk_cif0);
3251         //clk_enable_nolock(&clk_aclk_ipp);
3252 #endif
3253         /*************************aclk_lcdc1***********************/
3254 #if 1
3255         //clk_enable_nolock(&clk_aclk_vio1);
3256         //clk_enable_nolock(&clk_aclk_lcdc1);
3257         //clk_enable_nolock(&clk_aclk_rga);
3258 #endif
3259         /************************power domain**********************/
3260
3261 }
3262 static void periph_clk_set_init(void)
3263 {
3264         unsigned long aclk_p, hclk_p, pclk_p;
3265         unsigned long ppll_rate = general_pll_clk.rate;
3266         //aclk 148.5
3267
3268         /* general pll */
3269         switch (ppll_rate) {
3270                 case 148500 * KHZ:
3271                         aclk_p = 148500 * KHZ;
3272                         hclk_p = aclk_p >> 1;
3273                         pclk_p = aclk_p >> 2;
3274                         break;
3275                 case 297 * MHZ:
3276                         aclk_p = ppll_rate >> 1;
3277                         hclk_p = aclk_p >> 0;
3278                         pclk_p = aclk_p >> 1;
3279                         break;
3280                 case 300 * MHZ:
3281                         aclk_p = ppll_rate >> 1;
3282                         hclk_p = aclk_p >> 0;
3283                         pclk_p = aclk_p >> 1;
3284                         break;
3285                 case 384 * MHZ:
3286                         aclk_p = ppll_rate >> 1;
3287                         hclk_p = aclk_p >> 1;
3288                         pclk_p = aclk_p >> 2;
3289                         break;
3290                 case 594 * MHZ:
3291                         aclk_p = ppll_rate >> 2;
3292                         hclk_p = aclk_p >> 0;
3293                         pclk_p = aclk_p >> 1;
3294                         break;
3295                 case 768 * MHZ:
3296                         aclk_p = ppll_rate >> 2;
3297                         hclk_p = aclk_p >> 1;
3298                         pclk_p = aclk_p >> 2;
3299                         break;
3300                 case 891 * MHZ:
3301                         aclk_p = ppll_rate / 6;
3302                         hclk_p = aclk_p >> 0;
3303                         pclk_p = aclk_p >> 1;
3304                         break;
3305                 case 1188 * MHZ:
3306                         aclk_p = ppll_rate >> 3;
3307                         hclk_p = aclk_p >> 0;
3308                         pclk_p = aclk_p >> 1;
3309                         break;
3310
3311                 default:
3312                         aclk_p = 150 * MHZ;
3313                         hclk_p = 150 * MHZ;
3314                         pclk_p = 75 * MHZ;
3315                         break;
3316         }
3317         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3318         clk_set_rate_nolock(&aclk_periph, aclk_p);
3319         clk_set_rate_nolock(&hclk_periph, hclk_p);
3320         clk_set_rate_nolock(&pclk_periph, pclk_p);
3321 }
3322
3323 static void cpu_axi_init(void)
3324 {
3325         unsigned long cpu_div_rate = 0, aclk_cpu_rate = 0, hclk_cpu_rate = 0,
3326                       pclk_cpu_rate = 0, ahb2apb_cpu_rate = 0;
3327         unsigned long gpll_rate = general_pll_clk.rate;
3328
3329         switch (gpll_rate) {
3330                 case 297 * MHZ:
3331                         cpu_div_rate = gpll_rate;
3332                         aclk_cpu_rate = cpu_div_rate >> 0;
3333                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3334                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3335                         break;
3336
3337                 case 384 * MHZ:
3338                         cpu_div_rate = gpll_rate >> 1;
3339                         aclk_cpu_rate = cpu_div_rate >> 0;
3340                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3341                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3342                         break;
3343
3344                 case 594 * MHZ:
3345                         cpu_div_rate = gpll_rate >> 1;
3346                         aclk_cpu_rate = cpu_div_rate >> 0;
3347                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3348                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3349                         break;
3350
3351                 case 768 * MHZ:
3352                         cpu_div_rate = gpll_rate >> 2;
3353                         aclk_cpu_rate = cpu_div_rate >> 0;
3354                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3355                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3356                         break;
3357
3358                 case 891 * MHZ:
3359                         cpu_div_rate = gpll_rate / 3;
3360                         aclk_cpu_rate = cpu_div_rate >> 0;
3361                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3362                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3363                         break;
3364
3365                 case 1188 * MHZ:
3366                         cpu_div_rate = gpll_rate >> 2;
3367                         aclk_cpu_rate = cpu_div_rate >> 0;
3368                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3369                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3370                         break;
3371
3372                 default:
3373                         aclk_cpu_rate = 150 * MHZ;
3374                         hclk_cpu_rate = 150 * MHZ;
3375                         pclk_cpu_rate = 75 * MHZ;
3376                         break;
3377         }
3378         ahb2apb_cpu_rate = pclk_cpu_rate;
3379
3380         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3381         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3382         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3383         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3384         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3385         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3386 }
3387
3388 void rk30_clock_common_i2s_init(void)
3389 {
3390         unsigned long i2s_rate;
3391         //20 times
3392         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3393                 i2s_rate = 49152000;
3394         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3395                 i2s_rate = 24576000;
3396         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3397                 i2s_rate = 22579000;
3398         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3399                 i2s_rate = 12288000;
3400         } else {
3401                 i2s_rate = 49152000;
3402         }
3403
3404         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3405                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3406         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3407                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3408         } else {
3409                 if(general_pll_clk.rate > codec_pll_clk.rate)
3410                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3411                 else
3412                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3413         }
3414 }
3415 void rk30_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
3416 {
3417         struct clk *p_clk;
3418         unsigned long rate;
3419         if(!(gpll_clk->rate%(48*MHZ)))
3420         {
3421                 p_clk=gpll_clk;
3422                 rate=48*MHZ;
3423         }
3424         else if(!(cpll_clk->rate%(48*MHZ)))
3425         {
3426                 p_clk=cpll_clk;
3427                 rate=48*MHZ;
3428         }
3429         else if(!(gpll_clk->rate%(49500*KHZ)))
3430         {
3431                 p_clk=gpll_clk;
3432                 rate=(49500*KHZ);
3433         }
3434         else if(!(cpll_clk->rate%(49500*KHZ)))
3435         {
3436                 p_clk=cpll_clk;
3437                 rate=(49500*KHZ);
3438         }
3439         else
3440         {
3441                 if(cpll_clk->rate>gpll_clk->rate)
3442                 {
3443                         p_clk=cpll_clk;
3444                 }
3445                 else
3446                 {
3447                         p_clk=gpll_clk;
3448                 }
3449                 rate=50*MHZ;
3450         }
3451         clk_set_parent_nolock(&clk_uart_pll, p_clk);
3452         clk_set_rate_nolock(&clk_uart0_div,rate);
3453         clk_set_rate_nolock(&clk_uart1_div,rate);
3454         clk_set_rate_nolock(&clk_uart2_div,rate);
3455         clk_set_rate_nolock(&clk_uart3_div,rate);
3456 }
3457
3458 static void inline clock_set_div(struct clk *clk,u32 div)
3459 {
3460         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3461 }
3462
3463 static void inline clock_set_max_div(struct clk *clk)
3464 {
3465         set_cru_bits_w_msk(clk->div_max - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3466 }
3467
3468 static void div_clk_for_pll_init(void)
3469 {
3470         clock_set_max_div(&clk_cpu_div);
3471         clock_set_max_div(&aclk_vdpu);
3472         clock_set_max_div(&aclk_vepu);
3473         clock_set_max_div(&aclk_gpu);
3474         clock_set_max_div(&aclk_lcdc0_pre);
3475         clock_set_max_div(&aclk_lcdc1_pre);
3476         clock_set_max_div(&aclk_periph);
3477         clock_set_max_div(&dclk_lcdc0);
3478         clock_set_max_div(&dclk_lcdc1);
3479         clock_set_max_div(&cif0_out_div);
3480         clock_set_max_div(&clk_i2s0_div);
3481         clock_set_max_div(&clk_spdif_div);
3482         clock_set_max_div(&clk_uart0_div);
3483         clock_set_max_div(&clk_uart1_div);
3484         clock_set_max_div(&clk_uart2_div);
3485         clock_set_max_div(&clk_uart3_div);
3486         clock_set_max_div(&clk_hsicphy_12m);
3487         clock_set_max_div(&clk_hsadc_pll_div);
3488         clock_set_max_div(&clk_saradc);
3489 }
3490
3491 static u8 pll_flag = 0;
3492
3493 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3494 {
3495         //general
3496         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3497         lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
3498
3499         //code pll
3500         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3501
3502         cpu_axi_init();
3503         clk_set_rate_nolock(&clk_core, 816 * MHZ);
3504         //periph clk
3505         periph_clk_set_init();
3506
3507         //i2s
3508         rk30_clock_common_i2s_init();
3509
3510         // spi
3511         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3512         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3513
3514         // uart
3515         rk30_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
3516
3517         //mac
3518         if(!(gpll_rate % (50 * MHZ))) {
3519                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3520
3521         } else if((!(ddr_pll_clk.rate % (50 * MHZ))) && (ddr_pll_clk.rate != 24 * MHZ) && ((pll_flag & 0x2) == 0)) {
3522                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3523
3524         } else {
3525                 CLKDATA_DBG("mac can't get 50mhz, set to gpll\n");
3526                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3527         }
3528
3529         //hsadc
3530         //auto pll sel
3531         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3532
3533         //lcdc0 lcd auto sel pll
3534         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3535         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3536
3537         //cif
3538         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3539
3540         //axi lcdc auto sel
3541         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3542         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3543         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3544         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3545
3546         //axi vepu auto sel
3547         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3548         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3549
3550         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3551         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3552         //gpu auto sel
3553         clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
3554         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3555
3556         clk_set_rate_nolock(&clk_uart0, 49500000);
3557         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3558         clk_set_rate_nolock(&clk_sdio, 24750000);
3559 }
3560
3561 static struct clk def_ops_clk = {
3562         .get_parent = clksel_get_parent,
3563         .set_parent = clksel_set_parent,
3564 };
3565
3566 #ifdef CONFIG_PROC_FS
3567 struct clk_dump_ops dump_ops;
3568 #endif
3569 void rk_dump_clock_info(void);
3570 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3571 {
3572         struct clk_lookup *lk;
3573
3574         if (soc_is_rk3188plus()) {
3575                 arm_pll_clk.recalc = plus_plls_clk_recalc;
3576                 ddr_pll_clk.recalc = plus_plls_clk_recalc;
3577                 codec_pll_clk.recalc = plus_plls_clk_recalc;
3578                 general_pll_clk.recalc = plus_plls_clk_recalc;
3579
3580                 arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
3581                 codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
3582                 general_pll_clk.set_rate = plus_gpll_clk_set_rate;
3583         }
3584
3585         rk_efuse_init();
3586         pll_flag = rk_pll_flag();
3587         printk("CLKDATA_MSG: pll_flag = 0x%02x\n", pll_flag);
3588
3589         if (0 != pll_flag) {
3590                 CLKDATA_DBG("CPLL=%lu, GPLL=%lu;CPLL CAN NOT LOCK, SET CPLL BY PASS, USE GPLL REPLACE CPLL\n",
3591                                 cpll, gpll);
3592                 codec_pll_clk.mode = NULL;
3593                 cpll = 24 * MHZ;
3594                 gpll = 891 * MHZ;
3595         }
3596
3597         clk_register_dump_ops(&dump_ops);
3598         clk_register_default_ops_clk(&def_ops_clk);
3599         rk30_clock_flags = flags;
3600         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3601 #ifdef RK30_CLK_OFFBOARD_TEST
3602                 rk30_clkdev_add(lk);
3603 #else
3604                 clkdev_add(lk);
3605 #endif
3606                 clk_register(lk->clk);
3607         }
3608
3609         div_clk_for_pll_init();
3610         clk_recalculate_root_clocks_nolock();
3611
3612         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3613
3614         /*
3615          * Only enable those clocks we will need, let the drivers
3616          * enable other clocks as necessary
3617          */
3618
3619         rk30_init_enable_clocks();
3620 #if 0
3621         // print loader config
3622         CLKDATA_DBG("%s clks register dbg start\n", __func__);
3623         rk_dump_clock_info();
3624         rk30_clk_dump_regs();
3625
3626         CLKDATA_DBG("%s clks register dbg end\n", __func__);
3627 #endif
3628         /*
3629          * Disable any unused clocks left on by the bootloader
3630          */
3631         //clk_disable_unused();
3632         rk30_clock_common_init(gpll, cpll);
3633         preset_lpj = loops_per_jiffy;
3634
3635         //gpio6_b7
3636         //regfile_writel(0xc0004000,0x10c);
3637         //cru_writel(0x07000000,CRU_MISC_CON);
3638
3639 }
3640 extern int rk3188_dvfs_init(void);
3641
3642 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3643 {
3644         CLKDATA_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
3645                         gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3646         _rk30_clock_data_init(gpll, cpll, flags);
3647         rk3188_dvfs_init();
3648 }
3649
3650 /*
3651  * You can override arm_clk rate with armclk= cmdline option.
3652  */
3653 static int __init armclk_setup(char *str)
3654 {
3655         get_option(&str, &armclk);
3656
3657         if (!armclk)
3658                 return 0;
3659         if (armclk < 10000)
3660                 armclk *= MHZ;
3661         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3662         return 0;
3663 }
3664 #ifndef RK30_CLK_OFFBOARD_TEST
3665 early_param("armclk", armclk_setup);
3666 #endif
3667
3668
3669 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3670 {
3671         struct clk *ck;
3672         int i;
3673         unsigned long rate = clk->rate;
3674         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3675         for (i = 0; i < deep; i++)
3676                 printk("    ");
3677
3678         printk("%-11s ", clk->name);
3679 #ifndef RK30_CLK_OFFBOARD_TEST
3680         if (clk->flags & IS_PD) {
3681                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3682         }
3683 #endif
3684         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3685                 int idx = clk->gate_idx;
3686                 u32 v;
3687                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3688                 printk("%s ", v ? "off" : "on ");
3689         }
3690
3691         if (clk->pll) {
3692                 u32 pll_mode;
3693                 u32 pll_id = clk->pll->id;
3694                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3695                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3696                         printk("slow   ");
3697                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3698                         printk("normal ");
3699                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3700                         printk("deep   ");
3701
3702                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3703                         printk("bypass ");
3704         } else if(clk == &clk_ddr) {
3705                 rate = clk->recalc(clk);
3706         }
3707
3708         if (rate >= MHZ) {
3709                 if (rate % MHZ)
3710                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3711                 else
3712                         printk("%ld MHz", rate / MHZ);
3713         } else if (rate >= KHZ) {
3714                 if (rate % KHZ)
3715                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3716                 else
3717                         printk("%ld KHz", rate / KHZ);
3718         } else {
3719                 printk("%ld Hz", rate);
3720         }
3721
3722         printk(" usecount = %d", clk->usecount);
3723
3724         if (clk->parent)
3725                 printk(" parent = %s", clk->parent->name);
3726
3727         printk("\n");
3728
3729         list_for_each_entry(ck, root_clocks, node) {
3730                 if (ck->parent == clk)
3731                         rk_dump_clock(ck, deep + 1, root_clocks);
3732         }
3733 }
3734
3735 #if 1
3736 struct list_head *get_rk_clocks_head(void);
3737
3738 void rk_dump_clock_info(void)
3739 {
3740         struct clk* clk;
3741         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3742                 if (!clk->parent)
3743                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3744         }
3745 }
3746 #endif
3747
3748 #ifdef CONFIG_PROC_FS
3749
3750 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3751 {
3752         struct clk *ck;
3753         int i;
3754         unsigned long rate = clk->rate;
3755         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3756         for (i = 0; i < deep; i++)
3757                 seq_printf(s, "    ");
3758
3759         seq_printf(s, "%-11s ", clk->name);
3760 #ifndef RK30_CLK_OFFBOARD_TEST
3761         if (clk->flags & IS_PD) {
3762                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3763         }
3764 #endif
3765         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3766                 int idx = clk->gate_idx;
3767                 u32 v;
3768                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3769                 seq_printf(s, "%s ", v ? "off" : "on ");
3770         }
3771
3772         if (clk->pll) {
3773                 u32 pll_mode;
3774                 u32 pll_id = clk->pll->id;
3775                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3776                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3777                         seq_printf(s, "slow   ");
3778                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3779                         seq_printf(s, "normal ");
3780                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3781                         seq_printf(s, "deep   ");
3782
3783                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3784                         seq_printf(s, "bypass ");
3785         } else if(clk == &clk_ddr) {
3786                 rate = clk->recalc(clk);
3787         }
3788
3789         if (rate >= MHZ) {
3790                 if (rate % MHZ)
3791                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3792                 else
3793                         seq_printf(s, "%ld MHz", rate / MHZ);
3794         } else if (rate >= KHZ) {
3795                 if (rate % KHZ)
3796                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3797                 else
3798                         seq_printf(s, "%ld KHz", rate / KHZ);
3799         } else {
3800                 seq_printf(s, "%ld Hz", rate);
3801         }
3802
3803         seq_printf(s, " usecount = %d", clk->usecount);
3804
3805         if (clk->parent)
3806                 seq_printf(s, " parent = %s", clk->parent->name);
3807
3808         seq_printf(s, "\n");
3809
3810         list_for_each_entry(ck, root_clocks, node) {
3811                 if (ck->parent == clk)
3812                         dump_clock(s, ck, deep + 1, root_clocks);
3813         }
3814 }
3815
3816 static void dump_regs(struct seq_file *s)
3817 {
3818         int i = 0;
3819         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3820         seq_printf(s, "\nPLLRegisters:\n");
3821         for(i = 0; i < END_PLL_ID; i++) {
3822                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3823                                 cru_readl(PLL_CONS(i, 0)),
3824                                 cru_readl(PLL_CONS(i, 1)),
3825                                 cru_readl(PLL_CONS(i, 2)),
3826                                 cru_readl(PLL_CONS(i, 3))
3827                           );
3828         }
3829         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3830
3831         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3832                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3833         }
3834         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3835                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3836         }
3837         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3838         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3839
3840         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3841                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3842         }
3843         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3844         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3845
3846 }
3847
3848 void rk30_clk_dump_regs(void)
3849 {
3850         int i = 0;
3851         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3852         printk("\nPLLRegisters:\n");
3853         for(i = 0; i < END_PLL_ID; i++) {
3854                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3855                                 cru_readl(PLL_CONS(i, 0)),
3856                                 cru_readl(PLL_CONS(i, 1)),
3857                                 cru_readl(PLL_CONS(i, 2)),
3858                                 cru_readl(PLL_CONS(i, 3))
3859                       );
3860         }
3861         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3862
3863         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3864                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3865         }
3866         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3867                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3868         }
3869         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3870         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3871
3872         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3873                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3874         }
3875         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3876         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3877
3878 }
3879
3880
3881 #ifdef CONFIG_PROC_FS
3882 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3883 struct clk_dump_ops dump_ops = {
3884         .dump_clk = dump_clock,
3885         .dump_regs = dump_regs,
3886 };
3887 #endif
3888
3889
3890 #endif /* CONFIG_PROC_FS */
3891
3892
3893
3894
3895 #ifdef RK30_CLK_OFFBOARD_TEST
3896 struct clk *test_get_parent(struct clk *clk) {
3897         return clk->parent;
3898 }
3899
3900 void i2s_test(void)
3901 {
3902         struct clk *i2s_clk = &clk_i2s0;
3903
3904         clk_enable_nolock(i2s_clk);
3905
3906         clk_set_rate_nolock(i2s_clk, 12288000);
3907         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3908         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3909         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3910         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3911         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3912
3913 }
3914
3915 void uart_test(void)
3916 {
3917         struct clk *uart_clk = &clk_uart0;
3918
3919         clk_enable_nolock(uart_clk);
3920
3921         clk_set_rate_nolock(uart_clk, 12288000);
3922         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3923         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3924         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3925         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3926         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3927
3928 }
3929 void hsadc_test(void)
3930 {
3931         struct clk *hsadc_clk = &clk_hsadc;
3932
3933         printk("******************hsadc_test**********************\n");
3934         clk_enable_nolock(hsadc_clk);
3935
3936         clk_set_rate_nolock(hsadc_clk, 12288000);
3937         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3938
3939
3940         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3941         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3942
3943         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3944
3945         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3946
3947         printk("******************hsadc out clock**********************\n");
3948
3949         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3950         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3951         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3952         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3953
3954
3955
3956 }
3957
3958 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3959 {
3960         //arm
3961         printk("*********arm_pll_clk***********\n");
3962         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3963
3964         printk("*********set clk_core parent***********\n");
3965         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3966         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3967
3968         //general
3969         printk("*********general_pll_clk***********\n");
3970         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3971
3972         //code pll
3973         printk("*********codec_pll_clk***********\n");
3974         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3975
3976
3977         printk("*********periph_clk_set_init***********\n");
3978         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3979         periph_clk_set_init();
3980
3981 #if 0 //
3982         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3983 #else
3984         printk("*********clk i2s***********\n");
3985         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3986         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3987         i2s_test();
3988 #endif
3989         // spi
3990         clk_enable_nolock(&clk_spi0);
3991         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3992         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3993         //saradc
3994         clk_enable_nolock(&clk_saradc);
3995         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3996         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3997         //sdio
3998         clk_enable_nolock(&clk_sdio);
3999         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
4000         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
4001         // uart
4002         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
4003         uart_test();
4004         //mac
4005         printk("*********mac***********\n");
4006
4007         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
4008         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
4009
4010         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
4011         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
4012         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
4013
4014         printk("*********mac mii set***********\n");
4015         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
4016         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
4017         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
4018         //hsadc
4019         printk("*********hsadc 1***********\n");
4020         //auto pll
4021         hsadc_test();
4022         //lcdc
4023         clk_enable_nolock(&dclk_lcdc0);
4024
4025         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
4026         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
4027
4028         //cif
4029         clk_enable_nolock(&cif0_out);
4030
4031         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
4032         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
4033
4034         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
4035         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4036
4037         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
4038         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4039         //cif_in
4040         clk_enable_nolock(&cif0_in);
4041         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
4042         //axi lcdc
4043         clk_enable_nolock(&aclk_lcdc0);
4044         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
4045         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
4046         //axi vepu
4047         clk_enable_nolock(&aclk_vepu);
4048         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4049         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
4050
4051         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
4052         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
4053
4054         printk("test end\n");
4055
4056         /* arm pll
4057            clk_set_rate_nolock(&arm_pll_clk, armclk);
4058            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
4059            */
4060         //
4061         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
4062         //
4063         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4064         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
4065
4066 }
4067
4068
4069
4070
4071
4072 static LIST_HEAD(rk30_clocks);
4073 static DEFINE_MUTEX(rk30_clocks_mutex);
4074
4075 static inline int __rk30clk_get(struct clk *clk)
4076 {
4077         return 1;
4078 }
4079 void rk30_clkdev_add(struct clk_lookup *cl)
4080 {
4081         mutex_lock(&rk30_clocks_mutex);
4082         list_add_tail(&cl->node, &rk30_clocks);
4083         mutex_unlock(&rk30_clocks_mutex);
4084 }
4085 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
4086         struct clk_lookup *p, *cl = NULL;
4087         int match, best = 0;
4088
4089         list_for_each_entry(p, &rk30_clocks, node) {
4090                 match = 0;
4091                 if (p->dev_id) {
4092                         if (!dev_id || strcmp(p->dev_id, dev_id))
4093                                 continue;
4094                         match += 2;
4095                 }
4096                 if (p->con_id) {
4097                         if (!con_id || strcmp(p->con_id, con_id))
4098                                 continue;
4099                         match += 1;
4100                 }
4101
4102                 if (match > best) {
4103                         cl = p;
4104                         if (match != 3)
4105                                 best = match;
4106                         else
4107                                 break;
4108                 }
4109         }
4110         return cl;
4111 }
4112
4113 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
4114         struct clk_lookup *cl;
4115
4116         mutex_lock(&rk30_clocks_mutex);
4117         cl = rk30_clk_find(dev_id, con_id);
4118         if (cl && !__rk30clk_get(cl->clk))
4119                 cl = NULL;
4120         mutex_unlock(&rk30_clocks_mutex);
4121
4122         return cl ? cl->clk : ERR_PTR(-ENOENT);
4123 }
4124 //EXPORT_SYMBOL(rk30_clk_get_sys);
4125
4126 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
4127         const char *dev_id = dev ? dev_name(dev) : NULL;
4128         return rk30_clk_get_sys(dev_id, con_id);
4129 }
4130 //EXPORT_SYMBOL(rk30_clk_get);
4131
4132
4133 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
4134
4135 void rk30_clocks_test(void)
4136 {
4137         struct clk *test_gpll;
4138         test_gpll = rk30_clk_get(NULL, "general_pll");
4139         if(test_gpll) {
4140                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
4141                 printk("gpll rate=%lu\n", test_gpll->rate);
4142         }
4143         //while(1);
4144 }
4145
4146 void __init rk30_clock_init_test(void)
4147 {
4148
4149         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
4150         //while(1);
4151 }
4152
4153
4154 #endif
4155
4156