1 /* linux/arch/arm/mach-rk30/clock_data.c
3 * Copyright (C) 2012 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/hardirq.h>
24 #include <plat/efuse.h>
26 #include <mach/iomux.h>
27 #include <mach/clock.h>
29 #include <mach/dvfs.h>
33 #define MHZ (1000UL * 1000UL)
35 #define CLK_LOOPS_JIFFY_REF 11996091ULL
36 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
37 #define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
38 void rk30_clk_dump_regs(void);
42 #define CLK_FLG_EXT_27MHZ (1<<0)
44 #define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
45 #define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
46 #define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
47 #define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
49 #define CLK_FLG_UART_1_3M (1<<5)
57 u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
67 u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
68 unsigned long rst_dly;//us
71 #define SET_PLL_DATA(_pll_id,_table) \
78 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
80 .rate = (_mhz) * KHZ, \
81 .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
82 .pllcon1 = PLL_CLKF_SET(nf),\
83 .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
84 .rst_dly=((nr*500)/24+1),\
88 #define _APLL_SET_LPJ(_mhz) \
89 .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
92 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
93 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
96 .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
97 .pllcon1 = PLL_CLKF_SET(nf),\
98 .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
99 .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
100 .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
101 _APLL_SET_LPJ(_mhz),\
102 .rst_dly=((nr*500)/24+1),\
105 #define CRU_DIV_SET(mask,shift,max) \
111 #define CRU_SRC_SET(mask,shift ) \
115 #define CRU_PARENTS_SET(parents_array) \
116 .parents=(parents_array),\
117 .parents_num=ARRAY_SIZE((parents_array))
119 #define CRU_GATE_MODE_SET(_func,_IDX) \
130 #define GATE_CLK(NAME,PARENT,ID) \
131 static struct clk clk_##NAME = { \
135 .gate_idx = CLK_GATE_##ID, \
137 #ifdef RK30_CLK_OFFBOARD_TEST
138 u32 TEST_GRF_REG[0x240];
139 u32 TEST_CRU_REG[0x240];
140 #define cru_readl(offset) (TEST_CRU_REG[offset/4])
142 u32 cru_writel_is_pr(u32 offset)
144 return (offset == 0x4000);
146 void cru_writel(u32 v, u32 offset)
149 u32 mask_v = v >> 16;
150 TEST_CRU_REG[offset/4] &= (~mask_v);
154 TEST_CRU_REG[offset/4] |= v;
155 TEST_CRU_REG[offset/4] &= 0x0000ffff;
157 if(cru_writel_is_pr(offset)) {
158 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
163 void cru_writel_i2s(u32 v, u32 offset)
165 TEST_CRU_REG[offset/4] = v;
167 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
169 #define regfile_readl(offset) (0xffffffff)
170 //#define pmu_readl(offset) readl(RK30_GRF_BASE + offset)
171 void rk30_clkdev_add(struct clk_lookup *cl);
173 #define regfile_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
174 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
175 #define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
176 #define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
178 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
183 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
184 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
185 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
186 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
188 #define CLKDATA_DBG(fmt, args...) do {} while(0)
189 #define CLKDATA_LOG(fmt, args...) do {} while(0)
191 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
192 #define CLKDATA_WARNING(fmt, args...) printk("CLKDATA_WANING:\t"fmt, ##args)
195 #define get_cru_bits(con,mask,shift)\
196 ((cru_readl((con)) >> (shift)) & (mask))
198 #define set_cru_bits_w_msk(val,mask,shift,con)\
199 cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
202 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
203 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
206 static u32 rk30_clock_flags = 0;
207 static struct clk codec_pll_clk;
208 static struct clk general_pll_clk;
209 static struct clk arm_pll_clk;
210 static unsigned long lpj_gpll;
211 static unsigned int __initdata armclk = 504 * MHZ;
214 /************************clk recalc div rate*********************************/
217 static unsigned long clksel_recalc_div(struct clk *clk)
219 u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
221 unsigned long rate = clk->parent->rate / div;
222 pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
227 static unsigned long clksel_recalc_shift(struct clk *clk)
229 u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
230 unsigned long rate = clk->parent->rate >> shift;
231 pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
236 static unsigned long clksel_recalc_shift_2(struct clk *clk)
238 u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
239 unsigned long rate = clk->parent->rate >> shift;
240 pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
244 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
246 unsigned long rate = clk->parent->rate;
247 pr_debug("%s new clock rate is %lu\n", clk->name, rate);
250 /********************************set div rate***********************************/
253 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
256 for (div = 0; div < clk->div_max; div++) {
257 u32 new_rate = clk->parent->rate / (div + 1);
258 if (new_rate <= rate) {
259 set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
260 //clk->rate = new_rate;
261 pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
262 clk->name, rate, div + 1);
270 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
273 for (shift = 0; (1 << shift) < clk->div_max; shift++) {
274 u32 new_rate = clk->parent->rate >> shift;
275 if (new_rate <= rate) {
276 set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
277 clk->rate = new_rate;
278 pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
279 clk->name, rate, shift);
287 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
291 for (shift = 1; (1 << shift) < clk->div_max; shift++) {
292 u32 new_rate = clk->parent->rate >> shift;
293 if (new_rate <= rate) {
294 set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
295 clk->rate = new_rate;
296 pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
297 clk->name, rate, shift);
305 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
308 for (div = 2; div < clk->div_max; div += 2) {
309 u32 new_rate = clk->parent->rate / div;
310 if (new_rate <= rate) {
311 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
312 clk->rate = new_rate;
313 pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
314 __func__, clk->name, rate, div);
320 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
323 unsigned long new_rate;
324 for (div = 0; div < div_max; div++) {
325 new_rate = rate / (div + 1);
326 if (new_rate <= rate_out) {
330 return div_max ? div_max : 1;
332 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
335 unsigned long new_rate;
336 for (div = 1; div < div_max; div += 2) {
337 new_rate = rate / (div + 1);
338 if (new_rate <= rate_out) {
342 return div_max ? div_max : 1;
344 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
346 unsigned long new_rate[2] = {0, 0};
349 if(clk->rate == rate)
351 for(i = 0; i < 2; i++) {
352 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
353 new_rate[i] = clk->parents[i]->rate / div[i];
354 if(new_rate[i] == rate) {
356 return clk->parents[i];
359 if(new_rate[0] < new_rate[1])
364 return clk->parents[i];
366 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
368 unsigned long new_rate[2] = {0, 0};
371 if(clk->rate == rate)
373 for(i = 0; i < 2; i++) {
374 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
375 new_rate[i] = clk->parents[i]->rate / div[i];
376 if(new_rate[i] == rate) {
378 return clk->parents[i];
381 if(new_rate[0] < new_rate[1])
386 return clk->parents[i];
389 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
394 if(clk->rate == rate)
396 p_clk = get_freediv_parents_div(clk, rate, &div);
401 CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
402 if (clk->parent != p_clk) {
403 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
406 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
408 ret = clk_set_parent_nolock(clk, p_clk);
410 CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
415 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
418 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
423 if(clk->rate == rate)
425 p_clk = get_evendiv_parents_div(clk, rate, &div);
430 CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
431 if (clk->parent != p_clk) {
432 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
435 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
437 ret = clk_set_parent_nolock(clk, p_clk);
439 CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
444 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
448 //rate==div rate //hdmi
449 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
454 p_clk = get_freediv_parents_div(clk, rate, &div);
459 if((p_clk->rate / div) != rate || (p_clk->rate % div))
462 if (clk->parent != p_clk) {
463 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
464 clk->div_shift, clk->div_mask) + 1;
466 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
468 ret = clk_set_parent_nolock(clk, p_clk);
470 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
475 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
479 /***************************round********************************/
481 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
483 return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
486 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
490 if(clk->rate == rate)
492 p_clk = get_freediv_parents_div(clk, rate, &div);
495 return p_clk->rate / div;
498 /**************************************others seting************************************/
500 static struct clk *clksel_get_parent(struct clk *clk) {
501 return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
503 static int clksel_set_parent(struct clk *clk, struct clk *parent)
506 if (unlikely(!clk->parents))
508 for (i = 0; (i < clk->parents_num); i++) {
509 if (clk->parents[i] != parent)
511 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
517 static int gate_mode(struct clk *clk, int on)
519 int idx = clk->gate_idx;
520 if (idx >= CLK_GATE_MAX)
523 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
524 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
525 // CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
527 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
528 // CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
529 // CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
533 /*****************************frac set******************************************/
535 static unsigned long clksel_recalc_frac(struct clk *clk)
539 u32 r = cru_readl(clk->clksel_con), numerator, denominator;
540 if (r == 0) // FPGA ?
541 return clk->parent->rate;
543 denominator = r & 0xFFFF;
544 rate64 = (u64)clk->parent->rate * numerator;
545 do_div(rate64, denominator);
547 pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
551 static u32 clk_gcd(u32 numerator, u32 denominator)
555 if (!numerator || !denominator)
557 if (numerator > denominator) {
573 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
574 u32 *numerator, u32 *denominator)
577 gcd_vl = clk_gcd(rate, rate_out);
578 CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
581 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
585 *numerator = rate_out / gcd_vl;
586 *denominator = rate / gcd_vl;
588 CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
589 *numerator, *denominator, *denominator / *numerator);
591 if (*numerator > 0xffff || *denominator > 0xffff ||
592 (*denominator / (*numerator)) < 20) {
593 CLKDATA_ERR("can't get a available nume and deno\n");
600 /* *********************pll **************************/
602 #define rk30_clock_udelay(a) udelay(a);
604 /*********************pll lock status**********************************/
605 //#define GRF_SOC_CON0 0x15c
606 static void pll_wait_lock(int pll_idx)
608 u32 pll_state[4] = {1, 0, 2, 3};
609 u32 bit = 0x20u << pll_state[pll_idx];
610 int delay = 24000000;
612 if (regfile_readl(GRF_SOC_STATUS0) & bit)
617 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
624 /***************************pll function**********************************/
625 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
629 if (PLLS_IN_NORM(pll_id)) {
630 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
631 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
634 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
637 CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
638 ,PLL_CONS(pll_id,1),pll_con1, rate64);
642 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
643 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
644 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
646 do_div(rate64, PLL_NR(pll_con0));
647 do_div(rate64, PLL_NO(pll_con0));
651 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
652 pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
656 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
660 static unsigned long plls_clk_recalc(struct clk *clk)
662 return pll_clk_recalc(clk->pll->id, clk->parent->rate);
664 static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
668 if (PLLS_IN_NORM(pll_id)) {
669 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
670 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
672 u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
674 do_div(rate64, PLUS_PLL_NR(pll_con0));
675 do_div(rate64, PLUS_PLL_NO(pll_con0));
680 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
684 static unsigned long plus_plls_clk_recalc(struct clk *clk)
686 DVFS_DBG("%s: for rk3188 plus\n", __func__);
687 return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
690 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
693 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
694 cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
701 cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
702 cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
704 rk30_clock_udelay(1);
705 cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
707 pll_wait_lock(pll_id);
710 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
713 CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
714 cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
720 static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
723 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
726 cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
727 cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
728 cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
729 cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
730 rk30_clock_udelay(5);
733 cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
736 rk30_clock_udelay(clk_set->rst_dly);
737 pll_wait_lock(pll_id);
740 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
745 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
747 struct _pll_data *pll_data = c->pll;
748 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
750 while(clk_set->rate) {
751 if (clk_set->rate == rate) {
756 if(clk_set->rate == rate) {
757 pll_clk_set_rate(clk_set, pll_data->id);
758 lpj_gpll = CLK_LOOPS_RECALC(rate);
760 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
766 static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
768 struct _pll_data *pll_data = c->pll;
769 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
770 DVFS_DBG("%s: for rk3188 plus\n", __func__);
772 while(clk_set->rate) {
773 if (clk_set->rate == rate) {
778 if(clk_set->rate == rate) {
779 plus_pll_clk_set_rate(clk_set, pll_data->id);
780 lpj_gpll = CLK_LOOPS_RECALC(rate);
782 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
787 #define PLL_FREF_MIN (183*KHZ)
788 #define PLL_FREF_MAX (1500*MHZ)
790 #define PLL_FVCO_MIN (300*MHZ)
791 #define PLL_FVCO_MAX (1500*MHZ)
793 #define PLL_FOUT_MIN (18750*KHZ)
794 #define PLL_FOUT_MAX (1500*MHZ)
796 #define PLL_NF_MAX (65536)
797 #define PLL_NR_MAX (64)
798 #define PLL_NO_MAX (64)
800 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
802 u32 nr, nf, no, nonr;
806 unsigned long fref, fvco, fout;
809 CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
810 if(!fin_hz || !fout_hz || fout_hz == fin_hz)
812 gcd_val = clk_gcd(fin_hz, fout_hz);
813 YFfenzi = fout_hz / gcd_val;
814 YFfenmu = fin_hz / gcd_val;
819 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
821 for(no = 1; no <= PLL_NO_MAX; no++) {
822 if(!(no == 1 || !(no % 2)))
829 if(nr > PLL_NR_MAX) //PLL_NR_MAX
833 if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
836 fvco = (fin_hz / nr) * nf;
837 if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
840 if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
853 static int pll_clk_mode(struct clk *clk, int on)
855 u8 pll_id = clk->pll->id;
856 u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
857 u32 dly = (nr * 500) / 24 + 1;
858 CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
860 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
861 rk30_clock_udelay(dly);
862 pll_wait_lock(pll_id);
863 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
865 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
866 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
871 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
873 struct _pll_data *pll_data = c->pll;
874 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
875 struct pll_clk_set temp_clk_set;
876 u32 clk_nr, clk_nf, clk_no;
878 if(rate == 24 * MHZ) {
879 cru_writel(PLL_MODE_SLOW(pll_data->id), CRU_MODE_CON);
880 cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll_data->id, 3));
883 while(clk_set->rate) {
884 if (clk_set->rate == rate) {
889 if(clk_set->rate == rate) {
890 CLKDATA_DBG("cpll get a rate\n");
891 pll_clk_set_rate(clk_set, pll_data->id);
894 CLKDATA_DBG("cpll get auto calc a rate\n");
895 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
896 pr_err("cpll auto set rate error\n");
899 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
900 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
901 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
902 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
903 pll_clk_set_rate(&temp_clk_set, pll_data->id);
908 static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
910 struct _pll_data *pll_data = c->pll;
911 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
912 struct pll_clk_set temp_clk_set;
913 u32 clk_nr, clk_nf, clk_no;
914 DVFS_DBG("%s: for rk3188 plus\n", __func__);
916 while(clk_set->rate) {
917 if (clk_set->rate == rate) {
922 if(clk_set->rate == rate) {
923 CLKDATA_DBG("cpll get a rate\n");
924 plus_pll_clk_set_rate(clk_set, pll_data->id);
927 CLKDATA_DBG("cpll get auto calc a rate\n");
928 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
929 pr_err("cpll auto set rate error\n");
932 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
933 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
934 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
935 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
936 plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
943 /* ******************fixed input clk ***********************************************/
944 static struct clk xin24m = {
950 static struct clk clk_12m = {
957 /************************************pll func***************************/
958 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
959 struct apll_clk_set *tables) {
960 const struct apll_clk_set *ps, *pt;
962 /* find the arm_pll we want. */
965 if (pt->rate == rate) {
969 // we are sorted, and ps->rate > pt->rate.
970 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
976 //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
979 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
981 return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
984 struct arm_clks_div_set {
990 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
993 .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
994 .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
995 |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
996 |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
997 |AHB2APB_W_MSK |AHB2APB_##_ahb2apb,\
999 struct arm_clks_div_set arm_clk_div_tlb[] = {
1000 _arm_clks_div_set(50 , 2, 11, 11, 11, 11),//25,50,50,50,50
1001 _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
1002 _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
1003 _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
1004 _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
1005 _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
1006 _arm_clks_div_set(0 , 2, 11, 11, 11, 11),//25,50,50,50,50
1008 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
1010 for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
1011 if(arm_clk_div_tlb[i].rate >= rate)
1012 return &arm_clk_div_tlb[i];
1019 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1021 unsigned long flags;
1022 const struct apll_clk_set *ps;
1023 u32 pll_id = clk->pll->id;
1025 u32 old_aclk_div = 0, new_aclk_div;
1027 ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1029 old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1030 new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1032 CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1033 ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1035 if(general_pll_clk.rate > clk->rate) {
1036 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1041 // ungating cpu gpll path
1042 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1043 // CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1045 local_irq_save(flags);
1046 //div arm clk for gpll
1048 cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1049 cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1051 loops_per_jiffy = lpj_gpll / temp_div;
1054 /*if core src don't select gpll ,apll neet to enter slow mode */
1055 //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1058 cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
1065 cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1066 cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1068 rk30_clock_udelay(1);
1069 cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
1071 pll_wait_lock(pll_id);
1074 //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1077 if(new_aclk_div>=old_aclk_div) {
1078 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1079 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1082 cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1083 if(old_aclk_div>new_aclk_div) {
1084 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1085 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1088 cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1090 loops_per_jiffy = ps->lpj;
1093 //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1095 local_irq_restore(flags);
1099 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1100 // , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1102 CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1103 cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1104 cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1105 cru_readl(CRU_CLKSELS_CON(1)));
1109 static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1111 unsigned long flags;
1112 const struct apll_clk_set *ps;
1113 u32 pll_id = clk->pll->id;
1115 u32 old_aclk_div = 0, new_aclk_div;
1116 DVFS_DBG("%s: for rk3188 plus\n", __func__);
1118 ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1120 old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1121 new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1123 CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1124 ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1126 if(general_pll_clk.rate > clk->rate) {
1127 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1132 // ungating cpu gpll path
1133 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1134 // CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1136 local_irq_save(flags);
1137 //div arm clk for gpll
1139 cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1140 cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1142 loops_per_jiffy = lpj_gpll / temp_div;
1145 /*if core src don't select gpll ,apll neet to enter slow mode */
1146 //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1149 cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
1150 cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1151 cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1152 cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
1153 rk30_clock_udelay(5);
1156 cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
1159 rk30_clock_udelay(ps->rst_dly);
1160 pll_wait_lock(pll_id);
1162 if(new_aclk_div>=old_aclk_div) {
1163 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1164 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1167 cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1168 if(old_aclk_div>new_aclk_div) {
1169 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1170 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1173 cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1175 loops_per_jiffy = ps->lpj;
1178 //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1180 local_irq_restore(flags);
1184 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1185 // , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1187 CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1188 cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1189 cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1190 cru_readl(CRU_CLKSELS_CON(1)));
1194 /************************************pll clocks***************************/
1196 static const struct apll_clk_set apll_clks[] = {
1197 //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1198 // _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1199 _APLL_SET_CLKS(2208, 1, 92, 1, 8, 81, 81, 21, 41, 21),
1200 _APLL_SET_CLKS(2184, 1, 91, 1, 8, 81, 81, 21, 41, 21),
1201 _APLL_SET_CLKS(2160, 1, 90, 1, 8, 81, 81, 21, 41, 21),
1202 _APLL_SET_CLKS(2136, 1, 89, 1, 8, 81, 81, 21, 41, 21),
1203 _APLL_SET_CLKS(2112, 1, 88, 1, 8, 81, 81, 21, 41, 21),
1204 _APLL_SET_CLKS(2088, 1, 87, 1, 8, 81, 81, 21, 41, 21),
1205 _APLL_SET_CLKS(2064, 1, 86, 1, 8, 81, 81, 21, 41, 21),
1206 _APLL_SET_CLKS(2040, 1, 85, 1, 8, 81, 81, 21, 41, 21),
1207 _APLL_SET_CLKS(2016, 1, 84, 1, 8, 81, 81, 21, 41, 21),
1208 _APLL_SET_CLKS(1992, 1, 83, 1, 8, 81, 81, 21, 41, 21),
1209 _APLL_SET_CLKS(1968, 1, 82, 1, 8, 81, 81, 21, 41, 21),
1210 _APLL_SET_CLKS(1944, 1, 81, 1, 8, 81, 81, 21, 41, 21),
1211 _APLL_SET_CLKS(1920, 1, 80, 1, 8, 81, 81, 21, 41, 21),
1212 _APLL_SET_CLKS(1896, 1, 79, 1, 8, 81, 81, 21, 41, 21),
1213 _APLL_SET_CLKS(1872, 1, 78, 1, 8, 81, 81, 21, 41, 21),
1214 _APLL_SET_CLKS(1848, 1, 77, 1, 8, 81, 81, 21, 41, 21),
1215 _APLL_SET_CLKS(1824, 1, 76, 1, 8, 81, 81, 21, 41, 21),
1216 _APLL_SET_CLKS(1800, 1, 75, 1, 8, 81, 81, 21, 41, 21),
1217 _APLL_SET_CLKS(1776, 1, 74, 1, 8, 81, 81, 21, 41, 21),
1218 _APLL_SET_CLKS(1752, 1, 73, 1, 8, 81, 81, 21, 41, 21),
1219 _APLL_SET_CLKS(1728, 1, 72, 1, 8, 81, 81, 21, 41, 21),
1220 _APLL_SET_CLKS(1704, 1, 71, 1, 8, 81, 81, 21, 41, 21),
1221 _APLL_SET_CLKS(1680, 1, 70, 1, 8, 41, 41, 21, 41, 21),
1222 _APLL_SET_CLKS(1656, 1, 69, 1, 8, 41, 41, 21, 41, 21),
1223 _APLL_SET_CLKS(1632, 1, 68, 1, 8, 41, 41, 21, 41, 21),
1224 _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 41, 21, 41, 21),
1225 _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 41, 21, 41, 21),
1226 _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 41, 21, 41, 21),
1227 _APLL_SET_CLKS(1488, 1, 62, 1, 8, 41, 41, 21, 41, 21),
1228 _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 41, 21, 41, 21),
1229 _APLL_SET_CLKS(1440, 1, 60, 1, 8, 41, 41, 21, 41, 21),
1230 _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 41, 21, 41, 21),
1231 _APLL_SET_CLKS(1392, 1, 58, 1, 8, 41, 41, 21, 41, 21),
1232 _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 41, 21, 41, 21),
1233 _APLL_SET_CLKS(1344, 1, 56, 1, 8, 41, 41, 21, 41, 21),
1234 _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 41, 21, 41, 21),
1235 _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 41, 21, 41, 21),
1236 _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 41, 21, 41, 21),
1237 _APLL_SET_CLKS(1248, 1, 52, 1, 8, 41, 41, 21, 41, 21),
1238 _APLL_SET_CLKS(1224, 1, 51, 1, 8, 41, 41, 21, 41, 21),
1239 _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 41, 21, 41, 21),
1240 _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 41, 21, 41, 21),
1241 _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 41, 21, 41, 21),
1242 _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 41, 21, 41, 21),
1243 _APLL_SET_CLKS(1008, 1, 84, 2, 8, 41, 31, 21, 41, 21),
1244 _APLL_SET_CLKS(912, 1, 76, 2, 8, 41, 31, 21, 41, 21),
1245 _APLL_SET_CLKS(888, 1, 74, 2, 8, 41, 31, 21, 41, 21),
1246 _APLL_SET_CLKS(816 , 1, 68, 2, 8, 41, 31, 21, 41, 21),
1247 _APLL_SET_CLKS(792 , 1, 66, 2, 8, 41, 31, 21, 41, 21),
1248 _APLL_SET_CLKS(696 , 1, 58, 2, 8, 41, 31, 21, 41, 21),
1249 _APLL_SET_CLKS(600 , 1, 50, 2, 4, 41, 31, 21, 41, 21),
1250 _APLL_SET_CLKS(504 , 1, 84, 4, 4, 41, 21, 21, 41, 21),
1251 _APLL_SET_CLKS(408 , 1, 68, 4, 4, 21, 21, 21, 41, 21),
1252 _APLL_SET_CLKS(312 , 1, 52, 4, 2, 21, 21, 21, 21, 11),
1253 _APLL_SET_CLKS(252 , 1, 84, 8, 2, 21, 21, 21, 21, 11),
1254 _APLL_SET_CLKS(216 , 1, 72, 8, 2, 21, 21, 21, 21, 11),
1255 _APLL_SET_CLKS(126 , 1, 84, 16, 2, 11, 21, 11, 11, 11),
1256 _APLL_SET_CLKS(48 , 1, 64, 32, 2, 11, 11, 11, 11, 11),
1257 _APLL_SET_CLKS(0 , 1, 21, 4, 2, 11, 11, 11, 11, 11),
1260 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1261 static struct clk arm_pll_clk = {
1264 .mode = pll_clk_mode,
1265 .recalc = plls_clk_recalc,
1266 .set_rate = arm_pll_clk_set_rate,
1267 .round_rate = arm_pll_clk_round_rate,
1271 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1273 /* do nothing here */
1276 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1277 static struct clk ddr_pll_clk = {
1280 .recalc = plls_clk_recalc,
1281 .set_rate = ddr_pll_clk_set_rate,
1285 static const struct pll_clk_set cpll_clks[] = {
1286 _PLL_SET_CLKS(360000, 1, 60, 4),
1287 _PLL_SET_CLKS(408000, 1, 68, 4),
1288 _PLL_SET_CLKS(456000, 1, 76, 4),
1289 _PLL_SET_CLKS(504000, 1, 84, 4),
1290 _PLL_SET_CLKS(552000, 1, 46, 2),
1291 _PLL_SET_CLKS(594000, 2, 198, 4),
1292 _PLL_SET_CLKS(600000, 1, 50, 2),
1293 _PLL_SET_CLKS(742500, 8, 495, 2),
1294 _PLL_SET_CLKS(768000, 1, 64, 2),
1295 _PLL_SET_CLKS(798000, 2, 133, 2),
1296 _PLL_SET_CLKS(1188000, 2, 99, 1),
1297 _PLL_SET_CLKS( 0, 4, 133, 1),
1299 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1300 static struct clk codec_pll_clk = {
1301 .name = "codec_pll",
1303 .mode = pll_clk_mode,
1304 .recalc = plls_clk_recalc,
1305 .set_rate = cpll_clk_set_rate,
1309 static const struct pll_clk_set gpll_clks[] = {
1310 _PLL_SET_CLKS(148500, 2, 99, 8),
1311 _PLL_SET_CLKS(297000, 2, 198, 8),
1312 _PLL_SET_CLKS(300000, 1, 50, 4),
1313 _PLL_SET_CLKS(384000, 1, 64, 4),
1314 _PLL_SET_CLKS(594000, 2, 198, 4),
1315 _PLL_SET_CLKS(891000, 8, 594, 2),
1316 _PLL_SET_CLKS(1188000, 2, 99, 1),
1317 _PLL_SET_CLKS(1200000, 1, 50, 1),
1318 _PLL_SET_CLKS(0, 0, 0, 0),
1320 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1321 static struct clk general_pll_clk = {
1322 .name = "general_pll",
1324 .recalc = plls_clk_recalc,
1325 .set_rate = gpll_clk_set_rate,
1328 /********************************clocks***********************************/
1329 //GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1330 static struct clk clk_ddr_gpll_path = {
1331 .name = "ddr_gpll_path",
1332 .parent = &general_pll_clk,
1333 .recalc = clksel_recalc_parent_rate,
1334 .gate_idx = CLK_GATE_DDR_GPLL,
1338 /* core and cpu setting */
1339 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1341 CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1345 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1347 CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1348 return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1350 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1352 u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1353 unsigned long rate = 0;
1354 clk->parent = clk->get_parent(clk);
1355 rate = clk->parent->recalc(clk->parent) >> shift;
1356 CLKDATA_DBG("%s new clock rate is %lu (shift %u), parent=%s, rate=%lu\n",
1357 clk->name, rate, shift, clk->parent->name, clk->parent->rate);
1360 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1361 static struct clk clk_ddr = {
1363 .parent = &ddr_pll_clk,
1364 .get_parent = clksel_get_parent,
1365 .set_parent = clksel_set_parent,
1366 .recalc = ddr_clk_recalc_rate,
1367 .set_rate = ddr_clk_set_rate,
1368 .round_rate = ddr_clk_round_rate,
1369 .gate_idx = CLK_GATE_DDRPHY,
1370 .clksel_con = CRU_CLKSELS_CON(26),
1371 CRU_DIV_SET(0x3, 0, 4),
1373 CRU_PARENTS_SET(clk_ddr_parents),
1375 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1379 ret = clk_set_rate_nolock(c->parent, rate);
1381 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1385 set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1388 static unsigned long clk_core_get_rate(struct clk *c)
1390 u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1391 //c->parent->rate=c->parent->recalc(c->parent);
1392 return c->parent->rate / div;
1394 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1396 u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1397 return clk_round_rate_nolock(clk->parent, rate) / div;
1400 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1404 struct clk *old_prt;
1406 if(clk->parent == new_prt)
1408 if (unlikely(!clk->parents))
1410 CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1412 old_prt = clk->parent;
1414 if(clk->parents[0] == new_prt) {
1415 new_prt->set_rate(new_prt, 300 * MHZ);
1416 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1417 } else if(clk->parents[1] == new_prt) {
1419 if(new_prt->rate > old_prt->rate) {
1420 temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1421 set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1423 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1424 new_prt->set_rate(new_prt, 300 * MHZ);
1433 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1436 u32 old_aclk_div = 0, new_aclk_div;
1437 struct arm_clks_div_set *temp_clk_div;
1438 unsigned long arm_gpll_rate, arm_gpll_lpj;
1439 temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1440 arm_gpll_rate = c->parent->rate / temp_div;
1442 temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1444 temp_clk_div = &arm_clk_div_tlb[4];
1446 old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1447 new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1448 if(c->rate >= rate) {
1449 arm_gpll_lpj = lpj_gpll / temp_div;
1450 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1453 cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1454 cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1455 CRU_CLKSELS_CON(0));
1456 if((c->rate < rate)) {
1457 arm_gpll_lpj = lpj_gpll / temp_div;
1458 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1462 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1464 return c->parent->rate;
1466 static struct clk clk_core_gpll_path = {
1467 .name = "cpu_gpll_path",
1468 .parent = &general_pll_clk,
1469 .recalc = arm_core_gpll_clk_get_rate,
1470 .set_rate = core_gpll_clk_set_rate,
1471 CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1475 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1477 static struct clk clk_core = {
1479 .parent = &arm_pll_clk,
1480 .set_rate = clk_core_set_rate,
1481 .recalc = clk_core_get_rate,
1482 .round_rate = core_clk_round_rate,
1483 .set_parent = core_clksel_set_parent,
1484 .clksel_con = CRU_CLKSELS_CON(0),
1485 CRU_DIV_SET(0x1f, 9, 32),
1487 CRU_PARENTS_SET(clk_core_parents),
1489 GATE_CLK(l2c, clk_core, CLK_L2C);
1490 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1491 static unsigned long aclk_recalc(struct clk *clk)
1494 u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1499 rate = clk->parent->rate / div;
1500 pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1504 static struct clk core_periph = {
1505 .name = "core_periph",
1506 .parent = &clk_core,
1507 .gate_idx = CLK_GATE_CORE_PERIPH,
1508 .recalc = clksel_recalc_shift_2,
1509 .clksel_con = CRU_CLKSELS_CON(0),
1510 CRU_DIV_SET(0x3, 6, 16),
1512 static struct clk aclk_core = {
1513 .name = "aclk_core",
1514 .parent = &clk_core,
1515 .gate_idx = CLK_GATE_ACLK_CORE,
1516 .recalc = aclk_recalc,
1517 .clksel_con = CRU_CLKSELS_CON(1),
1518 CRU_DIV_SET(0x7, 3, 8),
1521 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1522 static struct clk clk_cpu_div = {
1524 .parent = &arm_pll_clk,
1525 .set_rate = clksel_set_rate_freediv,
1526 .recalc = clksel_recalc_div,
1527 .clksel_con = CRU_CLKSELS_CON(0),
1528 CRU_DIV_SET(0x1f, 0, 32),
1530 CRU_PARENTS_SET(clk_cpu_div_parents),
1533 static struct clk aclk_cpu = {
1535 .parent = &clk_cpu_div,
1536 .gate_idx = CLK_GATE_ACLK_CPU,
1539 static struct clk hclk_cpu = {
1541 .parent = &aclk_cpu,
1542 .gate_idx = CLK_GATE_HCLK_CPU,
1543 .recalc = clksel_recalc_shift,
1544 .set_rate = clksel_set_rate_shift,
1545 .clksel_con = CRU_CLKSELS_CON(1),
1546 CRU_DIV_SET(0x3, 8, 4),
1550 static struct clk pclk_cpu = {
1552 .parent = &aclk_cpu,
1553 .gate_idx = CLK_GATE_PCLK_CPU,
1554 .recalc = clksel_recalc_shift,
1555 .set_rate = clksel_set_rate_shift,
1556 .clksel_con = CRU_CLKSELS_CON(1),
1557 CRU_DIV_SET(0x3, 12, 8),
1560 static struct clk ahb2apb_cpu = {
1562 .parent = &hclk_cpu,
1563 .recalc = clksel_recalc_shift,
1564 .set_rate = clksel_set_rate_shift,
1565 .clksel_con = CRU_CLKSELS_CON(1),
1566 CRU_DIV_SET(0x3, 14, 4),
1570 static struct clk atclk_cpu = {
1571 .name = "atclk_cpu",
1572 .parent = &pclk_cpu,
1573 .gate_idx = CLK_GATE_ATCLK_CPU,
1577 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1579 unsigned long max_rate = rate / 100 * 105; /* +5% */
1580 return clkset_rate_freediv_autosel_parents(clk, max_rate);
1583 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1585 static struct clk aclk_gpu = {
1588 .recalc = clksel_recalc_div,
1589 .round_rate = clk_freediv_round_autosel_parents_rate,
1590 .set_rate = clkset_rate_freediv_autosel_parents,
1591 .clksel_con = CRU_CLKSELS_CON(34),
1592 .gate_idx = CLK_GATE_ACLK_GPU,
1593 CRU_DIV_SET(0x1f, 0, 32),
1594 CRU_SRC_SET(0x1, 7),
1595 CRU_PARENTS_SET(aclk_gpu_parents),
1598 /* vcodec setting */
1599 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1601 unsigned long rate = clk->parent->rate / 4;
1602 pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1606 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1608 static struct clk aclk_vepu = {
1609 .name = "aclk_vepu",
1610 .parent = &codec_pll_clk,
1612 .recalc = clksel_recalc_div,
1613 .set_rate = clkset_rate_freediv_autosel_parents,
1614 .clksel_con = CRU_CLKSELS_CON(32),
1615 .gate_idx = CLK_GATE_ACLK_VEPU,
1616 CRU_DIV_SET(0x1f, 0, 32),
1617 CRU_SRC_SET(0x1, 7),
1618 CRU_PARENTS_SET(aclk_vepu_parents),
1621 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1623 static struct clk aclk_vdpu = {
1624 .name = "aclk_vdpu",
1626 .recalc = clksel_recalc_div,
1627 .set_rate = clkset_rate_freediv_autosel_parents,
1628 .clksel_con = CRU_CLKSELS_CON(32),
1629 .gate_idx = CLK_GATE_ACLK_VDPU,
1630 CRU_DIV_SET(0x1f, 8, 32),
1631 CRU_SRC_SET(0x1, 15),
1632 CRU_PARENTS_SET(aclk_vdpu_parents),
1634 static struct clk hclk_vepu = {
1635 .name = "hclk_vepu",
1636 .parent = &aclk_vepu,
1638 .recalc = clksel_recalc_vpu_hclk,
1639 .gate_idx = CLK_GATE_HCLK_VEPU,
1642 static struct clk hclk_vdpu = {
1643 .name = "hclk_vdpu",
1644 .parent = &aclk_vdpu,
1646 .recalc = clksel_recalc_vpu_hclk,
1647 .gate_idx = CLK_GATE_HCLK_VDPU,
1650 /* aclk lcdc setting */
1651 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1653 static struct clk aclk_lcdc0_pre = {
1654 .name = "aclk_lcdc0_pre",
1655 .parent = &codec_pll_clk,
1657 .recalc = clksel_recalc_div,
1658 .set_rate = clkset_rate_freediv_autosel_parents,
1659 .gate_idx = CLK_GATE_ACLK_LCDC0_SRC,
1660 .clksel_con = CRU_CLKSELS_CON(31),
1661 CRU_DIV_SET(0x1f, 0, 32),
1662 CRU_SRC_SET(0x1, 7),
1663 CRU_PARENTS_SET(aclk_lcdc0_parents),
1666 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1668 static struct clk aclk_lcdc1_pre = {
1669 .name = "aclk_lcdc1_pre",
1670 .parent = &codec_pll_clk,
1672 .recalc = clksel_recalc_div,
1673 .set_rate = clkset_rate_freediv_autosel_parents,
1674 .gate_idx = CLK_GATE_ACLK_LCDC1_SRC,
1675 .clksel_con = CRU_CLKSELS_CON(31),
1676 CRU_DIV_SET(0x1f, 8, 32),
1677 CRU_SRC_SET(0x1, 15),
1678 CRU_PARENTS_SET(aclk_lcdc1_parents),
1681 /* aclk/hclk/pclk periph setting */
1682 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1684 static struct clk aclk_periph = {
1685 .name = "aclk_periph",
1686 .parent = &general_pll_clk,
1688 .gate_idx = CLK_GATE_ACLK_PERIPH,
1689 .recalc = clksel_recalc_div,
1690 .set_rate = clksel_set_rate_freediv,
1691 .clksel_con = CRU_CLKSELS_CON(10),
1692 CRU_DIV_SET(0x1f, 0, 32),
1694 CRU_PARENTS_SET(aclk_periph_parents),
1696 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1698 static struct clk pclk_periph = {
1699 .name = "pclk_periph",
1700 .parent = &aclk_periph,
1702 .gate_idx = CLK_GATE_PCLK_PERIPH,
1703 .recalc = clksel_recalc_shift,
1704 .set_rate = clksel_set_rate_shift,
1705 .clksel_con = CRU_CLKSELS_CON(10),
1706 CRU_DIV_SET(0x3, 12, 8),
1709 static struct clk hclk_periph = {
1710 .name = "hclk_periph",
1711 .parent = &aclk_periph,
1713 .gate_idx = CLK_GATE_HCLK_PERIPH,
1714 .recalc = clksel_recalc_shift,
1715 .set_rate = clksel_set_rate_shift,
1716 .clksel_con = CRU_CLKSELS_CON(10),
1717 CRU_DIV_SET(0x3, 8, 4),
1719 /* dclk lcdc setting */
1721 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1725 unsigned long new_rate;
1728 if(clk->rate == rate)
1730 for(i = 0; i < 2; i++) {
1731 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1732 new_rate = clk->parents[i]->rate / div;
1733 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1738 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1742 //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1744 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1745 clk->div_shift, clk->div_mask) + 1;
1747 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1749 if(clk->parents[i] != clk->parent) {
1750 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1754 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1755 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1758 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1762 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1764 if (rate == 27 * MHZ)
1765 return clkset_rate_freediv_autosel_parents(clk, rate);
1767 return clkset_rate_evendiv_autosel_parents(clk, rate);
1772 if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1773 parent = clk->parents[1];
1774 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1776 parent = clk->parents[0];
1778 //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1779 //clk->name,rate,parent->name,clk->parent->name);
1781 if(parent != clk->parents[1]) {
1782 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1784 CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1788 if (clk->parent != parent) {
1789 ret = clk_set_parent_nolock(clk, parent);
1791 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1799 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1800 static struct clk dclk_lcdc0 = {
1801 .name = "dclk_lcdc0",
1803 .set_rate = dclk_lcdc_set_rate,
1804 .recalc = clksel_recalc_div,
1805 .gate_idx = CLK_GATE_DCLK_LCDC0_SRC,
1806 .clksel_con = CRU_CLKSELS_CON(27),
1807 CRU_SRC_SET(0x1, 0),
1808 CRU_DIV_SET(0xff, 8, 256),
1809 CRU_PARENTS_SET(dclk_lcdc0_parents),
1812 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1813 static struct clk dclk_lcdc1 = {
1814 .name = "dclk_lcdc1",
1816 .set_rate = dclk_lcdc_set_rate,
1817 .recalc = clksel_recalc_div,
1818 .gate_idx = CLK_GATE_DCLK_LCDC1_SRC,
1819 .clksel_con = CRU_CLKSELS_CON(28),
1820 CRU_SRC_SET(0x1, 0),
1821 CRU_DIV_SET(0xff, 8, 256),
1822 CRU_PARENTS_SET(dclk_lcdc1_parents),
1827 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1828 static struct clk cif_out_pll = {
1829 .name = "cif_out_pll",
1830 .parent = &general_pll_clk,
1831 .clksel_con = CRU_CLKSELS_CON(29),
1832 CRU_SRC_SET(0x1, 0),
1833 CRU_PARENTS_SET(cifout_sel_pll_parents),
1836 static struct clk cif0_out_div = {
1837 .name = "cif0_out_div",
1838 .parent = &cif_out_pll,
1840 .recalc = clksel_recalc_div,
1841 .set_rate = clksel_set_rate_freediv,
1842 .gate_idx = CLK_GATE_CIF0_OUT,
1843 .clksel_con = CRU_CLKSELS_CON(29),
1844 CRU_DIV_SET(0x1f, 1, 32),
1847 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1852 if (rate == 24 * MHZ) {
1853 parent = clk->parents[1];
1855 parent = clk->parents[0];
1856 ret = clk_set_rate_nolock(parent, rate);
1860 if (clk->parent != parent)
1861 ret = clk_set_parent_nolock(clk, parent);
1866 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1867 static struct clk cif0_out = {
1869 .parent = &cif0_out_div,
1870 .set_rate = cif_out_set_rate,
1871 .clksel_con = CRU_CLKSELS_CON(29),
1872 CRU_SRC_SET(0x1, 7),
1873 CRU_PARENTS_SET(cif0_out_parents),
1876 static struct clk pclkin_cif0 = {
1877 .name = "pclkin_cif0",
1879 .gate_idx = CLK_GATE_PCLKIN_CIF0,
1882 static struct clk inv_cif0 = {
1884 .parent = &pclkin_cif0,
1887 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1888 static struct clk cif0_in = {
1890 .parent = &pclkin_cif0,
1891 .clksel_con = CRU_CLKSELS_CON(30),
1892 CRU_SRC_SET(0x1, 8),
1893 CRU_PARENTS_SET(cif0_in_parents),
1896 /* i2s/spdif setting */
1897 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1898 static struct clk clk_i2s_pll = {
1900 .parent = &general_pll_clk,
1901 .clksel_con = CRU_CLKSELS_CON(2),
1902 CRU_SRC_SET(0x1, 15),
1903 CRU_PARENTS_SET(clk_i2s_div_parents),
1906 static struct clk clk_i2s0_div = {
1908 .parent = &clk_i2s_pll,
1910 .recalc = clksel_recalc_div,
1911 .set_rate = clksel_set_rate_freediv,
1912 .round_rate = clksel_freediv_round_rate,
1913 .gate_idx = CLK_GATE_I2S0_SRC,
1914 .clksel_con = CRU_CLKSELS_CON(3),
1915 CRU_DIV_SET(0x7f, 0, 64),
1918 static struct clk clk_spdif_div = {
1919 .name = "spdif_div",
1920 .parent = &clk_i2s_pll,
1921 .recalc = clksel_recalc_div,
1922 .set_rate = clksel_set_rate_freediv,
1923 .round_rate = clksel_freediv_round_rate,
1925 .gate_idx = CLK_GATE_SPDIF_SRC,
1926 .clksel_con = CRU_CLKSELS_CON(5),
1927 CRU_DIV_SET(0x7f, 0, 64),
1929 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1931 u32 numerator, denominator;
1932 //clk_i2s_div->clk_i2s_pll->gpll/cpll
1933 //clk->parent->parent
1934 if(frac_div_get_seting(rate, clk->parent->parent->rate,
1935 &numerator, &denominator) == 0) {
1936 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1937 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1938 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1940 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1946 static struct clk clk_i2s0_frac_div = {
1947 .name = "i2s0_frac_div",
1948 .parent = &clk_i2s0_div,
1950 .gate_idx = CLK_GATE_I2S0_FRAC,
1951 .recalc = clksel_recalc_frac,
1952 .set_rate = clk_i2s_fracdiv_set_rate,
1953 .clksel_con = CRU_CLKSELS_CON(7),
1956 static struct clk clk_spdif_frac_div = {
1957 .name = "spdif_frac_div",
1958 .parent = &clk_spdif_div,
1960 .gate_idx = CLK_GATE_SPDIF_FRAC,
1961 .recalc = clksel_recalc_frac,
1962 .set_rate = clk_i2s_fracdiv_set_rate,
1963 .clksel_con = CRU_CLKSELS_CON(9),
1966 #define I2S_SRC_DIV (0x0)
1967 #define I2S_SRC_FRAC (0x1)
1968 #define I2S_SRC_12M (0x2)
1970 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1975 if (rate == clk->parents[I2S_SRC_12M]->rate) {
1976 parent = clk->parents[I2S_SRC_12M];
1977 } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1978 parent = clk->parents[I2S_SRC_DIV];
1980 parent = clk->parents[I2S_SRC_FRAC];
1983 CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1984 clk->name, rate, parent->name, clk->parent->name);
1986 if(parent != clk->parents[I2S_SRC_12M]) {
1987 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1989 CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1994 if (clk->parent != parent) {
1995 ret = clk_set_parent_nolock(clk, parent);
1997 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2005 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
2007 static struct clk clk_i2s0 = {
2009 .set_rate = i2s_set_rate,
2010 .clksel_con = CRU_CLKSELS_CON(3),
2011 CRU_SRC_SET(0x3, 8),
2012 CRU_PARENTS_SET(clk_i2s0_parents),
2015 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
2017 static struct clk clk_spdif = {
2019 .parent = &clk_spdif_frac_div,
2020 .set_rate = i2s_set_rate,
2021 .clksel_con = CRU_CLKSELS_CON(5),
2022 CRU_SRC_SET(0x3, 8),
2023 CRU_PARENTS_SET(clk_spdif_parents),
2026 /* otgphy setting */
2027 GATE_CLK(otgphy0, xin24m, OTGPHY0);
2028 GATE_CLK(otgphy1, xin24m, OTGPHY1);
2030 static struct clk clk_otgphy0_480m = {
2031 .name = "otgphy0_480m",
2032 .parent = &clk_otgphy0,
2034 static struct clk clk_otgphy1_480m = {
2035 .name = "otgphy1_480m",
2036 .parent = &clk_otgphy1,
2039 /* hsicphy setting */
2041 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
2042 static struct clk clk_hsicphy_480m = {
2043 .name = "hsicphy_480m",
2044 .parent = &clk_otgphy0_480m,
2045 .clksel_con = CRU_CLKSELS_CON(30),
2046 CRU_SRC_SET(0x3, 0),
2047 CRU_PARENTS_SET(clk_hsicphy_parents),
2049 static struct clk clk_hsicphy_12m = {
2050 .name = "hsicphy_12m",
2051 .parent = &clk_hsicphy_480m,
2052 .clksel_con = CRU_CLKSELS_CON(11),
2053 CRU_DIV_SET(0x3f, 8, 64),
2057 /* mac and rmii setting */
2059 static struct clk rmii_clkin = {
2060 .name = "rmii_clkin",
2062 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
2063 static struct clk clk_mac_pll_div = {
2064 .name = "mac_pll_div",
2065 .parent = &general_pll_clk,
2067 .gate_idx = CLK_GATE_MAC_SRC,
2068 .recalc = clksel_recalc_div,
2069 .set_rate = clksel_set_rate_freediv,
2070 .clksel_con = CRU_CLKSELS_CON(21),
2071 CRU_DIV_SET(0x1f, 8, 32),
2072 CRU_SRC_SET(0x1, 0),
2073 CRU_PARENTS_SET(clk_mac_ref_div_parents),
2076 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
2078 if(clk->parent == clk->parents[1]) {
2079 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
2081 } else if(clk->parent == clk->parents[0]) {
2082 return clk_set_rate_nolock(clk->parents[0], rate);
2087 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
2089 static struct clk clk_mac_ref = {
2091 .parent = &clk_mac_pll_div,
2092 .set_rate = clksel_mac_ref_set_rate,
2093 .clksel_con = CRU_CLKSELS_CON(21),
2094 CRU_SRC_SET(0x1, 4),
2095 CRU_PARENTS_SET(clk_mac_ref_parents),
2098 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
2100 return clk_set_parent_nolock(clk->parent, parent);
2103 static struct clk clk_mii_tx = {
2105 .parent = &clk_mac_ref,
2106 //.set_parent = clk_set_mii_tx_parent,
2108 .gate_idx = CLK_GATE_MAC_LBTEST,
2111 /* hsadc and saradc */
2112 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
2113 static struct clk clk_hsadc_pll_div = {
2114 .name = "hsadc_pll_div",
2115 .parent = &general_pll_clk,
2117 .gate_idx = CLK_GATE_HSADC_SRC,
2118 .recalc = clksel_recalc_div,
2119 .round_rate = clk_freediv_round_autosel_parents_rate,
2120 .set_rate = clkset_rate_freediv_autosel_parents,
2121 //.round_rate = clksel_freediv_round_rate,
2122 //.set_rate = clksel_set_rate_freediv,
2123 .clksel_con = CRU_CLKSELS_CON(22),
2124 CRU_DIV_SET(0xff, 8, 256),
2125 CRU_SRC_SET(0x1, 0),
2126 CRU_PARENTS_SET(clk_hsadc_pll_parents),
2128 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2130 u32 numerator, denominator;
2131 // clk_hsadc_pll_div->gpll/cpll
2132 //clk->parent->parent
2133 if(frac_div_get_seting(rate, clk->parent->parent->rate,
2134 &numerator, &denominator) == 0) {
2135 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2137 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2139 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2141 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2146 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2148 u32 numerator, denominator;
2150 // clk_hsadc_pll_div->gpll/cpll
2151 //clk->parent->parent
2152 for(i = 0; i < 2; i++) {
2153 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2154 &numerator, &denominator) == 0)
2160 if(clk->parent->parent != clk->parent->parents[i])
2161 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2163 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2165 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2167 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2169 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2175 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2177 u32 numerator, denominator;
2179 CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2180 if(frac_div_get_seting(rate, clk->parent->parent->rate,
2181 &numerator, &denominator) == 0)
2186 static struct clk clk_hsadc_frac_div = {
2187 .name = "hsadc_frac_div",
2188 .parent = &clk_hsadc_pll_div,
2190 .recalc = clksel_recalc_frac,
2191 .set_rate = clk_hsadc_fracdiv_set_rate_auto_parents,
2192 .round_rate = clk_hsadc_fracdiv_round_rate,
2193 .gate_idx = CLK_GATE_HSADC_FRAC_SRC,
2194 .clksel_con = CRU_CLKSELS_CON(23),
2197 #define HSADC_SRC_DIV 0x0
2198 #define HSADC_SRC_FRAC 0x1
2199 #define HSADC_SRC_EXT 0x2
2200 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2205 if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2206 CLKDATA_DBG("hsadc clk is form ext\n");
2208 } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2209 parent = clk->parents[HSADC_SRC_DIV];
2210 } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2211 parent = clk->parents[HSADC_SRC_FRAC];
2213 parent = clk->parents[HSADC_SRC_DIV];
2215 CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2216 clk->name, rate, parent->name, clk->parent->name);
2218 ret = clk_set_rate_nolock(parent, rate);
2220 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2223 if (clk->parent != parent) {
2224 ret = clk_set_parent_nolock(clk, parent);
2226 CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2233 static struct clk clk_hsadc_ext = {
2234 .name = "hsadc_ext",
2237 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2238 static struct clk clk_hsadc_out = {
2239 .name = "hsadc_out",
2240 .parent = &clk_hsadc_pll_div,
2241 .set_rate = clk_hsadc_set_rate,
2242 .clksel_con = CRU_CLKSELS_CON(22),
2243 CRU_SRC_SET(0x3, 4),
2244 CRU_PARENTS_SET(clk_hsadc_out_parents),
2246 static struct clk clk_hsadc_out_inv = {
2247 .name = "hsadc_out_inv",
2248 .parent = &clk_hsadc_out,
2251 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2252 static struct clk clk_hsadc = {
2254 .parent = &clk_hsadc_out,
2255 .clksel_con = CRU_CLKSELS_CON(22),
2256 CRU_SRC_SET(0x1, 7),
2257 CRU_PARENTS_SET(clk_hsadc_parents),
2260 static struct clk clk_saradc = {
2264 .recalc = clksel_recalc_div,
2265 .set_rate = clksel_set_rate_freediv,
2266 .gate_idx = CLK_GATE_SARADC_SRC,
2267 .clksel_con = CRU_CLKSELS_CON(24),
2268 CRU_DIV_SET(0xff, 8, 256),
2272 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2273 static struct clk clkn_smc = {
2279 static struct clk clk_spi0 = {
2281 .parent = &pclk_periph,
2283 .recalc = clksel_recalc_div,
2284 .set_rate = clksel_set_rate_freediv,
2285 .gate_idx = CLK_GATE_SPI0_SRC,
2286 .clksel_con = CRU_CLKSELS_CON(25),
2287 CRU_DIV_SET(0x7f, 0, 128),
2290 static struct clk clk_spi1 = {
2292 .parent = &pclk_periph,
2294 .recalc = clksel_recalc_div,
2295 .set_rate = clksel_set_rate_freediv,
2296 .gate_idx = CLK_GATE_SPI1_SRC,
2297 .clksel_con = CRU_CLKSELS_CON(25),
2298 CRU_DIV_SET(0x7f, 8, 128),
2301 /* sdmmc/sdio/emmc setting */
2302 static struct clk clk_sdmmc = {
2304 .parent = &hclk_periph,
2306 .recalc = clksel_recalc_div,
2307 .set_rate = clksel_set_rate_even,
2308 .gate_idx = CLK_GATE_MMC0_SRC,
2309 .clksel_con = CRU_CLKSELS_CON(11),
2310 CRU_DIV_SET(0x3f, 0, 64),
2313 static struct clk clk_sdio = {
2315 .parent = &hclk_periph,
2317 .recalc = clksel_recalc_div,
2318 .set_rate = clksel_set_rate_even,
2319 .gate_idx = CLK_GATE_SDIO_SRC,
2320 .clksel_con = CRU_CLKSELS_CON(12),
2321 CRU_DIV_SET(0x3f, 0, 64),
2325 static struct clk clk_emmc = {
2327 .parent = &hclk_periph,
2329 .recalc = clksel_recalc_div,
2330 .set_rate = clksel_set_rate_freediv,
2331 .gate_idx = CLK_GATE_EMMC_SRC,
2332 .clksel_con = CRU_CLKSELS_CON(12),
2333 CRU_DIV_SET(0x3f, 8, 64),
2337 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2338 static struct clk clk_uart_pll = {
2340 .parent = &general_pll_clk,
2341 .clksel_con = CRU_CLKSELS_CON(12),
2342 CRU_SRC_SET(0x1, 15),
2343 CRU_PARENTS_SET(clk_uart_src_parents),
2345 static struct clk clk_uart0_div = {
2346 .name = "uart0_div",
2347 .parent = &clk_uart_pll,
2349 .gate_idx = CLK_GATE_UART0_SRC,
2350 .recalc = clksel_recalc_div,
2351 .set_rate = clksel_set_rate_freediv,
2352 .round_rate = clksel_freediv_round_rate,
2353 .clksel_con = CRU_CLKSELS_CON(13),
2354 CRU_DIV_SET(0x7f, 0, 64),
2356 static struct clk clk_uart1_div = {
2357 .name = "uart1_div",
2358 .parent = &clk_uart_pll,
2360 .gate_idx = CLK_GATE_UART1_SRC,
2361 .recalc = clksel_recalc_div,
2362 .round_rate = clksel_freediv_round_rate,
2363 .set_rate = clksel_set_rate_freediv,
2364 .clksel_con = CRU_CLKSELS_CON(14),
2365 CRU_DIV_SET(0x7f, 0, 64),
2368 static struct clk clk_uart2_div = {
2369 .name = "uart2_div",
2370 .parent = &clk_uart_pll,
2372 .gate_idx = CLK_GATE_UART2_SRC,
2373 .recalc = clksel_recalc_div,
2374 .round_rate = clksel_freediv_round_rate,
2375 .set_rate = clksel_set_rate_freediv,
2376 .clksel_con = CRU_CLKSELS_CON(15),
2377 CRU_DIV_SET(0x7f, 0, 64),
2380 static struct clk clk_uart3_div = {
2381 .name = "uart3_div",
2382 .parent = &clk_uart_pll,
2384 .gate_idx = CLK_GATE_UART3_SRC,
2385 .recalc = clksel_recalc_div,
2386 .round_rate = clksel_freediv_round_rate,
2387 .set_rate = clksel_set_rate_freediv,
2388 .clksel_con = CRU_CLKSELS_CON(16),
2389 CRU_DIV_SET(0x7f, 0, 64),
2391 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2393 u32 numerator, denominator;
2394 //clk_uart0_div->clk_uart_pll->gpll/cpll
2395 //clk->parent->parent
2396 if(frac_div_get_seting(rate, clk->parent->parent->rate,
2397 &numerator, &denominator) == 0) {
2398 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2400 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2402 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2404 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2410 static struct clk clk_uart0_frac_div = {
2411 .name = "uart0_frac_div",
2412 .parent = &clk_uart0_div,
2414 .recalc = clksel_recalc_frac,
2415 .set_rate = clk_uart_fracdiv_set_rate,
2416 .gate_idx = CLK_GATE_UART0_FRAC_SRC,
2417 .clksel_con = CRU_CLKSELS_CON(17),
2419 static struct clk clk_uart1_frac_div = {
2420 .name = "uart1_frac_div",
2421 .parent = &clk_uart1_div,
2423 .recalc = clksel_recalc_frac,
2424 .set_rate = clk_uart_fracdiv_set_rate,
2425 .gate_idx = CLK_GATE_UART1_FRAC_SRC,
2426 .clksel_con = CRU_CLKSELS_CON(18),
2428 static struct clk clk_uart2_frac_div = {
2429 .name = "uart2_frac_div",
2431 .parent = &clk_uart2_div,
2432 .recalc = clksel_recalc_frac,
2433 .set_rate = clk_uart_fracdiv_set_rate,
2434 .gate_idx = CLK_GATE_UART2_FRAC_SRC,
2435 .clksel_con = CRU_CLKSELS_CON(19),
2437 static struct clk clk_uart3_frac_div = {
2438 .name = "uart3_frac_div",
2439 .parent = &clk_uart3_div,
2441 .recalc = clksel_recalc_frac,
2442 .set_rate = clk_uart_fracdiv_set_rate,
2443 .gate_idx = CLK_GATE_UART3_FRAC_SRC,
2444 .clksel_con = CRU_CLKSELS_CON(20),
2447 #define UART_SRC_DIV 0
2448 #define UART_SRC_FRAC 1
2449 #define UART_SRC_24M 2
2451 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2456 if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2457 parent = clk->parents[UART_SRC_24M];
2458 } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2459 parent = clk->parents[UART_SRC_DIV];
2461 parent = clk->parents[UART_SRC_FRAC];
2464 CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2465 clk->name, rate, parent->name, clk->parent->name);
2467 if(parent != clk->parents[UART_SRC_24M]) {
2468 ret = clk_set_rate_nolock(parent, rate);
2470 CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2475 if (clk->parent != parent) {
2476 ret = clk_set_parent_nolock(clk, parent);
2478 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2486 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2487 static struct clk clk_uart0 = {
2489 .set_rate = clk_uart_set_rate,
2490 .clksel_con = CRU_CLKSELS_CON(13),
2491 CRU_SRC_SET(0x3, 8),
2492 CRU_PARENTS_SET(clk_uart0_parents),
2495 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2496 static struct clk clk_uart1 = {
2498 .set_rate = clk_uart_set_rate,
2499 .clksel_con = CRU_CLKSELS_CON(14),
2500 CRU_SRC_SET(0x3, 8),
2501 CRU_PARENTS_SET(clk_uart1_parents),
2504 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2505 static struct clk clk_uart2 = {
2507 .set_rate = clk_uart_set_rate,
2508 .clksel_con = CRU_CLKSELS_CON(15),
2509 CRU_SRC_SET(0x3, 8),
2510 CRU_PARENTS_SET(clk_uart2_parents),
2512 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2513 static struct clk clk_uart3 = {
2515 .set_rate = clk_uart_set_rate,
2516 .clksel_con = CRU_CLKSELS_CON(16),
2517 CRU_SRC_SET(0x3, 8),
2518 CRU_PARENTS_SET(clk_uart3_parents),
2522 GATE_CLK(timer0, xin24m, TIMER0);
2523 GATE_CLK(timer1, xin24m, TIMER1);
2524 GATE_CLK(timer2, xin24m, TIMER2);
2525 GATE_CLK(timer3, xin24m, TIMER3);
2526 GATE_CLK(timer4, xin24m, TIMER4);
2527 GATE_CLK(timer5, xin24m, TIMER5);
2528 GATE_CLK(timer6, xin24m, TIMER6);
2530 /*********************power domain*******************************/
2532 #ifdef RK30_CLK_OFFBOARD_TEST
2533 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2534 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2536 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2537 #define _pmu_set_power_domain pmu_set_power_domain
2540 static int pd_video_mode(struct clk *clk, int on)
2543 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2544 gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2545 //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2546 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2547 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2548 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2549 pmu_set_power_domain(PD_VIDEO, on);
2550 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2551 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2552 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2556 static struct clk pd_video = {
2559 .mode = pd_video_mode,
2560 .gate_idx = PD_VIDEO,
2562 static int pd_display_mode(struct clk *clk, int on)
2565 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2566 gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2567 gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2568 gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2569 gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2570 //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2571 gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2572 gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2573 gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2574 gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2575 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2576 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2577 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2578 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2579 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2580 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2581 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2582 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2583 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2584 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2585 pmu_set_power_domain(PD_VIO, on);
2586 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2587 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2588 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2589 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2590 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2591 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2592 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2593 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2594 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2595 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2599 static struct clk pd_display = {
2602 .mode = pd_display_mode,
2605 static struct clk pd_lcdc0 = {
2606 .parent = &pd_display,
2609 static struct clk pd_lcdc1 = {
2610 .parent = &pd_display,
2613 static struct clk pd_cif0 = {
2614 .parent = &pd_display,
2617 static struct clk pd_rga = {
2618 .parent = &pd_display,
2621 static struct clk pd_ipp = {
2622 .parent = &pd_display,
2625 static struct clk pd_hdmi = {
2626 .parent = &pd_display,
2631 static int pd_gpu_mode(struct clk *clk, int on)
2634 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2635 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2636 pmu_set_power_domain(PD_GPU, on);
2637 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2641 static struct clk pd_gpu = {
2644 .mode = pd_gpu_mode,
2648 static int pm_off_mode(struct clk *clk, int on)
2650 _pmu_set_power_domain(clk->gate_idx, on); //on 1
2653 static struct clk pd_peri = {
2656 .mode = pm_off_mode,
2657 .gate_idx = PD_PERI,
2661 #define PD_CLK(name) \
2669 /************************rk30 fixed div clock****************************************/
2671 /*************************aclk_cpu***********************/
2673 GATE_CLK(dma1, aclk_cpu, ACLK_DMAC1);
2674 GATE_CLK(intmem, aclk_cpu, ACLK_INTMEM);
2675 GATE_CLK(aclk_strc_sys, aclk_cpu, ACLK_STRC_SYS);
2677 /*************************hclk_cpu***********************/
2679 GATE_CLK(rom, hclk_cpu, HCLK_ROM);
2680 GATE_CLK(hclk_i2s0_2ch, hclk_cpu, HCLK_I2S0_2CH);
2681 GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
2682 GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
2683 GATE_CLK(hclk_ahb2apb, hclk_cpu, HCLK_AHB2APB);
2684 GATE_CLK(hclk_vio_bus, hclk_cpu, HCLK_VIO_BUS);
2685 GATE_CLK(hclk_lcdc0, hclk_cpu, HCLK_LCDC0);
2686 GATE_CLK(hclk_lcdc1, hclk_cpu, HCLK_LCDC1);
2687 GATE_CLK(hclk_cif0, hclk_cpu, HCLK_CIF0);
2688 GATE_CLK(hclk_ipp, hclk_cpu, HCLK_IPP);
2689 GATE_CLK(hclk_rga, hclk_cpu, HCLK_RGA);
2690 GATE_CLK(hclk_imem0, hclk_cpu, HCLK_IMEM0);
2691 GATE_CLK(hclk_imem1, hclk_cpu, HCLK_IMEM1);
2693 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2694 GATE_CLK(pclk_uart0, ahb2apb_cpu, PCLK_UART0);
2695 GATE_CLK(pclk_uart1, ahb2apb_cpu, PCLK_UART1);
2696 /*************************pclk_cpu***********************/
2697 GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2698 GATE_CLK(pclk_timer0, pclk_cpu, PCLK_TIMER0);
2699 GATE_CLK(pclk_timer2, pclk_cpu, PCLK_TIMER2);
2700 GATE_CLK(i2c0, pclk_cpu, PCLK_I2C0);
2701 GATE_CLK(i2c1, pclk_cpu, PCLK_I2C1);
2702 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2703 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2704 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2705 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2706 GATE_CLK(tzpc, pclk_cpu, PCLK_TZPC);
2707 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2708 GATE_CLK(pclk_ddrpubl, pclk_cpu, PCLK_PUBL);
2709 GATE_CLK(dbg, pclk_cpu, PCLK_DBG);
2710 GATE_CLK(grf, pclk_cpu, PCLK_GRF);
2711 GATE_CLK(pmu, pclk_cpu, PCLK_PMU);
2713 /*************************aclk_periph***********************/
2715 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2716 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2717 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2718 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2719 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2720 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2722 /*************************hclk_periph***********************/
2723 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2724 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2725 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2726 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2727 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2728 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2729 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2730 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2731 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2732 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2733 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2734 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2735 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2736 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2737 /*************************pclk_periph***********************/
2738 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2739 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2740 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2741 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2742 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2743 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2744 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2745 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2746 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2747 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2748 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2749 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2750 /*************************aclk_lcdc0***********************/
2752 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2753 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2754 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2755 GATE_CLK(aclk_ipp, clk_aclk_vio0, ACLK_IPP);
2757 /*************************aclk_lcdc0***********************/
2759 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2760 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2761 GATE_CLK(aclk_rga, clk_aclk_vio1, ACLK_RGA);
2765 #define CLK(dev, con, ck) \
2773 #define CLK1(name) \
2777 .clk = &clk_##name,\
2782 static struct clk_lookup clks[] = {
2783 CLK(NULL, "xin24m", &xin24m),
2784 //CLK(NULL, "xin27m", &xin27m),
2785 CLK(NULL, "xin12m", &clk_12m),
2786 CLK(NULL, "arm_pll", &arm_pll_clk),
2787 CLK(NULL, "ddr_pll", &ddr_pll_clk),
2788 CLK(NULL, "codec_pll", &codec_pll_clk),
2789 CLK(NULL, "general_pll", &general_pll_clk),
2791 CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2792 CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2794 CLK(NULL, "ddr", &clk_ddr),
2795 CLK(NULL, "cpu", &clk_core),
2798 CLK("smp_twd", NULL, &core_periph),
2799 CLK(NULL, "aclk_core", &aclk_core),
2801 CLK(NULL, "logic", &clk_cpu_div),
2802 CLK(NULL, "aclk_cpu", &aclk_cpu),
2803 CLK(NULL, "pclk_cpu", &pclk_cpu),
2804 CLK(NULL, "atclk_cpu", &atclk_cpu),
2805 CLK(NULL, "hclk_cpu", &hclk_cpu),
2806 CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2808 CLK(NULL, "gpu", &aclk_gpu),
2810 CLK(NULL, "aclk_vepu", &aclk_vepu),
2811 CLK(NULL, "hclk_vepu", &hclk_vepu),
2812 CLK(NULL, "aclk_vdpu", &aclk_vdpu),
2813 CLK(NULL, "hclk_vdpu", &hclk_vdpu),
2815 CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2816 CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2818 CLK(NULL, "aclk_periph", &aclk_periph),
2819 CLK(NULL, "pclk_periph", &pclk_periph),
2820 CLK(NULL, "hclk_periph", &hclk_periph),
2822 CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2823 CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2825 CLK(NULL, "cif_out_pll", &cif_out_pll),
2826 CLK(NULL, "cif0_out_div", &cif0_out_div),
2827 CLK(NULL, "cif0_out", &cif0_out),
2829 CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2830 CLK(NULL, "inv_cif0", &inv_cif0),
2831 CLK(NULL, "cif0_in", &cif0_in),
2834 CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2835 CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2836 CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2839 CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2840 CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2841 CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2845 CLK1(spdif_frac_div),
2855 CLK(NULL, "rmii_clkin", &rmii_clkin),
2856 CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2860 CLK1(hsadc_pll_div),
2861 CLK1(hsadc_frac_div),
2864 CLK1(hsadc_out_inv),
2870 CLK(NULL, "smc_inv", &clkn_smc),
2872 CLK("rk29xx_spim.0", "spi", &clk_spi0),
2873 CLK("rk29xx_spim.1", "spi", &clk_spi1),
2875 CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2876 CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2880 CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2881 CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2882 CLK("rk_serial.0", "uart", &clk_uart0),
2883 CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2884 CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2885 CLK("rk_serial.1", "uart", &clk_uart1),
2886 CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2887 CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2888 CLK("rk_serial.2", "uart", &clk_uart2),
2889 CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2890 CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2891 CLK("rk_serial.3", "uart", &clk_uart3),
2901 /*************************aclk_cpu***********************/
2904 CLK1(aclk_strc_sys),
2906 /*************************hclk_cpu***********************/
2908 CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2910 CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2923 /*************************pclk_cpu***********************/
2927 CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2928 CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2934 CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2935 CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2936 CLK1(pclk_ddrupctl),
2942 /*************************aclk_periph***********************/
2946 CLK1(aclk_peri_niu),
2947 CLK1(aclk_cpu_peri),
2948 CLK1(aclk_peri_axi_matrix),
2950 /*************************hclk_periph***********************/
2951 CLK1(hclk_peri_axi_matrix),
2952 CLK1(hclk_peri_ahb_arbi),
2953 CLK1(hclk_emem_peri),
2956 CLK1(hclk_usb_peri),
2961 CLK1(hclk_pidfilter),
2962 CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2963 CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2966 /*************************pclk_periph***********************/
2967 CLK1(pclk_peri_axi_matrix),
2970 CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2971 CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2972 CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2973 CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2974 CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2975 CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2976 CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2980 /*************************aclk_lcdc0***********************/
2982 CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2986 /*************************aclk_lcdc1***********************/
2988 CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2990 /************************power domain**********************/
3004 static void __init rk30_init_enable_clocks(void)
3007 //clk_enable_nolock(&xin24m);
3008 //clk_enable_nolock(&clk_12m);
3009 //clk_enable_nolock(&arm_pll_clk);
3010 //clk_enable_nolock(&ddr_pll_clk);
3011 //clk_enable_nolock(&codec_pll_clk);
3012 //clk_enable_nolock(&general_pll_clk);
3014 clk_enable_nolock(&clk_ddr);
3015 //clk_enable_nolock(&clk_core);
3016 clk_enable_nolock(&clk_cpu_div);
3017 clk_enable_nolock(&clk_core_gpll_path);
3018 clk_enable_nolock(&clk_l2c);
3019 clk_enable_nolock(&clk_core_dbg);
3020 clk_enable_nolock(&core_periph);
3021 clk_enable_nolock(&aclk_core);
3022 //clk_enable_nolock(&aclk_cpu);
3023 //clk_enable_nolock(&pclk_cpu);
3024 clk_enable_nolock(&atclk_cpu);
3025 //clk_enable_nolock(&hclk_cpu);
3026 clk_enable_nolock(&ahb2apb_cpu);
3028 clk_enable_nolock(&clk_gpu);
3029 clk_enable_nolock(&aclk_gpu);
3030 clk_enable_nolock(&aclk_gpu_slv);
3031 clk_enable_nolock(&aclk_gpu_mst);
3033 clk_enable_nolock(&aclk_vepu);
3034 clk_enable_nolock(&hclk_vepu);
3035 clk_enable_nolock(&aclk_vdpu);
3036 clk_enable_nolock(&hclk_vdpu);
3038 clk_enable_nolock(&aclk_lcdc0_pre);
3039 clk_enable_nolock(&aclk_lcdc1_pre);
3041 clk_enable_nolock(&aclk_periph);
3042 clk_enable_nolock(&pclk_periph);
3043 clk_enable_nolock(&hclk_periph);
3046 clk_enable_nolock(&dclk_lcdc0);
3047 clk_enable_nolock(&dclk_lcdc1);
3049 clk_enable_nolock(&cif_out_pll);
3050 clk_enable_nolock(&cif0_out_div);
3052 clk_enable_nolock(&cif0_out);
3053 clk_enable_nolock(&pclkin_cif0);
3054 clk_enable_nolock(&inv_cif0);
3055 clk_enable_nolock(&cif0_in);
3057 clk_enable_nolock(&clk_i2s_pll);
3058 clk_enable_nolock(&clk_i2s0_div);
3059 clk_enable_nolock(&clk_i2s0_frac_div);
3060 clk_enable_nolock(&clk_i2s0);
3063 clk_enable_nolock(&clk_i2s0_div);
3064 clk_enable_nolock(&clk_i2s0_frac_div);
3065 clk_enable_nolock(&clk_i2s0);
3067 clk_enable_nolock(&clk_spdif_div);
3068 clk_enable_nolock(&clk_spdif_frac_div);
3069 clk_enable_nolock(&clk_spdif);
3072 clk_enable_nolock(&clk_otgphy0);
3073 clk_enable_nolock(&clk_otgphy1);
3074 clk_enable_nolock(&clk_otgphy0_480m);
3075 clk_enable_nolock(&clk_otgphy1_480m);
3076 clk_enable_nolock(&clk_hsicphy_480m);
3077 clk_enable_nolock(&clk_hsicphy_12m);
3081 clk_enable_nolock(&rmii_clkin);
3082 clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
3083 clk_enable_nolock(&clk_mac_ref);
3084 clk_enable_nolock(&clk_mii_tx);
3088 clk_enable_nolock(&clk_hsadc_pll_div);
3089 clk_enable_nolock(&clk_hsadc_frac_div);
3090 clk_enable_nolock(&clk_hsadc_ext);
3091 clk_enable_nolock(&clk_hsadc_out);
3092 clk_enable_nolock(&clk_hsadc_out_inv);
3093 clk_enable_nolock(&clk_hsadc);
3095 clk_enable_nolock(&clk_saradc);
3098 clk_enable_nolock(&clk_smc);
3099 clk_enable_nolock(&clkn_smc);
3102 clk_enable_nolock(&clk_spi0);
3103 clk_enable_nolock(&clk_spi1);
3106 clk_enable_nolock(&clk_sdmmc);
3107 clk_enable_nolock(&clk_sdio);
3108 clk_enable_nolock(&clk_emmc);
3111 clk_enable_nolock(&clk_uart_pll);
3112 clk_enable_nolock(&clk_uart0_div);
3113 clk_enable_nolock(&clk_uart0_frac_div);
3114 clk_enable_nolock(&clk_uart0);
3115 clk_enable_nolock(&clk_uart1_div);
3116 clk_enable_nolock(&clk_uart1_frac_div);
3117 clk_enable_nolock(&clk_uart1);
3118 clk_enable_nolock(&clk_uart2_div);
3119 clk_enable_nolock(&clk_uart2_frac_div);
3120 clk_enable_nolock(&clk_uart2);
3121 clk_enable_nolock(&clk_uart3_div);
3122 clk_enable_nolock(&clk_uart3_frac_div);
3123 clk_enable_nolock(&clk_uart3);
3125 #if CONFIG_RK_DEBUG_UART == 0
3126 clk_enable_nolock(&clk_uart0);
3127 clk_enable_nolock(&clk_pclk_uart0);
3128 #elif CONFIG_RK_DEBUG_UART == 1
3129 clk_enable_nolock(&clk_uart1);
3130 clk_enable_nolock(&clk_pclk_uart1);
3132 #elif CONFIG_RK_DEBUG_UART == 2
3133 clk_enable_nolock(&clk_uart2);
3134 clk_enable_nolock(&clk_pclk_uart2);
3136 #elif CONFIG_RK_DEBUG_UART == 3
3137 clk_enable_nolock(&clk_uart3);
3138 clk_enable_nolock(&clk_pclk_uart3);
3142 clk_enable_nolock(&clk_timer0);
3143 clk_enable_nolock(&clk_timer1);
3144 clk_enable_nolock(&clk_timer2);
3147 /*************************aclk_cpu***********************/
3148 clk_enable_nolock(&clk_dma1);
3149 clk_enable_nolock(&clk_intmem);
3150 clk_enable_nolock(&clk_aclk_strc_sys);
3152 /*************************hclk_cpu***********************/
3153 clk_enable_nolock(&clk_rom);
3155 clk_enable_nolock(&clk_hclk_i2s0_2ch);
3157 clk_enable_nolock(&clk_hclk_i2s0_2ch);
3158 clk_enable_nolock(&clk_hclk_spdif);
3160 clk_enable_nolock(&clk_hclk_cpubus);
3161 clk_enable_nolock(&clk_hclk_ahb2apb);
3162 clk_enable_nolock(&clk_hclk_vio_bus);
3164 clk_enable_nolock(&clk_hclk_lcdc0);
3165 clk_enable_nolock(&clk_hclk_lcdc1);
3166 clk_enable_nolock(&clk_hclk_cif0);
3167 clk_enable_nolock(&clk_hclk_ipp);
3168 clk_enable_nolock(&clk_hclk_rga);
3170 clk_enable_nolock(&clk_hclk_imem0);
3171 clk_enable_nolock(&clk_hclk_imem1);
3173 /*************************pclk_cpu***********************/
3175 clk_enable_nolock(&clk_pwm01);
3176 clk_enable_nolock(&clk_pclk_timer0);
3177 clk_enable_nolock(&clk_pclk_timer1);
3178 clk_enable_nolock(&clk_pclk_timer2);
3179 clk_enable_nolock(&clk_i2c0);
3180 clk_enable_nolock(&clk_i2c1);
3181 clk_enable_nolock(&clk_gpio0);
3182 clk_enable_nolock(&clk_gpio1);
3183 clk_enable_nolock(&clk_gpio2);
3184 clk_enable_nolock(&clk_efuse);
3186 clk_enable_nolock(&clk_tzpc);
3187 //clk_enable_nolock(&clk_pclk_uart0);
3188 //clk_enable_nolock(&clk_pclk_uart1);
3189 clk_enable_nolock(&clk_pclk_ddrupctl);
3190 clk_enable_nolock(&clk_pclk_ddrpubl);
3191 clk_enable_nolock(&clk_dbg);
3192 clk_enable_nolock(&clk_grf);
3193 clk_enable_nolock(&clk_pmu);
3195 /*************************aclk_periph***********************/
3196 clk_enable_nolock(&clk_dma2);
3197 clk_enable_nolock(&clk_aclk_smc);
3198 clk_enable_nolock(&clk_aclk_peri_niu);
3199 clk_enable_nolock(&clk_aclk_cpu_peri);
3200 clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3202 /*************************hclk_periph***********************/
3203 clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3204 clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3205 clk_enable_nolock(&clk_hclk_emem_peri);
3206 //clk_enable_nolock(&clk_hclk_mac);
3207 clk_enable_nolock(&clk_nandc);
3208 clk_enable_nolock(&clk_hclk_usb_peri);
3210 clk_enable_nolock(&clk_hclk_otg0);
3211 clk_enable_nolock(&clk_hclk_otg1);
3212 clk_enable_nolock(&clk_hclk_hsic);
3213 clk_enable_nolock(&clk_hclk_gps);
3214 clk_enable_nolock(&clk_hclk_hsadc);
3215 clk_enable_nolock(&clk_hclk_pidfilter);
3216 clk_enable_nolock(&clk_hclk_sdmmc);
3217 clk_enable_nolock(&clk_hclk_sdio);
3218 clk_enable_nolock(&clk_hclk_emmc);
3221 /*************************pclk_periph***********************/
3222 clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3224 clk_enable_nolock(&clk_pwm23);
3225 clk_enable_nolock(&clk_wdt);
3226 clk_enable_nolock(&clk_pclk_spi0);
3227 clk_enable_nolock(&clk_pclk_spi1);
3228 clk_enable_nolock(&clk_pclk_uart2);
3229 clk_enable_nolock(&clk_pclk_uart3);
3232 clk_enable_nolock(&clk_i2c2);
3233 clk_enable_nolock(&clk_i2c3);
3234 clk_enable_nolock(&clk_i2c4);
3235 clk_enable_nolock(&clk_gpio3);
3236 clk_enable_nolock(&clk_pclk_saradc);
3238 /*************************aclk_lcdc0***********************/
3240 //clk_enable_nolock(&clk_aclk_vio0);
3241 //clk_enable_nolock(&clk_aclk_lcdc0);
3242 //clk_enable_nolock(&clk_aclk_cif0);
3243 //clk_enable_nolock(&clk_aclk_ipp);
3245 /*************************aclk_lcdc1***********************/
3247 //clk_enable_nolock(&clk_aclk_vio1);
3248 //clk_enable_nolock(&clk_aclk_lcdc1);
3249 //clk_enable_nolock(&clk_aclk_rga);
3251 /************************power domain**********************/
3254 static void periph_clk_set_init(void)
3256 unsigned long aclk_p, hclk_p, pclk_p;
3257 unsigned long ppll_rate = general_pll_clk.rate;
3261 switch (ppll_rate) {
3263 aclk_p = 148500 * KHZ;
3264 hclk_p = aclk_p >> 1;
3265 pclk_p = aclk_p >> 2;
3268 aclk_p = ppll_rate >> 1;
3269 hclk_p = aclk_p >> 0;
3270 pclk_p = aclk_p >> 1;
3273 aclk_p = ppll_rate >> 1;
3274 hclk_p = aclk_p >> 0;
3275 pclk_p = aclk_p >> 1;
3278 aclk_p = ppll_rate >> 1;
3279 hclk_p = aclk_p >> 1;
3280 pclk_p = aclk_p >> 2;
3283 aclk_p = ppll_rate >> 2;
3284 hclk_p = aclk_p >> 0;
3285 pclk_p = aclk_p >> 1;
3288 aclk_p = ppll_rate / 6;
3289 hclk_p = aclk_p >> 0;
3290 pclk_p = aclk_p >> 1;
3293 aclk_p = ppll_rate >> 3;
3294 hclk_p = aclk_p >> 0;
3295 pclk_p = aclk_p >> 1;
3304 clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3305 clk_set_rate_nolock(&aclk_periph, aclk_p);
3306 clk_set_rate_nolock(&hclk_periph, hclk_p);
3307 clk_set_rate_nolock(&pclk_periph, pclk_p);
3310 static void cpu_axi_init(void)
3312 unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3313 unsigned long gpll_rate = general_pll_clk.rate;
3315 switch (gpll_rate) {
3317 cpu_div_rate = gpll_rate;
3318 aclk_cpu_rate = cpu_div_rate >> 0;
3319 hclk_cpu_rate = aclk_cpu_rate >> 1;
3320 pclk_cpu_rate = aclk_cpu_rate >> 2;
3323 cpu_div_rate = gpll_rate >> 1;
3324 aclk_cpu_rate = cpu_div_rate >> 0;
3325 hclk_cpu_rate = aclk_cpu_rate >> 1;
3326 pclk_cpu_rate = aclk_cpu_rate >> 2;
3329 cpu_div_rate = gpll_rate >> 1;
3330 aclk_cpu_rate = cpu_div_rate >> 0;
3331 hclk_cpu_rate = aclk_cpu_rate >> 1;
3332 pclk_cpu_rate = aclk_cpu_rate >> 2;
3336 cpu_div_rate = gpll_rate / 3;
3337 aclk_cpu_rate = cpu_div_rate >> 0;
3338 hclk_cpu_rate = aclk_cpu_rate >> 1;
3339 pclk_cpu_rate = aclk_cpu_rate >> 2;
3343 cpu_div_rate = gpll_rate >> 2;
3344 aclk_cpu_rate = cpu_div_rate >> 0;
3345 hclk_cpu_rate = aclk_cpu_rate >> 1;
3346 pclk_cpu_rate = aclk_cpu_rate >> 2;
3350 aclk_cpu_rate = 150 * MHZ;
3351 hclk_cpu_rate = 150 * MHZ;
3352 pclk_cpu_rate = 75 * MHZ;
3355 ahb2apb_cpu_rate = pclk_cpu_rate;
3357 clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3358 clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3359 clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3360 clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3361 clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3362 clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3365 void rk30_clock_common_i2s_init(void)
3367 unsigned long i2s_rate;
3369 if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3370 i2s_rate = 49152000;
3371 } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3372 i2s_rate = 24576000;
3373 } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3374 i2s_rate = 22579000;
3375 } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3376 i2s_rate = 12288000;
3378 i2s_rate = 49152000;
3381 if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3382 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3383 } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3384 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3386 if(general_pll_clk.rate > codec_pll_clk.rate)
3387 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3389 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3392 void rk30_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
3396 if(!(gpll_clk->rate%(48*MHZ)))
3401 else if(!(cpll_clk->rate%(48*MHZ)))
3406 else if(!(gpll_clk->rate%(49500*KHZ)))
3411 else if(!(cpll_clk->rate%(49500*KHZ)))
3418 if(cpll_clk->rate>gpll_clk->rate)
3428 clk_set_parent_nolock(&clk_uart_pll, p_clk);
3429 clk_set_rate_nolock(&clk_uart0_div,rate);
3430 clk_set_rate_nolock(&clk_uart1_div,rate);
3431 clk_set_rate_nolock(&clk_uart2_div,rate);
3432 clk_set_rate_nolock(&clk_uart3_div,rate);
3435 static void inline clock_set_div(struct clk *clk,u32 div)
3437 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3440 static void inline clock_set_max_div(struct clk *clk)
3442 set_cru_bits_w_msk(clk->div_max - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3445 static void div_clk_for_pll_init(void)
3447 clock_set_max_div(&clk_cpu_div);
3448 clock_set_max_div(&aclk_vdpu);
3449 clock_set_max_div(&aclk_vepu);
3450 clock_set_max_div(&aclk_gpu);
3451 clock_set_max_div(&aclk_lcdc0_pre);
3452 clock_set_max_div(&aclk_lcdc1_pre);
3453 clock_set_max_div(&aclk_periph);
3454 clock_set_max_div(&dclk_lcdc0);
3455 clock_set_max_div(&dclk_lcdc1);
3456 clock_set_max_div(&cif0_out_div);
3457 clock_set_max_div(&clk_i2s0_div);
3458 clock_set_max_div(&clk_spdif_div);
3459 clock_set_max_div(&clk_uart0_div);
3460 clock_set_max_div(&clk_uart1_div);
3461 clock_set_max_div(&clk_uart2_div);
3462 clock_set_max_div(&clk_uart3_div);
3463 clock_set_max_div(&clk_hsicphy_12m);
3464 clock_set_max_div(&clk_hsadc_pll_div);
3465 clock_set_max_div(&clk_saradc);
3468 static u8 pll_flag = 0;
3470 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3473 clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3475 clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3478 clk_set_rate_nolock(&clk_core, 816 * MHZ);
3480 periph_clk_set_init();
3483 rk30_clock_common_i2s_init();
3486 clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3487 clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3490 rk30_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
3493 if(!(gpll_rate % (50 * MHZ))) {
3494 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3496 } else if((!(ddr_pll_clk.rate % (50 * MHZ))) && (ddr_pll_clk.rate != 24 * MHZ) && ((pll_flag & 0x2) == 0)) {
3497 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3500 CLKDATA_DBG("mac can't get 50mhz, set to gpll\n");
3501 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3506 //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3508 //lcdc0 lcd auto sel pll
3509 clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3510 clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3513 clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3516 clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3517 clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3518 clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3519 clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3522 //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3523 //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3525 clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3526 clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3528 clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
3529 clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3531 clk_set_rate_nolock(&clk_uart0, 49500000);
3532 clk_set_rate_nolock(&clk_sdmmc, 24750000);
3533 clk_set_rate_nolock(&clk_sdio, 24750000);
3536 static struct clk def_ops_clk = {
3537 .get_parent = clksel_get_parent,
3538 .set_parent = clksel_set_parent,
3541 #ifdef CONFIG_PROC_FS
3542 struct clk_dump_ops dump_ops;
3544 void rk_dump_clock_info(void);
3545 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3547 struct clk_lookup *lk;
3549 if (soc_is_rk3188plus()) {
3550 arm_pll_clk.recalc = plus_plls_clk_recalc;
3551 ddr_pll_clk.recalc = plus_plls_clk_recalc;
3552 codec_pll_clk.recalc = plus_plls_clk_recalc;
3553 general_pll_clk.recalc = plus_plls_clk_recalc;
3555 arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
3556 codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
3557 general_pll_clk.set_rate = plus_gpll_clk_set_rate;
3561 pll_flag = rk_pll_flag();
3562 printk("CLKDATA_MSG: pll_flag = 0x%02x\n", pll_flag);
3564 if (0 != pll_flag) {
3565 CLKDATA_DBG("CPLL=%lu, GPLL=%lu;CPLL CAN NOT LOCK, SET CPLL BY PASS, USE GPLL REPLACE CPLL\n",
3571 clk_register_dump_ops(&dump_ops);
3572 clk_register_default_ops_clk(&def_ops_clk);
3573 rk30_clock_flags = flags;
3574 for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3575 #ifdef RK30_CLK_OFFBOARD_TEST
3576 rk30_clkdev_add(lk);
3580 clk_register(lk->clk);
3583 div_clk_for_pll_init();
3584 clk_recalculate_root_clocks_nolock();
3586 loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3589 * Only enable those clocks we will need, let the drivers
3590 * enable other clocks as necessary
3593 rk30_init_enable_clocks();
3595 // print loader config
3596 CLKDATA_DBG("%s clks register dbg start\n", __func__);
3597 rk_dump_clock_info();
3598 rk30_clk_dump_regs();
3600 CLKDATA_DBG("%s clks register dbg end\n", __func__);
3603 * Disable any unused clocks left on by the bootloader
3605 //clk_disable_unused();
3606 rk30_clock_common_init(gpll, cpll);
3607 preset_lpj = loops_per_jiffy;
3610 //regfile_writel(0xc0004000,0x10c);
3611 //cru_writel(0x07000000,CRU_MISC_CON);
3614 extern int rk3188_dvfs_init(void);
3616 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3618 CLKDATA_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
3619 gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3620 _rk30_clock_data_init(gpll, cpll, flags);
3625 * You can override arm_clk rate with armclk= cmdline option.
3627 static int __init armclk_setup(char *str)
3629 get_option(&str, &armclk);
3635 //clk_set_rate_nolock(&arm_pll_clk, armclk);
3638 #ifndef RK30_CLK_OFFBOARD_TEST
3639 early_param("armclk", armclk_setup);
3643 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3647 unsigned long rate = clk->rate;
3648 //CLKDATA_DBG("dump_clock %s\n",clk->name);
3649 for (i = 0; i < deep; i++)
3652 printk("%-11s ", clk->name);
3653 #ifndef RK30_CLK_OFFBOARD_TEST
3654 if (clk->flags & IS_PD) {
3655 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3658 if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3659 int idx = clk->gate_idx;
3661 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3662 printk("%s ", v ? "off" : "on ");
3667 u32 pll_id = clk->pll->id;
3668 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3669 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3671 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3673 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3676 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3678 } else if(clk == &clk_ddr) {
3679 rate = clk->recalc(clk);
3684 printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3686 printk("%ld MHz", rate / MHZ);
3687 } else if (rate >= KHZ) {
3689 printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3691 printk("%ld KHz", rate / KHZ);
3693 printk("%ld Hz", rate);
3696 printk(" usecount = %d", clk->usecount);
3699 printk(" parent = %s", clk->parent->name);
3703 list_for_each_entry(ck, root_clocks, node) {
3704 if (ck->parent == clk)
3705 rk_dump_clock(ck, deep + 1, root_clocks);
3710 struct list_head *get_rk_clocks_head(void);
3712 void rk_dump_clock_info(void)
3715 list_for_each_entry(clk, get_rk_clocks_head(), node) {
3717 rk_dump_clock(clk, 0,get_rk_clocks_head());
3722 #ifdef CONFIG_PROC_FS
3724 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3728 unsigned long rate = clk->rate;
3729 //CLKDATA_DBG("dump_clock %s\n",clk->name);
3730 for (i = 0; i < deep; i++)
3733 seq_printf(s, "%-11s ", clk->name);
3734 #ifndef RK30_CLK_OFFBOARD_TEST
3735 if (clk->flags & IS_PD) {
3736 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3739 if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3740 int idx = clk->gate_idx;
3742 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3743 seq_printf(s, "%s ", v ? "off" : "on ");
3748 u32 pll_id = clk->pll->id;
3749 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3750 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3751 seq_printf(s, "slow ");
3752 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3753 seq_printf(s, "normal ");
3754 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3755 seq_printf(s, "deep ");
3757 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3758 seq_printf(s, "bypass ");
3759 } else if(clk == &clk_ddr) {
3760 rate = clk->recalc(clk);
3765 seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3767 seq_printf(s, "%ld MHz", rate / MHZ);
3768 } else if (rate >= KHZ) {
3770 seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3772 seq_printf(s, "%ld KHz", rate / KHZ);
3774 seq_printf(s, "%ld Hz", rate);
3777 seq_printf(s, " usecount = %d", clk->usecount);
3780 seq_printf(s, " parent = %s", clk->parent->name);
3782 seq_printf(s, "\n");
3784 list_for_each_entry(ck, root_clocks, node) {
3785 if (ck->parent == clk)
3786 dump_clock(s, ck, deep + 1, root_clocks);
3790 static void dump_regs(struct seq_file *s)
3793 seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3794 seq_printf(s, "\nPLLRegisters:\n");
3795 for(i = 0; i < END_PLL_ID; i++) {
3796 seq_printf(s, "pll%d :cons:%x,%x,%x,%x\n", i,
3797 cru_readl(PLL_CONS(i, 0)),
3798 cru_readl(PLL_CONS(i, 1)),
3799 cru_readl(PLL_CONS(i, 2)),
3800 cru_readl(PLL_CONS(i, 3))
3803 seq_printf(s, "MODE :%x\n", cru_readl(CRU_MODE_CON));
3805 for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3806 seq_printf(s, "CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3808 for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3809 seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3811 seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3812 seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3814 for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3815 seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3817 seq_printf(s, "CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
3818 seq_printf(s, "GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
3822 void rk30_clk_dump_regs(void)
3825 printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3826 printk("\nPLLRegisters:\n");
3827 for(i = 0; i < END_PLL_ID; i++) {
3828 printk("pll%d :cons:%x,%x,%x,%x\n", i,
3829 cru_readl(PLL_CONS(i, 0)),
3830 cru_readl(PLL_CONS(i, 1)),
3831 cru_readl(PLL_CONS(i, 2)),
3832 cru_readl(PLL_CONS(i, 3))
3835 printk("MODE :%x\n", cru_readl(CRU_MODE_CON));
3837 for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3838 printk("CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3840 for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3841 printk("CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3843 printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3844 printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3846 for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3847 printk("SOFTRST%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3849 printk("CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
3850 printk("GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
3855 #ifdef CONFIG_PROC_FS
3856 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3857 struct clk_dump_ops dump_ops = {
3858 .dump_clk = dump_clock,
3859 .dump_regs = dump_regs,
3864 #endif /* CONFIG_PROC_FS */
3869 #ifdef RK30_CLK_OFFBOARD_TEST
3870 struct clk *test_get_parent(struct clk *clk) {
3876 struct clk *i2s_clk = &clk_i2s0;
3878 clk_enable_nolock(i2s_clk);
3880 clk_set_rate_nolock(i2s_clk, 12288000);
3881 printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3882 clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3883 printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3884 clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3885 printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3889 void uart_test(void)
3891 struct clk *uart_clk = &clk_uart0;
3893 clk_enable_nolock(uart_clk);
3895 clk_set_rate_nolock(uart_clk, 12288000);
3896 printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3897 clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3898 printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3899 clk_set_rate_nolock(uart_clk, 12 * MHZ);
3900 printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3903 void hsadc_test(void)
3905 struct clk *hsadc_clk = &clk_hsadc;
3907 printk("******************hsadc_test**********************\n");
3908 clk_enable_nolock(hsadc_clk);
3910 clk_set_rate_nolock(hsadc_clk, 12288000);
3911 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3914 clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3915 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3917 clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3919 clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3921 printk("******************hsadc out clock**********************\n");
3923 clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3924 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3925 clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3926 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3932 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3935 printk("*********arm_pll_clk***********\n");
3936 clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3938 printk("*********set clk_core parent***********\n");
3939 clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3940 clk_set_rate_nolock(&clk_core, 504 * MHZ);
3943 printk("*********general_pll_clk***********\n");
3944 clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3947 printk("*********codec_pll_clk***********\n");
3948 clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3951 printk("*********periph_clk_set_init***********\n");
3952 clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3953 periph_clk_set_init();
3956 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3958 printk("*********clk i2s***********\n");
3959 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3960 printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3964 clk_enable_nolock(&clk_spi0);
3965 clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3966 printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3968 clk_enable_nolock(&clk_saradc);
3969 clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3970 printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3972 clk_enable_nolock(&clk_sdio);
3973 clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3974 printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3976 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3979 printk("*********mac***********\n");
3981 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3982 printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3984 //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3985 clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3986 printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3988 printk("*********mac mii set***********\n");
3989 clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3990 clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3991 printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3993 printk("*********hsadc 1***********\n");
3997 clk_enable_nolock(&dclk_lcdc0);
3999 clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
4000 clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
4003 clk_enable_nolock(&cif0_out);
4005 clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
4006 printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
4008 clk_set_rate_nolock(&cif0_out, 60 * MHZ);
4009 printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4011 clk_set_rate_nolock(&cif0_out, 24 * MHZ);
4012 printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4014 clk_enable_nolock(&cif0_in);
4015 clk_set_rate_nolock(&cif0_in, 24 * MHZ);
4017 clk_enable_nolock(&aclk_lcdc0);
4018 clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
4019 printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
4021 clk_enable_nolock(&aclk_vepu);
4022 clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4023 printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
4025 clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
4026 printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
4028 printk("test end\n");
4031 clk_set_rate_nolock(&arm_pll_clk, armclk);
4032 clk_set_rate_nolock(&clk_core, armclk);//pll:core =1:1
4035 //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
4037 //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4038 //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
4046 static LIST_HEAD(rk30_clocks);
4047 static DEFINE_MUTEX(rk30_clocks_mutex);
4049 static inline int __rk30clk_get(struct clk *clk)
4053 void rk30_clkdev_add(struct clk_lookup *cl)
4055 mutex_lock(&rk30_clocks_mutex);
4056 list_add_tail(&cl->node, &rk30_clocks);
4057 mutex_unlock(&rk30_clocks_mutex);
4059 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
4060 struct clk_lookup *p, *cl = NULL;
4061 int match, best = 0;
4063 list_for_each_entry(p, &rk30_clocks, node) {
4066 if (!dev_id || strcmp(p->dev_id, dev_id))
4071 if (!con_id || strcmp(p->con_id, con_id))
4087 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
4088 struct clk_lookup *cl;
4090 mutex_lock(&rk30_clocks_mutex);
4091 cl = rk30_clk_find(dev_id, con_id);
4092 if (cl && !__rk30clk_get(cl->clk))
4094 mutex_unlock(&rk30_clocks_mutex);
4096 return cl ? cl->clk : ERR_PTR(-ENOENT);
4098 //EXPORT_SYMBOL(rk30_clk_get_sys);
4100 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
4101 const char *dev_id = dev ? dev_name(dev) : NULL;
4102 return rk30_clk_get_sys(dev_id, con_id);
4104 //EXPORT_SYMBOL(rk30_clk_get);
4107 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
4109 void rk30_clocks_test(void)
4111 struct clk *test_gpll;
4112 test_gpll = rk30_clk_get(NULL, "general_pll");
4114 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
4115 printk("gpll rate=%lu\n", test_gpll->rate);
4120 void __init rk30_clock_init_test(void)
4123 rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);