arch/arm/mach-rk3188/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <plat/efuse.h>
  25 #include <mach/cru.h>
  26 #include <mach/iomux.h>
  27 #include <mach/clock.h>
  28 #include <mach/pmu.h>
  29 #include <mach/dvfs.h>
  30 #include <mach/ddr.h>
  31 #include <mach/cpu.h>
  32
  33 #define MHZ                     (1000UL * 1000UL)
  34 #define KHZ                     (1000UL)
  35 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  36 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
  37 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  38 void rk30_clk_dump_regs(void);
  39
  40 //flags bit
  41 //has extern 27mhz
  42 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  43 //max i2s rate
  44 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  45 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  46 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  47 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  48 //uart 1m\3m
  49 #define CLK_FLG_UART_1_3M                       (1<<5)
  50
  51 #define ARCH_RK31
  52
  53 struct apll_clk_set {
  54         unsigned long   rate;
  55         u32     pllcon0;
  56         u32     pllcon1;
  57         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  58         u32     rst_dly;//us
  59         u32     clksel0;
  60         u32     clksel1;
  61         unsigned long   lpj;
  62 };
  63 struct pll_clk_set {
  64         unsigned long   rate;
  65         u32     pllcon0;
  66         u32     pllcon1;
  67         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  68         unsigned long   rst_dly;//us
  69 };
  70
  71 #define SET_PLL_DATA(_pll_id,_table) \
  72 {\
  73         .id=(_pll_id),\
  74         .table=(_table),\
  75 }
  76
  77
  78 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  79 { \
  80         .rate   = (_mhz) * KHZ, \
  81         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  82         .pllcon1 = PLL_CLKF_SET(nf),\
  83         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  84         .rst_dly=((nr*500)/24+1),\
  85 }
  86
  87
  88 #define _APLL_SET_LPJ(_mhz) \
  89         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  90
  91
  92 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  93                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  94 { \
  95         .rate   = _mhz * MHZ, \
  96         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  97         .pllcon1 = PLL_CLKF_SET(nf),\
  98         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  99         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
 100         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
 101         _APLL_SET_LPJ(_mhz),\
 102         .rst_dly=((nr*500)/24+1),\
 103 }
 104
 105 #define CRU_DIV_SET(mask,shift,max) \
 106         .div_mask=(mask),\
 107 .div_shift=(shift),\
 108 .div_max=(max)
 109
 110
 111 #define CRU_SRC_SET(mask,shift ) \
 112         .src_mask=(mask),\
 113 .src_shift=(shift)
 114
 115 #define CRU_PARENTS_SET(parents_array) \
 116         .parents=(parents_array),\
 117 .parents_num=ARRAY_SIZE((parents_array))
 118
 119 #define CRU_GATE_MODE_SET(_func,_IDX) \
 120         .mode=_func,\
 121 .gate_idx=(_IDX)
 122
 123 struct clk_src_sel {
 124         struct clk      *parent;
 125         u8      value;//crt bit
 126         u8      flag;
 127         //selgate
 128 };
 129
 130 #define GATE_CLK(NAME,PARENT,ID) \
 131         static struct clk clk_##NAME = { \
 132                 .name           = #NAME, \
 133                 .parent         = &PARENT, \
 134                 .mode           = gate_mode, \
 135                 .gate_idx       = CLK_GATE_##ID, \
 136         }
 137 #ifdef RK30_CLK_OFFBOARD_TEST
 138 u32 TEST_GRF_REG[0x240];
 139 u32 TEST_CRU_REG[0x240];
 140 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 141
 142 u32 cru_writel_is_pr(u32 offset)
 143 {
 144         return (offset == 0x4000);
 145 }
 146 void cru_writel(u32 v, u32 offset)
 147 {
 148
 149         u32 mask_v = v >> 16;
 150         TEST_CRU_REG[offset/4] &= (~mask_v);
 151
 152         v &= (mask_v);
 153
 154         TEST_CRU_REG[offset/4] |= v;
 155         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 156
 157         if(cru_writel_is_pr(offset)) {
 158                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 159
 160         }
 161
 162 }
 163 void cru_writel_i2s(u32 v, u32 offset)
 164 {
 165         TEST_CRU_REG[offset/4] = v;
 166 }
 167 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 168
 169 #define regfile_readl(offset)   (0xffffffff)
 170 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 171 void rk30_clkdev_add(struct clk_lookup *cl);
 172 #else
 173 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 174 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 175 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 176 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 177
 178 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 179 #endif
 180
 181 //#define DEBUG
 182 #ifdef DEBUG
 183 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 184 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 185 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
 186 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
 187 #else
 188 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 189 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 190 #endif
 191 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 192 #define CLKDATA_WARNING(fmt, args...) printk("CLKDATA_WANING:\t"fmt, ##args)
 193
 194
 195 #define get_cru_bits(con,mask,shift)\
 196         ((cru_readl((con)) >> (shift)) & (mask))
 197
 198 #define set_cru_bits_w_msk(val,mask,shift,con)\
 199         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 200
 201
 202 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 203                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 204
 205
 206 static u32 rk30_clock_flags = 0;
 207 static struct clk codec_pll_clk;
 208 static struct clk general_pll_clk;
 209 static struct clk arm_pll_clk;
 210 static unsigned long lpj_gpll;
 211 static unsigned int __initdata armclk = 504 * MHZ;
 212
 213
 214 /************************clk recalc div rate*********************************/
 215
 216 //for free div
 217 static unsigned long clksel_recalc_div(struct clk *clk)
 218 {
 219         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 220
 221         unsigned long rate = clk->parent->rate / div;
 222         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 223         return rate;
 224 }
 225
 226 //for div 1 2 4 2^n
 227 static unsigned long clksel_recalc_shift(struct clk *clk)
 228 {
 229         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 230         unsigned long rate = clk->parent->rate >> shift;
 231         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 232         return rate;
 233 }
 234
 235
 236 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 237 {
 238         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 239         unsigned long rate = clk->parent->rate >> shift;
 240         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 241         return rate;
 242 }
 243
 244 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 245 {
 246         unsigned long rate = clk->parent->rate;
 247         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 248         return rate;
 249 }
 250 /********************************set div rate***********************************/
 251
 252 //for free div
 253 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 254 {
 255         u32 div;
 256         for (div = 0; div < clk->div_max; div++) {
 257                 u32 new_rate = clk->parent->rate / (div + 1);
 258                 if (new_rate <= rate) {
 259                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 260                         //clk->rate = new_rate;
 261                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 262                                         clk->name, rate, div + 1);
 263                         return 0;
 264                 }
 265         }
 266         return -ENOENT;
 267 }
 268
 269 //for div 1 2 4 2^n
 270 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 271 {
 272         u32 shift;
 273         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 274                 u32 new_rate = clk->parent->rate >> shift;
 275                 if (new_rate <= rate) {
 276                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 277                         clk->rate = new_rate;
 278                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 279                                         clk->name, rate, shift);
 280                         return 0;
 281                 }
 282         }
 283         return -ENOENT;
 284 }
 285
 286 //for div 2 4 2^n
 287 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 288 {
 289         u32 shift;
 290
 291         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 292                 u32 new_rate = clk->parent->rate >> shift;
 293                 if (new_rate <= rate) {
 294                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 295                         clk->rate = new_rate;
 296                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 297                                         clk->name, rate, shift);
 298                         return 0;
 299                 }
 300         }
 301         return -ENOENT;
 302 }
 303
 304 //for div 1 2 4 2*n
 305 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 306 {
 307         u32 div;
 308         for (div = 2; div < clk->div_max; div += 2) {
 309                 u32 new_rate = clk->parent->rate / div;
 310                 if (new_rate <= rate) {
 311                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 312                         clk->rate = new_rate;
 313                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 314                                         __func__, clk->name, rate, div);
 315                         return 0;
 316                 }
 317         }
 318         return -ENOENT;
 319 }
 320 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 321 {
 322         u32 div;
 323         unsigned long new_rate;
 324         for (div = 0; div < div_max; div++) {
 325                 new_rate = rate / (div + 1);
 326                 if (new_rate <= rate_out) {
 327                         return div + 1;
 328                 }
 329         }
 330         return div_max ? div_max : 1;
 331 }
 332 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 333 {
 334         u32 div;
 335         unsigned long new_rate;
 336         for (div = 1; div < div_max; div += 2) {
 337                 new_rate = rate / (div + 1);
 338                 if (new_rate <= rate_out) {
 339                         return div + 1;
 340                 }
 341         }
 342         return div_max ? div_max : 1;
 343 }
 344 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 345         u32 div[2] = {0, 0};
 346         unsigned long new_rate[2] = {0, 0};
 347         u32 i;
 348
 349         if(clk->rate == rate)
 350                 return clk->parent;
 351         for(i = 0; i < 2; i++) {
 352                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 353                 new_rate[i] = clk->parents[i]->rate / div[i];
 354                 if(new_rate[i] == rate) {
 355                         *div_out = div[i];
 356                         return clk->parents[i];
 357                 }
 358         }
 359         if(new_rate[0] < new_rate[1])
 360                 i = 1;
 361         else
 362                 i = 0;
 363         *div_out = div[i];
 364         return clk->parents[i];
 365 }
 366 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 367         u32 div[2] = {0, 0};
 368         unsigned long new_rate[2] = {0, 0};
 369         u32 i;
 370
 371         if(clk->rate == rate)
 372                 return clk->parent;
 373         for(i = 0; i < 2; i++) {
 374                 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 375                 new_rate[i] = clk->parents[i]->rate / div[i];
 376                 if(new_rate[i] == rate) {
 377                         *div_out = div[i];
 378                         return clk->parents[i];
 379                 }
 380         }
 381         if(new_rate[0] < new_rate[1])
 382                 i = 1;
 383         else
 384                 i = 0;
 385         *div_out = div[i];
 386         return clk->parents[i];
 387 }
 388
 389 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 390 {
 391         struct clk *p_clk;
 392         u32 div, old_div;
 393         int ret = 0;
 394         if(clk->rate == rate)
 395                 return 0;
 396         p_clk = get_freediv_parents_div(clk, rate, &div);
 397
 398         if(!p_clk)
 399                 return -ENOENT;
 400
 401         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 402         if (clk->parent != p_clk) {
 403                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 404
 405                 if(div > old_div) {
 406                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 407                 }
 408                 ret = clk_set_parent_nolock(clk, p_clk);
 409                 if(ret) {
 410                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 411                         return -ENOENT;
 412                 }
 413         }
 414         //set div
 415         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 416         return 0;
 417 }
 418 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 419 {
 420         struct clk *p_clk;
 421         u32 div, old_div;
 422         int ret = 0;
 423         if(clk->rate == rate)
 424                 return 0;
 425         p_clk = get_evendiv_parents_div(clk, rate, &div);
 426
 427         if(!p_clk)
 428                 return -ENOENT;
 429
 430         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 431         if (clk->parent != p_clk) {
 432                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 433
 434                 if(div > old_div) {
 435                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 436                 }
 437                 ret = clk_set_parent_nolock(clk, p_clk);
 438                 if(ret) {
 439                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 440                         return -ENOENT;
 441                 }
 442         }
 443         //set div
 444         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 445         return 0;
 446 }
 447
 448 //rate==div rate //hdmi
 449 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 450 {
 451         struct clk *p_clk;
 452         u32 div, old_div;
 453         int ret;
 454         p_clk = get_freediv_parents_div(clk, rate, &div);
 455
 456         if(!p_clk)
 457                 return -ENOENT;
 458
 459         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 460                 return -ENOENT;
 461
 462         if (clk->parent != p_clk) {
 463                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 464                                 clk->div_shift, clk->div_mask) + 1;
 465                 if(div > old_div) {
 466                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 467                 }
 468                 ret = clk_set_parent_nolock(clk, p_clk);
 469                 if (ret) {
 470                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 471                         return ret;
 472                 }
 473         }
 474         //set div
 475         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 476         return 0;
 477 }
 478
 479 /***************************round********************************/
 480
 481 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 482 {
 483         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 484 }
 485
 486 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 487 {
 488         u32 div;
 489         struct clk *p_clk;
 490         if(clk->rate == rate)
 491                 return clk->rate;
 492         p_clk = get_freediv_parents_div(clk, rate, &div);
 493         if(!p_clk)
 494                 return 0;
 495         return p_clk->rate / div;
 496 }
 497
 498 /**************************************others seting************************************/
 499
 500 static struct clk *clksel_get_parent(struct clk *clk) {
 501         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 502 }
 503 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 504 {
 505         u32 i;
 506         if (unlikely(!clk->parents))
 507                 return -EINVAL;
 508         for (i = 0; (i < clk->parents_num); i++) {
 509                 if (clk->parents[i] != parent)
 510                         continue;
 511                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 512                 return 0;
 513         }
 514         return -EINVAL;
 515 }
 516
 517 static int gate_mode(struct clk *clk, int on)
 518 {
 519         int idx = clk->gate_idx;
 520         if (idx >= CLK_GATE_MAX)
 521                 return -EINVAL;
 522         if(on) {
 523                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 524                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 525                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 526         } else {
 527                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 528                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 529                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 530         }
 531         return 0;
 532 }
 533 /*****************************frac set******************************************/
 534
 535 static unsigned long clksel_recalc_frac(struct clk *clk)
 536 {
 537         unsigned long rate;
 538         u64 rate64;
 539         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 540         if (r == 0) // FPGA ?
 541                 return clk->parent->rate;
 542         numerator = r >> 16;
 543         denominator = r & 0xFFFF;
 544         rate64 = (u64)clk->parent->rate * numerator;
 545         do_div(rate64, denominator);
 546         rate = rate64;
 547         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 548         return rate;
 549 }
 550
 551 static u32 clk_gcd(u32 numerator, u32 denominator)
 552 {
 553         u32 a, b;
 554
 555         if (!numerator || !denominator)
 556                 return 0;
 557         if (numerator > denominator) {
 558                 a = numerator;
 559                 b = denominator;
 560         } else {
 561                 a = denominator;
 562                 b = numerator;
 563         }
 564         while (b != 0) {
 565                 int r = b;
 566                 b = a % b;
 567                 a = r;
 568         }
 569
 570         return a;
 571 }
 572
 573 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 574                 u32 *numerator, u32 *denominator)
 575 {
 576         u32 gcd_vl;
 577         gcd_vl = clk_gcd(rate, rate_out);
 578         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 579
 580         if (!gcd_vl) {
 581                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 582                 return -ENOENT;
 583         }
 584
 585         *numerator = rate_out / gcd_vl;
 586         *denominator = rate / gcd_vl;
 587
 588         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 589                         *numerator, *denominator, *denominator / *numerator);
 590
 591         if (*numerator > 0xffff || *denominator > 0xffff ||
 592                         (*denominator / (*numerator)) < 20) {
 593                 CLKDATA_ERR("can't get a available nume and deno\n");
 594                 return -ENOENT;
 595         }
 596
 597         return 0;
 598
 599 }
 600 /* *********************pll **************************/
 601
 602 #define rk30_clock_udelay(a) udelay(a);
 603
 604 /*********************pll lock status**********************************/
 605 //#define GRF_SOC_CON0       0x15c
 606 static void pll_wait_lock(int pll_idx)
 607 {
 608         u32 pll_state[4] = {1, 0, 2, 3};
 609         u32 bit = 0x20u << pll_state[pll_idx];
 610         int delay = 24000000;
 611         while (delay > 0) {
 612                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 613                         break;
 614                 delay--;
 615         }
 616         if (delay == 0) {
 617                 CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
 618                                 cru_readl(PLL_CONS(pll_idx, 0)),
 619                                 cru_readl(PLL_CONS(pll_idx, 1)),
 620                                 cru_readl(PLL_CONS(pll_idx, 2)),
 621                                 cru_readl(PLL_CONS(pll_idx, 3)));
 622
 623                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 624                 while(1);
 625         }
 626 }
 627
 628
 629
 630 /***************************pll function**********************************/
 631 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 632 {
 633         unsigned long rate;
 634
 635         if (PLLS_IN_NORM(pll_id)) {
 636                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 637                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 638
 639
 640                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 641
 642                 /*
 643                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 644                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 645                    */
 646
 647
 648                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 649                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 650                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 651
 652                 do_div(rate64, PLL_NR(pll_con0));
 653                 do_div(rate64, PLL_NO(pll_con0));
 654
 655                 rate = rate64;
 656                 /*
 657                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 658                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 659                    */
 660         } else {
 661                 rate = parent_rate;
 662                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 663         }
 664         return rate;
 665 }
 666 static unsigned long plls_clk_recalc(struct clk *clk)
 667 {
 668         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 669 }
 670 static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 671 {
 672         unsigned long rate;
 673
 674         if (PLLS_IN_NORM(pll_id)) {
 675                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 676                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 677
 678                 u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
 679
 680                 do_div(rate64, PLUS_PLL_NR(pll_con0));
 681                 do_div(rate64, PLUS_PLL_NO(pll_con0));
 682
 683                 rate = rate64;
 684         } else {
 685                 rate = parent_rate;
 686                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 687         }
 688         return rate;
 689 }
 690 static unsigned long plus_plls_clk_recalc(struct clk *clk)
 691 {
 692         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 693         return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
 694 }
 695
 696 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 697 {
 698         //enter slowmode
 699         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 700         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 701         dsb();
 702         dsb();
 703         dsb();
 704         dsb();
 705         dsb();
 706         dsb();
 707         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 708         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 709
 710         rk30_clock_udelay(1);
 711         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 712
 713         pll_wait_lock(pll_id);
 714
 715         //return form slow
 716         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 717
 718         /*
 719            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 720            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 721            */
 722
 723         return 0;
 724 }
 725
 726 static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 727 {
 728         //enter slowmode
 729         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 730
 731         //enter rest
 732         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
 733         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 734         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 735         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
 736         rk30_clock_udelay(5);
 737
 738         //return form rest
 739         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
 740
 741         //wating lock state
 742         rk30_clock_udelay(clk_set->rst_dly);
 743         pll_wait_lock(pll_id);
 744
 745         //return form slow
 746         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 747
 748         return 0;
 749 }
 750
 751 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 752 {
 753         struct _pll_data *pll_data = c->pll;
 754         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 755
 756         while(clk_set->rate) {
 757                 if (clk_set->rate == rate) {
 758                         break;
 759                 }
 760                 clk_set++;
 761         }
 762         if(clk_set->rate == rate) {
 763                 pll_clk_set_rate(clk_set, pll_data->id);
 764                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 765         } else {
 766                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 767                 return -1;
 768         }
 769         return 0;
 770 }
 771
 772 static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
 773 {
 774         struct _pll_data *pll_data = c->pll;
 775         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 776         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 777
 778         while(clk_set->rate) {
 779                 if (clk_set->rate == rate) {
 780                         break;
 781                 }
 782                 clk_set++;
 783         }
 784         if(clk_set->rate == rate) {
 785                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 786                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 787         } else {
 788                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 789                 return -1;
 790         }
 791         return 0;
 792 }
 793 #define PLL_FREF_MIN (183*KHZ)
 794 #define PLL_FREF_MAX (1500*MHZ)
 795
 796 #define PLL_FVCO_MIN (300*MHZ)
 797 #define PLL_FVCO_MAX (1500*MHZ)
 798
 799 #define PLL_FOUT_MIN (18750*KHZ)
 800 #define PLL_FOUT_MAX (1500*MHZ)
 801
 802 #define PLL_NF_MAX (65536)
 803 #define PLL_NR_MAX (64)
 804 #define PLL_NO_MAX (64)
 805
 806 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 807 {
 808         u32 nr, nf, no, nonr;
 809         u32 n;
 810         u32 YFfenzi;
 811         u32 YFfenmu;
 812         unsigned long fref, fvco, fout;
 813         u32 gcd_val = 0;
 814
 815         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 816         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 817                 return 0;
 818         gcd_val = clk_gcd(fin_hz, fout_hz);
 819         YFfenzi = fout_hz / gcd_val;
 820         YFfenmu = fin_hz / gcd_val;
 821
 822         for(n = 1;; n++) {
 823                 nf = YFfenzi * n;
 824                 nonr = YFfenmu * n;
 825                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 826                         break;
 827                 for(no = 1; no <= PLL_NO_MAX; no++) {
 828                         if(!(no == 1 || !(no % 2)))
 829                                 continue;
 830
 831                         if(nonr % no)
 832                                 continue;
 833                         nr = nonr / no;
 834
 835                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 836                                 continue;
 837
 838                         fref = fin_hz / nr;
 839                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 840                                 continue;
 841
 842                         fvco = (fin_hz / nr) * nf;
 843                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 844                                 continue;
 845                         fout = fvco / no;
 846                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 847                                 continue;
 848                         *clk_nr = nr;
 849                         *clk_no = no;
 850                         *clk_nf = nf;
 851                         return 1;
 852
 853                 }
 854
 855         }
 856         return 0;
 857 }
 858
 859 static int pll_clk_mode(struct clk *clk, int on)
 860 {
 861         u8 pll_id = clk->pll->id;
 862         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 863         u32 dly = (nr * 500) / 24 + 1;
 864         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 865         if (on) {
 866                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 867                 rk30_clock_udelay(dly);
 868                 pll_wait_lock(pll_id);
 869                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 870         } else {
 871                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 872                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 873         }
 874         return 0;
 875 }
 876
 877 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 878 {
 879         struct _pll_data *pll_data = c->pll;
 880         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 881         struct pll_clk_set temp_clk_set;
 882         u32 clk_nr, clk_nf, clk_no;
 883
 884         if(rate == 24 * MHZ) {
 885                 cru_writel(PLL_MODE_SLOW(pll_data->id), CRU_MODE_CON);
 886                 cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll_data->id, 3));
 887                 return 0;
 888         }
 889         while(clk_set->rate) {
 890                 if (clk_set->rate == rate) {
 891                         break;
 892                 }
 893                 clk_set++;
 894         }
 895         if(clk_set->rate == rate) {
 896                 CLKDATA_DBG("cpll get a rate\n");
 897                 pll_clk_set_rate(clk_set, pll_data->id);
 898
 899         } else {
 900                 CLKDATA_DBG("cpll get auto calc a rate\n");
 901                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 902                         pr_err("cpll auto set rate error\n");
 903                         return -ENOENT;
 904                 }
 905                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 906                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 907                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 908                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 909                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 910
 911         }
 912         return 0;
 913 }
 914 static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
 915 {
 916         struct _pll_data *pll_data = c->pll;
 917         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 918         struct pll_clk_set temp_clk_set;
 919         u32 clk_nr, clk_nf, clk_no;
 920         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 921
 922         while(clk_set->rate) {
 923                 if (clk_set->rate == rate) {
 924                         break;
 925                 }
 926                 clk_set++;
 927         }
 928         if(clk_set->rate == rate) {
 929                 CLKDATA_DBG("cpll get a rate\n");
 930                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 931
 932         } else {
 933                 CLKDATA_DBG("cpll get auto calc a rate\n");
 934                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 935                         pr_err("cpll auto set rate error\n");
 936                         return -ENOENT;
 937                 }
 938                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 939                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 940                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 941                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 942                 plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
 943
 944         }
 945         return 0;
 946 }
 947
 948
 949 /* ******************fixed input clk ***********************************************/
 950 static struct clk xin24m = {
 951         .name           = "xin24m",
 952         .rate           = 24 * MHZ,
 953         .flags          = RATE_FIXED,
 954 };
 955
 956 static struct clk clk_12m = {
 957         .name           = "clk_12m",
 958         .parent         = &xin24m,
 959         .rate           = 12 * MHZ,
 960         .flags          = RATE_FIXED,
 961 };
 962
 963 /************************************pll func***************************/
 964 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 965                 struct apll_clk_set *tables) {
 966         const struct apll_clk_set *ps, *pt;
 967
 968         /* find the arm_pll we want. */
 969         ps = pt = tables;
 970         while (pt->rate) {
 971                 if (pt->rate == rate) {
 972                         ps = pt;
 973                         break;
 974                 }
 975                 // we are sorted, and ps->rate > pt->rate.
 976                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 977                         ps = pt;
 978                 if (pt->rate < rate)
 979                         break;
 980                 pt++;
 981         }
 982         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 983         return ps;
 984 }
 985 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 986 {
 987         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 988 }
 989 #if 1
 990 struct arm_clks_div_set {
 991         u32 rate;
 992         u32     clksel0;
 993         u32     clksel1;
 994 };
 995
 996 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 997 { \
 998         .rate    =_mhz,\
 999         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
1000         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
1001         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
1002         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
1003         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
1004 }
1005 struct arm_clks_div_set arm_clk_div_tlb[] = {
1006         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
1007         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
1008         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
1009         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
1010         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
1011         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
1012         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
1013 };
1014 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
1015         int i = 0;
1016         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
1017                 if(arm_clk_div_tlb[i].rate >= rate)
1018                         return &arm_clk_div_tlb[i];
1019         }
1020         return NULL;
1021 }
1022
1023 #endif
1024
1025 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1026 {
1027         unsigned long flags;
1028         const struct apll_clk_set *ps;
1029         u32 pll_id = clk->pll->id;
1030         u32 temp_div;
1031         u32 old_aclk_div = 0, new_aclk_div;
1032
1033         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1034
1035         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1036         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1037
1038         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1039                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1040
1041         if(general_pll_clk.rate > clk->rate) {
1042                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1043         } else {
1044                 temp_div = 1;
1045         }
1046
1047         // ungating cpu gpll path
1048         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1049         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1050
1051         local_irq_save(flags);
1052         //div arm clk for gpll
1053
1054         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1055         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1056
1057         loops_per_jiffy = lpj_gpll / temp_div;
1058         smp_wmb();
1059
1060         /*if core src don't select gpll ,apll neet to enter slow mode */
1061         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1062
1063
1064         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
1065         dsb();
1066         dsb();
1067         dsb();
1068         dsb();
1069         dsb();
1070         dsb();
1071         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1072         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1073
1074         rk30_clock_udelay(1);
1075         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
1076
1077         pll_wait_lock(pll_id);
1078
1079         //return form slow
1080         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1081         //reparent to apll
1082
1083         if(new_aclk_div>=old_aclk_div) {
1084                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1085                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1086         }
1087
1088         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1089         if(old_aclk_div>new_aclk_div) {
1090                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1091                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1092         }
1093
1094         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1095
1096         loops_per_jiffy = ps->lpj;
1097         smp_wmb();
1098
1099         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1100
1101         local_irq_restore(flags);
1102
1103         //gate gpll path
1104         // FIXME
1105         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1106         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1107
1108         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1109                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1110                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1111                         cru_readl(CRU_CLKSELS_CON(1)));
1112         return 0;
1113 }
1114
1115 static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1116 {
1117         unsigned long flags;
1118         const struct apll_clk_set *ps;
1119         u32 pll_id = clk->pll->id;
1120         u32 temp_div;
1121         u32 old_aclk_div = 0, new_aclk_div;
1122         DVFS_DBG("%s: for rk3188 plus\n", __func__);
1123
1124         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1125
1126         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1127         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1128
1129         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1130                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1131
1132         if(general_pll_clk.rate > clk->rate) {
1133                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1134         } else {
1135                 temp_div = 1;
1136         }
1137
1138         // ungating cpu gpll path
1139         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1140         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1141
1142         local_irq_save(flags);
1143         //div arm clk for gpll
1144
1145         cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1146         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1147
1148         loops_per_jiffy = lpj_gpll / temp_div;
1149         smp_wmb();
1150
1151         /*if core src don't select gpll ,apll neet to enter slow mode */
1152         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1153
1154         //enter rest
1155         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
1156         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1157         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1158         cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
1159         rk30_clock_udelay(5);
1160
1161         //return form rest
1162         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
1163
1164         //wating lock state
1165         rk30_clock_udelay(ps->rst_dly);
1166         pll_wait_lock(pll_id);
1167
1168         if(new_aclk_div>=old_aclk_div) {
1169                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1170                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1171         }
1172
1173         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1174         if(old_aclk_div>new_aclk_div) {
1175                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1176                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1177         }
1178
1179         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1180
1181         loops_per_jiffy = ps->lpj;
1182         smp_wmb();
1183
1184         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1185
1186         local_irq_restore(flags);
1187
1188         //gate gpll path
1189         // FIXME
1190         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1191         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1192
1193         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1194                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1195                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1196                         cru_readl(CRU_CLKSELS_CON(1)));
1197         return 0;
1198 }
1199
1200 /************************************pll clocks***************************/
1201
1202 static const struct apll_clk_set apll_clks[] = {
1203         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1204         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1205         _APLL_SET_CLKS(2208, 1, 92, 1, 8,       81, 81, 21, 41, 21),
1206         _APLL_SET_CLKS(2184, 1, 91, 1, 8,       81, 81, 21, 41, 21),
1207         _APLL_SET_CLKS(2160, 1, 90, 1, 8,       81, 81, 21, 41, 21),
1208         _APLL_SET_CLKS(2136, 1, 89, 1, 8,       81, 81, 21, 41, 21),
1209         _APLL_SET_CLKS(2112, 1, 88, 1, 8,       81, 81, 21, 41, 21),
1210         _APLL_SET_CLKS(2088, 1, 87, 1, 8,       81, 81, 21, 41, 21),
1211         _APLL_SET_CLKS(2064, 1, 86, 1, 8,       81, 81, 21, 41, 21),
1212         _APLL_SET_CLKS(2040, 1, 85, 1, 8,       81, 81, 21, 41, 21),
1213         _APLL_SET_CLKS(2016, 1, 84, 1, 8,       81, 81, 21, 41, 21),
1214         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1215         _APLL_SET_CLKS(1968, 1, 82, 1, 8,       81, 81, 21, 41, 21),
1216         _APLL_SET_CLKS(1944, 1, 81, 1, 8,       81, 81, 21, 41, 21),
1217         _APLL_SET_CLKS(1920, 1, 80, 1, 8,       81, 81, 21, 41, 21),
1218         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1219         _APLL_SET_CLKS(1872, 1, 78, 1, 8,       81, 81, 21, 41, 21),
1220         _APLL_SET_CLKS(1848, 1, 77, 1, 8,       81, 81, 21, 41, 21),
1221         _APLL_SET_CLKS(1824, 1, 76, 1, 8,       81, 81, 21, 41, 21),
1222         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1223         _APLL_SET_CLKS(1776, 1, 74, 1, 8,       81, 81, 21, 41, 21),
1224         _APLL_SET_CLKS(1752, 1, 73, 1, 8,       81, 81, 21, 41, 21),
1225         _APLL_SET_CLKS(1728, 1, 72, 1, 8,       81, 81, 21, 41, 21),
1226         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1227         _APLL_SET_CLKS(1680, 1, 70, 1, 8,       41, 41, 21, 41, 21),
1228         _APLL_SET_CLKS(1656, 1, 69, 1, 8,       41, 41, 21, 41, 21),
1229         _APLL_SET_CLKS(1632, 1, 68, 1, 8,       41, 41, 21, 41, 21),
1230         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1231         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1232         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1233         _APLL_SET_CLKS(1488, 1, 62, 1, 8,       41, 41, 21, 41, 21),
1234         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1235         _APLL_SET_CLKS(1440, 1, 60, 1, 8,       41, 41, 21, 41, 21),
1236         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1237         _APLL_SET_CLKS(1392, 1, 58, 1, 8,       41, 41, 21, 41, 21),
1238         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1239         _APLL_SET_CLKS(1344, 1, 56, 1, 8,       41, 41, 21, 41, 21),
1240         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1241         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1242         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1243         _APLL_SET_CLKS(1248, 1, 52, 1, 8,       41, 41, 21, 41, 21),
1244         _APLL_SET_CLKS(1224, 1, 51, 1, 8,       41, 41, 21, 41, 21),
1245         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1246         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1247         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1248         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1249         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1250         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1251         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1252         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1253         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1254         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1255         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1256         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1257         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1258         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1259         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1260         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1261         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1262         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1263         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1264
1265 };
1266 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1267 static struct clk arm_pll_clk = {
1268         .name           = "arm_pll",
1269         .parent         = &xin24m,
1270         .mode           = pll_clk_mode,
1271         .recalc         = plls_clk_recalc,
1272         .set_rate       = arm_pll_clk_set_rate,
1273         .round_rate     = arm_pll_clk_round_rate,
1274         .pll            = &apll_data,
1275 };
1276
1277 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1278 {
1279         /* do nothing here */
1280         return 0;
1281 }
1282 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1283 static struct clk ddr_pll_clk = {
1284         .name           = "ddr_pll",
1285         .parent         = &xin24m,
1286         .recalc         = plls_clk_recalc,
1287         .set_rate       = ddr_pll_clk_set_rate,
1288         .pll            = &dpll_data,
1289 };
1290
1291 static const struct pll_clk_set cpll_clks[] = {
1292         _PLL_SET_CLKS(360000, 1,  60,   4),
1293         _PLL_SET_CLKS(408000, 1,  68,   4),
1294         _PLL_SET_CLKS(456000, 1,  76,   4),
1295         _PLL_SET_CLKS(504000, 1,  84,   4),
1296         _PLL_SET_CLKS(552000, 1,  46,   2),
1297         _PLL_SET_CLKS(594000, 2,  198,  4),
1298         _PLL_SET_CLKS(600000, 1,  50,   2),
1299         _PLL_SET_CLKS(742500, 8,  495,  2),
1300         _PLL_SET_CLKS(768000, 1,  64,   2),
1301         _PLL_SET_CLKS(798000, 2,  133,  2),
1302         _PLL_SET_CLKS(1188000, 2, 99,   1),
1303         _PLL_SET_CLKS(     0, 4,  133,  1),
1304 };
1305 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1306 static struct clk codec_pll_clk = {
1307         .name           = "codec_pll",
1308         .parent         = &xin24m,
1309         .mode           = pll_clk_mode,
1310         .recalc         = plls_clk_recalc,
1311         .set_rate       = cpll_clk_set_rate,
1312         .pll            = &cpll_data,
1313 };
1314
1315 static const struct pll_clk_set gpll_clks[] = {
1316         _PLL_SET_CLKS(148500,   2,      99,     8),
1317         _PLL_SET_CLKS(297000,   2,      198,    8),
1318         _PLL_SET_CLKS(300000,   1,      50,     4),
1319         _PLL_SET_CLKS(384000,   1,      64,     4),
1320         _PLL_SET_CLKS(594000,   2,      198,    4),
1321         _PLL_SET_CLKS(891000,   8,      594,    2),
1322         _PLL_SET_CLKS(1188000,  2,      99,     1),
1323         _PLL_SET_CLKS(1200000,  1,      50,     1),
1324         _PLL_SET_CLKS(0,        0,       0,     0),
1325 };
1326 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1327 static struct clk general_pll_clk = {
1328         .name           = "general_pll",
1329         .parent         = &xin24m,
1330         .recalc         = plls_clk_recalc,
1331         .set_rate       = gpll_clk_set_rate,
1332         .pll            = &gpll_data
1333 };
1334 /********************************clocks***********************************/
1335 //GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1336 static struct clk clk_ddr_gpll_path = {
1337         .name           = "ddr_gpll_path",
1338         .parent         = &general_pll_clk,
1339         .recalc         = clksel_recalc_parent_rate,
1340         .gate_idx       = CLK_GATE_DDR_GPLL,
1341         .mode           = gate_mode,
1342 };
1343
1344 /* core and cpu setting */
1345 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1346 {
1347         CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1348         return 0;
1349 }
1350
1351 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1352 {
1353         CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1354         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1355 }
1356 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1357 {
1358         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1359         unsigned long rate = 0;
1360         clk->parent = clk->get_parent(clk);
1361         rate = clk->parent->recalc(clk->parent) >> shift;
1362         CLKDATA_DBG("%s new clock rate is %lu (shift %u), parent=%s, rate=%lu\n",
1363                         clk->name, rate, shift, clk->parent->name, clk->parent->rate);
1364         return rate;
1365 }
1366 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1367 static struct clk clk_ddr = {
1368         .name           = "ddr",
1369         .parent         = &ddr_pll_clk,
1370         .get_parent     = clksel_get_parent,
1371         .set_parent     = clksel_set_parent,
1372         .recalc         = ddr_clk_recalc_rate,
1373         .set_rate       = ddr_clk_set_rate,
1374         .round_rate     = ddr_clk_round_rate,
1375         .gate_idx       = CLK_GATE_DDRPHY,
1376         .clksel_con     = CRU_CLKSELS_CON(26),
1377         CRU_DIV_SET(0x3, 0, 4),
1378         CRU_SRC_SET(1, 8),
1379         CRU_PARENTS_SET(clk_ddr_parents),
1380 };
1381 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1382 {
1383         int ret;
1384
1385         ret = clk_set_rate_nolock(c->parent, rate);
1386         if (ret) {
1387                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1388                 return ret;
1389         }
1390         //set arm pll div 1
1391         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1392         return 0;
1393 }
1394 static unsigned long clk_core_get_rate(struct clk *c)
1395 {
1396         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1397         //c->parent->rate=c->parent->recalc(c->parent);
1398         return c->parent->rate / div;
1399 }
1400 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1401 {
1402         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1403         return clk_round_rate_nolock(clk->parent, rate) / div;
1404 }
1405
1406 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1407 {
1408
1409         u32 temp_div;
1410         struct clk *old_prt;
1411
1412         if(clk->parent == new_prt)
1413                 return 0;
1414         if (unlikely(!clk->parents))
1415                 return -EINVAL;
1416         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1417         //arm
1418         old_prt = clk->parent;
1419
1420         if(clk->parents[0] == new_prt) {
1421                 new_prt->set_rate(new_prt, 300 * MHZ);
1422                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1423         } else if(clk->parents[1] == new_prt) {
1424
1425                 if(new_prt->rate > old_prt->rate) {
1426                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1427                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1428                 }
1429                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1430                 new_prt->set_rate(new_prt, 300 * MHZ);
1431         } else
1432                 return -1;
1433
1434
1435         return 0;
1436
1437 }
1438
1439 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1440 {
1441         u32 temp_div;
1442         u32 old_aclk_div = 0, new_aclk_div;
1443         struct arm_clks_div_set *temp_clk_div;
1444         unsigned long arm_gpll_rate, arm_gpll_lpj;
1445         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1446         arm_gpll_rate = c->parent->rate / temp_div;
1447
1448         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1449         if(!temp_clk_div)
1450                 temp_clk_div = &arm_clk_div_tlb[4];
1451
1452         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1453         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1454         if(c->rate >= rate) {
1455                 arm_gpll_lpj = lpj_gpll / temp_div;
1456                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1457         }
1458
1459         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1460         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1461                         CRU_CLKSELS_CON(0));
1462         if((c->rate < rate)) {
1463                 arm_gpll_lpj = lpj_gpll / temp_div;
1464                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1465         }
1466         return 0;
1467 }
1468 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1469 {
1470         return c->parent->rate;
1471 }
1472 static struct clk clk_core_gpll_path = {
1473         .name           = "cpu_gpll_path",
1474         .parent         = &general_pll_clk,
1475         .recalc         = arm_core_gpll_clk_get_rate,
1476         .set_rate       = core_gpll_clk_set_rate,
1477         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1478 };
1479
1480
1481 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1482
1483 static struct clk clk_core = {
1484         .name           = "core",
1485         .parent         = &arm_pll_clk,
1486         .set_rate       = clk_core_set_rate,
1487         .recalc         = clk_core_get_rate,
1488         .round_rate     = core_clk_round_rate,
1489         .set_parent     = core_clksel_set_parent,
1490         .clksel_con     = CRU_CLKSELS_CON(0),
1491         CRU_DIV_SET(0x1f, 9, 32),
1492         CRU_SRC_SET(1, 8),
1493         CRU_PARENTS_SET(clk_core_parents),
1494 };
1495 GATE_CLK(l2c, clk_core, CLK_L2C);
1496 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1497 static unsigned long aclk_recalc(struct clk *clk)
1498 {
1499         unsigned long rate;
1500         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1501
1502         BUG_ON(div > 5);
1503         if (div >= 5)
1504                 div = 8;
1505         rate = clk->parent->rate / div;
1506         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1507
1508         return rate;
1509 };
1510 static struct clk core_periph = {
1511         .name           = "core_periph",
1512         .parent         = &clk_core,
1513         .gate_idx       = CLK_GATE_CORE_PERIPH,
1514         .recalc         = clksel_recalc_shift_2,
1515         .clksel_con     = CRU_CLKSELS_CON(0),
1516         CRU_DIV_SET(0x3, 6, 16),
1517 };
1518 static struct clk aclk_core = {
1519         .name           = "aclk_core",
1520         .parent         = &clk_core,
1521         .gate_idx       = CLK_GATE_ACLK_CORE,
1522         .recalc         = aclk_recalc,
1523         .clksel_con     = CRU_CLKSELS_CON(1),
1524         CRU_DIV_SET(0x7, 3, 8),
1525 };
1526
1527 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1528 static struct clk clk_cpu_div = {
1529         .name           = "cpu_div",
1530         .parent         = &arm_pll_clk,
1531         .set_rate       = clksel_set_rate_freediv,
1532         .recalc         = clksel_recalc_div,
1533         .clksel_con     = CRU_CLKSELS_CON(0),
1534         CRU_DIV_SET(0x1f, 0, 32),
1535         CRU_SRC_SET(1, 5),
1536         CRU_PARENTS_SET(clk_cpu_div_parents),
1537 };
1538
1539 static struct clk aclk_cpu = {
1540         .name           = "aclk_cpu",
1541         .parent         = &clk_cpu_div,
1542         .gate_idx       = CLK_GATE_ACLK_CPU,
1543 };
1544
1545 static struct clk hclk_cpu = {
1546         .name           = "hclk_cpu",
1547         .parent         = &aclk_cpu,
1548         .gate_idx       = CLK_GATE_HCLK_CPU,
1549         .recalc         = clksel_recalc_shift,
1550         .set_rate       = clksel_set_rate_shift,
1551         .clksel_con     = CRU_CLKSELS_CON(1),
1552         CRU_DIV_SET(0x3, 8, 4),
1553
1554 };
1555
1556 static struct clk pclk_cpu = {
1557         .name           = "pclk_cpu",
1558         .parent         = &aclk_cpu,
1559         .gate_idx       = CLK_GATE_PCLK_CPU,
1560         .recalc         = clksel_recalc_shift,
1561         .set_rate       = clksel_set_rate_shift,
1562         .clksel_con     = CRU_CLKSELS_CON(1),
1563         CRU_DIV_SET(0x3, 12, 8),
1564 };
1565
1566 static struct clk ahb2apb_cpu = {
1567         .name           = "ahb2apb",
1568         .parent         = &hclk_cpu,
1569         .recalc         = clksel_recalc_shift,
1570         .set_rate       = clksel_set_rate_shift,
1571         .clksel_con     = CRU_CLKSELS_CON(1),
1572         CRU_DIV_SET(0x3, 14, 4),
1573 };
1574
1575
1576 static struct clk atclk_cpu = {
1577         .name           = "atclk_cpu",
1578         .parent         = &pclk_cpu,
1579         .gate_idx       = CLK_GATE_ATCLK_CPU,
1580 };
1581
1582 /* GPU setting */
1583 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1584 {
1585         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1586         return clkset_rate_freediv_autosel_parents(clk, max_rate);
1587 };
1588
1589 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1590
1591 static struct clk aclk_gpu = {
1592         .name           = "aclk_gpu",
1593         .mode           = gate_mode,
1594         .recalc         = clksel_recalc_div,
1595         .round_rate     = clk_freediv_round_autosel_parents_rate,
1596         .set_rate       = clkset_rate_freediv_autosel_parents,
1597         .clksel_con     = CRU_CLKSELS_CON(34),
1598         .gate_idx       = CLK_GATE_ACLK_GPU,
1599         CRU_DIV_SET(0x1f, 0, 32),
1600         CRU_SRC_SET(0x1, 7),
1601         CRU_PARENTS_SET(aclk_gpu_parents),
1602 };
1603
1604 /* vcodec setting */
1605 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1606 {
1607         unsigned long rate = clk->parent->rate / 4;
1608         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1609         return rate;
1610 }
1611
1612 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1613
1614 static struct clk aclk_vepu = {
1615         .name           = "aclk_vepu",
1616         .parent         = &codec_pll_clk,
1617         .mode           = gate_mode,
1618         .recalc         = clksel_recalc_div,
1619         .set_rate       = clkset_rate_freediv_autosel_parents,
1620         .clksel_con     = CRU_CLKSELS_CON(32),
1621         .gate_idx       = CLK_GATE_ACLK_VEPU,
1622         CRU_DIV_SET(0x1f, 0, 32),
1623         CRU_SRC_SET(0x1, 7),
1624         CRU_PARENTS_SET(aclk_vepu_parents),
1625 };
1626
1627 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1628
1629 static struct clk aclk_vdpu = {
1630         .name           = "aclk_vdpu",
1631         .mode           = gate_mode,
1632         .recalc         = clksel_recalc_div,
1633         .set_rate       = clkset_rate_freediv_autosel_parents,
1634         .clksel_con     = CRU_CLKSELS_CON(32),
1635         .gate_idx       = CLK_GATE_ACLK_VDPU,
1636         CRU_DIV_SET(0x1f, 8, 32),
1637         CRU_SRC_SET(0x1, 15),
1638         CRU_PARENTS_SET(aclk_vdpu_parents),
1639 };
1640 static struct clk hclk_vepu = {
1641         .name           = "hclk_vepu",
1642         .parent         = &aclk_vepu,
1643         .mode           = gate_mode,
1644         .recalc         = clksel_recalc_vpu_hclk,
1645         .gate_idx       = CLK_GATE_HCLK_VEPU,
1646 };
1647
1648 static struct clk hclk_vdpu = {
1649         .name           = "hclk_vdpu",
1650         .parent         = &aclk_vdpu,
1651         .mode           = gate_mode,
1652         .recalc         = clksel_recalc_vpu_hclk,
1653         .gate_idx       = CLK_GATE_HCLK_VDPU,
1654 };
1655
1656 /* aclk lcdc setting */
1657 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1658
1659 static struct clk aclk_lcdc0_pre = {
1660         .name           = "aclk_lcdc0_pre",
1661         .parent         = &codec_pll_clk,
1662         .mode           = gate_mode,
1663         .recalc         = clksel_recalc_div,
1664         .set_rate       = clkset_rate_freediv_autosel_parents,
1665         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1666         .clksel_con     = CRU_CLKSELS_CON(31),
1667         CRU_DIV_SET(0x1f, 0, 32),
1668         CRU_SRC_SET(0x1, 7),
1669         CRU_PARENTS_SET(aclk_lcdc0_parents),
1670 };
1671
1672 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1673
1674 static struct clk aclk_lcdc1_pre = {
1675         .name           = "aclk_lcdc1_pre",
1676         .parent         = &codec_pll_clk,
1677         .mode           = gate_mode,
1678         .recalc         = clksel_recalc_div,
1679         .set_rate       = clkset_rate_freediv_autosel_parents,
1680         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1681         .clksel_con     = CRU_CLKSELS_CON(31),
1682         CRU_DIV_SET(0x1f, 8, 32),
1683         CRU_SRC_SET(0x1, 15),
1684         CRU_PARENTS_SET(aclk_lcdc1_parents),
1685 };
1686
1687 /* aclk/hclk/pclk periph setting */
1688 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1689
1690 static struct clk aclk_periph = {
1691         .name           = "aclk_periph",
1692         .parent         = &general_pll_clk,
1693         .mode           = gate_mode,
1694         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1695         .recalc         = clksel_recalc_div,
1696         .set_rate       = clksel_set_rate_freediv,
1697         .clksel_con     = CRU_CLKSELS_CON(10),
1698         CRU_DIV_SET(0x1f, 0, 32),
1699         CRU_SRC_SET(1, 15),
1700         CRU_PARENTS_SET(aclk_periph_parents),
1701 };
1702 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1703
1704 static struct clk pclk_periph = {
1705         .name           = "pclk_periph",
1706         .parent         = &aclk_periph,
1707         .mode           = gate_mode,
1708         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1709         .recalc         = clksel_recalc_shift,
1710         .set_rate       = clksel_set_rate_shift,
1711         .clksel_con     = CRU_CLKSELS_CON(10),
1712         CRU_DIV_SET(0x3, 12, 8),
1713 };
1714
1715 static struct clk hclk_periph = {
1716         .name           = "hclk_periph",
1717         .parent         = &aclk_periph,
1718         .mode           = gate_mode,
1719         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1720         .recalc         = clksel_recalc_shift,
1721         .set_rate       = clksel_set_rate_shift,
1722         .clksel_con     = CRU_CLKSELS_CON(10),
1723         CRU_DIV_SET(0x3, 8, 4),
1724 };
1725 /* dclk lcdc setting */
1726 // FIXME
1727 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1728 {
1729         u32 div, old_div;
1730         int i;
1731         unsigned long new_rate;
1732         int ret = 0;
1733
1734         if(clk->rate == rate)
1735                 return 0;
1736         for(i = 0; i < 2; i++) {
1737                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1738                 new_rate = clk->parents[i]->rate / div;
1739                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1740                         break;
1741                 }
1742         }
1743         if(i >= 2) {
1744                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1745                 return -1;
1746         }
1747
1748         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1749
1750         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1751                         clk->div_shift, clk->div_mask) + 1;
1752         if(div > old_div)
1753                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1754
1755         if(clk->parents[i] != clk->parent) {
1756                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1757         }
1758
1759         if (ret) {
1760                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1761                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1762                 return ret;
1763         }
1764         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1765         return 0;
1766 }
1767
1768 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1769 {
1770         if (rate == 27 * MHZ)
1771                 return clkset_rate_freediv_autosel_parents(clk, rate);
1772         else
1773                 return clkset_rate_evendiv_autosel_parents(clk, rate);
1774
1775 #if 0
1776         int ret = 0;
1777         struct clk *parent;
1778         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1779                 parent = clk->parents[1];
1780                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1781         } else {
1782                 parent = clk->parents[0];
1783         }
1784         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1785         //clk->name,rate,parent->name,clk->parent->name);
1786
1787         if(parent != clk->parents[1]) {
1788                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1789                 if (ret) {
1790                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1791                         return ret;
1792                 }
1793         }
1794         if (clk->parent != parent) {
1795                 ret = clk_set_parent_nolock(clk, parent);
1796                 if (ret) {
1797                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1798                         return ret;
1799                 }
1800         }
1801         return ret;
1802 #endif
1803 }
1804
1805 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1806 static struct clk dclk_lcdc0 = {
1807         .name           = "dclk_lcdc0",
1808         .mode           = gate_mode,
1809         .set_rate       = dclk_lcdc_set_rate,
1810         .recalc         = clksel_recalc_div,
1811         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1812         .clksel_con     = CRU_CLKSELS_CON(27),
1813         CRU_SRC_SET(0x1, 0),
1814         CRU_DIV_SET(0xff, 8, 256),
1815         CRU_PARENTS_SET(dclk_lcdc0_parents),
1816 };
1817
1818 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1819 static struct clk dclk_lcdc1 = {
1820         .name           = "dclk_lcdc1",
1821         .mode           = gate_mode,
1822         .set_rate       = dclk_lcdc_set_rate,
1823         .recalc         = clksel_recalc_div,
1824         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1825         .clksel_con     = CRU_CLKSELS_CON(28),
1826         CRU_SRC_SET(0x1, 0),
1827         CRU_DIV_SET(0xff, 8, 256),
1828         CRU_PARENTS_SET(dclk_lcdc1_parents),
1829 };
1830
1831 /* cif setting */
1832 // FIXME
1833 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1834 static struct clk cif_out_pll = {
1835         .name           = "cif_out_pll",
1836         .parent         = &general_pll_clk,
1837         .clksel_con     = CRU_CLKSELS_CON(29),
1838         CRU_SRC_SET(0x1, 0),
1839         CRU_PARENTS_SET(cifout_sel_pll_parents),
1840 };
1841
1842 static struct clk cif0_out_div = {
1843         .name           = "cif0_out_div",
1844         .parent         = &cif_out_pll,
1845         .mode           = gate_mode,
1846         .recalc         = clksel_recalc_div,
1847         .set_rate       = clksel_set_rate_freediv,
1848         .gate_idx       = CLK_GATE_CIF0_OUT,
1849         .clksel_con     = CRU_CLKSELS_CON(29),
1850         CRU_DIV_SET(0x1f, 1, 32),
1851 };
1852
1853 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1854 {
1855         int ret = 0;
1856         struct clk *parent;
1857
1858         if (rate == 24 * MHZ) {
1859                 parent = clk->parents[1];
1860         } else {
1861                 parent = clk->parents[0];
1862                 ret = clk_set_rate_nolock(parent, rate);
1863                 if (ret)
1864                         return ret;
1865         }
1866         if (clk->parent != parent)
1867                 ret = clk_set_parent_nolock(clk, parent);
1868
1869         return ret;
1870 }
1871
1872 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1873 static struct clk cif0_out = {
1874         .name           = "cif0_out",
1875         .parent         = &cif0_out_div,
1876         .set_rate       = cif_out_set_rate,
1877         .clksel_con     = CRU_CLKSELS_CON(29),
1878         CRU_SRC_SET(0x1, 7),
1879         CRU_PARENTS_SET(cif0_out_parents),
1880 };
1881
1882 static struct clk pclkin_cif0 = {
1883         .name           = "pclkin_cif0",
1884         .mode           = gate_mode,
1885         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1886 };
1887
1888 static struct clk inv_cif0 = {
1889         .name           = "inv_cif0",
1890         .parent         = &pclkin_cif0,
1891 };
1892
1893 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1894 static struct clk cif0_in = {
1895         .name           = "cif0_in",
1896         .parent         = &pclkin_cif0,
1897         .clksel_con     = CRU_CLKSELS_CON(30),
1898         CRU_SRC_SET(0x1, 8),
1899         CRU_PARENTS_SET(cif0_in_parents),
1900 };
1901
1902 /* i2s/spdif setting */
1903 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1904 static struct clk clk_i2s_pll = {
1905         .name           = "i2s_pll",
1906         .parent         = &general_pll_clk,
1907         .clksel_con     = CRU_CLKSELS_CON(2),
1908         CRU_SRC_SET(0x1, 15),
1909         CRU_PARENTS_SET(clk_i2s_div_parents),
1910 };
1911
1912 static struct clk clk_i2s0_div = {
1913         .name           = "i2s0_div",
1914         .parent         = &clk_i2s_pll,
1915         .mode           = gate_mode,
1916         .recalc         = clksel_recalc_div,
1917         .set_rate       = clksel_set_rate_freediv,
1918         .round_rate     = clksel_freediv_round_rate,
1919         .gate_idx       = CLK_GATE_I2S0_SRC,
1920         .clksel_con     = CRU_CLKSELS_CON(3),
1921         CRU_DIV_SET(0x7f, 0, 64),
1922 };
1923
1924 static struct clk clk_spdif_div = {
1925         .name           = "spdif_div",
1926         .parent         = &clk_i2s_pll,
1927         .recalc         = clksel_recalc_div,
1928         .set_rate       = clksel_set_rate_freediv,
1929         .round_rate     = clksel_freediv_round_rate,
1930         .mode           = gate_mode,
1931         .gate_idx       = CLK_GATE_SPDIF_SRC,
1932         .clksel_con     = CRU_CLKSELS_CON(5),
1933         CRU_DIV_SET(0x7f, 0, 64),
1934 };
1935 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1936 {
1937         u32 numerator, denominator;
1938         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1939         //clk->parent->parent
1940         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1941                                 &numerator, &denominator) == 0) {
1942                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1943                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1944                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1945         } else {
1946                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1947                 return -ENOENT;
1948         }
1949         return 0;
1950 }
1951
1952 static struct clk clk_i2s0_frac_div = {
1953         .name           = "i2s0_frac_div",
1954         .parent         = &clk_i2s0_div,
1955         .mode           = gate_mode,
1956         .gate_idx       = CLK_GATE_I2S0_FRAC,
1957         .recalc         = clksel_recalc_frac,
1958         .set_rate       = clk_i2s_fracdiv_set_rate,
1959         .clksel_con     = CRU_CLKSELS_CON(7),
1960 };
1961
1962 static struct clk clk_spdif_frac_div = {
1963         .name           = "spdif_frac_div",
1964         .parent         = &clk_spdif_div,
1965         .mode           = gate_mode,
1966         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1967         .recalc         = clksel_recalc_frac,
1968         .set_rate       = clk_i2s_fracdiv_set_rate,
1969         .clksel_con     = CRU_CLKSELS_CON(9),
1970 };
1971
1972 #define I2S_SRC_DIV     (0x0)
1973 #define I2S_SRC_FRAC    (0x1)
1974 #define I2S_SRC_12M     (0x2)
1975
1976 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1977 {
1978         int ret = -EINVAL;
1979         struct clk *parent;
1980
1981         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1982                 parent = clk->parents[I2S_SRC_12M];
1983         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1984                 parent = clk->parents[I2S_SRC_DIV];
1985         } else {
1986                 parent = clk->parents[I2S_SRC_FRAC];
1987         }
1988
1989         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1990                         clk->name, rate, parent->name, clk->parent->name);
1991
1992         if(parent != clk->parents[I2S_SRC_12M]) {
1993                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1994                 if (ret) {
1995                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1996                         return ret;
1997                 }
1998         }
1999
2000         if (clk->parent != parent) {
2001                 ret = clk_set_parent_nolock(clk, parent);
2002                 if (ret) {
2003                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2004                         return ret;
2005                 }
2006         }
2007
2008         return ret;
2009 };
2010
2011 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
2012
2013 static struct clk clk_i2s0 = {
2014         .name           = "i2s0",
2015         .set_rate       = i2s_set_rate,
2016         .clksel_con     = CRU_CLKSELS_CON(3),
2017         CRU_SRC_SET(0x3, 8),
2018         CRU_PARENTS_SET(clk_i2s0_parents),
2019 };
2020
2021 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
2022
2023 static struct clk clk_spdif = {
2024         .name           = "spdif",
2025         .parent         = &clk_spdif_frac_div,
2026         .set_rate       = i2s_set_rate,
2027         .clksel_con = CRU_CLKSELS_CON(5),
2028         CRU_SRC_SET(0x3, 8),
2029         CRU_PARENTS_SET(clk_spdif_parents),
2030 };
2031
2032 /* otgphy setting */
2033 GATE_CLK(otgphy0, xin24m, OTGPHY0);
2034 GATE_CLK(otgphy1, xin24m, OTGPHY1);
2035
2036 static struct clk clk_otgphy0_480m = {
2037         .name           = "otgphy0_480m",
2038         .parent         = &clk_otgphy0,
2039 };
2040 static struct clk clk_otgphy1_480m = {
2041         .name           = "otgphy1_480m",
2042         .parent         = &clk_otgphy1,
2043 };
2044
2045 /* hsicphy setting */
2046 #ifdef ARCH_RK31
2047 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
2048 static struct clk clk_hsicphy_480m = {
2049         .name           = "hsicphy_480m",
2050         .parent         = &clk_otgphy0_480m,
2051         .clksel_con      = CRU_CLKSELS_CON(30),
2052         CRU_SRC_SET(0x3, 0),
2053         CRU_PARENTS_SET(clk_hsicphy_parents),
2054 };
2055 static struct clk clk_hsicphy_12m = {
2056         .name           = "hsicphy_12m",
2057         .parent         = &clk_hsicphy_480m,
2058         .clksel_con     = CRU_CLKSELS_CON(11),
2059         CRU_DIV_SET(0x3f, 8, 64),
2060 };
2061 #endif
2062
2063 /* mac and rmii setting */
2064 // FIXME
2065 static struct clk rmii_clkin = {
2066         .name           = "rmii_clkin",
2067 };
2068 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
2069 static struct clk clk_mac_pll_div = {
2070         .name           = "mac_pll_div",
2071         .parent         = &general_pll_clk,
2072         .mode           = gate_mode,
2073         .gate_idx       = CLK_GATE_MAC_SRC,
2074         .recalc         = clksel_recalc_div,
2075         .set_rate       = clksel_set_rate_freediv,
2076         .clksel_con     = CRU_CLKSELS_CON(21),
2077         CRU_DIV_SET(0x1f, 8, 32),
2078         CRU_SRC_SET(0x1, 0),
2079         CRU_PARENTS_SET(clk_mac_ref_div_parents),
2080 };
2081
2082 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
2083 {
2084         if(clk->parent == clk->parents[1]) {
2085                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
2086                 return -ENOENT;
2087         } else if(clk->parent == clk->parents[0]) {
2088                 return clk_set_rate_nolock(clk->parents[0], rate);
2089         }
2090         return -ENOENT;
2091 }
2092
2093 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
2094
2095 static struct clk clk_mac_ref = {
2096         .name           = "mac_ref",
2097         .parent         = &clk_mac_pll_div,
2098         .set_rate       = clksel_mac_ref_set_rate,
2099         .clksel_con     = CRU_CLKSELS_CON(21),
2100         CRU_SRC_SET(0x1, 4),
2101         CRU_PARENTS_SET(clk_mac_ref_parents),
2102 };
2103
2104 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
2105 {
2106         return clk_set_parent_nolock(clk->parent, parent);
2107 }
2108
2109 static struct clk clk_mii_tx = {
2110         .name           = "mii_tx",
2111         .parent         = &clk_mac_ref,
2112         //.set_parent   = clk_set_mii_tx_parent,
2113         .mode           = gate_mode,
2114         .gate_idx       = CLK_GATE_MAC_LBTEST,
2115 };
2116
2117 /* hsadc and saradc */
2118 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
2119 static struct clk clk_hsadc_pll_div = {
2120         .name           = "hsadc_pll_div",
2121         .parent         = &general_pll_clk,
2122         .mode           = gate_mode,
2123         .gate_idx       = CLK_GATE_HSADC_SRC,
2124         .recalc         = clksel_recalc_div,
2125         .round_rate     = clk_freediv_round_autosel_parents_rate,
2126         .set_rate       = clkset_rate_freediv_autosel_parents,
2127         //.round_rate   = clksel_freediv_round_rate,
2128         //.set_rate     = clksel_set_rate_freediv,
2129         .clksel_con = CRU_CLKSELS_CON(22),
2130         CRU_DIV_SET(0xff, 8, 256),
2131         CRU_SRC_SET(0x1, 0),
2132         CRU_PARENTS_SET(clk_hsadc_pll_parents),
2133 };
2134 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2135 {
2136         u32 numerator, denominator;
2137         //        clk_hsadc_pll_div->gpll/cpll
2138         //clk->parent->parent
2139         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2140                                 &numerator, &denominator) == 0) {
2141                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2142
2143                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2144
2145                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2146         } else {
2147                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2148                 return -ENOENT;
2149         }
2150         return 0;
2151 }
2152 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2153 {
2154         u32 numerator, denominator;
2155         u32 i, ret = 0;
2156         //        clk_hsadc_pll_div->gpll/cpll
2157         //clk->parent->parent
2158         for(i = 0; i < 2; i++) {
2159                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2160                                         &numerator, &denominator) == 0)
2161                         break;
2162         }
2163         if(i >= 2)
2164                 return -ENOENT;
2165
2166         if(clk->parent->parent != clk->parent->parents[i])
2167                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2168         if(ret == 0) {
2169                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2170
2171                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2172
2173                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2174         } else {
2175                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2176                 return -ENOENT;
2177         }
2178         return 0;
2179 }
2180
2181 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2182 {
2183         u32 numerator, denominator;
2184
2185         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2186         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2187                                 &numerator, &denominator) == 0)
2188                 return rate;
2189
2190         return 0;
2191 }
2192 static struct clk clk_hsadc_frac_div = {
2193         .name           = "hsadc_frac_div",
2194         .parent         = &clk_hsadc_pll_div,
2195         .mode           = gate_mode,
2196         .recalc         = clksel_recalc_frac,
2197         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2198         .round_rate     = clk_hsadc_fracdiv_round_rate,
2199         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
2200         .clksel_con     = CRU_CLKSELS_CON(23),
2201 };
2202
2203 #define HSADC_SRC_DIV 0x0
2204 #define HSADC_SRC_FRAC 0x1
2205 #define HSADC_SRC_EXT 0x2
2206 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2207 {
2208         int ret = -EINVAL;
2209         struct clk *parent;
2210
2211         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2212                 CLKDATA_DBG("hsadc clk is form ext\n");
2213                 return 0;
2214         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2215                 parent = clk->parents[HSADC_SRC_DIV];
2216         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2217                 parent = clk->parents[HSADC_SRC_FRAC];
2218         } else
2219                 parent = clk->parents[HSADC_SRC_DIV];
2220
2221         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2222                         clk->name, rate, parent->name, clk->parent->name);
2223
2224         ret = clk_set_rate_nolock(parent, rate);
2225         if (ret) {
2226                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2227                 return ret;
2228         }
2229         if (clk->parent != parent) {
2230                 ret = clk_set_parent_nolock(clk, parent);
2231                 if (ret) {
2232                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2233                         return ret;
2234                 }
2235         }
2236         return ret;
2237 }
2238
2239 static struct clk clk_hsadc_ext = {
2240         .name           = "hsadc_ext",
2241 };
2242
2243 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2244 static struct clk clk_hsadc_out = {
2245         .name           = "hsadc_out",
2246         .parent         = &clk_hsadc_pll_div,
2247         .set_rate       = clk_hsadc_set_rate,
2248         .clksel_con     = CRU_CLKSELS_CON(22),
2249         CRU_SRC_SET(0x3, 4),
2250         CRU_PARENTS_SET(clk_hsadc_out_parents),
2251 };
2252 static struct clk clk_hsadc_out_inv = {
2253         .name           = "hsadc_out_inv",
2254         .parent         = &clk_hsadc_out,
2255 };
2256
2257 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2258 static struct clk clk_hsadc = {
2259         .name           = "hsadc",
2260         .parent         = &clk_hsadc_out,
2261         .clksel_con     = CRU_CLKSELS_CON(22),
2262         CRU_SRC_SET(0x1, 7),
2263         CRU_PARENTS_SET(clk_hsadc_parents),
2264 };
2265
2266 static struct clk clk_saradc = {
2267         .name           = "saradc",
2268         .parent         = &xin24m,
2269         .mode           = gate_mode,
2270         .recalc         = clksel_recalc_div,
2271         .set_rate       = clksel_set_rate_freediv,
2272         .gate_idx       = CLK_GATE_SARADC_SRC,
2273         .clksel_con     = CRU_CLKSELS_CON(24),
2274         CRU_DIV_SET(0xff, 8, 256),
2275 };
2276
2277 /* smc setting */
2278 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2279 static struct clk clkn_smc = {
2280         .name           = "smc_inv",
2281         .parent         = &clk_smc,
2282 };
2283
2284 /* spi setting */
2285 static struct clk clk_spi0 = {
2286         .name           = "spi0",
2287         .parent         = &pclk_periph,
2288         .mode           = gate_mode,
2289         .recalc         = clksel_recalc_div,
2290         .set_rate       = clksel_set_rate_freediv,
2291         .gate_idx       = CLK_GATE_SPI0_SRC,
2292         .clksel_con     = CRU_CLKSELS_CON(25),
2293         CRU_DIV_SET(0x7f, 0, 128),
2294 };
2295
2296 static struct clk clk_spi1 = {
2297         .name           = "spi1",
2298         .parent         = &pclk_periph,
2299         .mode           = gate_mode,
2300         .recalc         = clksel_recalc_div,
2301         .set_rate       = clksel_set_rate_freediv,
2302         .gate_idx       = CLK_GATE_SPI1_SRC,
2303         .clksel_con     = CRU_CLKSELS_CON(25),
2304         CRU_DIV_SET(0x7f, 8, 128),
2305 };
2306
2307 /* sdmmc/sdio/emmc setting */
2308 static struct clk clk_sdmmc = {
2309         .name           = "sdmmc",
2310         .parent         = &hclk_periph,
2311         .mode           = gate_mode,
2312         .recalc         = clksel_recalc_div,
2313         .set_rate       = clksel_set_rate_even,
2314         .gate_idx       = CLK_GATE_MMC0_SRC,
2315         .clksel_con     = CRU_CLKSELS_CON(11),
2316         CRU_DIV_SET(0x3f, 0, 64),
2317 };
2318
2319 static struct clk clk_sdio = {
2320         .name           = "sdio",
2321         .parent         = &hclk_periph,
2322         .mode           = gate_mode,
2323         .recalc         = clksel_recalc_div,
2324         .set_rate       = clksel_set_rate_even,
2325         .gate_idx       = CLK_GATE_SDIO_SRC,
2326         .clksel_con     = CRU_CLKSELS_CON(12),
2327         CRU_DIV_SET(0x3f, 0, 64),
2328
2329 };
2330
2331 static struct clk clk_emmc = {
2332         .name           = "emmc",
2333         .parent         = &hclk_periph,
2334         .mode           = gate_mode,
2335         .recalc         = clksel_recalc_div,
2336         .set_rate       = clksel_set_rate_freediv,
2337         .gate_idx       = CLK_GATE_EMMC_SRC,
2338         .clksel_con     = CRU_CLKSELS_CON(12),
2339         CRU_DIV_SET(0x3f, 8, 64),
2340 };
2341
2342 /* uart setting */
2343 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2344 static struct clk clk_uart_pll = {
2345         .name           = "uart_pll",
2346         .parent         = &general_pll_clk,
2347         .clksel_con     = CRU_CLKSELS_CON(12),
2348         CRU_SRC_SET(0x1, 15),
2349         CRU_PARENTS_SET(clk_uart_src_parents),
2350 };
2351 static struct clk clk_uart0_div = {
2352         .name           = "uart0_div",
2353         .parent         = &clk_uart_pll,
2354         .mode           = gate_mode,
2355         .gate_idx       = CLK_GATE_UART0_SRC,
2356         .recalc         = clksel_recalc_div,
2357         .set_rate       = clksel_set_rate_freediv,
2358         .round_rate     = clksel_freediv_round_rate,
2359         .clksel_con     = CRU_CLKSELS_CON(13),
2360         CRU_DIV_SET(0x7f, 0, 64),
2361 };
2362 static struct clk clk_uart1_div = {
2363         .name           = "uart1_div",
2364         .parent         = &clk_uart_pll,
2365         .mode           = gate_mode,
2366         .gate_idx       = CLK_GATE_UART1_SRC,
2367         .recalc         = clksel_recalc_div,
2368         .round_rate     = clksel_freediv_round_rate,
2369         .set_rate       = clksel_set_rate_freediv,
2370         .clksel_con     = CRU_CLKSELS_CON(14),
2371         CRU_DIV_SET(0x7f, 0, 64),
2372 };
2373
2374 static struct clk clk_uart2_div = {
2375         .name           = "uart2_div",
2376         .parent         = &clk_uart_pll,
2377         .mode           = gate_mode,
2378         .gate_idx       = CLK_GATE_UART2_SRC,
2379         .recalc         = clksel_recalc_div,
2380         .round_rate     = clksel_freediv_round_rate,
2381         .set_rate       = clksel_set_rate_freediv,
2382         .clksel_con     = CRU_CLKSELS_CON(15),
2383         CRU_DIV_SET(0x7f, 0, 64),
2384 };
2385
2386 static struct clk clk_uart3_div = {
2387         .name           = "uart3_div",
2388         .parent         = &clk_uart_pll,
2389         .mode           = gate_mode,
2390         .gate_idx       = CLK_GATE_UART3_SRC,
2391         .recalc         = clksel_recalc_div,
2392         .round_rate     = clksel_freediv_round_rate,
2393         .set_rate       = clksel_set_rate_freediv,
2394         .clksel_con     = CRU_CLKSELS_CON(16),
2395         CRU_DIV_SET(0x7f, 0, 64),
2396 };
2397 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2398 {
2399         u32 numerator, denominator;
2400         //clk_uart0_div->clk_uart_pll->gpll/cpll
2401         //clk->parent->parent
2402         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2403                                 &numerator, &denominator) == 0) {
2404                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2405
2406                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2407
2408                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2409         } else {
2410                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2411                 return -ENOENT;
2412         }
2413         return 0;
2414 }
2415
2416 static struct clk clk_uart0_frac_div = {
2417         .name           = "uart0_frac_div",
2418         .parent         = &clk_uart0_div,
2419         .mode           = gate_mode,
2420         .recalc         = clksel_recalc_frac,
2421         .set_rate       = clk_uart_fracdiv_set_rate,
2422         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2423         .clksel_con     = CRU_CLKSELS_CON(17),
2424 };
2425 static struct clk clk_uart1_frac_div = {
2426         .name           = "uart1_frac_div",
2427         .parent         = &clk_uart1_div,
2428         .mode           = gate_mode,
2429         .recalc         = clksel_recalc_frac,
2430         .set_rate       = clk_uart_fracdiv_set_rate,
2431         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2432         .clksel_con     = CRU_CLKSELS_CON(18),
2433 };
2434 static struct clk clk_uart2_frac_div = {
2435         .name           = "uart2_frac_div",
2436         .mode           = gate_mode,
2437         .parent         = &clk_uart2_div,
2438         .recalc         = clksel_recalc_frac,
2439         .set_rate       = clk_uart_fracdiv_set_rate,
2440         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2441         .clksel_con     = CRU_CLKSELS_CON(19),
2442 };
2443 static struct clk clk_uart3_frac_div = {
2444         .name           = "uart3_frac_div",
2445         .parent         = &clk_uart3_div,
2446         .mode           = gate_mode,
2447         .recalc         = clksel_recalc_frac,
2448         .set_rate       = clk_uart_fracdiv_set_rate,
2449         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2450         .clksel_con     = CRU_CLKSELS_CON(20),
2451 };
2452
2453 #define UART_SRC_DIV 0
2454 #define UART_SRC_FRAC 1
2455 #define UART_SRC_24M 2
2456
2457 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2458 {
2459         int ret = 0;
2460         struct clk *parent;
2461
2462         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2463                 parent = clk->parents[UART_SRC_24M];
2464         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2465                 parent = clk->parents[UART_SRC_DIV];
2466         } else {
2467                 parent = clk->parents[UART_SRC_FRAC];
2468         }
2469
2470         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2471                         clk->name, rate, parent->name, clk->parent->name);
2472
2473         if(parent != clk->parents[UART_SRC_24M]) {
2474                 ret = clk_set_rate_nolock(parent, rate);
2475                 if (ret) {
2476                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2477                         return ret;
2478                 }
2479         }
2480
2481         if (clk->parent != parent) {
2482                 ret = clk_set_parent_nolock(clk, parent);
2483                 if (ret) {
2484                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2485                         return ret;
2486                 }
2487         }
2488
2489         return ret;
2490 }
2491
2492 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2493 static struct clk clk_uart0 = {
2494         .name           = "uart0",
2495         .set_rate       = clk_uart_set_rate,
2496         .clksel_con     = CRU_CLKSELS_CON(13),
2497         CRU_SRC_SET(0x3, 8),
2498         CRU_PARENTS_SET(clk_uart0_parents),
2499 };
2500
2501 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2502 static struct clk clk_uart1 = {
2503         .name           = "uart1",
2504         .set_rate       = clk_uart_set_rate,
2505         .clksel_con     = CRU_CLKSELS_CON(14),
2506         CRU_SRC_SET(0x3, 8),
2507         CRU_PARENTS_SET(clk_uart1_parents),
2508 };
2509
2510 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2511 static struct clk clk_uart2 = {
2512         .name           = "uart2",
2513         .set_rate       = clk_uart_set_rate,
2514         .clksel_con     = CRU_CLKSELS_CON(15),
2515         CRU_SRC_SET(0x3, 8),
2516         CRU_PARENTS_SET(clk_uart2_parents),
2517 };
2518 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2519 static struct clk clk_uart3 = {
2520         .name           = "uart3",
2521         .set_rate       = clk_uart_set_rate,
2522         .clksel_con     = CRU_CLKSELS_CON(16),
2523         CRU_SRC_SET(0x3, 8),
2524         CRU_PARENTS_SET(clk_uart3_parents),
2525 };
2526
2527 /* timer setting */
2528 GATE_CLK(timer0, xin24m, TIMER0);
2529 GATE_CLK(timer1, xin24m, TIMER1);
2530 GATE_CLK(timer2, xin24m, TIMER2);
2531 GATE_CLK(timer3, xin24m, TIMER3);
2532 GATE_CLK(timer4, xin24m, TIMER4);
2533 GATE_CLK(timer5, xin24m, TIMER5);
2534 GATE_CLK(timer6, xin24m, TIMER6);
2535
2536 /*********************power domain*******************************/
2537 #if 1
2538 #ifdef RK30_CLK_OFFBOARD_TEST
2539 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2540 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2541 #else
2542 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2543 #define _pmu_set_power_domain pmu_set_power_domain
2544 #endif
2545
2546 static int pd_video_mode(struct clk *clk, int on)
2547 {
2548         u32 gate[3];
2549         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2550         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2551         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2552         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2553         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2554         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2555         pmu_set_power_domain(PD_VIDEO, on);
2556         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2557         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2558         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2559         return 0;
2560 }
2561
2562 static struct clk pd_video = {
2563         .name   = "pd_video",
2564         .flags  = IS_PD,
2565         .mode   = pd_video_mode,
2566         .gate_idx       = PD_VIDEO,
2567 };
2568 static int pd_display_mode(struct clk *clk, int on)
2569 {
2570         u32 gate[10];
2571         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2572         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2573         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2574         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2575         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2576         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2577         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2578         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2579         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2580         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2581         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2582         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2583         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2584         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2585         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2586         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2587         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2588         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2589         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2590         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2591         pmu_set_power_domain(PD_VIO, on);
2592         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2593         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2594         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2595         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2596         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2597         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2598         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2599         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2600         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2601         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2602         return 0;
2603 }
2604
2605 static struct clk pd_display = {
2606         .name   = "pd_vio",
2607         .flags  = IS_PD,
2608         .mode   = pd_display_mode,
2609         .gate_idx       = PD_VIO,
2610 };
2611 static struct clk pd_lcdc0 = {
2612         .parent = &pd_display,
2613         .name   = "pd_lcdc0",
2614 };
2615 static struct clk pd_lcdc1 = {
2616         .parent = &pd_display,
2617         .name   = "pd_lcdc1",
2618 };
2619 static struct clk pd_cif0 = {
2620         .parent = &pd_display,
2621         .name   = "pd_cif0",
2622 };
2623 static struct clk pd_rga = {
2624         .parent = &pd_display,
2625         .name   = "pd_rga",
2626 };
2627 static struct clk pd_ipp = {
2628         .parent = &pd_display,
2629         .name   = "pd_ipp",
2630 };
2631 static struct clk pd_hdmi = {
2632         .parent = &pd_display,
2633         .name   = "pd_hdmi",
2634 };
2635
2636
2637 static int pd_gpu_mode(struct clk *clk, int on)
2638 {
2639         u32 gate[3];
2640         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2641         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2642         pmu_set_power_domain(PD_GPU, on);
2643         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2644         return 0;
2645 }
2646
2647 static struct clk pd_gpu = {
2648         .name   = "pd_gpu",
2649         .flags  = IS_PD,
2650         .mode   = pd_gpu_mode,
2651         .gate_idx       = PD_GPU,
2652 };
2653
2654 static int pm_off_mode(struct clk *clk, int on)
2655 {
2656         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2657         return 0;
2658 }
2659 static struct clk pd_peri = {
2660         .name   = "pd_peri",
2661         .flags  = IS_PD,
2662         .mode   = pm_off_mode,
2663         .gate_idx       = PD_PERI,
2664 };
2665
2666
2667 #define PD_CLK(name) \
2668 {\
2669         .dev_id = NULL,\
2670         .con_id = #name,\
2671         .clk = &name,\
2672 }
2673
2674 #endif
2675 /************************rk30 fixed div clock****************************************/
2676
2677 /*************************aclk_cpu***********************/
2678
2679 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2680 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2681 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2682
2683 /*************************hclk_cpu***********************/
2684
2685 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2686 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2687 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2688 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2689 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2690 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2691 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2692 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2693 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2694 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2695 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2696 GATE_CLK(hclk_imem0,    hclk_cpu,       HCLK_IMEM0);
2697 GATE_CLK(hclk_imem1,    hclk_cpu,       HCLK_IMEM1);
2698
2699 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2700 GATE_CLK(pclk_uart0,    ahb2apb_cpu, PCLK_UART0);
2701 GATE_CLK(pclk_uart1,    ahb2apb_cpu, PCLK_UART1);
2702 /*************************pclk_cpu***********************/
2703 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2704 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2705 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2706 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2707 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2708 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2709 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2710 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2711 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2712 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2713 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2714 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2715 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2716 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2717 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2718
2719 /*************************aclk_periph***********************/
2720
2721 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2722 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2723 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2724 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2725 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2726 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2727
2728 /*************************hclk_periph***********************/
2729 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2730 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2731 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2732 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2733 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2734 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2735 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2736 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2737 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2738 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2739 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2740 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2741 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2742 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2743 /*************************pclk_periph***********************/
2744 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2745 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2746 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2747 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2748 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2749 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2750 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2751 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2752 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2753 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2754 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2755 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2756 /*************************aclk_lcdc0***********************/
2757
2758 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2759 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2760 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2761 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2762
2763 /*************************aclk_lcdc0***********************/
2764
2765 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2766 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2767 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2768
2769
2770 #if 1
2771 #define CLK(dev, con, ck) \
2772 {\
2773         .dev_id = dev,\
2774         .con_id = con,\
2775         .clk = ck,\
2776 }
2777
2778
2779 #define CLK1(name) \
2780 {\
2781         .dev_id = NULL,\
2782         .con_id = #name,\
2783         .clk = &clk_##name,\
2784 }
2785
2786 #endif
2787
2788 static struct clk_lookup clks[] = {
2789         CLK(NULL, "xin24m", &xin24m),
2790         //CLK(NULL, "xin27m", &xin27m),
2791         CLK(NULL, "xin12m", &clk_12m),
2792         CLK(NULL, "arm_pll", &arm_pll_clk),
2793         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2794         CLK(NULL, "codec_pll", &codec_pll_clk),
2795         CLK(NULL, "general_pll", &general_pll_clk),
2796
2797         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2798         CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2799
2800         CLK(NULL, "ddr", &clk_ddr),
2801         CLK(NULL, "cpu", &clk_core),
2802         CLK1(l2c),
2803         CLK1(core_dbg),
2804         CLK("smp_twd", NULL, &core_periph),
2805         CLK(NULL, "aclk_core", &aclk_core),
2806
2807         CLK(NULL, "logic", &clk_cpu_div),
2808         CLK(NULL, "aclk_cpu", &aclk_cpu),
2809         CLK(NULL, "pclk_cpu", &pclk_cpu),
2810         CLK(NULL, "atclk_cpu", &atclk_cpu),
2811         CLK(NULL, "hclk_cpu", &hclk_cpu),
2812         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2813
2814         CLK(NULL, "gpu",        &aclk_gpu),
2815
2816         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2817         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2818         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2819         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2820
2821         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2822         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2823
2824         CLK(NULL, "aclk_periph", &aclk_periph),
2825         CLK(NULL, "pclk_periph", &pclk_periph),
2826         CLK(NULL, "hclk_periph", &hclk_periph),
2827
2828         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2829         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2830
2831         CLK(NULL, "cif_out_pll", &cif_out_pll),
2832         CLK(NULL, "cif0_out_div", &cif0_out_div),
2833         CLK(NULL, "cif0_out", &cif0_out),
2834
2835         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2836         CLK(NULL, "inv_cif0", &inv_cif0),
2837         CLK(NULL, "cif0_in", &cif0_in),
2838
2839         CLK1(i2s_pll),
2840         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2841         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2842         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2843
2844         // actually no i2s1
2845         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2846         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2847         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2848
2849
2850         CLK1(spdif_div),
2851         CLK1(spdif_frac_div),
2852         CLK1(spdif),
2853
2854         CLK1(otgphy0),
2855         CLK1(otgphy1),
2856         CLK1(otgphy0_480m),
2857         CLK1(otgphy1_480m),
2858         CLK1(hsicphy_480m),
2859         CLK1(hsicphy_12m),
2860
2861         CLK(NULL, "rmii_clkin", &rmii_clkin),
2862         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2863         CLK1(mac_ref),
2864         CLK1(mii_tx),
2865
2866         CLK1(hsadc_pll_div),
2867         CLK1(hsadc_frac_div),
2868         CLK1(hsadc_ext),
2869         CLK1(hsadc_out),
2870         CLK1(hsadc_out_inv),
2871         CLK1(hsadc),
2872
2873         CLK1(saradc),
2874
2875         CLK1(smc),
2876         CLK(NULL, "smc_inv",    &clkn_smc),
2877
2878         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2879         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2880
2881         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2882         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2883         CLK1(emmc),
2884
2885         CLK1(uart_pll),
2886         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2887         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2888         CLK("rk_serial.0", "uart", &clk_uart0),
2889         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2890         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2891         CLK("rk_serial.1", "uart", &clk_uart1),
2892         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2893         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2894         CLK("rk_serial.2", "uart", &clk_uart2),
2895         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2896         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2897         CLK("rk_serial.3", "uart", &clk_uart3),
2898
2899         CLK1(timer0),
2900         CLK1(timer1),
2901         CLK1(timer2),
2902         CLK1(timer3),
2903         CLK1(timer4),
2904         CLK1(timer5),
2905         CLK1(timer6),
2906
2907         /*************************aclk_cpu***********************/
2908         CLK1(dma1),
2909         CLK1(intmem),
2910         CLK1(aclk_strc_sys),
2911
2912         /*************************hclk_cpu***********************/
2913         CLK1(rom),
2914         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2915         // actually no i2s1
2916         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2917         CLK1(hclk_spdif),
2918         CLK1(hclk_cpubus),
2919         CLK1(hclk_ahb2apb),
2920         CLK1(hclk_vio_bus),
2921         CLK1(hclk_lcdc0),
2922         CLK1(hclk_lcdc1),
2923         CLK1(hclk_cif0),
2924         CLK1(hclk_ipp),
2925         CLK1(hclk_rga),
2926         CLK1(hclk_imem0),
2927         CLK1(hclk_imem1),
2928
2929         /*************************pclk_cpu***********************/
2930         CLK1(pwm01),
2931         CLK1(pclk_timer0),
2932         CLK1(pclk_timer2),
2933         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2934         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2935         CLK1(gpio0),
2936         CLK1(gpio1),
2937         CLK1(gpio2),
2938         CLK1(efuse),
2939         CLK1(tzpc),
2940         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2941         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2942         CLK1(pclk_ddrupctl),
2943         CLK1(pclk_ddrpubl),
2944         CLK1(dbg),
2945         CLK1(grf),
2946         CLK1(pmu),
2947
2948         /*************************aclk_periph***********************/
2949         CLK1(dma2),
2950         CLK1(aclk_smc),
2951         CLK1(aclk_gps),
2952         CLK1(aclk_peri_niu),
2953         CLK1(aclk_cpu_peri),
2954         CLK1(aclk_peri_axi_matrix),
2955
2956         /*************************hclk_periph***********************/
2957         CLK1(hclk_peri_axi_matrix),
2958         CLK1(hclk_peri_ahb_arbi),
2959         CLK1(hclk_emem_peri),
2960         CLK1(hclk_mac),
2961         CLK1(nandc),
2962         CLK1(hclk_usb_peri),
2963         CLK1(hclk_otg0),
2964         CLK1(hclk_otg1),
2965         CLK1(hclk_hsic),
2966         CLK1(hclk_hsadc),
2967         CLK1(hclk_pidfilter),
2968         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2969         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2970         CLK1(hclk_emmc),
2971
2972         /*************************pclk_periph***********************/
2973         CLK1(pclk_peri_axi_matrix),
2974         CLK1(pwm23),
2975         CLK1(wdt),
2976         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2977         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2978         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2979         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2980         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2981         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2982         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2983         CLK1(gpio3),
2984         CLK1(pclk_saradc),
2985
2986         /*************************aclk_lcdc0***********************/
2987         CLK1(aclk_vio0),
2988         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2989         CLK1(aclk_cif0),
2990         CLK1(aclk_ipp),
2991
2992         /*************************aclk_lcdc1***********************/
2993         CLK1(aclk_vio1),
2994         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2995         CLK1(aclk_rga),
2996         /************************power domain**********************/
2997
2998         PD_CLK(pd_peri),
2999         PD_CLK(pd_display),
3000         PD_CLK(pd_lcdc0),
3001         PD_CLK(pd_lcdc1),
3002         PD_CLK(pd_cif0),
3003         //PD_CLK(pd_cif1),
3004         PD_CLK(pd_rga),
3005         PD_CLK(pd_ipp),
3006         //PD_CLK(pd_video),
3007         PD_CLK(pd_gpu),
3008         //PD_CLK(pd_dbg),
3009 };
3010 static void __init rk30_init_enable_clocks(void)
3011 {
3012         #if 0
3013         //clk_enable_nolock(&xin24m);
3014         //clk_enable_nolock(&clk_12m);
3015         //clk_enable_nolock(&arm_pll_clk);
3016         //clk_enable_nolock(&ddr_pll_clk);
3017         //clk_enable_nolock(&codec_pll_clk);
3018         //clk_enable_nolock(&general_pll_clk);
3019         #endif
3020         clk_enable_nolock(&clk_ddr);
3021         //clk_enable_nolock(&clk_core);
3022         clk_enable_nolock(&clk_cpu_div);
3023         clk_enable_nolock(&clk_core_gpll_path);
3024         clk_enable_nolock(&clk_l2c);
3025         clk_enable_nolock(&clk_core_dbg);
3026         clk_enable_nolock(&core_periph);
3027         clk_enable_nolock(&aclk_core);
3028         //clk_enable_nolock(&aclk_cpu);
3029         //clk_enable_nolock(&pclk_cpu);
3030         clk_enable_nolock(&atclk_cpu);
3031         //clk_enable_nolock(&hclk_cpu);
3032         clk_enable_nolock(&ahb2apb_cpu);
3033         #if 0
3034          clk_enable_nolock(&clk_gpu);
3035          clk_enable_nolock(&aclk_gpu);
3036          clk_enable_nolock(&aclk_gpu_slv);
3037          clk_enable_nolock(&aclk_gpu_mst);
3038
3039          clk_enable_nolock(&aclk_vepu);
3040          clk_enable_nolock(&hclk_vepu);
3041          clk_enable_nolock(&aclk_vdpu);
3042          clk_enable_nolock(&hclk_vdpu);
3043
3044          clk_enable_nolock(&aclk_lcdc0_pre);
3045          clk_enable_nolock(&aclk_lcdc1_pre);
3046
3047          clk_enable_nolock(&aclk_periph);
3048         clk_enable_nolock(&pclk_periph);
3049         clk_enable_nolock(&hclk_periph);
3050         #endif
3051         #if 0
3052          clk_enable_nolock(&dclk_lcdc0);
3053          clk_enable_nolock(&dclk_lcdc1);
3054
3055          clk_enable_nolock(&cif_out_pll);
3056          clk_enable_nolock(&cif0_out_div);
3057
3058          clk_enable_nolock(&cif0_out);
3059          clk_enable_nolock(&pclkin_cif0);
3060          clk_enable_nolock(&inv_cif0);
3061          clk_enable_nolock(&cif0_in);
3062
3063          clk_enable_nolock(&clk_i2s_pll);
3064          clk_enable_nolock(&clk_i2s0_div);
3065          clk_enable_nolock(&clk_i2s0_frac_div);
3066          clk_enable_nolock(&clk_i2s0);
3067
3068           actually no i2s1
3069          clk_enable_nolock(&clk_i2s0_div);
3070          clk_enable_nolock(&clk_i2s0_frac_div);
3071          clk_enable_nolock(&clk_i2s0);
3072
3073         clk_enable_nolock(&clk_spdif_div);
3074         clk_enable_nolock(&clk_spdif_frac_div);
3075         clk_enable_nolock(&clk_spdif);
3076         #endif
3077         #if 0
3078         clk_enable_nolock(&clk_otgphy0);
3079         clk_enable_nolock(&clk_otgphy1);
3080         clk_enable_nolock(&clk_otgphy0_480m);
3081         clk_enable_nolock(&clk_otgphy1_480m);
3082         clk_enable_nolock(&clk_hsicphy_480m);
3083         clk_enable_nolock(&clk_hsicphy_12m);
3084         #endif
3085
3086         #if 0
3087         clk_enable_nolock(&rmii_clkin);
3088         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
3089         clk_enable_nolock(&clk_mac_ref);
3090         clk_enable_nolock(&clk_mii_tx);
3091         #endif
3092
3093         #if 0
3094         clk_enable_nolock(&clk_hsadc_pll_div);
3095         clk_enable_nolock(&clk_hsadc_frac_div);
3096         clk_enable_nolock(&clk_hsadc_ext);
3097         clk_enable_nolock(&clk_hsadc_out);
3098         clk_enable_nolock(&clk_hsadc_out_inv);
3099         clk_enable_nolock(&clk_hsadc);
3100
3101         clk_enable_nolock(&clk_saradc);
3102         #endif
3103         /*
3104         clk_enable_nolock(&clk_smc);
3105         clk_enable_nolock(&clkn_smc);
3106         */
3107         /*
3108         clk_enable_nolock(&clk_spi0);
3109         clk_enable_nolock(&clk_spi1);
3110         */
3111         /*
3112         clk_enable_nolock(&clk_sdmmc);
3113         clk_enable_nolock(&clk_sdio);
3114         clk_enable_nolock(&clk_emmc);
3115         */
3116         #if 0
3117         clk_enable_nolock(&clk_uart_pll);
3118         clk_enable_nolock(&clk_uart0_div);
3119         clk_enable_nolock(&clk_uart0_frac_div);
3120         clk_enable_nolock(&clk_uart0);
3121         clk_enable_nolock(&clk_uart1_div);
3122         clk_enable_nolock(&clk_uart1_frac_div);
3123         clk_enable_nolock(&clk_uart1);
3124         clk_enable_nolock(&clk_uart2_div);
3125         clk_enable_nolock(&clk_uart2_frac_div);
3126         clk_enable_nolock(&clk_uart2);
3127         clk_enable_nolock(&clk_uart3_div);
3128         clk_enable_nolock(&clk_uart3_frac_div);
3129         clk_enable_nolock(&clk_uart3);
3130         #endif
3131         #if CONFIG_RK_DEBUG_UART == 0
3132                 clk_enable_nolock(&clk_uart0);
3133                 clk_enable_nolock(&clk_pclk_uart0);
3134         #elif CONFIG_RK_DEBUG_UART == 1
3135                 clk_enable_nolock(&clk_uart1);
3136                 clk_enable_nolock(&clk_pclk_uart1);
3137
3138         #elif CONFIG_RK_DEBUG_UART == 2
3139                 clk_enable_nolock(&clk_uart2);
3140                 clk_enable_nolock(&clk_pclk_uart2);
3141
3142         #elif CONFIG_RK_DEBUG_UART == 3
3143                 clk_enable_nolock(&clk_uart3);
3144                 clk_enable_nolock(&clk_pclk_uart3);
3145
3146         #endif
3147         #if 0
3148         clk_enable_nolock(&clk_timer0);
3149         clk_enable_nolock(&clk_timer1);
3150         clk_enable_nolock(&clk_timer2);
3151         #endif
3152
3153         /*************************aclk_cpu***********************/
3154         clk_enable_nolock(&clk_dma1);
3155         clk_enable_nolock(&clk_intmem);
3156         clk_enable_nolock(&clk_aclk_strc_sys);
3157
3158         /*************************hclk_cpu***********************/
3159         clk_enable_nolock(&clk_rom);
3160         #if 0
3161         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3162         // actually no i2s1
3163         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3164         clk_enable_nolock(&clk_hclk_spdif);
3165         #endif
3166         clk_enable_nolock(&clk_hclk_cpubus);
3167         clk_enable_nolock(&clk_hclk_ahb2apb);
3168         clk_enable_nolock(&clk_hclk_vio_bus);
3169         #if 0
3170         clk_enable_nolock(&clk_hclk_lcdc0);
3171         clk_enable_nolock(&clk_hclk_lcdc1);
3172         clk_enable_nolock(&clk_hclk_cif0);
3173         clk_enable_nolock(&clk_hclk_ipp);
3174         clk_enable_nolock(&clk_hclk_rga);
3175         #endif
3176         clk_enable_nolock(&clk_hclk_imem0);
3177         clk_enable_nolock(&clk_hclk_imem1);
3178
3179         /*************************pclk_cpu***********************/
3180         #if 0
3181         clk_enable_nolock(&clk_pwm01);
3182         clk_enable_nolock(&clk_pclk_timer0);
3183         clk_enable_nolock(&clk_pclk_timer1);
3184         clk_enable_nolock(&clk_pclk_timer2);
3185         clk_enable_nolock(&clk_i2c0);
3186         clk_enable_nolock(&clk_i2c1);
3187         clk_enable_nolock(&clk_gpio0);
3188         clk_enable_nolock(&clk_gpio1);
3189         clk_enable_nolock(&clk_gpio2);
3190         clk_enable_nolock(&clk_efuse);
3191         #endif
3192         clk_enable_nolock(&clk_tzpc);
3193         //clk_enable_nolock(&clk_pclk_uart0);
3194         //clk_enable_nolock(&clk_pclk_uart1);
3195         clk_enable_nolock(&clk_pclk_ddrupctl);
3196         clk_enable_nolock(&clk_pclk_ddrpubl);
3197         clk_enable_nolock(&clk_dbg);
3198         clk_enable_nolock(&clk_grf);
3199         clk_enable_nolock(&clk_pmu);
3200
3201         /*************************aclk_periph***********************/
3202         clk_enable_nolock(&clk_dma2);
3203         clk_enable_nolock(&clk_aclk_smc);
3204         clk_enable_nolock(&clk_aclk_peri_niu);
3205         clk_enable_nolock(&clk_aclk_cpu_peri);
3206         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3207
3208         /*************************hclk_periph***********************/
3209         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3210         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3211         clk_enable_nolock(&clk_hclk_emem_peri);
3212         //clk_enable_nolock(&clk_hclk_mac);
3213         clk_enable_nolock(&clk_nandc);
3214         clk_enable_nolock(&clk_hclk_usb_peri);
3215         #if 0
3216         clk_enable_nolock(&clk_hclk_otg0);
3217         clk_enable_nolock(&clk_hclk_otg1);
3218         clk_enable_nolock(&clk_hclk_hsic);
3219         clk_enable_nolock(&clk_hclk_gps);
3220         clk_enable_nolock(&clk_hclk_hsadc);
3221         clk_enable_nolock(&clk_hclk_pidfilter);
3222         clk_enable_nolock(&clk_hclk_sdmmc);
3223         clk_enable_nolock(&clk_hclk_sdio);
3224         clk_enable_nolock(&clk_hclk_emmc);
3225         #endif
3226
3227         /*************************pclk_periph***********************/
3228         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3229         #if 0
3230         clk_enable_nolock(&clk_pwm23);
3231         clk_enable_nolock(&clk_wdt);
3232         clk_enable_nolock(&clk_pclk_spi0);
3233         clk_enable_nolock(&clk_pclk_spi1);
3234         clk_enable_nolock(&clk_pclk_uart2);
3235         clk_enable_nolock(&clk_pclk_uart3);
3236         #endif
3237         #if 0
3238         clk_enable_nolock(&clk_i2c2);
3239         clk_enable_nolock(&clk_i2c3);
3240         clk_enable_nolock(&clk_i2c4);
3241         clk_enable_nolock(&clk_gpio3);
3242         clk_enable_nolock(&clk_pclk_saradc);
3243         #endif
3244         /*************************aclk_lcdc0***********************/
3245 #if 1
3246         //clk_enable_nolock(&clk_aclk_vio0);
3247         //clk_enable_nolock(&clk_aclk_lcdc0);
3248         //clk_enable_nolock(&clk_aclk_cif0);
3249         //clk_enable_nolock(&clk_aclk_ipp);
3250 #endif
3251         /*************************aclk_lcdc1***********************/
3252 #if 1
3253         //clk_enable_nolock(&clk_aclk_vio1);
3254         //clk_enable_nolock(&clk_aclk_lcdc1);
3255         //clk_enable_nolock(&clk_aclk_rga);
3256 #endif
3257         /************************power domain**********************/
3258
3259 }
3260 static void periph_clk_set_init(void)
3261 {
3262         unsigned long aclk_p, hclk_p, pclk_p;
3263         unsigned long ppll_rate = general_pll_clk.rate;
3264         //aclk 148.5
3265
3266         /* general pll */
3267         switch (ppll_rate) {
3268                 case 148500 * KHZ:
3269                         aclk_p = 148500 * KHZ;
3270                         hclk_p = aclk_p >> 1;
3271                         pclk_p = aclk_p >> 2;
3272                         break;
3273                 case 297 * MHZ:
3274                         aclk_p = ppll_rate >> 1;
3275                         hclk_p = aclk_p >> 0;
3276                         pclk_p = aclk_p >> 1;
3277                         break;
3278                 case 300 * MHZ:
3279                         aclk_p = ppll_rate >> 1;
3280                         hclk_p = aclk_p >> 0;
3281                         pclk_p = aclk_p >> 1;
3282                         break;
3283                 case 384 * MHZ:
3284                         aclk_p = ppll_rate >> 1;
3285                         hclk_p = aclk_p >> 1;
3286                         pclk_p = aclk_p >> 2;
3287                         break;
3288                 case 594 * MHZ:
3289                         aclk_p = ppll_rate >> 2;
3290                         hclk_p = aclk_p >> 0;
3291                         pclk_p = aclk_p >> 1;
3292                         break;
3293                 case 891 * MHZ:
3294                         aclk_p = ppll_rate / 6;
3295                         hclk_p = aclk_p >> 0;
3296                         pclk_p = aclk_p >> 1;
3297                         break;
3298                 case 1188 * MHZ:
3299                         aclk_p = ppll_rate >> 3;
3300                         hclk_p = aclk_p >> 0;
3301                         pclk_p = aclk_p >> 1;
3302                         break;
3303
3304                 default:
3305                         aclk_p = 150 * MHZ;
3306                         hclk_p = 150 * MHZ;
3307                         pclk_p = 75 * MHZ;
3308                         break;
3309         }
3310         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3311         clk_set_rate_nolock(&aclk_periph, aclk_p);
3312         clk_set_rate_nolock(&hclk_periph, hclk_p);
3313         clk_set_rate_nolock(&pclk_periph, pclk_p);
3314 }
3315
3316 static void cpu_axi_init(void)
3317 {
3318         unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3319         unsigned long gpll_rate = general_pll_clk.rate;
3320
3321         switch (gpll_rate) {
3322                 case 297 * MHZ:
3323                         cpu_div_rate = gpll_rate;
3324                         aclk_cpu_rate = cpu_div_rate >> 0;
3325                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3326                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3327                         break;
3328                 case 384 * MHZ:
3329                         cpu_div_rate = gpll_rate >> 1;
3330                         aclk_cpu_rate = cpu_div_rate >> 0;
3331                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3332                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3333                         break;
3334                 case 594 * MHZ:
3335                         cpu_div_rate = gpll_rate >> 1;
3336                         aclk_cpu_rate = cpu_div_rate >> 0;
3337                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3338                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3339                         break;
3340
3341                 case 891 * MHZ:
3342                         cpu_div_rate = gpll_rate / 3;
3343                         aclk_cpu_rate = cpu_div_rate >> 0;
3344                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3345                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3346                         break;
3347
3348                 case 1188 * MHZ:
3349                         cpu_div_rate = gpll_rate >> 2;
3350                         aclk_cpu_rate = cpu_div_rate >> 0;
3351                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3352                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3353                         break;
3354
3355                 default:
3356                         aclk_cpu_rate = 150 * MHZ;
3357                         hclk_cpu_rate = 150 * MHZ;
3358                         pclk_cpu_rate = 75 * MHZ;
3359                         break;
3360         }
3361         ahb2apb_cpu_rate = pclk_cpu_rate;
3362
3363         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3364         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3365         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3366         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3367         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3368         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3369 }
3370
3371 void rk30_clock_common_i2s_init(void)
3372 {
3373         unsigned long i2s_rate;
3374         //20 times
3375         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3376                 i2s_rate = 49152000;
3377         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3378                 i2s_rate = 24576000;
3379         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3380                 i2s_rate = 22579000;
3381         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3382                 i2s_rate = 12288000;
3383         } else {
3384                 i2s_rate = 49152000;
3385         }
3386
3387         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3388                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3389         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3390                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3391         } else {
3392                 if(general_pll_clk.rate > codec_pll_clk.rate)
3393                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3394                 else
3395                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3396         }
3397 }
3398 void rk30_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
3399 {
3400         struct clk *p_clk;
3401         unsigned long rate;
3402         if(!(gpll_clk->rate%(48*MHZ)))
3403         {
3404                 p_clk=gpll_clk;
3405                 rate=48*MHZ;
3406         }
3407         else if(!(cpll_clk->rate%(48*MHZ)))
3408         {
3409                 p_clk=cpll_clk;
3410                 rate=48*MHZ;
3411         }
3412         else if(!(gpll_clk->rate%(49500*KHZ)))
3413         {
3414                 p_clk=gpll_clk;
3415                 rate=(49500*KHZ);
3416         }
3417         else if(!(cpll_clk->rate%(49500*KHZ)))
3418         {
3419                 p_clk=cpll_clk;
3420                 rate=(49500*KHZ);
3421         }
3422         else
3423         {
3424                 if(cpll_clk->rate>gpll_clk->rate)
3425                 {
3426                         p_clk=cpll_clk;
3427                 }
3428                 else
3429                 {
3430                         p_clk=gpll_clk;
3431                 }
3432                 rate=50*MHZ;
3433         }
3434         clk_set_parent_nolock(&clk_uart_pll, p_clk);
3435         clk_set_rate_nolock(&clk_uart0_div,rate);
3436         clk_set_rate_nolock(&clk_uart1_div,rate);
3437         clk_set_rate_nolock(&clk_uart2_div,rate);
3438         clk_set_rate_nolock(&clk_uart3_div,rate);
3439 }
3440
3441 static void inline clock_set_div(struct clk *clk,u32 div)
3442 {
3443         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3444 }
3445
3446 static void inline clock_set_max_div(struct clk *clk)
3447 {
3448         set_cru_bits_w_msk(clk->div_max - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3449 }
3450
3451 static void div_clk_for_pll_init(void)
3452 {
3453         clock_set_max_div(&clk_cpu_div);
3454         clock_set_max_div(&aclk_vdpu);
3455         clock_set_max_div(&aclk_vepu);
3456         clock_set_max_div(&aclk_gpu);
3457         clock_set_max_div(&aclk_lcdc0_pre);
3458         clock_set_max_div(&aclk_lcdc1_pre);
3459         clock_set_max_div(&aclk_periph);
3460         clock_set_max_div(&dclk_lcdc0);
3461         clock_set_max_div(&dclk_lcdc1);
3462         clock_set_max_div(&cif0_out_div);
3463         clock_set_max_div(&clk_i2s0_div);
3464         clock_set_max_div(&clk_spdif_div);
3465         clock_set_max_div(&clk_uart0_div);
3466         clock_set_max_div(&clk_uart1_div);
3467         clock_set_max_div(&clk_uart2_div);
3468         clock_set_max_div(&clk_uart3_div);
3469         clock_set_max_div(&clk_hsicphy_12m);
3470         clock_set_max_div(&clk_hsadc_pll_div);
3471         clock_set_max_div(&clk_saradc);
3472 }
3473
3474 static u8 pll_flag = 0;
3475
3476 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3477 {
3478         //general
3479         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3480         lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
3481
3482         //code pll
3483         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3484
3485         cpu_axi_init();
3486         clk_set_rate_nolock(&clk_core, 816 * MHZ);
3487         //periph clk
3488         periph_clk_set_init();
3489
3490         //i2s
3491         rk30_clock_common_i2s_init();
3492
3493         // spi
3494         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3495         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3496
3497         // uart
3498         rk30_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
3499
3500         //mac
3501         if(!(gpll_rate % (50 * MHZ))) {
3502                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3503
3504         } else if((!(ddr_pll_clk.rate % (50 * MHZ))) && (ddr_pll_clk.rate != 24 * MHZ) && ((pll_flag & 0x2) == 0)) {
3505                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3506
3507         } else {
3508                 CLKDATA_DBG("mac can't get 50mhz, set to gpll\n");
3509                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3510         }
3511
3512         //hsadc
3513         //auto pll sel
3514         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3515
3516         //lcdc0 lcd auto sel pll
3517         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3518         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3519
3520         //cif
3521         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3522
3523         //axi lcdc auto sel
3524         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3525         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3526         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3527         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3528
3529         //axi vepu auto sel
3530         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3531         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3532
3533         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3534         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3535         //gpu auto sel
3536         clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
3537         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3538
3539         clk_set_rate_nolock(&clk_uart0, 49500000);
3540         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3541         clk_set_rate_nolock(&clk_sdio, 24750000);
3542 }
3543
3544 static struct clk def_ops_clk = {
3545         .get_parent = clksel_get_parent,
3546         .set_parent = clksel_set_parent,
3547 };
3548
3549 #ifdef CONFIG_PROC_FS
3550 struct clk_dump_ops dump_ops;
3551 #endif
3552 void rk_dump_clock_info(void);
3553 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3554 {
3555         struct clk_lookup *lk;
3556
3557         if (soc_is_rk3188plus()) {
3558                 arm_pll_clk.recalc = plus_plls_clk_recalc;
3559                 ddr_pll_clk.recalc = plus_plls_clk_recalc;
3560                 codec_pll_clk.recalc = plus_plls_clk_recalc;
3561                 general_pll_clk.recalc = plus_plls_clk_recalc;
3562
3563                 arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
3564                 codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
3565                 general_pll_clk.set_rate = plus_gpll_clk_set_rate;
3566         }
3567
3568         rk_efuse_init();
3569         pll_flag = rk_pll_flag();
3570         printk("CLKDATA_MSG: pll_flag = 0x%02x\n", pll_flag);
3571
3572         if (0 != pll_flag) {
3573                 CLKDATA_DBG("CPLL=%lu, GPLL=%lu;CPLL CAN NOT LOCK, SET CPLL BY PASS, USE GPLL REPLACE CPLL\n",
3574                                 cpll, gpll);
3575                 cpll = 24 * MHZ;
3576                 gpll = 891 * MHZ;
3577         }
3578
3579         clk_register_dump_ops(&dump_ops);
3580         clk_register_default_ops_clk(&def_ops_clk);
3581         rk30_clock_flags = flags;
3582         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3583 #ifdef RK30_CLK_OFFBOARD_TEST
3584                 rk30_clkdev_add(lk);
3585 #else
3586                 clkdev_add(lk);
3587 #endif
3588                 clk_register(lk->clk);
3589         }
3590
3591         div_clk_for_pll_init();
3592         clk_recalculate_root_clocks_nolock();
3593
3594         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3595
3596         /*
3597          * Only enable those clocks we will need, let the drivers
3598          * enable other clocks as necessary
3599          */
3600
3601         rk30_init_enable_clocks();
3602 #if 0
3603         // print loader config
3604         CLKDATA_DBG("%s clks register dbg start\n", __func__);
3605         rk_dump_clock_info();
3606         rk30_clk_dump_regs();
3607
3608         CLKDATA_DBG("%s clks register dbg end\n", __func__);
3609 #endif
3610         /*
3611          * Disable any unused clocks left on by the bootloader
3612          */
3613         //clk_disable_unused();
3614         rk30_clock_common_init(gpll, cpll);
3615         preset_lpj = loops_per_jiffy;
3616
3617         //gpio6_b7
3618         //regfile_writel(0xc0004000,0x10c);
3619         //cru_writel(0x07000000,CRU_MISC_CON);
3620
3621 }
3622 extern int rk3188_dvfs_init(void);
3623
3624 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3625 {
3626         CLKDATA_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
3627                         gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3628         _rk30_clock_data_init(gpll, cpll, flags);
3629         rk3188_dvfs_init();
3630 }
3631
3632 /*
3633  * You can override arm_clk rate with armclk= cmdline option.
3634  */
3635 static int __init armclk_setup(char *str)
3636 {
3637         get_option(&str, &armclk);
3638
3639         if (!armclk)
3640                 return 0;
3641         if (armclk < 10000)
3642                 armclk *= MHZ;
3643         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3644         return 0;
3645 }
3646 #ifndef RK30_CLK_OFFBOARD_TEST
3647 early_param("armclk", armclk_setup);
3648 #endif
3649
3650
3651 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3652 {
3653         struct clk *ck;
3654         int i;
3655         unsigned long rate = clk->rate;
3656         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3657         for (i = 0; i < deep; i++)
3658                 printk("    ");
3659
3660         printk("%-11s ", clk->name);
3661 #ifndef RK30_CLK_OFFBOARD_TEST
3662         if (clk->flags & IS_PD) {
3663                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3664         }
3665 #endif
3666         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3667                 int idx = clk->gate_idx;
3668                 u32 v;
3669                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3670                 printk("%s ", v ? "off" : "on ");
3671         }
3672
3673         if (clk->pll) {
3674                 u32 pll_mode;
3675                 u32 pll_id = clk->pll->id;
3676                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3677                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3678                         printk("slow   ");
3679                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3680                         printk("normal ");
3681                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3682                         printk("deep   ");
3683
3684                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3685                         printk("bypass ");
3686         } else if(clk == &clk_ddr) {
3687                 rate = clk->recalc(clk);
3688         }
3689
3690         if (rate >= MHZ) {
3691                 if (rate % MHZ)
3692                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3693                 else
3694                         printk("%ld MHz", rate / MHZ);
3695         } else if (rate >= KHZ) {
3696                 if (rate % KHZ)
3697                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3698                 else
3699                         printk("%ld KHz", rate / KHZ);
3700         } else {
3701                 printk("%ld Hz", rate);
3702         }
3703
3704         printk(" usecount = %d", clk->usecount);
3705
3706         if (clk->parent)
3707                 printk(" parent = %s", clk->parent->name);
3708
3709         printk("\n");
3710
3711         list_for_each_entry(ck, root_clocks, node) {
3712                 if (ck->parent == clk)
3713                         rk_dump_clock(ck, deep + 1, root_clocks);
3714         }
3715 }
3716
3717 #if 1
3718 struct list_head *get_rk_clocks_head(void);
3719
3720 void rk_dump_clock_info(void)
3721 {
3722         struct clk* clk;
3723         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3724                 if (!clk->parent)
3725                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3726         }
3727 }
3728 #endif
3729
3730 #ifdef CONFIG_PROC_FS
3731
3732 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3733 {
3734         struct clk *ck;
3735         int i;
3736         unsigned long rate = clk->rate;
3737         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3738         for (i = 0; i < deep; i++)
3739                 seq_printf(s, "    ");
3740
3741         seq_printf(s, "%-11s ", clk->name);
3742 #ifndef RK30_CLK_OFFBOARD_TEST
3743         if (clk->flags & IS_PD) {
3744                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3745         }
3746 #endif
3747         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3748                 int idx = clk->gate_idx;
3749                 u32 v;
3750                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3751                 seq_printf(s, "%s ", v ? "off" : "on ");
3752         }
3753
3754         if (clk->pll) {
3755                 u32 pll_mode;
3756                 u32 pll_id = clk->pll->id;
3757                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3758                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3759                         seq_printf(s, "slow   ");
3760                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3761                         seq_printf(s, "normal ");
3762                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3763                         seq_printf(s, "deep   ");
3764
3765                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3766                         seq_printf(s, "bypass ");
3767         } else if(clk == &clk_ddr) {
3768                 rate = clk->recalc(clk);
3769         }
3770
3771         if (rate >= MHZ) {
3772                 if (rate % MHZ)
3773                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3774                 else
3775                         seq_printf(s, "%ld MHz", rate / MHZ);
3776         } else if (rate >= KHZ) {
3777                 if (rate % KHZ)
3778                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3779                 else
3780                         seq_printf(s, "%ld KHz", rate / KHZ);
3781         } else {
3782                 seq_printf(s, "%ld Hz", rate);
3783         }
3784
3785         seq_printf(s, " usecount = %d", clk->usecount);
3786
3787         if (clk->parent)
3788                 seq_printf(s, " parent = %s", clk->parent->name);
3789
3790         seq_printf(s, "\n");
3791
3792         list_for_each_entry(ck, root_clocks, node) {
3793                 if (ck->parent == clk)
3794                         dump_clock(s, ck, deep + 1, root_clocks);
3795         }
3796 }
3797
3798 static void dump_regs(struct seq_file *s)
3799 {
3800         int i = 0;
3801         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3802         seq_printf(s, "\nPLLRegisters:\n");
3803         for(i = 0; i < END_PLL_ID; i++) {
3804                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3805                                 cru_readl(PLL_CONS(i, 0)),
3806                                 cru_readl(PLL_CONS(i, 1)),
3807                                 cru_readl(PLL_CONS(i, 2)),
3808                                 cru_readl(PLL_CONS(i, 3))
3809                           );
3810         }
3811         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3812
3813         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3814                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3815         }
3816         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3817                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3818         }
3819         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3820         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3821
3822         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3823                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3824         }
3825         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3826         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3827
3828 }
3829
3830 void rk30_clk_dump_regs(void)
3831 {
3832         int i = 0;
3833         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3834         printk("\nPLLRegisters:\n");
3835         for(i = 0; i < END_PLL_ID; i++) {
3836                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3837                                 cru_readl(PLL_CONS(i, 0)),
3838                                 cru_readl(PLL_CONS(i, 1)),
3839                                 cru_readl(PLL_CONS(i, 2)),
3840                                 cru_readl(PLL_CONS(i, 3))
3841                       );
3842         }
3843         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3844
3845         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3846                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3847         }
3848         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3849                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3850         }
3851         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3852         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3853
3854         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3855                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3856         }
3857         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3858         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3859
3860 }
3861
3862
3863 #ifdef CONFIG_PROC_FS
3864 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3865 struct clk_dump_ops dump_ops = {
3866         .dump_clk = dump_clock,
3867         .dump_regs = dump_regs,
3868 };
3869 #endif
3870
3871
3872 #endif /* CONFIG_PROC_FS */
3873
3874
3875
3876
3877 #ifdef RK30_CLK_OFFBOARD_TEST
3878 struct clk *test_get_parent(struct clk *clk) {
3879         return clk->parent;
3880 }
3881
3882 void i2s_test(void)
3883 {
3884         struct clk *i2s_clk = &clk_i2s0;
3885
3886         clk_enable_nolock(i2s_clk);
3887
3888         clk_set_rate_nolock(i2s_clk, 12288000);
3889         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3890         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3891         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3892         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3893         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3894
3895 }
3896
3897 void uart_test(void)
3898 {
3899         struct clk *uart_clk = &clk_uart0;
3900
3901         clk_enable_nolock(uart_clk);
3902
3903         clk_set_rate_nolock(uart_clk, 12288000);
3904         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3905         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3906         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3907         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3908         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3909
3910 }
3911 void hsadc_test(void)
3912 {
3913         struct clk *hsadc_clk = &clk_hsadc;
3914
3915         printk("******************hsadc_test**********************\n");
3916         clk_enable_nolock(hsadc_clk);
3917
3918         clk_set_rate_nolock(hsadc_clk, 12288000);
3919         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3920
3921
3922         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3923         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3924
3925         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3926
3927         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3928
3929         printk("******************hsadc out clock**********************\n");
3930
3931         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3932         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3933         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3934         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3935
3936
3937
3938 }
3939
3940 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3941 {
3942         //arm
3943         printk("*********arm_pll_clk***********\n");
3944         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3945
3946         printk("*********set clk_core parent***********\n");
3947         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3948         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3949
3950         //general
3951         printk("*********general_pll_clk***********\n");
3952         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3953
3954         //code pll
3955         printk("*********codec_pll_clk***********\n");
3956         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3957
3958
3959         printk("*********periph_clk_set_init***********\n");
3960         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3961         periph_clk_set_init();
3962
3963 #if 0 //
3964         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3965 #else
3966         printk("*********clk i2s***********\n");
3967         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3968         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3969         i2s_test();
3970 #endif
3971         // spi
3972         clk_enable_nolock(&clk_spi0);
3973         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3974         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3975         //saradc
3976         clk_enable_nolock(&clk_saradc);
3977         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3978         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3979         //sdio
3980         clk_enable_nolock(&clk_sdio);
3981         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3982         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3983         // uart
3984         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3985         uart_test();
3986         //mac
3987         printk("*********mac***********\n");
3988
3989         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3990         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3991
3992         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3993         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3994         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3995
3996         printk("*********mac mii set***********\n");
3997         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3998         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3999         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
4000         //hsadc
4001         printk("*********hsadc 1***********\n");
4002         //auto pll
4003         hsadc_test();
4004         //lcdc
4005         clk_enable_nolock(&dclk_lcdc0);
4006
4007         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
4008         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
4009
4010         //cif
4011         clk_enable_nolock(&cif0_out);
4012
4013         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
4014         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
4015
4016         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
4017         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4018
4019         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
4020         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
4021         //cif_in
4022         clk_enable_nolock(&cif0_in);
4023         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
4024         //axi lcdc
4025         clk_enable_nolock(&aclk_lcdc0);
4026         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
4027         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
4028         //axi vepu
4029         clk_enable_nolock(&aclk_vepu);
4030         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4031         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
4032
4033         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
4034         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
4035
4036         printk("test end\n");
4037
4038         /* arm pll
4039            clk_set_rate_nolock(&arm_pll_clk, armclk);
4040            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
4041            */
4042         //
4043         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
4044         //
4045         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
4046         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
4047
4048 }
4049
4050
4051
4052
4053
4054 static LIST_HEAD(rk30_clocks);
4055 static DEFINE_MUTEX(rk30_clocks_mutex);
4056
4057 static inline int __rk30clk_get(struct clk *clk)
4058 {
4059         return 1;
4060 }
4061 void rk30_clkdev_add(struct clk_lookup *cl)
4062 {
4063         mutex_lock(&rk30_clocks_mutex);
4064         list_add_tail(&cl->node, &rk30_clocks);
4065         mutex_unlock(&rk30_clocks_mutex);
4066 }
4067 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
4068         struct clk_lookup *p, *cl = NULL;
4069         int match, best = 0;
4070
4071         list_for_each_entry(p, &rk30_clocks, node) {
4072                 match = 0;
4073                 if (p->dev_id) {
4074                         if (!dev_id || strcmp(p->dev_id, dev_id))
4075                                 continue;
4076                         match += 2;
4077                 }
4078                 if (p->con_id) {
4079                         if (!con_id || strcmp(p->con_id, con_id))
4080                                 continue;
4081                         match += 1;
4082                 }
4083
4084                 if (match > best) {
4085                         cl = p;
4086                         if (match != 3)
4087                                 best = match;
4088                         else
4089                                 break;
4090                 }
4091         }
4092         return cl;
4093 }
4094
4095 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
4096         struct clk_lookup *cl;
4097
4098         mutex_lock(&rk30_clocks_mutex);
4099         cl = rk30_clk_find(dev_id, con_id);
4100         if (cl && !__rk30clk_get(cl->clk))
4101                 cl = NULL;
4102         mutex_unlock(&rk30_clocks_mutex);
4103
4104         return cl ? cl->clk : ERR_PTR(-ENOENT);
4105 }
4106 //EXPORT_SYMBOL(rk30_clk_get_sys);
4107
4108 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
4109         const char *dev_id = dev ? dev_name(dev) : NULL;
4110         return rk30_clk_get_sys(dev_id, con_id);
4111 }
4112 //EXPORT_SYMBOL(rk30_clk_get);
4113
4114
4115 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
4116
4117 void rk30_clocks_test(void)
4118 {
4119         struct clk *test_gpll;
4120         test_gpll = rk30_clk_get(NULL, "general_pll");
4121         if(test_gpll) {
4122                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
4123                 printk("gpll rate=%lu\n", test_gpll->rate);
4124         }
4125         //while(1);
4126 }
4127
4128 void __init rk30_clock_init_test(void)
4129 {
4130
4131         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
4132         //while(1);
4133 }
4134
4135
4136 #endif
4137
4138