1 /* linux/arch/arm/mach-rk30/clock_data.c
3 * Copyright (C) 2012 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/hardirq.h>
25 #include <mach/iomux.h>
26 #include <mach/clock.h>
28 #include <mach/dvfs.h>
32 #define MHZ (1000UL * 1000UL)
34 #define CLK_LOOPS_JIFFY_REF 11996091ULL
35 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
36 #define CLK_LOOPS_RECALC(new_rate) div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
37 void rk30_clk_dump_regs(void);
41 #define CLK_FLG_EXT_27MHZ (1<<0)
43 #define CLK_FLG_MAX_I2S_12288KHZ (1<<1)
44 #define CLK_FLG_MAX_I2S_22579_2KHZ (1<<2)
45 #define CLK_FLG_MAX_I2S_24576KHZ (1<<3)
46 #define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
48 #define CLK_FLG_UART_1_3M (1<<5)
56 u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
66 u32 pllcon2; //nb=bwadj+1;0:11;nb=nf/2
67 unsigned long rst_dly;//us
70 #define SET_PLL_DATA(_pll_id,_table) \
77 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
79 .rate = (_mhz) * KHZ, \
80 .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
81 .pllcon1 = PLL_CLKF_SET(nf),\
82 .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
83 .rst_dly=((nr*500)/24+1),\
87 #define _APLL_SET_LPJ(_mhz) \
88 .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
91 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
92 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
95 .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
96 .pllcon1 = PLL_CLKF_SET(nf),\
97 .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
98 .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
99 .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
100 _APLL_SET_LPJ(_mhz),\
101 .rst_dly=((nr*500)/24+1),\
104 #define CRU_DIV_SET(mask,shift,max) \
110 #define CRU_SRC_SET(mask,shift ) \
114 #define CRU_PARENTS_SET(parents_array) \
115 .parents=(parents_array),\
116 .parents_num=ARRAY_SIZE((parents_array))
118 #define CRU_GATE_MODE_SET(_func,_IDX) \
129 #define GATE_CLK(NAME,PARENT,ID) \
130 static struct clk clk_##NAME = { \
134 .gate_idx = CLK_GATE_##ID, \
136 #ifdef RK30_CLK_OFFBOARD_TEST
137 u32 TEST_GRF_REG[0x240];
138 u32 TEST_CRU_REG[0x240];
139 #define cru_readl(offset) (TEST_CRU_REG[offset/4])
141 u32 cru_writel_is_pr(u32 offset)
143 return (offset == 0x4000);
145 void cru_writel(u32 v, u32 offset)
148 u32 mask_v = v >> 16;
149 TEST_CRU_REG[offset/4] &= (~mask_v);
153 TEST_CRU_REG[offset/4] |= v;
154 TEST_CRU_REG[offset/4] &= 0x0000ffff;
156 if(cru_writel_is_pr(offset)) {
157 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
162 void cru_writel_i2s(u32 v, u32 offset)
164 TEST_CRU_REG[offset/4] = v;
166 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
168 #define regfile_readl(offset) (0xffffffff)
169 //#define pmu_readl(offset) readl(RK30_GRF_BASE + offset)
170 void rk30_clkdev_add(struct clk_lookup *cl);
172 #define regfile_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
173 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
174 #define cru_readl(offset) readl_relaxed(RK30_CRU_BASE + offset)
175 #define cru_writel(v, offset) do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
177 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
182 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
183 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
184 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
185 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
187 #define CLKDATA_DBG(fmt, args...) do {} while(0)
188 #define CLKDATA_LOG(fmt, args...) do {} while(0)
190 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
191 #define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
194 #define get_cru_bits(con,mask,shift)\
195 ((cru_readl((con)) >> (shift)) & (mask))
197 #define set_cru_bits_w_msk(val,mask,shift,con)\
198 cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
201 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
202 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
205 static u32 rk30_clock_flags = 0;
206 static struct clk codec_pll_clk;
207 static struct clk general_pll_clk;
208 static struct clk arm_pll_clk;
209 static unsigned long lpj_gpll;
210 static unsigned int __initdata armclk = 504 * MHZ;
213 /************************clk recalc div rate*********************************/
216 static unsigned long clksel_recalc_div(struct clk *clk)
218 u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
220 unsigned long rate = clk->parent->rate / div;
221 pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
226 static unsigned long clksel_recalc_shift(struct clk *clk)
228 u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
229 unsigned long rate = clk->parent->rate >> shift;
230 pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
235 static unsigned long clksel_recalc_shift_2(struct clk *clk)
237 u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
238 unsigned long rate = clk->parent->rate >> shift;
239 pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
243 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
245 unsigned long rate = clk->parent->rate;
246 pr_debug("%s new clock rate is %lu\n", clk->name, rate);
249 /********************************set div rate***********************************/
252 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
255 for (div = 0; div < clk->div_max; div++) {
256 u32 new_rate = clk->parent->rate / (div + 1);
257 if (new_rate <= rate) {
258 set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
259 //clk->rate = new_rate;
260 pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
261 clk->name, rate, div + 1);
269 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
272 for (shift = 0; (1 << shift) < clk->div_max; shift++) {
273 u32 new_rate = clk->parent->rate >> shift;
274 if (new_rate <= rate) {
275 set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
276 clk->rate = new_rate;
277 pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
278 clk->name, rate, shift);
286 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
290 for (shift = 1; (1 << shift) < clk->div_max; shift++) {
291 u32 new_rate = clk->parent->rate >> shift;
292 if (new_rate <= rate) {
293 set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
294 clk->rate = new_rate;
295 pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
296 clk->name, rate, shift);
304 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
307 for (div = 2; div < clk->div_max; div += 2) {
308 u32 new_rate = clk->parent->rate / div;
309 if (new_rate <= rate) {
310 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
311 clk->rate = new_rate;
312 pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
313 __func__, clk->name, rate, div);
319 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
322 unsigned long new_rate;
323 for (div = 0; div < div_max; div++) {
324 new_rate = rate / (div + 1);
325 if (new_rate <= rate_out) {
329 return div_max ? div_max : 1;
331 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
334 unsigned long new_rate;
335 for (div = 1; div < div_max; div += 2) {
336 new_rate = rate / (div + 1);
337 if (new_rate <= rate_out) {
341 return div_max ? div_max : 1;
343 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
345 unsigned long new_rate[2] = {0, 0};
348 if(clk->rate == rate)
350 for(i = 0; i < 2; i++) {
351 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
352 new_rate[i] = clk->parents[i]->rate / div[i];
353 if(new_rate[i] == rate) {
355 return clk->parents[i];
358 if(new_rate[0] < new_rate[1])
363 return clk->parents[i];
365 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
367 unsigned long new_rate[2] = {0, 0};
370 if(clk->rate == rate)
372 for(i = 0; i < 2; i++) {
373 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
374 new_rate[i] = clk->parents[i]->rate / div[i];
375 if(new_rate[i] == rate) {
377 return clk->parents[i];
380 if(new_rate[0] < new_rate[1])
385 return clk->parents[i];
388 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
393 if(clk->rate == rate)
395 p_clk = get_freediv_parents_div(clk, rate, &div);
400 CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
401 if (clk->parent != p_clk) {
402 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
405 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
407 ret = clk_set_parent_nolock(clk, p_clk);
409 CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
414 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
417 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
422 if(clk->rate == rate)
424 p_clk = get_evendiv_parents_div(clk, rate, &div);
429 CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
430 if (clk->parent != p_clk) {
431 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
434 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
436 ret = clk_set_parent_nolock(clk, p_clk);
438 CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
443 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
447 //rate==div rate //hdmi
448 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
453 p_clk = get_freediv_parents_div(clk, rate, &div);
458 if((p_clk->rate / div) != rate || (p_clk->rate % div))
461 if (clk->parent != p_clk) {
462 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
463 clk->div_shift, clk->div_mask) + 1;
465 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
467 ret = clk_set_parent_nolock(clk, p_clk);
469 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
474 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
478 /***************************round********************************/
480 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
482 return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
485 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
489 if(clk->rate == rate)
491 p_clk = get_freediv_parents_div(clk, rate, &div);
494 return p_clk->rate / div;
497 /**************************************others seting************************************/
499 static struct clk *clksel_get_parent(struct clk *clk) {
500 return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
502 static int clksel_set_parent(struct clk *clk, struct clk *parent)
505 if (unlikely(!clk->parents))
507 for (i = 0; (i < clk->parents_num); i++) {
508 if (clk->parents[i] != parent)
510 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
516 static int gate_mode(struct clk *clk, int on)
518 int idx = clk->gate_idx;
519 if (idx >= CLK_GATE_MAX)
522 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
523 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
524 // CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
526 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
527 // CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
528 // CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
532 /*****************************frac set******************************************/
534 static unsigned long clksel_recalc_frac(struct clk *clk)
538 u32 r = cru_readl(clk->clksel_con), numerator, denominator;
539 if (r == 0) // FPGA ?
540 return clk->parent->rate;
542 denominator = r & 0xFFFF;
543 rate64 = (u64)clk->parent->rate * numerator;
544 do_div(rate64, denominator);
546 pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
550 static u32 clk_gcd(u32 numerator, u32 denominator)
554 if (!numerator || !denominator)
556 if (numerator > denominator) {
572 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
573 u32 *numerator, u32 *denominator)
576 gcd_vl = clk_gcd(rate, rate_out);
577 CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
580 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
584 *numerator = rate_out / gcd_vl;
585 *denominator = rate / gcd_vl;
587 CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
588 *numerator, *denominator, *denominator / *numerator);
590 if (*numerator > 0xffff || *denominator > 0xffff ||
591 (*denominator / (*numerator)) < 20) {
592 CLKDATA_ERR("can't get a available nume and deno\n");
599 /* *********************pll **************************/
601 #define rk30_clock_udelay(a) udelay(a);
603 /*********************pll lock status**********************************/
604 //#define GRF_SOC_CON0 0x15c
605 static void pll_wait_lock(int pll_idx)
607 u32 pll_state[4] = {1, 0, 2, 3};
608 u32 bit = 0x20u << pll_state[pll_idx];
609 int delay = 24000000;
611 if (regfile_readl(GRF_SOC_STATUS0) & bit)
616 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
623 /***************************pll function**********************************/
624 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
628 if (PLLS_IN_NORM(pll_id)) {
629 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
630 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
633 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
636 CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
637 ,PLL_CONS(pll_id,1),pll_con1, rate64);
641 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
642 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
643 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
645 do_div(rate64, PLL_NR(pll_con0));
646 do_div(rate64, PLL_NO(pll_con0));
650 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
651 pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
655 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
659 static unsigned long plls_clk_recalc(struct clk *clk)
661 return pll_clk_recalc(clk->pll->id, clk->parent->rate);
663 static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
667 if (PLLS_IN_NORM(pll_id)) {
668 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
669 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
671 u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
673 do_div(rate64, PLUS_PLL_NR(pll_con0));
674 do_div(rate64, PLUS_PLL_NO(pll_con0));
679 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
683 static unsigned long plus_plls_clk_recalc(struct clk *clk)
685 DVFS_DBG("%s: for rk3188 plus\n", __func__);
686 return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
689 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
692 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
693 cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
700 cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
701 cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
703 rk30_clock_udelay(1);
704 cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
706 pll_wait_lock(pll_id);
709 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
712 CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
713 cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
719 static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
722 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
725 cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
726 cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
727 cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
728 cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
729 rk30_clock_udelay(5);
732 cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
735 rk30_clock_udelay(clk_set->rst_dly);
736 pll_wait_lock(pll_id);
739 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
744 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
746 struct _pll_data *pll_data = c->pll;
747 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
749 while(clk_set->rate) {
750 if (clk_set->rate == rate) {
755 if(clk_set->rate == rate) {
756 pll_clk_set_rate(clk_set, pll_data->id);
757 lpj_gpll = CLK_LOOPS_RECALC(rate);
759 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
765 static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
767 struct _pll_data *pll_data = c->pll;
768 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
769 DVFS_DBG("%s: for rk3188 plus\n", __func__);
771 while(clk_set->rate) {
772 if (clk_set->rate == rate) {
777 if(clk_set->rate == rate) {
778 plus_pll_clk_set_rate(clk_set, pll_data->id);
779 lpj_gpll = CLK_LOOPS_RECALC(rate);
781 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
786 #define PLL_FREF_MIN (183*KHZ)
787 #define PLL_FREF_MAX (1500*MHZ)
789 #define PLL_FVCO_MIN (300*MHZ)
790 #define PLL_FVCO_MAX (1500*MHZ)
792 #define PLL_FOUT_MIN (18750*KHZ)
793 #define PLL_FOUT_MAX (1500*MHZ)
795 #define PLL_NF_MAX (65536)
796 #define PLL_NR_MAX (64)
797 #define PLL_NO_MAX (64)
799 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
801 u32 nr, nf, no, nonr;
805 unsigned long fref, fvco, fout;
808 CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
809 if(!fin_hz || !fout_hz || fout_hz == fin_hz)
811 gcd_val = clk_gcd(fin_hz, fout_hz);
812 YFfenzi = fout_hz / gcd_val;
813 YFfenmu = fin_hz / gcd_val;
818 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
820 for(no = 1; no <= PLL_NO_MAX; no++) {
821 if(!(no == 1 || !(no % 2)))
828 if(nr > PLL_NR_MAX) //PLL_NR_MAX
832 if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
835 fvco = (fin_hz / nr) * nf;
836 if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
839 if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
852 static int pll_clk_mode(struct clk *clk, int on)
854 u8 pll_id = clk->pll->id;
855 u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
856 u32 dly = (nr * 500) / 24 + 1;
857 CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
859 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
860 rk30_clock_udelay(dly);
861 pll_wait_lock(pll_id);
862 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
864 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
865 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
870 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
872 struct _pll_data *pll_data = c->pll;
873 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
874 struct pll_clk_set temp_clk_set;
875 u32 clk_nr, clk_nf, clk_no;
878 while(clk_set->rate) {
879 if (clk_set->rate == rate) {
884 if(clk_set->rate == rate) {
885 CLKDATA_DBG("cpll get a rate\n");
886 pll_clk_set_rate(clk_set, pll_data->id);
889 CLKDATA_DBG("cpll get auto calc a rate\n");
890 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
891 pr_err("cpll auto set rate error\n");
894 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
895 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
896 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
897 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
898 pll_clk_set_rate(&temp_clk_set, pll_data->id);
903 static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
905 struct _pll_data *pll_data = c->pll;
906 struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
907 struct pll_clk_set temp_clk_set;
908 u32 clk_nr, clk_nf, clk_no;
909 DVFS_DBG("%s: for rk3188 plus\n", __func__);
911 while(clk_set->rate) {
912 if (clk_set->rate == rate) {
917 if(clk_set->rate == rate) {
918 CLKDATA_DBG("cpll get a rate\n");
919 plus_pll_clk_set_rate(clk_set, pll_data->id);
922 CLKDATA_DBG("cpll get auto calc a rate\n");
923 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
924 pr_err("cpll auto set rate error\n");
927 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
928 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
929 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
930 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
931 plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
938 /* ******************fixed input clk ***********************************************/
939 static struct clk xin24m = {
945 static struct clk clk_12m = {
952 /************************************pll func***************************/
953 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
954 struct apll_clk_set *tables) {
955 const struct apll_clk_set *ps, *pt;
957 /* find the arm_pll we want. */
960 if (pt->rate == rate) {
964 // we are sorted, and ps->rate > pt->rate.
965 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
971 //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
974 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
976 return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
979 struct arm_clks_div_set {
985 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
988 .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
989 .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
990 |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
991 |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
992 |AHB2APB_W_MSK |AHB2APB_##_ahb2apb,\
994 struct arm_clks_div_set arm_clk_div_tlb[] = {
995 _arm_clks_div_set(50 , 2, 11, 11, 11, 11),//25,50,50,50,50
996 _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
997 _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
998 _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
999 _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
1000 _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
1001 _arm_clks_div_set(0 , 2, 11, 11, 11, 11),//25,50,50,50,50
1003 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
1005 for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
1006 if(arm_clk_div_tlb[i].rate >= rate)
1007 return &arm_clk_div_tlb[i];
1014 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1016 unsigned long flags;
1017 const struct apll_clk_set *ps;
1018 u32 pll_id = clk->pll->id;
1020 u32 old_aclk_div = 0, new_aclk_div;
1022 ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1024 old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1025 new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1027 CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1028 ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1030 if(general_pll_clk.rate > clk->rate) {
1031 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1036 // ungating cpu gpll path
1037 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1038 // CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1040 local_irq_save(flags);
1041 //div arm clk for gpll
1043 cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1044 cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1046 loops_per_jiffy = lpj_gpll / temp_div;
1049 /*if core src don't select gpll ,apll neet to enter slow mode */
1050 //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1053 cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
1060 cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1061 cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1063 rk30_clock_udelay(1);
1064 cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
1066 pll_wait_lock(pll_id);
1069 //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1072 if(new_aclk_div>=old_aclk_div) {
1073 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1074 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1077 cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1078 if(old_aclk_div>new_aclk_div) {
1079 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1080 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1083 cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1085 loops_per_jiffy = ps->lpj;
1088 //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1090 local_irq_restore(flags);
1094 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1095 // , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1097 CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1098 cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1099 cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1100 cru_readl(CRU_CLKSELS_CON(1)));
1104 static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1106 unsigned long flags;
1107 const struct apll_clk_set *ps;
1108 u32 pll_id = clk->pll->id;
1110 u32 old_aclk_div = 0, new_aclk_div;
1111 DVFS_DBG("%s: for rk3188 plus\n", __func__);
1113 ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1115 old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1116 new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1118 CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1119 ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1121 if(general_pll_clk.rate > clk->rate) {
1122 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1127 // ungating cpu gpll path
1128 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1129 // CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1131 local_irq_save(flags);
1132 //div arm clk for gpll
1134 cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1135 cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1137 loops_per_jiffy = lpj_gpll / temp_div;
1140 /*if core src don't select gpll ,apll neet to enter slow mode */
1141 //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1144 cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
1145 cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1146 cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1147 cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
1148 rk30_clock_udelay(5);
1151 cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
1154 rk30_clock_udelay(ps->rst_dly);
1155 pll_wait_lock(pll_id);
1157 if(new_aclk_div>=old_aclk_div) {
1158 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1159 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1162 cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1163 if(old_aclk_div>new_aclk_div) {
1164 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1165 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1168 cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1170 loops_per_jiffy = ps->lpj;
1173 //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1175 local_irq_restore(flags);
1179 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1180 // , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1182 CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1183 cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1184 cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1185 cru_readl(CRU_CLKSELS_CON(1)));
1189 /************************************pll clocks***************************/
1191 static const struct apll_clk_set apll_clks[] = {
1192 //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1193 // _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1194 _APLL_SET_CLKS(2208, 1, 92, 1, 8, 81, 81, 21, 41, 21),
1195 _APLL_SET_CLKS(2184, 1, 91, 1, 8, 81, 81, 21, 41, 21),
1196 _APLL_SET_CLKS(2160, 1, 90, 1, 8, 81, 81, 21, 41, 21),
1197 _APLL_SET_CLKS(2136, 1, 89, 1, 8, 81, 81, 21, 41, 21),
1198 _APLL_SET_CLKS(2112, 1, 88, 1, 8, 81, 81, 21, 41, 21),
1199 _APLL_SET_CLKS(2088, 1, 87, 1, 8, 81, 81, 21, 41, 21),
1200 _APLL_SET_CLKS(2064, 1, 86, 1, 8, 81, 81, 21, 41, 21),
1201 _APLL_SET_CLKS(2040, 1, 85, 1, 8, 81, 81, 21, 41, 21),
1202 _APLL_SET_CLKS(2016, 1, 84, 1, 8, 81, 81, 21, 41, 21),
1203 _APLL_SET_CLKS(1992, 1, 83, 1, 8, 81, 81, 21, 41, 21),
1204 _APLL_SET_CLKS(1968, 1, 82, 1, 8, 81, 81, 21, 41, 21),
1205 _APLL_SET_CLKS(1944, 1, 81, 1, 8, 81, 81, 21, 41, 21),
1206 _APLL_SET_CLKS(1920, 1, 80, 1, 8, 81, 81, 21, 41, 21),
1207 _APLL_SET_CLKS(1896, 1, 79, 1, 8, 81, 81, 21, 41, 21),
1208 _APLL_SET_CLKS(1872, 1, 78, 1, 8, 81, 81, 21, 41, 21),
1209 _APLL_SET_CLKS(1848, 1, 77, 1, 8, 81, 81, 21, 41, 21),
1210 _APLL_SET_CLKS(1824, 1, 76, 1, 8, 81, 81, 21, 41, 21),
1211 _APLL_SET_CLKS(1800, 1, 75, 1, 8, 81, 81, 21, 41, 21),
1212 _APLL_SET_CLKS(1776, 1, 74, 1, 8, 81, 81, 21, 41, 21),
1213 _APLL_SET_CLKS(1752, 1, 73, 1, 8, 81, 81, 21, 41, 21),
1214 _APLL_SET_CLKS(1728, 1, 72, 1, 8, 81, 81, 21, 41, 21),
1215 _APLL_SET_CLKS(1704, 1, 71, 1, 8, 81, 81, 21, 41, 21),
1216 _APLL_SET_CLKS(1680, 1, 70, 1, 8, 41, 41, 21, 41, 21),
1217 _APLL_SET_CLKS(1656, 1, 69, 1, 8, 41, 41, 21, 41, 21),
1218 _APLL_SET_CLKS(1632, 1, 68, 1, 8, 41, 41, 21, 41, 21),
1219 _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 41, 21, 41, 21),
1220 _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 41, 21, 41, 21),
1221 _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 41, 21, 41, 21),
1222 _APLL_SET_CLKS(1488, 1, 62, 1, 8, 41, 41, 21, 41, 21),
1223 _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 41, 21, 41, 21),
1224 _APLL_SET_CLKS(1440, 1, 60, 1, 8, 41, 41, 21, 41, 21),
1225 _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 41, 21, 41, 21),
1226 _APLL_SET_CLKS(1392, 1, 58, 1, 8, 41, 41, 21, 41, 21),
1227 _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 41, 21, 41, 21),
1228 _APLL_SET_CLKS(1344, 1, 56, 1, 8, 41, 41, 21, 41, 21),
1229 _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 41, 21, 41, 21),
1230 _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 41, 21, 41, 21),
1231 _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 41, 21, 41, 21),
1232 _APLL_SET_CLKS(1248, 1, 52, 1, 8, 41, 41, 21, 41, 21),
1233 _APLL_SET_CLKS(1224, 1, 51, 1, 8, 41, 41, 21, 41, 21),
1234 _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 41, 21, 41, 21),
1235 _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 41, 21, 41, 21),
1236 _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 41, 21, 41, 21),
1237 _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 41, 21, 41, 21),
1238 _APLL_SET_CLKS(1008, 1, 84, 2, 8, 41, 31, 21, 41, 21),
1239 _APLL_SET_CLKS(912, 1, 76, 2, 8, 41, 31, 21, 41, 21),
1240 _APLL_SET_CLKS(888, 1, 74, 2, 8, 41, 31, 21, 41, 21),
1241 _APLL_SET_CLKS(816 , 1, 68, 2, 8, 41, 31, 21, 41, 21),
1242 _APLL_SET_CLKS(792 , 1, 66, 2, 8, 41, 31, 21, 41, 21),
1243 _APLL_SET_CLKS(696 , 1, 58, 2, 8, 41, 31, 21, 41, 21),
1244 _APLL_SET_CLKS(600 , 1, 50, 2, 4, 41, 31, 21, 41, 21),
1245 _APLL_SET_CLKS(504 , 1, 84, 4, 4, 41, 21, 21, 41, 21),
1246 _APLL_SET_CLKS(408 , 1, 68, 4, 4, 21, 21, 21, 41, 21),
1247 _APLL_SET_CLKS(312 , 1, 52, 4, 2, 21, 21, 21, 21, 11),
1248 _APLL_SET_CLKS(252 , 1, 84, 8, 2, 21, 21, 21, 21, 11),
1249 _APLL_SET_CLKS(216 , 1, 72, 8, 2, 21, 21, 21, 21, 11),
1250 _APLL_SET_CLKS(126 , 1, 84, 16, 2, 11, 21, 11, 11, 11),
1251 _APLL_SET_CLKS(48 , 1, 64, 32, 2, 11, 11, 11, 11, 11),
1252 _APLL_SET_CLKS(0 , 1, 21, 4, 2, 11, 11, 11, 11, 11),
1255 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1256 static struct clk arm_pll_clk = {
1259 .mode = pll_clk_mode,
1260 .recalc = plls_clk_recalc,
1261 .set_rate = arm_pll_clk_set_rate,
1262 .round_rate = arm_pll_clk_round_rate,
1266 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1268 /* do nothing here */
1271 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1272 static struct clk ddr_pll_clk = {
1275 .recalc = plls_clk_recalc,
1276 .set_rate = ddr_pll_clk_set_rate,
1280 static const struct pll_clk_set cpll_clks[] = {
1281 _PLL_SET_CLKS(360000, 1, 60, 4),
1282 _PLL_SET_CLKS(408000, 1, 68, 4),
1283 _PLL_SET_CLKS(456000, 1, 76, 4),
1284 _PLL_SET_CLKS(504000, 1, 84, 4),
1285 _PLL_SET_CLKS(552000, 1, 46, 2),
1286 _PLL_SET_CLKS(600000, 1, 50, 2),
1287 _PLL_SET_CLKS(742500, 8, 495, 2),
1288 _PLL_SET_CLKS(768000, 1, 64, 2),
1289 _PLL_SET_CLKS(798000, 2, 133, 2),
1290 _PLL_SET_CLKS(1188000, 2, 99, 1),
1291 _PLL_SET_CLKS( 0, 4, 133, 1),
1293 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1294 static struct clk codec_pll_clk = {
1295 .name = "codec_pll",
1297 .mode = pll_clk_mode,
1298 .recalc = plls_clk_recalc,
1299 .set_rate = cpll_clk_set_rate,
1303 static const struct pll_clk_set gpll_clks[] = {
1304 _PLL_SET_CLKS(148500, 2, 99, 8),
1305 _PLL_SET_CLKS(297000, 2, 198, 8),
1306 _PLL_SET_CLKS(300000, 1, 50, 4),
1307 _PLL_SET_CLKS(594000, 2, 198, 4),
1308 _PLL_SET_CLKS(1188000, 2, 99, 1),
1309 _PLL_SET_CLKS(1200000, 1, 50, 1),
1310 _PLL_SET_CLKS(0, 0, 0, 0),
1312 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1313 static struct clk general_pll_clk = {
1314 .name = "general_pll",
1316 .recalc = plls_clk_recalc,
1317 .set_rate = gpll_clk_set_rate,
1320 /********************************clocks***********************************/
1321 GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1323 /* core and cpu setting */
1324 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1326 CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1330 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1332 CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1333 return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1335 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1337 u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1338 unsigned long rate = clk->parent->recalc(clk->parent) >> shift;
1339 //CLKDATA_DBG("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1342 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1343 static struct clk clk_ddr = {
1345 .parent = &ddr_pll_clk,
1346 .recalc = ddr_clk_recalc_rate,
1347 .set_rate = ddr_clk_set_rate,
1348 .round_rate = ddr_clk_round_rate,
1349 .gate_idx = CLK_GATE_DDRPHY,
1350 .clksel_con = CRU_CLKSELS_CON(26),
1351 CRU_DIV_SET(0x3, 0, 4),
1353 CRU_PARENTS_SET(clk_ddr_parents),
1355 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1359 ret = clk_set_rate_nolock(c->parent, rate);
1361 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1365 set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1368 static unsigned long clk_core_get_rate(struct clk *c)
1370 u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1371 //c->parent->rate=c->parent->recalc(c->parent);
1372 return c->parent->rate / div;
1374 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1376 u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1377 return clk_round_rate_nolock(clk->parent, rate) / div;
1380 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1384 struct clk *old_prt;
1386 if(clk->parent == new_prt)
1388 if (unlikely(!clk->parents))
1390 CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1392 old_prt = clk->parent;
1394 if(clk->parents[0] == new_prt) {
1395 new_prt->set_rate(new_prt, 300 * MHZ);
1396 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1397 } else if(clk->parents[1] == new_prt) {
1399 if(new_prt->rate > old_prt->rate) {
1400 temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1401 set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1403 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1404 new_prt->set_rate(new_prt, 300 * MHZ);
1413 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1416 u32 old_aclk_div = 0, new_aclk_div;
1417 struct arm_clks_div_set *temp_clk_div;
1418 unsigned long arm_gpll_rate, arm_gpll_lpj;
1419 temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1420 arm_gpll_rate = c->parent->rate / temp_div;
1422 temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1424 temp_clk_div = &arm_clk_div_tlb[4];
1426 old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1427 new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1428 if(c->rate >= rate) {
1429 arm_gpll_lpj = lpj_gpll / temp_div;
1430 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1433 cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1434 cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1435 CRU_CLKSELS_CON(0));
1436 if((c->rate < rate)) {
1437 arm_gpll_lpj = lpj_gpll / temp_div;
1438 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1442 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1444 return c->parent->rate;
1446 static struct clk clk_core_gpll_path = {
1447 .name = "cpu_gpll_path",
1448 .parent = &general_pll_clk,
1449 .recalc = arm_core_gpll_clk_get_rate,
1450 .set_rate = core_gpll_clk_set_rate,
1451 CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1455 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1457 static struct clk clk_core = {
1459 .parent = &arm_pll_clk,
1460 .set_rate = clk_core_set_rate,
1461 .recalc = clk_core_get_rate,
1462 .round_rate = core_clk_round_rate,
1463 .set_parent = core_clksel_set_parent,
1464 .clksel_con = CRU_CLKSELS_CON(0),
1465 CRU_DIV_SET(0x1f, 9, 32),
1467 CRU_PARENTS_SET(clk_core_parents),
1469 GATE_CLK(l2c, clk_core, CLK_L2C);
1470 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1471 static unsigned long aclk_recalc(struct clk *clk)
1474 u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1479 rate = clk->parent->rate / div;
1480 pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1484 static struct clk core_periph = {
1485 .name = "core_periph",
1486 .parent = &clk_core,
1487 .gate_idx = CLK_GATE_CORE_PERIPH,
1488 .recalc = clksel_recalc_shift_2,
1489 .clksel_con = CRU_CLKSELS_CON(0),
1490 CRU_DIV_SET(0x3, 6, 16),
1492 static struct clk aclk_core = {
1493 .name = "aclk_core",
1494 .parent = &clk_core,
1495 .gate_idx = CLK_GATE_ACLK_CORE,
1496 .recalc = aclk_recalc,
1497 .clksel_con = CRU_CLKSELS_CON(1),
1498 CRU_DIV_SET(0x7, 3, 8),
1501 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1502 static struct clk clk_cpu_div = {
1504 .parent = &arm_pll_clk,
1505 .set_rate = clksel_set_rate_freediv,
1506 .recalc = clksel_recalc_div,
1507 .clksel_con = CRU_CLKSELS_CON(0),
1508 CRU_DIV_SET(0x1f, 0, 32),
1510 CRU_PARENTS_SET(clk_cpu_div_parents),
1513 static struct clk aclk_cpu = {
1515 .parent = &clk_cpu_div,
1516 .gate_idx = CLK_GATE_ACLK_CPU,
1519 static struct clk hclk_cpu = {
1521 .parent = &aclk_cpu,
1522 .gate_idx = CLK_GATE_HCLK_CPU,
1523 .recalc = clksel_recalc_shift,
1524 .set_rate = clksel_set_rate_shift,
1525 .clksel_con = CRU_CLKSELS_CON(1),
1526 CRU_DIV_SET(0x3, 8, 4),
1530 static struct clk pclk_cpu = {
1532 .parent = &aclk_cpu,
1533 .gate_idx = CLK_GATE_PCLK_CPU,
1534 .recalc = clksel_recalc_shift,
1535 .set_rate = clksel_set_rate_shift,
1536 .clksel_con = CRU_CLKSELS_CON(1),
1537 CRU_DIV_SET(0x3, 12, 8),
1540 static struct clk ahb2apb_cpu = {
1542 .parent = &hclk_cpu,
1543 .recalc = clksel_recalc_shift,
1544 .set_rate = clksel_set_rate_shift,
1545 .clksel_con = CRU_CLKSELS_CON(1),
1546 CRU_DIV_SET(0x3, 14, 4),
1550 static struct clk atclk_cpu = {
1551 .name = "atclk_cpu",
1552 .parent = &pclk_cpu,
1553 .gate_idx = CLK_GATE_ATCLK_CPU,
1557 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1559 unsigned long max_rate = rate / 100 * 105; /* +5% */
1560 return clkset_rate_freediv_autosel_parents(clk, max_rate);
1563 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1565 static struct clk aclk_gpu = {
1568 .recalc = clksel_recalc_div,
1569 .round_rate = clk_freediv_round_autosel_parents_rate,
1570 .set_rate = clkset_rate_freediv_autosel_parents,
1571 .clksel_con = CRU_CLKSELS_CON(34),
1572 .gate_idx = CLK_GATE_ACLK_GPU,
1573 CRU_DIV_SET(0x1f, 0, 32),
1574 CRU_SRC_SET(0x1, 7),
1575 CRU_PARENTS_SET(aclk_gpu_parents),
1578 /* vcodec setting */
1579 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1581 unsigned long rate = clk->parent->rate / 4;
1582 pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1586 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1588 static struct clk aclk_vepu = {
1589 .name = "aclk_vepu",
1590 .parent = &codec_pll_clk,
1592 .recalc = clksel_recalc_div,
1593 .set_rate = clkset_rate_freediv_autosel_parents,
1594 .clksel_con = CRU_CLKSELS_CON(32),
1595 .gate_idx = CLK_GATE_ACLK_VEPU,
1596 CRU_DIV_SET(0x1f, 0, 32),
1597 CRU_SRC_SET(0x1, 7),
1598 CRU_PARENTS_SET(aclk_vepu_parents),
1601 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1603 static struct clk aclk_vdpu = {
1604 .name = "aclk_vdpu",
1606 .recalc = clksel_recalc_div,
1607 .set_rate = clkset_rate_freediv_autosel_parents,
1608 .clksel_con = CRU_CLKSELS_CON(32),
1609 .gate_idx = CLK_GATE_ACLK_VDPU,
1610 CRU_DIV_SET(0x1f, 8, 32),
1611 CRU_SRC_SET(0x1, 15),
1612 CRU_PARENTS_SET(aclk_vdpu_parents),
1614 static struct clk hclk_vepu = {
1615 .name = "hclk_vepu",
1616 .parent = &aclk_vepu,
1618 .recalc = clksel_recalc_vpu_hclk,
1619 .gate_idx = CLK_GATE_HCLK_VEPU,
1622 static struct clk hclk_vdpu = {
1623 .name = "hclk_vdpu",
1624 .parent = &aclk_vdpu,
1626 .recalc = clksel_recalc_vpu_hclk,
1627 .gate_idx = CLK_GATE_HCLK_VDPU,
1630 /* aclk lcdc setting */
1631 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1633 static struct clk aclk_lcdc0_pre = {
1634 .name = "aclk_lcdc0_pre",
1635 .parent = &codec_pll_clk,
1637 .recalc = clksel_recalc_div,
1638 .set_rate = clkset_rate_freediv_autosel_parents,
1639 .gate_idx = CLK_GATE_ACLK_LCDC0_SRC,
1640 .clksel_con = CRU_CLKSELS_CON(31),
1641 CRU_DIV_SET(0x1f, 0, 32),
1642 CRU_SRC_SET(0x1, 7),
1643 CRU_PARENTS_SET(aclk_lcdc0_parents),
1646 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1648 static struct clk aclk_lcdc1_pre = {
1649 .name = "aclk_lcdc1_pre",
1650 .parent = &codec_pll_clk,
1652 .recalc = clksel_recalc_div,
1653 .set_rate = clkset_rate_freediv_autosel_parents,
1654 .gate_idx = CLK_GATE_ACLK_LCDC1_SRC,
1655 .clksel_con = CRU_CLKSELS_CON(31),
1656 CRU_DIV_SET(0x1f, 8, 32),
1657 CRU_SRC_SET(0x1, 15),
1658 CRU_PARENTS_SET(aclk_lcdc1_parents),
1661 /* aclk/hclk/pclk periph setting */
1662 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1664 static struct clk aclk_periph = {
1665 .name = "aclk_periph",
1666 .parent = &general_pll_clk,
1668 .gate_idx = CLK_GATE_ACLK_PERIPH,
1669 .recalc = clksel_recalc_div,
1670 .set_rate = clksel_set_rate_freediv,
1671 .clksel_con = CRU_CLKSELS_CON(10),
1672 CRU_DIV_SET(0x1f, 0, 32),
1674 CRU_PARENTS_SET(aclk_periph_parents),
1676 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1678 static struct clk pclk_periph = {
1679 .name = "pclk_periph",
1680 .parent = &aclk_periph,
1682 .gate_idx = CLK_GATE_PCLK_PERIPH,
1683 .recalc = clksel_recalc_shift,
1684 .set_rate = clksel_set_rate_shift,
1685 .clksel_con = CRU_CLKSELS_CON(10),
1686 CRU_DIV_SET(0x3, 12, 8),
1689 static struct clk hclk_periph = {
1690 .name = "hclk_periph",
1691 .parent = &aclk_periph,
1693 .gate_idx = CLK_GATE_HCLK_PERIPH,
1694 .recalc = clksel_recalc_shift,
1695 .set_rate = clksel_set_rate_shift,
1696 .clksel_con = CRU_CLKSELS_CON(10),
1697 CRU_DIV_SET(0x3, 8, 4),
1699 /* dclk lcdc setting */
1701 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1705 unsigned long new_rate;
1708 if(clk->rate == rate)
1710 for(i = 0; i < 2; i++) {
1711 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1712 new_rate = clk->parents[i]->rate / div;
1713 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1718 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1722 //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1724 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1725 clk->div_shift, clk->div_mask) + 1;
1727 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1729 if(clk->parents[i] != clk->parent) {
1730 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1734 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1735 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1738 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1742 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1744 if (rate == 27 * MHZ)
1745 return clkset_rate_freediv_autosel_parents(clk, rate);
1747 return clkset_rate_evendiv_autosel_parents(clk, rate);
1752 if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1753 parent = clk->parents[1];
1754 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1756 parent = clk->parents[0];
1758 //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1759 //clk->name,rate,parent->name,clk->parent->name);
1761 if(parent != clk->parents[1]) {
1762 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1764 CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1768 if (clk->parent != parent) {
1769 ret = clk_set_parent_nolock(clk, parent);
1771 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1779 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1780 static struct clk dclk_lcdc0 = {
1781 .name = "dclk_lcdc0",
1783 .set_rate = dclk_lcdc_set_rate,
1784 .recalc = clksel_recalc_div,
1785 .gate_idx = CLK_GATE_DCLK_LCDC0_SRC,
1786 .clksel_con = CRU_CLKSELS_CON(27),
1787 CRU_SRC_SET(0x1, 0),
1788 CRU_DIV_SET(0xff, 8, 256),
1789 CRU_PARENTS_SET(dclk_lcdc0_parents),
1792 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1793 static struct clk dclk_lcdc1 = {
1794 .name = "dclk_lcdc1",
1796 .set_rate = dclk_lcdc_set_rate,
1797 .recalc = clksel_recalc_div,
1798 .gate_idx = CLK_GATE_DCLK_LCDC1_SRC,
1799 .clksel_con = CRU_CLKSELS_CON(28),
1800 CRU_SRC_SET(0x1, 0),
1801 CRU_DIV_SET(0xff, 8, 256),
1802 CRU_PARENTS_SET(dclk_lcdc1_parents),
1807 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1808 static struct clk cif_out_pll = {
1809 .name = "cif_out_pll",
1810 .parent = &general_pll_clk,
1811 .clksel_con = CRU_CLKSELS_CON(29),
1812 CRU_SRC_SET(0x1, 0),
1813 CRU_PARENTS_SET(cifout_sel_pll_parents),
1816 static struct clk cif0_out_div = {
1817 .name = "cif0_out_div",
1818 .parent = &cif_out_pll,
1820 .recalc = clksel_recalc_div,
1821 .set_rate = clksel_set_rate_freediv,
1822 .gate_idx = CLK_GATE_CIF0_OUT,
1823 .clksel_con = CRU_CLKSELS_CON(29),
1824 CRU_DIV_SET(0x1f, 1, 32),
1827 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1832 if (rate == 24 * MHZ) {
1833 parent = clk->parents[1];
1835 parent = clk->parents[0];
1836 ret = clk_set_rate_nolock(parent, rate);
1840 if (clk->parent != parent)
1841 ret = clk_set_parent_nolock(clk, parent);
1846 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1847 static struct clk cif0_out = {
1849 .parent = &cif0_out_div,
1850 .set_rate = cif_out_set_rate,
1851 .clksel_con = CRU_CLKSELS_CON(29),
1852 CRU_SRC_SET(0x1, 7),
1853 CRU_PARENTS_SET(cif0_out_parents),
1856 static struct clk pclkin_cif0 = {
1857 .name = "pclkin_cif0",
1859 .gate_idx = CLK_GATE_PCLKIN_CIF0,
1862 static struct clk inv_cif0 = {
1864 .parent = &pclkin_cif0,
1867 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1868 static struct clk cif0_in = {
1870 .parent = &pclkin_cif0,
1871 .clksel_con = CRU_CLKSELS_CON(30),
1872 CRU_SRC_SET(0x1, 8),
1873 CRU_PARENTS_SET(cif0_in_parents),
1876 /* i2s/spdif setting */
1877 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1878 static struct clk clk_i2s_pll = {
1880 .parent = &general_pll_clk,
1881 .clksel_con = CRU_CLKSELS_CON(2),
1882 CRU_SRC_SET(0x1, 15),
1883 CRU_PARENTS_SET(clk_i2s_div_parents),
1886 static struct clk clk_i2s0_div = {
1888 .parent = &clk_i2s_pll,
1890 .recalc = clksel_recalc_div,
1891 .set_rate = clksel_set_rate_freediv,
1892 .round_rate = clksel_freediv_round_rate,
1893 .gate_idx = CLK_GATE_I2S0_SRC,
1894 .clksel_con = CRU_CLKSELS_CON(3),
1895 CRU_DIV_SET(0x7f, 0, 64),
1898 static struct clk clk_spdif_div = {
1899 .name = "spdif_div",
1900 .parent = &clk_i2s_pll,
1901 .recalc = clksel_recalc_div,
1902 .set_rate = clksel_set_rate_freediv,
1903 .round_rate = clksel_freediv_round_rate,
1905 .gate_idx = CLK_GATE_SPDIF_SRC,
1906 .clksel_con = CRU_CLKSELS_CON(5),
1907 CRU_DIV_SET(0x7f, 0, 64),
1909 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1911 u32 numerator, denominator;
1912 //clk_i2s_div->clk_i2s_pll->gpll/cpll
1913 //clk->parent->parent
1914 if(frac_div_get_seting(rate, clk->parent->parent->rate,
1915 &numerator, &denominator) == 0) {
1916 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1917 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1918 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1920 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1926 static struct clk clk_i2s0_frac_div = {
1927 .name = "i2s0_frac_div",
1928 .parent = &clk_i2s0_div,
1930 .gate_idx = CLK_GATE_I2S0_FRAC,
1931 .recalc = clksel_recalc_frac,
1932 .set_rate = clk_i2s_fracdiv_set_rate,
1933 .clksel_con = CRU_CLKSELS_CON(7),
1936 static struct clk clk_spdif_frac_div = {
1937 .name = "spdif_frac_div",
1938 .parent = &clk_spdif_div,
1940 .gate_idx = CLK_GATE_SPDIF_FRAC,
1941 .recalc = clksel_recalc_frac,
1942 .set_rate = clk_i2s_fracdiv_set_rate,
1943 .clksel_con = CRU_CLKSELS_CON(9),
1946 #define I2S_SRC_DIV (0x0)
1947 #define I2S_SRC_FRAC (0x1)
1948 #define I2S_SRC_12M (0x2)
1950 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1955 if (rate == clk->parents[I2S_SRC_12M]->rate) {
1956 parent = clk->parents[I2S_SRC_12M];
1957 } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1958 parent = clk->parents[I2S_SRC_DIV];
1960 parent = clk->parents[I2S_SRC_FRAC];
1963 CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1964 clk->name, rate, parent->name, clk->parent->name);
1966 if(parent != clk->parents[I2S_SRC_12M]) {
1967 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1969 CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1974 if (clk->parent != parent) {
1975 ret = clk_set_parent_nolock(clk, parent);
1977 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1985 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
1987 static struct clk clk_i2s0 = {
1989 .set_rate = i2s_set_rate,
1990 .clksel_con = CRU_CLKSELS_CON(3),
1991 CRU_SRC_SET(0x3, 8),
1992 CRU_PARENTS_SET(clk_i2s0_parents),
1995 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
1997 static struct clk clk_spdif = {
1999 .parent = &clk_spdif_frac_div,
2000 .set_rate = i2s_set_rate,
2001 .clksel_con = CRU_CLKSELS_CON(5),
2002 CRU_SRC_SET(0x3, 8),
2003 CRU_PARENTS_SET(clk_spdif_parents),
2006 /* otgphy setting */
2007 GATE_CLK(otgphy0, xin24m, OTGPHY0);
2008 GATE_CLK(otgphy1, xin24m, OTGPHY1);
2010 static struct clk clk_otgphy0_480m = {
2011 .name = "otgphy0_480m",
2012 .parent = &clk_otgphy0,
2014 static struct clk clk_otgphy1_480m = {
2015 .name = "otgphy1_480m",
2016 .parent = &clk_otgphy1,
2019 /* hsicphy setting */
2021 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
2022 static struct clk clk_hsicphy_480m = {
2023 .name = "hsicphy_480m",
2024 .parent = &clk_otgphy0_480m,
2025 .clksel_con = CRU_CLKSELS_CON(30),
2026 CRU_SRC_SET(0x3, 0),
2027 CRU_PARENTS_SET(clk_hsicphy_parents),
2029 static struct clk clk_hsicphy_12m = {
2030 .name = "hsicphy_12m",
2031 .parent = &clk_hsicphy_480m,
2032 .clksel_con = CRU_CLKSELS_CON(11),
2033 CRU_DIV_SET(0x3f, 8, 64),
2037 /* mac and rmii setting */
2039 static struct clk rmii_clkin = {
2040 .name = "rmii_clkin",
2042 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
2043 static struct clk clk_mac_pll_div = {
2044 .name = "mac_pll_div",
2045 .parent = &general_pll_clk,
2047 .gate_idx = CLK_GATE_MAC_SRC,
2048 .recalc = clksel_recalc_div,
2049 .set_rate = clksel_set_rate_freediv,
2050 .clksel_con = CRU_CLKSELS_CON(21),
2051 CRU_DIV_SET(0x1f, 8, 32),
2052 CRU_SRC_SET(0x1, 0),
2053 CRU_PARENTS_SET(clk_mac_ref_div_parents),
2056 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
2058 if(clk->parent == clk->parents[1]) {
2059 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
2061 } else if(clk->parent == clk->parents[0]) {
2062 return clk_set_rate_nolock(clk->parents[0], rate);
2067 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
2069 static struct clk clk_mac_ref = {
2071 .parent = &clk_mac_pll_div,
2072 .set_rate = clksel_mac_ref_set_rate,
2073 .clksel_con = CRU_CLKSELS_CON(21),
2074 CRU_SRC_SET(0x1, 4),
2075 CRU_PARENTS_SET(clk_mac_ref_parents),
2078 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
2080 return clk_set_parent_nolock(clk->parent, parent);
2083 static struct clk clk_mii_tx = {
2085 .parent = &clk_mac_ref,
2086 //.set_parent = clk_set_mii_tx_parent,
2088 .gate_idx = CLK_GATE_MAC_LBTEST,
2091 /* hsadc and saradc */
2092 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
2093 static struct clk clk_hsadc_pll_div = {
2094 .name = "hsadc_pll_div",
2095 .parent = &general_pll_clk,
2097 .gate_idx = CLK_GATE_HSADC_SRC,
2098 .recalc = clksel_recalc_div,
2099 .round_rate = clk_freediv_round_autosel_parents_rate,
2100 .set_rate = clkset_rate_freediv_autosel_parents,
2101 //.round_rate = clksel_freediv_round_rate,
2102 //.set_rate = clksel_set_rate_freediv,
2103 .clksel_con = CRU_CLKSELS_CON(22),
2104 CRU_DIV_SET(0xff, 8, 256),
2105 CRU_SRC_SET(0x1, 0),
2106 CRU_PARENTS_SET(clk_hsadc_pll_parents),
2108 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2110 u32 numerator, denominator;
2111 // clk_hsadc_pll_div->gpll/cpll
2112 //clk->parent->parent
2113 if(frac_div_get_seting(rate, clk->parent->parent->rate,
2114 &numerator, &denominator) == 0) {
2115 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2117 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2119 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2121 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2126 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2128 u32 numerator, denominator;
2130 // clk_hsadc_pll_div->gpll/cpll
2131 //clk->parent->parent
2132 for(i = 0; i < 2; i++) {
2133 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2134 &numerator, &denominator) == 0)
2140 if(clk->parent->parent != clk->parent->parents[i])
2141 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2143 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2145 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2147 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2149 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2155 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2157 u32 numerator, denominator;
2159 CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2160 if(frac_div_get_seting(rate, clk->parent->parent->rate,
2161 &numerator, &denominator) == 0)
2166 static struct clk clk_hsadc_frac_div = {
2167 .name = "hsadc_frac_div",
2168 .parent = &clk_hsadc_pll_div,
2170 .recalc = clksel_recalc_frac,
2171 .set_rate = clk_hsadc_fracdiv_set_rate_auto_parents,
2172 .round_rate = clk_hsadc_fracdiv_round_rate,
2173 .gate_idx = CLK_GATE_HSADC_FRAC_SRC,
2174 .clksel_con = CRU_CLKSELS_CON(23),
2177 #define HSADC_SRC_DIV 0x0
2178 #define HSADC_SRC_FRAC 0x1
2179 #define HSADC_SRC_EXT 0x2
2180 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2185 if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2186 CLKDATA_DBG("hsadc clk is form ext\n");
2188 } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2189 parent = clk->parents[HSADC_SRC_DIV];
2190 } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2191 parent = clk->parents[HSADC_SRC_FRAC];
2193 parent = clk->parents[HSADC_SRC_DIV];
2195 CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2196 clk->name, rate, parent->name, clk->parent->name);
2198 ret = clk_set_rate_nolock(parent, rate);
2200 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2203 if (clk->parent != parent) {
2204 ret = clk_set_parent_nolock(clk, parent);
2206 CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2213 static struct clk clk_hsadc_ext = {
2214 .name = "hsadc_ext",
2217 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2218 static struct clk clk_hsadc_out = {
2219 .name = "hsadc_out",
2220 .parent = &clk_hsadc_pll_div,
2221 .set_rate = clk_hsadc_set_rate,
2222 .clksel_con = CRU_CLKSELS_CON(22),
2223 CRU_SRC_SET(0x3, 4),
2224 CRU_PARENTS_SET(clk_hsadc_out_parents),
2226 static struct clk clk_hsadc_out_inv = {
2227 .name = "hsadc_out_inv",
2228 .parent = &clk_hsadc_out,
2231 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2232 static struct clk clk_hsadc = {
2234 .parent = &clk_hsadc_out,
2235 .clksel_con = CRU_CLKSELS_CON(22),
2236 CRU_SRC_SET(0x1, 7),
2237 CRU_PARENTS_SET(clk_hsadc_parents),
2240 static struct clk clk_saradc = {
2244 .recalc = clksel_recalc_div,
2245 .set_rate = clksel_set_rate_freediv,
2246 .gate_idx = CLK_GATE_SARADC_SRC,
2247 .clksel_con = CRU_CLKSELS_CON(24),
2248 CRU_DIV_SET(0xff, 8, 256),
2252 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2253 static struct clk clkn_smc = {
2259 static struct clk clk_spi0 = {
2261 .parent = &pclk_periph,
2263 .recalc = clksel_recalc_div,
2264 .set_rate = clksel_set_rate_freediv,
2265 .gate_idx = CLK_GATE_SPI0_SRC,
2266 .clksel_con = CRU_CLKSELS_CON(25),
2267 CRU_DIV_SET(0x7f, 0, 128),
2270 static struct clk clk_spi1 = {
2272 .parent = &pclk_periph,
2274 .recalc = clksel_recalc_div,
2275 .set_rate = clksel_set_rate_freediv,
2276 .gate_idx = CLK_GATE_SPI1_SRC,
2277 .clksel_con = CRU_CLKSELS_CON(25),
2278 CRU_DIV_SET(0x7f, 8, 128),
2281 /* sdmmc/sdio/emmc setting */
2282 static struct clk clk_sdmmc = {
2284 .parent = &hclk_periph,
2286 .recalc = clksel_recalc_div,
2287 .set_rate = clksel_set_rate_even,
2288 .gate_idx = CLK_GATE_MMC0_SRC,
2289 .clksel_con = CRU_CLKSELS_CON(11),
2290 CRU_DIV_SET(0x3f, 0, 64),
2293 static struct clk clk_sdio = {
2295 .parent = &hclk_periph,
2297 .recalc = clksel_recalc_div,
2298 .set_rate = clksel_set_rate_even,
2299 .gate_idx = CLK_GATE_SDIO_SRC,
2300 .clksel_con = CRU_CLKSELS_CON(12),
2301 CRU_DIV_SET(0x3f, 0, 64),
2305 static struct clk clk_emmc = {
2307 .parent = &hclk_periph,
2309 .recalc = clksel_recalc_div,
2310 .set_rate = clksel_set_rate_freediv,
2311 .gate_idx = CLK_GATE_EMMC_SRC,
2312 .clksel_con = CRU_CLKSELS_CON(12),
2313 CRU_DIV_SET(0x3f, 8, 64),
2317 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2318 static struct clk clk_uart_pll = {
2320 .parent = &general_pll_clk,
2321 .clksel_con = CRU_CLKSELS_CON(12),
2322 CRU_SRC_SET(0x1, 15),
2323 CRU_PARENTS_SET(clk_uart_src_parents),
2325 static struct clk clk_uart0_div = {
2326 .name = "uart0_div",
2327 .parent = &clk_uart_pll,
2329 .gate_idx = CLK_GATE_UART0_SRC,
2330 .recalc = clksel_recalc_div,
2331 .set_rate = clksel_set_rate_freediv,
2332 .round_rate = clksel_freediv_round_rate,
2333 .clksel_con = CRU_CLKSELS_CON(13),
2334 CRU_DIV_SET(0x7f, 0, 64),
2336 static struct clk clk_uart1_div = {
2337 .name = "uart1_div",
2338 .parent = &clk_uart_pll,
2340 .gate_idx = CLK_GATE_UART1_SRC,
2341 .recalc = clksel_recalc_div,
2342 .round_rate = clksel_freediv_round_rate,
2343 .set_rate = clksel_set_rate_freediv,
2344 .clksel_con = CRU_CLKSELS_CON(14),
2345 CRU_DIV_SET(0x7f, 0, 64),
2348 static struct clk clk_uart2_div = {
2349 .name = "uart2_div",
2350 .parent = &clk_uart_pll,
2352 .gate_idx = CLK_GATE_UART2_SRC,
2353 .recalc = clksel_recalc_div,
2354 .round_rate = clksel_freediv_round_rate,
2355 .set_rate = clksel_set_rate_freediv,
2356 .clksel_con = CRU_CLKSELS_CON(15),
2357 CRU_DIV_SET(0x7f, 0, 64),
2360 static struct clk clk_uart3_div = {
2361 .name = "uart3_div",
2362 .parent = &clk_uart_pll,
2364 .gate_idx = CLK_GATE_UART3_SRC,
2365 .recalc = clksel_recalc_div,
2366 .round_rate = clksel_freediv_round_rate,
2367 .set_rate = clksel_set_rate_freediv,
2368 .clksel_con = CRU_CLKSELS_CON(16),
2369 CRU_DIV_SET(0x7f, 0, 64),
2371 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2373 u32 numerator, denominator;
2374 //clk_uart0_div->clk_uart_pll->gpll/cpll
2375 //clk->parent->parent
2376 if(frac_div_get_seting(rate, clk->parent->parent->rate,
2377 &numerator, &denominator) == 0) {
2378 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2380 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2382 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2384 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2390 static struct clk clk_uart0_frac_div = {
2391 .name = "uart0_frac_div",
2392 .parent = &clk_uart0_div,
2394 .recalc = clksel_recalc_frac,
2395 .set_rate = clk_uart_fracdiv_set_rate,
2396 .gate_idx = CLK_GATE_UART0_FRAC_SRC,
2397 .clksel_con = CRU_CLKSELS_CON(17),
2399 static struct clk clk_uart1_frac_div = {
2400 .name = "uart1_frac_div",
2401 .parent = &clk_uart1_div,
2403 .recalc = clksel_recalc_frac,
2404 .set_rate = clk_uart_fracdiv_set_rate,
2405 .gate_idx = CLK_GATE_UART1_FRAC_SRC,
2406 .clksel_con = CRU_CLKSELS_CON(18),
2408 static struct clk clk_uart2_frac_div = {
2409 .name = "uart2_frac_div",
2411 .parent = &clk_uart2_div,
2412 .recalc = clksel_recalc_frac,
2413 .set_rate = clk_uart_fracdiv_set_rate,
2414 .gate_idx = CLK_GATE_UART2_FRAC_SRC,
2415 .clksel_con = CRU_CLKSELS_CON(19),
2417 static struct clk clk_uart3_frac_div = {
2418 .name = "uart3_frac_div",
2419 .parent = &clk_uart3_div,
2421 .recalc = clksel_recalc_frac,
2422 .set_rate = clk_uart_fracdiv_set_rate,
2423 .gate_idx = CLK_GATE_UART3_FRAC_SRC,
2424 .clksel_con = CRU_CLKSELS_CON(20),
2427 #define UART_SRC_DIV 0
2428 #define UART_SRC_FRAC 1
2429 #define UART_SRC_24M 2
2431 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2436 if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2437 parent = clk->parents[UART_SRC_24M];
2438 } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2439 parent = clk->parents[UART_SRC_DIV];
2441 parent = clk->parents[UART_SRC_FRAC];
2444 CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2445 clk->name, rate, parent->name, clk->parent->name);
2447 if(parent != clk->parents[UART_SRC_24M]) {
2448 ret = clk_set_rate_nolock(parent, rate);
2450 CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2455 if (clk->parent != parent) {
2456 ret = clk_set_parent_nolock(clk, parent);
2458 CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2466 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2467 static struct clk clk_uart0 = {
2469 .set_rate = clk_uart_set_rate,
2470 .clksel_con = CRU_CLKSELS_CON(13),
2471 CRU_SRC_SET(0x3, 8),
2472 CRU_PARENTS_SET(clk_uart0_parents),
2475 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2476 static struct clk clk_uart1 = {
2478 .set_rate = clk_uart_set_rate,
2479 .clksel_con = CRU_CLKSELS_CON(14),
2480 CRU_SRC_SET(0x3, 8),
2481 CRU_PARENTS_SET(clk_uart1_parents),
2484 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2485 static struct clk clk_uart2 = {
2487 .set_rate = clk_uart_set_rate,
2488 .clksel_con = CRU_CLKSELS_CON(15),
2489 CRU_SRC_SET(0x3, 8),
2490 CRU_PARENTS_SET(clk_uart2_parents),
2492 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2493 static struct clk clk_uart3 = {
2495 .set_rate = clk_uart_set_rate,
2496 .clksel_con = CRU_CLKSELS_CON(16),
2497 CRU_SRC_SET(0x3, 8),
2498 CRU_PARENTS_SET(clk_uart3_parents),
2502 GATE_CLK(timer0, xin24m, TIMER0);
2503 GATE_CLK(timer1, xin24m, TIMER1);
2504 GATE_CLK(timer2, xin24m, TIMER2);
2505 GATE_CLK(timer3, xin24m, TIMER3);
2506 GATE_CLK(timer4, xin24m, TIMER4);
2507 GATE_CLK(timer5, xin24m, TIMER5);
2508 GATE_CLK(timer6, xin24m, TIMER6);
2510 /*********************power domain*******************************/
2512 #ifdef RK30_CLK_OFFBOARD_TEST
2513 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2514 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2516 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2517 #define _pmu_set_power_domain pmu_set_power_domain
2520 static int pd_video_mode(struct clk *clk, int on)
2523 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2524 gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2525 //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2526 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2527 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2528 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2529 pmu_set_power_domain(PD_VIDEO, on);
2530 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2531 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2532 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2536 static struct clk pd_video = {
2539 .mode = pd_video_mode,
2540 .gate_idx = PD_VIDEO,
2542 static int pd_display_mode(struct clk *clk, int on)
2545 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2546 gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2547 gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2548 gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2549 gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2550 //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2551 gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2552 gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2553 gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2554 gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2555 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2556 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2557 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2558 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2559 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2560 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2561 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2562 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2563 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2564 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2565 pmu_set_power_domain(PD_VIO, on);
2566 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2567 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2568 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2569 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2570 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2571 //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2572 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2573 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2574 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2575 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2579 static struct clk pd_display = {
2582 .mode = pd_display_mode,
2585 static struct clk pd_lcdc0 = {
2586 .parent = &pd_display,
2589 static struct clk pd_lcdc1 = {
2590 .parent = &pd_display,
2593 static struct clk pd_cif0 = {
2594 .parent = &pd_display,
2597 static struct clk pd_rga = {
2598 .parent = &pd_display,
2601 static struct clk pd_ipp = {
2602 .parent = &pd_display,
2605 static struct clk pd_hdmi = {
2606 .parent = &pd_display,
2611 static int pd_gpu_mode(struct clk *clk, int on)
2614 gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2615 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2616 pmu_set_power_domain(PD_GPU, on);
2617 cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2621 static struct clk pd_gpu = {
2624 .mode = pd_gpu_mode,
2628 static int pm_off_mode(struct clk *clk, int on)
2630 _pmu_set_power_domain(clk->gate_idx, on); //on 1
2633 static struct clk pd_peri = {
2636 .mode = pm_off_mode,
2637 .gate_idx = PD_PERI,
2641 #define PD_CLK(name) \
2649 /************************rk30 fixed div clock****************************************/
2651 /*************************aclk_cpu***********************/
2653 GATE_CLK(dma1, aclk_cpu, ACLK_DMAC1);
2654 GATE_CLK(intmem, aclk_cpu, ACLK_INTMEM);
2655 GATE_CLK(aclk_strc_sys, aclk_cpu, ACLK_STRC_SYS);
2657 /*************************hclk_cpu***********************/
2659 GATE_CLK(rom, hclk_cpu, HCLK_ROM);
2660 GATE_CLK(hclk_i2s0_2ch, hclk_cpu, HCLK_I2S0_2CH);
2661 GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
2662 GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
2663 GATE_CLK(hclk_ahb2apb, hclk_cpu, HCLK_AHB2APB);
2664 GATE_CLK(hclk_vio_bus, hclk_cpu, HCLK_VIO_BUS);
2665 GATE_CLK(hclk_lcdc0, hclk_cpu, HCLK_LCDC0);
2666 GATE_CLK(hclk_lcdc1, hclk_cpu, HCLK_LCDC1);
2667 GATE_CLK(hclk_cif0, hclk_cpu, HCLK_CIF0);
2668 GATE_CLK(hclk_ipp, hclk_cpu, HCLK_IPP);
2669 GATE_CLK(hclk_rga, hclk_cpu, HCLK_RGA);
2670 GATE_CLK(hclk_imem0, hclk_cpu, HCLK_IMEM0);
2671 GATE_CLK(hclk_imem1, hclk_cpu, HCLK_IMEM1);
2673 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2674 GATE_CLK(pclk_uart0, ahb2apb_cpu, PCLK_UART0);
2675 GATE_CLK(pclk_uart1, ahb2apb_cpu, PCLK_UART1);
2676 /*************************pclk_cpu***********************/
2677 GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2678 GATE_CLK(pclk_timer0, pclk_cpu, PCLK_TIMER0);
2679 GATE_CLK(pclk_timer2, pclk_cpu, PCLK_TIMER2);
2680 GATE_CLK(i2c0, pclk_cpu, PCLK_I2C0);
2681 GATE_CLK(i2c1, pclk_cpu, PCLK_I2C1);
2682 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2683 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2684 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2685 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2686 GATE_CLK(tzpc, pclk_cpu, PCLK_TZPC);
2687 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2688 GATE_CLK(pclk_ddrpubl, pclk_cpu, PCLK_PUBL);
2689 GATE_CLK(dbg, pclk_cpu, PCLK_DBG);
2690 GATE_CLK(grf, pclk_cpu, PCLK_GRF);
2691 GATE_CLK(pmu, pclk_cpu, PCLK_PMU);
2693 /*************************aclk_periph***********************/
2695 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2696 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2697 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2698 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2699 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2700 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2702 /*************************hclk_periph***********************/
2703 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2704 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2705 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2706 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2707 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2708 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2709 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2710 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2711 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2712 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2713 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2714 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2715 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2716 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2717 /*************************pclk_periph***********************/
2718 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2719 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2720 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2721 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2722 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2723 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2724 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2725 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2726 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2727 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2728 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2729 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2730 /*************************aclk_lcdc0***********************/
2732 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2733 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2734 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2735 GATE_CLK(aclk_ipp, clk_aclk_vio0, ACLK_IPP);
2737 /*************************aclk_lcdc0***********************/
2739 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2740 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2741 GATE_CLK(aclk_rga, clk_aclk_vio1, ACLK_RGA);
2745 #define CLK(dev, con, ck) \
2753 #define CLK1(name) \
2757 .clk = &clk_##name,\
2762 static struct clk_lookup clks[] = {
2763 CLK(NULL, "xin24m", &xin24m),
2764 //CLK(NULL, "xin27m", &xin27m),
2765 CLK(NULL, "xin12m", &clk_12m),
2766 CLK(NULL, "arm_pll", &arm_pll_clk),
2767 CLK(NULL, "ddr_pll", &ddr_pll_clk),
2768 CLK(NULL, "codec_pll", &codec_pll_clk),
2769 CLK(NULL, "general_pll", &general_pll_clk),
2771 CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2772 CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2774 CLK(NULL, "ddr", &clk_ddr),
2775 CLK(NULL, "cpu", &clk_core),
2778 CLK("smp_twd", NULL, &core_periph),
2779 CLK(NULL, "aclk_core", &aclk_core),
2781 CLK(NULL, "logic", &clk_cpu_div),
2782 CLK(NULL, "aclk_cpu", &aclk_cpu),
2783 CLK(NULL, "pclk_cpu", &pclk_cpu),
2784 CLK(NULL, "atclk_cpu", &atclk_cpu),
2785 CLK(NULL, "hclk_cpu", &hclk_cpu),
2786 CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2788 CLK(NULL, "gpu", &aclk_gpu),
2790 CLK(NULL, "aclk_vepu", &aclk_vepu),
2791 CLK(NULL, "hclk_vepu", &hclk_vepu),
2792 CLK(NULL, "aclk_vdpu", &aclk_vdpu),
2793 CLK(NULL, "hclk_vdpu", &hclk_vdpu),
2795 CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2796 CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2798 CLK(NULL, "aclk_periph", &aclk_periph),
2799 CLK(NULL, "pclk_periph", &pclk_periph),
2800 CLK(NULL, "hclk_periph", &hclk_periph),
2802 CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2803 CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2805 CLK(NULL, "cif_out_pll", &cif_out_pll),
2806 CLK(NULL, "cif0_out_div", &cif0_out_div),
2807 CLK(NULL, "cif0_out", &cif0_out),
2809 CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2810 CLK(NULL, "inv_cif0", &inv_cif0),
2811 CLK(NULL, "cif0_in", &cif0_in),
2814 CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2815 CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2816 CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2819 CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2820 CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2821 CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2825 CLK1(spdif_frac_div),
2835 CLK(NULL, "rmii_clkin", &rmii_clkin),
2836 CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2840 CLK1(hsadc_pll_div),
2841 CLK1(hsadc_frac_div),
2844 CLK1(hsadc_out_inv),
2850 CLK(NULL, "smc_inv", &clkn_smc),
2852 CLK("rk29xx_spim.0", "spi", &clk_spi0),
2853 CLK("rk29xx_spim.1", "spi", &clk_spi1),
2855 CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2856 CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2860 CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2861 CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2862 CLK("rk_serial.0", "uart", &clk_uart0),
2863 CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2864 CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2865 CLK("rk_serial.1", "uart", &clk_uart1),
2866 CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2867 CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2868 CLK("rk_serial.2", "uart", &clk_uart2),
2869 CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2870 CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2871 CLK("rk_serial.3", "uart", &clk_uart3),
2881 /*************************aclk_cpu***********************/
2884 CLK1(aclk_strc_sys),
2886 /*************************hclk_cpu***********************/
2888 CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2890 CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2903 /*************************pclk_cpu***********************/
2907 CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2908 CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2914 CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2915 CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2916 CLK1(pclk_ddrupctl),
2922 /*************************aclk_periph***********************/
2926 CLK1(aclk_peri_niu),
2927 CLK1(aclk_cpu_peri),
2928 CLK1(aclk_peri_axi_matrix),
2930 /*************************hclk_periph***********************/
2931 CLK1(hclk_peri_axi_matrix),
2932 CLK1(hclk_peri_ahb_arbi),
2933 CLK1(hclk_emem_peri),
2936 CLK1(hclk_usb_peri),
2941 CLK1(hclk_pidfilter),
2942 CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2943 CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2946 /*************************pclk_periph***********************/
2947 CLK1(pclk_peri_axi_matrix),
2950 CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2951 CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2952 CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2953 CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2954 CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2955 CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2956 CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2960 /*************************aclk_lcdc0***********************/
2962 CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2966 /*************************aclk_lcdc1***********************/
2968 CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2970 /************************power domain**********************/
2984 static void __init rk30_init_enable_clocks(void)
2987 //clk_enable_nolock(&xin24m);
2988 //clk_enable_nolock(&clk_12m);
2989 //clk_enable_nolock(&arm_pll_clk);
2990 //clk_enable_nolock(&ddr_pll_clk);
2991 //clk_enable_nolock(&codec_pll_clk);
2992 //clk_enable_nolock(&general_pll_clk);
2994 clk_enable_nolock(&clk_ddr);
2995 //clk_enable_nolock(&clk_core);
2996 clk_enable_nolock(&clk_cpu_div);
2997 clk_enable_nolock(&clk_core_gpll_path);
2998 clk_enable_nolock(&clk_l2c);
2999 clk_enable_nolock(&clk_core_dbg);
3000 clk_enable_nolock(&core_periph);
3001 clk_enable_nolock(&aclk_core);
3002 //clk_enable_nolock(&aclk_cpu);
3003 //clk_enable_nolock(&pclk_cpu);
3004 clk_enable_nolock(&atclk_cpu);
3005 //clk_enable_nolock(&hclk_cpu);
3006 clk_enable_nolock(&ahb2apb_cpu);
3008 clk_enable_nolock(&clk_gpu);
3009 clk_enable_nolock(&aclk_gpu);
3010 clk_enable_nolock(&aclk_gpu_slv);
3011 clk_enable_nolock(&aclk_gpu_mst);
3013 clk_enable_nolock(&aclk_vepu);
3014 clk_enable_nolock(&hclk_vepu);
3015 clk_enable_nolock(&aclk_vdpu);
3016 clk_enable_nolock(&hclk_vdpu);
3018 clk_enable_nolock(&aclk_lcdc0_pre);
3019 clk_enable_nolock(&aclk_lcdc1_pre);
3021 clk_enable_nolock(&aclk_periph);
3022 clk_enable_nolock(&pclk_periph);
3023 clk_enable_nolock(&hclk_periph);
3026 clk_enable_nolock(&dclk_lcdc0);
3027 clk_enable_nolock(&dclk_lcdc1);
3029 clk_enable_nolock(&cif_out_pll);
3030 clk_enable_nolock(&cif0_out_div);
3032 clk_enable_nolock(&cif0_out);
3033 clk_enable_nolock(&pclkin_cif0);
3034 clk_enable_nolock(&inv_cif0);
3035 clk_enable_nolock(&cif0_in);
3037 clk_enable_nolock(&clk_i2s_pll);
3038 clk_enable_nolock(&clk_i2s0_div);
3039 clk_enable_nolock(&clk_i2s0_frac_div);
3040 clk_enable_nolock(&clk_i2s0);
3043 clk_enable_nolock(&clk_i2s0_div);
3044 clk_enable_nolock(&clk_i2s0_frac_div);
3045 clk_enable_nolock(&clk_i2s0);
3047 clk_enable_nolock(&clk_spdif_div);
3048 clk_enable_nolock(&clk_spdif_frac_div);
3049 clk_enable_nolock(&clk_spdif);
3052 clk_enable_nolock(&clk_otgphy0);
3053 clk_enable_nolock(&clk_otgphy1);
3054 clk_enable_nolock(&clk_otgphy0_480m);
3055 clk_enable_nolock(&clk_otgphy1_480m);
3056 clk_enable_nolock(&clk_hsicphy_480m);
3057 clk_enable_nolock(&clk_hsicphy_12m);
3061 clk_enable_nolock(&rmii_clkin);
3062 clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
3063 clk_enable_nolock(&clk_mac_ref);
3064 clk_enable_nolock(&clk_mii_tx);
3068 clk_enable_nolock(&clk_hsadc_pll_div);
3069 clk_enable_nolock(&clk_hsadc_frac_div);
3070 clk_enable_nolock(&clk_hsadc_ext);
3071 clk_enable_nolock(&clk_hsadc_out);
3072 clk_enable_nolock(&clk_hsadc_out_inv);
3073 clk_enable_nolock(&clk_hsadc);
3075 clk_enable_nolock(&clk_saradc);
3078 clk_enable_nolock(&clk_smc);
3079 clk_enable_nolock(&clkn_smc);
3082 clk_enable_nolock(&clk_spi0);
3083 clk_enable_nolock(&clk_spi1);
3086 clk_enable_nolock(&clk_sdmmc);
3087 clk_enable_nolock(&clk_sdio);
3088 clk_enable_nolock(&clk_emmc);
3091 clk_enable_nolock(&clk_uart_pll);
3092 clk_enable_nolock(&clk_uart0_div);
3093 clk_enable_nolock(&clk_uart0_frac_div);
3094 clk_enable_nolock(&clk_uart0);
3095 clk_enable_nolock(&clk_uart1_div);
3096 clk_enable_nolock(&clk_uart1_frac_div);
3097 clk_enable_nolock(&clk_uart1);
3098 clk_enable_nolock(&clk_uart2_div);
3099 clk_enable_nolock(&clk_uart2_frac_div);
3100 clk_enable_nolock(&clk_uart2);
3101 clk_enable_nolock(&clk_uart3_div);
3102 clk_enable_nolock(&clk_uart3_frac_div);
3103 clk_enable_nolock(&clk_uart3);
3105 #if CONFIG_RK_DEBUG_UART == 0
3106 clk_enable_nolock(&clk_uart0);
3107 clk_enable_nolock(&clk_pclk_uart0);
3108 #elif CONFIG_RK_DEBUG_UART == 1
3109 clk_enable_nolock(&clk_uart1);
3110 clk_enable_nolock(&clk_pclk_uart1);
3112 #elif CONFIG_RK_DEBUG_UART == 2
3113 clk_enable_nolock(&clk_uart2);
3114 clk_enable_nolock(&clk_pclk_uart2);
3116 #elif CONFIG_RK_DEBUG_UART == 3
3117 clk_enable_nolock(&clk_uart3);
3118 clk_enable_nolock(&clk_pclk_uart3);
3122 clk_enable_nolock(&clk_timer0);
3123 clk_enable_nolock(&clk_timer1);
3124 clk_enable_nolock(&clk_timer2);
3127 /*************************aclk_cpu***********************/
3128 clk_enable_nolock(&clk_dma1);
3129 clk_enable_nolock(&clk_intmem);
3130 clk_enable_nolock(&clk_aclk_strc_sys);
3132 /*************************hclk_cpu***********************/
3133 clk_enable_nolock(&clk_rom);
3135 clk_enable_nolock(&clk_hclk_i2s0_2ch);
3137 clk_enable_nolock(&clk_hclk_i2s0_2ch);
3138 clk_enable_nolock(&clk_hclk_spdif);
3140 clk_enable_nolock(&clk_hclk_cpubus);
3141 clk_enable_nolock(&clk_hclk_ahb2apb);
3142 clk_enable_nolock(&clk_hclk_vio_bus);
3144 clk_enable_nolock(&clk_hclk_lcdc0);
3145 clk_enable_nolock(&clk_hclk_lcdc1);
3146 clk_enable_nolock(&clk_hclk_cif0);
3147 clk_enable_nolock(&clk_hclk_ipp);
3148 clk_enable_nolock(&clk_hclk_rga);
3150 clk_enable_nolock(&clk_hclk_imem0);
3151 clk_enable_nolock(&clk_hclk_imem1);
3153 /*************************pclk_cpu***********************/
3155 clk_enable_nolock(&clk_pwm01);
3156 clk_enable_nolock(&clk_pclk_timer0);
3157 clk_enable_nolock(&clk_pclk_timer1);
3158 clk_enable_nolock(&clk_pclk_timer2);
3159 clk_enable_nolock(&clk_i2c0);
3160 clk_enable_nolock(&clk_i2c1);
3161 clk_enable_nolock(&clk_gpio0);
3162 clk_enable_nolock(&clk_gpio1);
3163 clk_enable_nolock(&clk_gpio2);
3164 clk_enable_nolock(&clk_efuse);
3166 clk_enable_nolock(&clk_tzpc);
3167 //clk_enable_nolock(&clk_pclk_uart0);
3168 //clk_enable_nolock(&clk_pclk_uart1);
3169 clk_enable_nolock(&clk_pclk_ddrupctl);
3170 clk_enable_nolock(&clk_pclk_ddrpubl);
3171 clk_enable_nolock(&clk_dbg);
3172 clk_enable_nolock(&clk_grf);
3173 clk_enable_nolock(&clk_pmu);
3175 /*************************aclk_periph***********************/
3176 clk_enable_nolock(&clk_dma2);
3177 clk_enable_nolock(&clk_aclk_smc);
3178 clk_enable_nolock(&clk_aclk_peri_niu);
3179 clk_enable_nolock(&clk_aclk_cpu_peri);
3180 clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3182 /*************************hclk_periph***********************/
3183 clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3184 clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3185 clk_enable_nolock(&clk_hclk_emem_peri);
3186 //clk_enable_nolock(&clk_hclk_mac);
3187 clk_enable_nolock(&clk_nandc);
3188 clk_enable_nolock(&clk_hclk_usb_peri);
3190 clk_enable_nolock(&clk_hclk_otg0);
3191 clk_enable_nolock(&clk_hclk_otg1);
3192 clk_enable_nolock(&clk_hclk_hsic);
3193 clk_enable_nolock(&clk_hclk_gps);
3194 clk_enable_nolock(&clk_hclk_hsadc);
3195 clk_enable_nolock(&clk_hclk_pidfilter);
3196 clk_enable_nolock(&clk_hclk_sdmmc);
3197 clk_enable_nolock(&clk_hclk_sdio);
3198 clk_enable_nolock(&clk_hclk_emmc);
3201 /*************************pclk_periph***********************/
3202 clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3204 clk_enable_nolock(&clk_pwm23);
3205 clk_enable_nolock(&clk_wdt);
3206 clk_enable_nolock(&clk_pclk_spi0);
3207 clk_enable_nolock(&clk_pclk_spi1);
3208 clk_enable_nolock(&clk_pclk_uart2);
3209 clk_enable_nolock(&clk_pclk_uart3);
3212 clk_enable_nolock(&clk_i2c2);
3213 clk_enable_nolock(&clk_i2c3);
3214 clk_enable_nolock(&clk_i2c4);
3215 clk_enable_nolock(&clk_gpio3);
3216 clk_enable_nolock(&clk_pclk_saradc);
3218 /*************************aclk_lcdc0***********************/
3220 //clk_enable_nolock(&clk_aclk_vio0);
3221 //clk_enable_nolock(&clk_aclk_lcdc0);
3222 //clk_enable_nolock(&clk_aclk_cif0);
3223 //clk_enable_nolock(&clk_aclk_ipp);
3225 /*************************aclk_lcdc1***********************/
3227 //clk_enable_nolock(&clk_aclk_vio1);
3228 //clk_enable_nolock(&clk_aclk_lcdc1);
3229 //clk_enable_nolock(&clk_aclk_rga);
3231 /************************power domain**********************/
3234 static void periph_clk_set_init(void)
3236 unsigned long aclk_p, hclk_p, pclk_p;
3237 unsigned long ppll_rate = general_pll_clk.rate;
3241 switch (ppll_rate) {
3243 aclk_p = 148500 * KHZ;
3244 hclk_p = aclk_p >> 1;
3245 pclk_p = aclk_p >> 2;
3248 aclk_p = aclk_p >> 3; // 0
3249 hclk_p = aclk_p >> 1;
3250 pclk_p = aclk_p >> 2;
3253 aclk_p = ppll_rate >> 1;
3254 hclk_p = aclk_p >> 0;
3255 pclk_p = aclk_p >> 1;
3259 aclk_p = ppll_rate >> 1;
3260 hclk_p = aclk_p >> 0;
3261 pclk_p = aclk_p >> 1;
3264 aclk_p = ppll_rate >> 2;
3265 hclk_p = aclk_p >> 0;
3266 pclk_p = aclk_p >> 1;
3274 clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3275 clk_set_rate_nolock(&aclk_periph, aclk_p);
3276 clk_set_rate_nolock(&hclk_periph, hclk_p);
3277 clk_set_rate_nolock(&pclk_periph, pclk_p);
3280 static void cpu_axi_init(void)
3282 unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3283 unsigned long gpll_rate = general_pll_clk.rate;
3285 switch (gpll_rate) {
3287 cpu_div_rate = gpll_rate;
3288 aclk_cpu_rate = cpu_div_rate >> 0;
3289 hclk_cpu_rate = aclk_cpu_rate >> 1;
3290 pclk_cpu_rate = aclk_cpu_rate >> 2;
3294 cpu_div_rate = gpll_rate >> 1;
3295 aclk_cpu_rate = cpu_div_rate >> 0;
3296 hclk_cpu_rate = aclk_cpu_rate >> 1;
3297 pclk_cpu_rate = aclk_cpu_rate >> 2;
3300 aclk_cpu_rate = 150 * MHZ;
3301 hclk_cpu_rate = 150 * MHZ;
3302 pclk_cpu_rate = 75 * MHZ;
3305 ahb2apb_cpu_rate = pclk_cpu_rate;
3307 clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3308 clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3309 clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3310 clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3311 clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3312 clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3315 void rk30_clock_common_i2s_init(void)
3317 unsigned long i2s_rate;
3319 if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3320 i2s_rate = 49152000;
3321 } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3322 i2s_rate = 24576000;
3323 } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3324 i2s_rate = 22579000;
3325 } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3326 i2s_rate = 12288000;
3328 i2s_rate = 49152000;
3331 if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3332 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3333 } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3334 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3336 if(general_pll_clk.rate > codec_pll_clk.rate)
3337 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3339 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3343 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3347 clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3349 clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3352 clk_set_rate_nolock(&clk_core, 816 * MHZ);
3354 periph_clk_set_init();
3357 rk30_clock_common_i2s_init();
3360 clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3361 clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3364 if(rk30_clock_flags & CLK_FLG_UART_1_3M)
3365 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3367 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3369 if(!(gpll_rate % (50 * MHZ)))
3370 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3371 else if(!(ddr_pll_clk.rate % (50 * MHZ)))
3372 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3374 CLKDATA_ERR("mac can't get 50mhz\n");
3378 //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3380 //lcdc0 lcd auto sel pll
3381 clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3382 clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3385 clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3388 clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3389 clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3390 clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3391 clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3394 //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3395 //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3397 clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3398 clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3400 clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
3401 clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3403 clk_set_rate_nolock(&clk_uart0, 49500000);
3404 clk_set_rate_nolock(&clk_sdmmc, 24750000);
3405 clk_set_rate_nolock(&clk_sdio, 24750000);
3409 static struct clk def_ops_clk = {
3410 .get_parent = clksel_get_parent,
3411 .set_parent = clksel_set_parent,
3414 #ifdef CONFIG_PROC_FS
3415 struct clk_dump_ops dump_ops;
3417 void rk_dump_clock_info(void);
3418 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3420 struct clk_lookup *lk;
3422 if (soc_is_rk3188plus()) {
3423 arm_pll_clk.recalc = plus_plls_clk_recalc;
3424 ddr_pll_clk.recalc = plus_plls_clk_recalc;
3425 codec_pll_clk.recalc = plus_plls_clk_recalc;
3426 general_pll_clk.recalc = plus_plls_clk_recalc;
3428 arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
3429 codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
3430 general_pll_clk.set_rate = plus_gpll_clk_set_rate;
3432 clk_register_dump_ops(&dump_ops);
3433 clk_register_default_ops_clk(&def_ops_clk);
3434 rk30_clock_flags = flags;
3435 for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3436 #ifdef RK30_CLK_OFFBOARD_TEST
3437 rk30_clkdev_add(lk);
3441 clk_register(lk->clk);
3443 clk_recalculate_root_clocks_nolock();
3445 loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3448 * Only enable those clocks we will need, let the drivers
3449 * enable other clocks as necessary
3451 rk30_init_enable_clocks();
3453 // print loader config
3454 CLKDATA_DBG("%s clks register dbg start\n", __func__);
3455 rk_dump_clock_info();
3456 rk30_clk_dump_regs();
3458 CLKDATA_DBG("%s clks register dbg end\n", __func__);
3461 * Disable any unused clocks left on by the bootloader
3463 //clk_disable_unused();
3464 rk30_clock_common_init(gpll, cpll);
3465 preset_lpj = loops_per_jiffy;
3468 //regfile_writel(0xc0004000,0x10c);
3469 //cru_writel(0x07000000,CRU_MISC_CON);
3472 extern int rk3188_dvfs_init(void);
3474 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3476 DVFS_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
3477 gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3478 _rk30_clock_data_init(gpll, cpll, flags);
3483 * You can override arm_clk rate with armclk= cmdline option.
3485 static int __init armclk_setup(char *str)
3487 get_option(&str, &armclk);
3493 //clk_set_rate_nolock(&arm_pll_clk, armclk);
3496 #ifndef RK30_CLK_OFFBOARD_TEST
3497 early_param("armclk", armclk_setup);
3501 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3505 unsigned long rate = clk->rate;
3506 //CLKDATA_DBG("dump_clock %s\n",clk->name);
3507 for (i = 0; i < deep; i++)
3510 printk("%-11s ", clk->name);
3511 #ifndef RK30_CLK_OFFBOARD_TEST
3512 if (clk->flags & IS_PD) {
3513 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3516 if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3517 int idx = clk->gate_idx;
3519 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3520 printk("%s ", v ? "off" : "on ");
3525 u32 pll_id = clk->pll->id;
3526 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3527 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3529 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3531 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3534 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3536 } else if(clk == &clk_ddr) {
3537 rate = clk->recalc(clk);
3542 printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3544 printk("%ld MHz", rate / MHZ);
3545 } else if (rate >= KHZ) {
3547 printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3549 printk("%ld KHz", rate / KHZ);
3551 printk("%ld Hz", rate);
3554 printk(" usecount = %d", clk->usecount);
3557 printk(" parent = %s", clk->parent->name);
3561 list_for_each_entry(ck, root_clocks, node) {
3562 if (ck->parent == clk)
3563 rk_dump_clock(ck, deep + 1, root_clocks);
3568 struct list_head *get_rk_clocks_head(void);
3570 void rk_dump_clock_info(void)
3573 list_for_each_entry(clk, get_rk_clocks_head(), node) {
3575 rk_dump_clock(clk, 0,get_rk_clocks_head());
3580 #ifdef CONFIG_PROC_FS
3582 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3586 unsigned long rate = clk->rate;
3587 //CLKDATA_DBG("dump_clock %s\n",clk->name);
3588 for (i = 0; i < deep; i++)
3591 seq_printf(s, "%-11s ", clk->name);
3592 #ifndef RK30_CLK_OFFBOARD_TEST
3593 if (clk->flags & IS_PD) {
3594 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3597 if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3598 int idx = clk->gate_idx;
3600 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3601 seq_printf(s, "%s ", v ? "off" : "on ");
3606 u32 pll_id = clk->pll->id;
3607 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3608 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3609 seq_printf(s, "slow ");
3610 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3611 seq_printf(s, "normal ");
3612 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3613 seq_printf(s, "deep ");
3615 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3616 seq_printf(s, "bypass ");
3617 } else if(clk == &clk_ddr) {
3618 rate = clk->recalc(clk);
3623 seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3625 seq_printf(s, "%ld MHz", rate / MHZ);
3626 } else if (rate >= KHZ) {
3628 seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3630 seq_printf(s, "%ld KHz", rate / KHZ);
3632 seq_printf(s, "%ld Hz", rate);
3635 seq_printf(s, " usecount = %d", clk->usecount);
3638 seq_printf(s, " parent = %s", clk->parent->name);
3640 seq_printf(s, "\n");
3642 list_for_each_entry(ck, root_clocks, node) {
3643 if (ck->parent == clk)
3644 dump_clock(s, ck, deep + 1, root_clocks);
3648 static void dump_regs(struct seq_file *s)
3651 seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3652 seq_printf(s, "\nPLLRegisters:\n");
3653 for(i = 0; i < END_PLL_ID; i++) {
3654 seq_printf(s, "pll%d :cons:%x,%x,%x,%x\n", i,
3655 cru_readl(PLL_CONS(i, 0)),
3656 cru_readl(PLL_CONS(i, 1)),
3657 cru_readl(PLL_CONS(i, 2)),
3658 cru_readl(PLL_CONS(i, 3))
3661 seq_printf(s, "MODE :%x\n", cru_readl(CRU_MODE_CON));
3663 for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3664 seq_printf(s, "CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3666 for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3667 seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3669 seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3670 seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3672 for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3673 seq_printf(s, "CLKGATE%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3675 seq_printf(s, "CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
3676 seq_printf(s, "GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
3680 void rk30_clk_dump_regs(void)
3683 printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3684 printk("\nPLLRegisters:\n");
3685 for(i = 0; i < END_PLL_ID; i++) {
3686 printk("pll%d :cons:%x,%x,%x,%x\n", i,
3687 cru_readl(PLL_CONS(i, 0)),
3688 cru_readl(PLL_CONS(i, 1)),
3689 cru_readl(PLL_CONS(i, 2)),
3690 cru_readl(PLL_CONS(i, 3))
3693 printk("MODE :%x\n", cru_readl(CRU_MODE_CON));
3695 for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3696 printk("CLKSEL%d :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3698 for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3699 printk("CLKGATE%d :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3701 printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3702 printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3704 for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3705 printk("SOFTRST%d :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3707 printk("CRU MISC :%x\n", cru_readl(CRU_MISC_CON));
3708 printk("GLB_CNT_TH :%x\n", cru_readl(CRU_GLB_CNT_TH));
3713 #ifdef CONFIG_PROC_FS
3714 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3715 struct clk_dump_ops dump_ops = {
3716 .dump_clk = dump_clock,
3717 .dump_regs = dump_regs,
3722 #endif /* CONFIG_PROC_FS */
3727 #ifdef RK30_CLK_OFFBOARD_TEST
3728 struct clk *test_get_parent(struct clk *clk) {
3734 struct clk *i2s_clk = &clk_i2s0;
3736 clk_enable_nolock(i2s_clk);
3738 clk_set_rate_nolock(i2s_clk, 12288000);
3739 printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3740 clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3741 printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3742 clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3743 printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3747 void uart_test(void)
3749 struct clk *uart_clk = &clk_uart0;
3751 clk_enable_nolock(uart_clk);
3753 clk_set_rate_nolock(uart_clk, 12288000);
3754 printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3755 clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3756 printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3757 clk_set_rate_nolock(uart_clk, 12 * MHZ);
3758 printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3761 void hsadc_test(void)
3763 struct clk *hsadc_clk = &clk_hsadc;
3765 printk("******************hsadc_test**********************\n");
3766 clk_enable_nolock(hsadc_clk);
3768 clk_set_rate_nolock(hsadc_clk, 12288000);
3769 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3772 clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3773 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3775 clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3777 clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3779 printk("******************hsadc out clock**********************\n");
3781 clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3782 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3783 clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3784 printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3790 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3793 printk("*********arm_pll_clk***********\n");
3794 clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3796 printk("*********set clk_core parent***********\n");
3797 clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3798 clk_set_rate_nolock(&clk_core, 504 * MHZ);
3801 printk("*********general_pll_clk***********\n");
3802 clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3805 printk("*********codec_pll_clk***********\n");
3806 clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3809 printk("*********periph_clk_set_init***********\n");
3810 clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3811 periph_clk_set_init();
3814 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3816 printk("*********clk i2s***********\n");
3817 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3818 printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3822 clk_enable_nolock(&clk_spi0);
3823 clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3824 printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3826 clk_enable_nolock(&clk_saradc);
3827 clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3828 printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3830 clk_enable_nolock(&clk_sdio);
3831 clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3832 printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3834 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3837 printk("*********mac***********\n");
3839 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3840 printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3842 //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3843 clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3844 printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3846 printk("*********mac mii set***********\n");
3847 clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3848 clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3849 printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3851 printk("*********hsadc 1***********\n");
3855 clk_enable_nolock(&dclk_lcdc0);
3857 clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
3858 clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
3861 clk_enable_nolock(&cif0_out);
3863 clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3864 printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
3866 clk_set_rate_nolock(&cif0_out, 60 * MHZ);
3867 printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3869 clk_set_rate_nolock(&cif0_out, 24 * MHZ);
3870 printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3872 clk_enable_nolock(&cif0_in);
3873 clk_set_rate_nolock(&cif0_in, 24 * MHZ);
3875 clk_enable_nolock(&aclk_lcdc0);
3876 clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
3877 printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
3879 clk_enable_nolock(&aclk_vepu);
3880 clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3881 printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
3883 clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
3884 printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
3886 printk("test end\n");
3889 clk_set_rate_nolock(&arm_pll_clk, armclk);
3890 clk_set_rate_nolock(&clk_core, armclk);//pll:core =1:1
3893 //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3895 //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3896 //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3904 static LIST_HEAD(rk30_clocks);
3905 static DEFINE_MUTEX(rk30_clocks_mutex);
3907 static inline int __rk30clk_get(struct clk *clk)
3911 void rk30_clkdev_add(struct clk_lookup *cl)
3913 mutex_lock(&rk30_clocks_mutex);
3914 list_add_tail(&cl->node, &rk30_clocks);
3915 mutex_unlock(&rk30_clocks_mutex);
3917 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
3918 struct clk_lookup *p, *cl = NULL;
3919 int match, best = 0;
3921 list_for_each_entry(p, &rk30_clocks, node) {
3924 if (!dev_id || strcmp(p->dev_id, dev_id))
3929 if (!con_id || strcmp(p->con_id, con_id))
3945 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
3946 struct clk_lookup *cl;
3948 mutex_lock(&rk30_clocks_mutex);
3949 cl = rk30_clk_find(dev_id, con_id);
3950 if (cl && !__rk30clk_get(cl->clk))
3952 mutex_unlock(&rk30_clocks_mutex);
3954 return cl ? cl->clk : ERR_PTR(-ENOENT);
3956 //EXPORT_SYMBOL(rk30_clk_get_sys);
3958 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
3959 const char *dev_id = dev ? dev_name(dev) : NULL;
3960 return rk30_clk_get_sys(dev_id, con_id);
3962 //EXPORT_SYMBOL(rk30_clk_get);
3965 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3967 void rk30_clocks_test(void)
3969 struct clk *test_gpll;
3970 test_gpll = rk30_clk_get(NULL, "general_pll");
3972 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
3973 printk("gpll rate=%lu\n", test_gpll->rate);
3978 void __init rk30_clock_init_test(void)
3981 rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);