arch/arm/mach-rk3188/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include <mach/clock.h>
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29 #include <mach/ddr.h>
  30 #include <mach/cpu.h>
  31
  32 #define MHZ                     (1000UL * 1000UL)
  33 #define KHZ                     (1000UL)
  34 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  35 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
  36 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  37 void rk30_clk_dump_regs(void);
  38
  39 //flags bit
  40 //has extern 27mhz
  41 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  42 //max i2s rate
  43 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  44 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  45 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  46 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  47 //uart 1m\3m
  48 #define CLK_FLG_UART_1_3M                       (1<<5)
  49
  50 #define ARCH_RK31
  51
  52 struct apll_clk_set {
  53         unsigned long   rate;
  54         u32     pllcon0;
  55         u32     pllcon1;
  56         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  57         u32     rst_dly;//us
  58         u32     clksel0;
  59         u32     clksel1;
  60         unsigned long   lpj;
  61 };
  62 struct pll_clk_set {
  63         unsigned long   rate;
  64         u32     pllcon0;
  65         u32     pllcon1;
  66         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  67         unsigned long   rst_dly;//us
  68 };
  69
  70 #define SET_PLL_DATA(_pll_id,_table) \
  71 {\
  72         .id=(_pll_id),\
  73         .table=(_table),\
  74 }
  75
  76
  77 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  78 { \
  79         .rate   = (_mhz) * KHZ, \
  80         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  81         .pllcon1 = PLL_CLKF_SET(nf),\
  82         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  83         .rst_dly=((nr*500)/24+1),\
  84 }
  85
  86
  87 #define _APLL_SET_LPJ(_mhz) \
  88         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  89
  90
  91 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  92                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  93 { \
  94         .rate   = _mhz * MHZ, \
  95         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  96         .pllcon1 = PLL_CLKF_SET(nf),\
  97         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  98         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
  99         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
 100         _APLL_SET_LPJ(_mhz),\
 101         .rst_dly=((nr*500)/24+1),\
 102 }
 103
 104 #define CRU_DIV_SET(mask,shift,max) \
 105         .div_mask=(mask),\
 106 .div_shift=(shift),\
 107 .div_max=(max)
 108
 109
 110 #define CRU_SRC_SET(mask,shift ) \
 111         .src_mask=(mask),\
 112 .src_shift=(shift)
 113
 114 #define CRU_PARENTS_SET(parents_array) \
 115         .parents=(parents_array),\
 116 .parents_num=ARRAY_SIZE((parents_array))
 117
 118 #define CRU_GATE_MODE_SET(_func,_IDX) \
 119         .mode=_func,\
 120 .gate_idx=(_IDX)
 121
 122 struct clk_src_sel {
 123         struct clk      *parent;
 124         u8      value;//crt bit
 125         u8      flag;
 126         //selgate
 127 };
 128
 129 #define GATE_CLK(NAME,PARENT,ID) \
 130         static struct clk clk_##NAME = { \
 131                 .name           = #NAME, \
 132                 .parent         = &PARENT, \
 133                 .mode           = gate_mode, \
 134                 .gate_idx       = CLK_GATE_##ID, \
 135         }
 136 #ifdef RK30_CLK_OFFBOARD_TEST
 137 u32 TEST_GRF_REG[0x240];
 138 u32 TEST_CRU_REG[0x240];
 139 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 140
 141 u32 cru_writel_is_pr(u32 offset)
 142 {
 143         return (offset == 0x4000);
 144 }
 145 void cru_writel(u32 v, u32 offset)
 146 {
 147
 148         u32 mask_v = v >> 16;
 149         TEST_CRU_REG[offset/4] &= (~mask_v);
 150
 151         v &= (mask_v);
 152
 153         TEST_CRU_REG[offset/4] |= v;
 154         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 155
 156         if(cru_writel_is_pr(offset)) {
 157                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 158
 159         }
 160
 161 }
 162 void cru_writel_i2s(u32 v, u32 offset)
 163 {
 164         TEST_CRU_REG[offset/4] = v;
 165 }
 166 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 167
 168 #define regfile_readl(offset)   (0xffffffff)
 169 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 170 void rk30_clkdev_add(struct clk_lookup *cl);
 171 #else
 172 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 173 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 174 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 175 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 176
 177 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 178 #endif
 179
 180 //#define DEBUG
 181 #ifdef DEBUG
 182 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 183 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 184 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
 185 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
 186 #else
 187 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 188 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 189 #endif
 190 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 191 #define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
 192
 193
 194 #define get_cru_bits(con,mask,shift)\
 195         ((cru_readl((con)) >> (shift)) & (mask))
 196
 197 #define set_cru_bits_w_msk(val,mask,shift,con)\
 198         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 199
 200
 201 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 202                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 203
 204
 205 static u32 rk30_clock_flags = 0;
 206 static struct clk codec_pll_clk;
 207 static struct clk general_pll_clk;
 208 static struct clk arm_pll_clk;
 209 static unsigned long lpj_gpll;
 210 static unsigned int __initdata armclk = 504 * MHZ;
 211
 212
 213 /************************clk recalc div rate*********************************/
 214
 215 //for free div
 216 static unsigned long clksel_recalc_div(struct clk *clk)
 217 {
 218         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 219
 220         unsigned long rate = clk->parent->rate / div;
 221         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 222         return rate;
 223 }
 224
 225 //for div 1 2 4 2^n
 226 static unsigned long clksel_recalc_shift(struct clk *clk)
 227 {
 228         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 229         unsigned long rate = clk->parent->rate >> shift;
 230         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 231         return rate;
 232 }
 233
 234
 235 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 236 {
 237         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 238         unsigned long rate = clk->parent->rate >> shift;
 239         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 240         return rate;
 241 }
 242
 243 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 244 {
 245         unsigned long rate = clk->parent->rate;
 246         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 247         return rate;
 248 }
 249 /********************************set div rate***********************************/
 250
 251 //for free div
 252 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 253 {
 254         u32 div;
 255         for (div = 0; div < clk->div_max; div++) {
 256                 u32 new_rate = clk->parent->rate / (div + 1);
 257                 if (new_rate <= rate) {
 258                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 259                         //clk->rate = new_rate;
 260                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 261                                         clk->name, rate, div + 1);
 262                         return 0;
 263                 }
 264         }
 265         return -ENOENT;
 266 }
 267
 268 //for div 1 2 4 2^n
 269 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 270 {
 271         u32 shift;
 272         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 273                 u32 new_rate = clk->parent->rate >> shift;
 274                 if (new_rate <= rate) {
 275                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 276                         clk->rate = new_rate;
 277                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 278                                         clk->name, rate, shift);
 279                         return 0;
 280                 }
 281         }
 282         return -ENOENT;
 283 }
 284
 285 //for div 2 4 2^n
 286 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 287 {
 288         u32 shift;
 289
 290         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 291                 u32 new_rate = clk->parent->rate >> shift;
 292                 if (new_rate <= rate) {
 293                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 294                         clk->rate = new_rate;
 295                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 296                                         clk->name, rate, shift);
 297                         return 0;
 298                 }
 299         }
 300         return -ENOENT;
 301 }
 302
 303 //for div 1 2 4 2*n
 304 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 305 {
 306         u32 div;
 307         for (div = 2; div < clk->div_max; div += 2) {
 308                 u32 new_rate = clk->parent->rate / div;
 309                 if (new_rate <= rate) {
 310                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 311                         clk->rate = new_rate;
 312                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 313                                         __func__, clk->name, rate, div);
 314                         return 0;
 315                 }
 316         }
 317         return -ENOENT;
 318 }
 319 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 320 {
 321         u32 div;
 322         unsigned long new_rate;
 323         for (div = 0; div < div_max; div++) {
 324                 new_rate = rate / (div + 1);
 325                 if (new_rate <= rate_out) {
 326                         return div + 1;
 327                 }
 328         }
 329         return div_max ? div_max : 1;
 330 }
 331 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 332 {
 333         u32 div;
 334         unsigned long new_rate;
 335         for (div = 1; div < div_max; div += 2) {
 336                 new_rate = rate / (div + 1);
 337                 if (new_rate <= rate_out) {
 338                         return div + 1;
 339                 }
 340         }
 341         return div_max ? div_max : 1;
 342 }
 343 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 344         u32 div[2] = {0, 0};
 345         unsigned long new_rate[2] = {0, 0};
 346         u32 i;
 347
 348         if(clk->rate == rate)
 349                 return clk->parent;
 350         for(i = 0; i < 2; i++) {
 351                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 352                 new_rate[i] = clk->parents[i]->rate / div[i];
 353                 if(new_rate[i] == rate) {
 354                         *div_out = div[i];
 355                         return clk->parents[i];
 356                 }
 357         }
 358         if(new_rate[0] < new_rate[1])
 359                 i = 1;
 360         else
 361                 i = 0;
 362         *div_out = div[i];
 363         return clk->parents[i];
 364 }
 365 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 366         u32 div[2] = {0, 0};
 367         unsigned long new_rate[2] = {0, 0};
 368         u32 i;
 369
 370         if(clk->rate == rate)
 371                 return clk->parent;
 372         for(i = 0; i < 2; i++) {
 373                 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 374                 new_rate[i] = clk->parents[i]->rate / div[i];
 375                 if(new_rate[i] == rate) {
 376                         *div_out = div[i];
 377                         return clk->parents[i];
 378                 }
 379         }
 380         if(new_rate[0] < new_rate[1])
 381                 i = 1;
 382         else
 383                 i = 0;
 384         *div_out = div[i];
 385         return clk->parents[i];
 386 }
 387
 388 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 389 {
 390         struct clk *p_clk;
 391         u32 div, old_div;
 392         int ret = 0;
 393         if(clk->rate == rate)
 394                 return 0;
 395         p_clk = get_freediv_parents_div(clk, rate, &div);
 396
 397         if(!p_clk)
 398                 return -ENOENT;
 399
 400         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 401         if (clk->parent != p_clk) {
 402                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 403
 404                 if(div > old_div) {
 405                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 406                 }
 407                 ret = clk_set_parent_nolock(clk, p_clk);
 408                 if(ret) {
 409                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 410                         return -ENOENT;
 411                 }
 412         }
 413         //set div
 414         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 415         return 0;
 416 }
 417 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 418 {
 419         struct clk *p_clk;
 420         u32 div, old_div;
 421         int ret = 0;
 422         if(clk->rate == rate)
 423                 return 0;
 424         p_clk = get_evendiv_parents_div(clk, rate, &div);
 425
 426         if(!p_clk)
 427                 return -ENOENT;
 428
 429         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 430         if (clk->parent != p_clk) {
 431                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 432
 433                 if(div > old_div) {
 434                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 435                 }
 436                 ret = clk_set_parent_nolock(clk, p_clk);
 437                 if(ret) {
 438                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 439                         return -ENOENT;
 440                 }
 441         }
 442         //set div
 443         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 444         return 0;
 445 }
 446
 447 //rate==div rate //hdmi
 448 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 449 {
 450         struct clk *p_clk;
 451         u32 div, old_div;
 452         int ret;
 453         p_clk = get_freediv_parents_div(clk, rate, &div);
 454
 455         if(!p_clk)
 456                 return -ENOENT;
 457
 458         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 459                 return -ENOENT;
 460
 461         if (clk->parent != p_clk) {
 462                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 463                                 clk->div_shift, clk->div_mask) + 1;
 464                 if(div > old_div) {
 465                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 466                 }
 467                 ret = clk_set_parent_nolock(clk, p_clk);
 468                 if (ret) {
 469                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 470                         return ret;
 471                 }
 472         }
 473         //set div
 474         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 475         return 0;
 476 }
 477
 478 /***************************round********************************/
 479
 480 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 481 {
 482         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 483 }
 484
 485 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 486 {
 487         u32 div;
 488         struct clk *p_clk;
 489         if(clk->rate == rate)
 490                 return clk->rate;
 491         p_clk = get_freediv_parents_div(clk, rate, &div);
 492         if(!p_clk)
 493                 return 0;
 494         return p_clk->rate / div;
 495 }
 496
 497 /**************************************others seting************************************/
 498
 499 static struct clk *clksel_get_parent(struct clk *clk) {
 500         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 501 }
 502 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 503 {
 504         u32 i;
 505         if (unlikely(!clk->parents))
 506                 return -EINVAL;
 507         for (i = 0; (i < clk->parents_num); i++) {
 508                 if (clk->parents[i] != parent)
 509                         continue;
 510                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 511                 return 0;
 512         }
 513         return -EINVAL;
 514 }
 515
 516 static int gate_mode(struct clk *clk, int on)
 517 {
 518         int idx = clk->gate_idx;
 519         if (idx >= CLK_GATE_MAX)
 520                 return -EINVAL;
 521         if(on) {
 522                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 523                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 524                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 525         } else {
 526                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 527                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 528                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 529         }
 530         return 0;
 531 }
 532 /*****************************frac set******************************************/
 533
 534 static unsigned long clksel_recalc_frac(struct clk *clk)
 535 {
 536         unsigned long rate;
 537         u64 rate64;
 538         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 539         if (r == 0) // FPGA ?
 540                 return clk->parent->rate;
 541         numerator = r >> 16;
 542         denominator = r & 0xFFFF;
 543         rate64 = (u64)clk->parent->rate * numerator;
 544         do_div(rate64, denominator);
 545         rate = rate64;
 546         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 547         return rate;
 548 }
 549
 550 static u32 clk_gcd(u32 numerator, u32 denominator)
 551 {
 552         u32 a, b;
 553
 554         if (!numerator || !denominator)
 555                 return 0;
 556         if (numerator > denominator) {
 557                 a = numerator;
 558                 b = denominator;
 559         } else {
 560                 a = denominator;
 561                 b = numerator;
 562         }
 563         while (b != 0) {
 564                 int r = b;
 565                 b = a % b;
 566                 a = r;
 567         }
 568
 569         return a;
 570 }
 571
 572 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 573                 u32 *numerator, u32 *denominator)
 574 {
 575         u32 gcd_vl;
 576         gcd_vl = clk_gcd(rate, rate_out);
 577         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 578
 579         if (!gcd_vl) {
 580                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 581                 return -ENOENT;
 582         }
 583
 584         *numerator = rate_out / gcd_vl;
 585         *denominator = rate / gcd_vl;
 586
 587         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 588                         *numerator, *denominator, *denominator / *numerator);
 589
 590         if (*numerator > 0xffff || *denominator > 0xffff ||
 591                         (*denominator / (*numerator)) < 20) {
 592                 CLKDATA_ERR("can't get a available nume and deno\n");
 593                 return -ENOENT;
 594         }
 595
 596         return 0;
 597
 598 }
 599 /* *********************pll **************************/
 600
 601 #define rk30_clock_udelay(a) udelay(a);
 602
 603 /*********************pll lock status**********************************/
 604 //#define GRF_SOC_CON0       0x15c
 605 static void pll_wait_lock(int pll_idx)
 606 {
 607         u32 pll_state[4] = {1, 0, 2, 3};
 608         u32 bit = 0x20u << pll_state[pll_idx];
 609         int delay = 24000000;
 610         while (delay > 0) {
 611                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 612                         break;
 613                 delay--;
 614         }
 615         if (delay == 0) {
 616                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 617                 while(1);
 618         }
 619 }
 620
 621
 622
 623 /***************************pll function**********************************/
 624 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 625 {
 626         unsigned long rate;
 627
 628         if (PLLS_IN_NORM(pll_id)) {
 629                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 630                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 631
 632
 633                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 634
 635                 /*
 636                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 637                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 638                    */
 639
 640
 641                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 642                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 643                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 644
 645                 do_div(rate64, PLL_NR(pll_con0));
 646                 do_div(rate64, PLL_NO(pll_con0));
 647
 648                 rate = rate64;
 649                 /*
 650                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 651                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 652                    */
 653         } else {
 654                 rate = parent_rate;
 655                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 656         }
 657         return rate;
 658 }
 659 static unsigned long plls_clk_recalc(struct clk *clk)
 660 {
 661         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 662 }
 663 static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 664 {
 665         unsigned long rate;
 666
 667         if (PLLS_IN_NORM(pll_id)) {
 668                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 669                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 670
 671                 u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
 672
 673                 do_div(rate64, PLUS_PLL_NR(pll_con0));
 674                 do_div(rate64, PLUS_PLL_NO(pll_con0));
 675
 676                 rate = rate64;
 677         } else {
 678                 rate = parent_rate;
 679                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 680         }
 681         return rate;
 682 }
 683 static unsigned long plus_plls_clk_recalc(struct clk *clk)
 684 {
 685         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 686         return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
 687 }
 688
 689 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 690 {
 691         //enter slowmode
 692         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 693         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 694         dsb();
 695         dsb();
 696         dsb();
 697         dsb();
 698         dsb();
 699         dsb();
 700         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 701         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 702
 703         rk30_clock_udelay(1);
 704         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 705
 706         pll_wait_lock(pll_id);
 707
 708         //return form slow
 709         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 710
 711         /*
 712            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 713            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 714            */
 715
 716         return 0;
 717 }
 718
 719 static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 720 {
 721         //enter slowmode
 722         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 723
 724         //enter rest
 725         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
 726         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 727         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 728         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
 729         rk30_clock_udelay(5);
 730
 731         //return form rest
 732         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
 733
 734         //wating lock state
 735         rk30_clock_udelay(clk_set->rst_dly);
 736         pll_wait_lock(pll_id);
 737
 738         //return form slow
 739         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 740
 741         return 0;
 742 }
 743
 744 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 745 {
 746         struct _pll_data *pll_data = c->pll;
 747         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 748
 749         while(clk_set->rate) {
 750                 if (clk_set->rate == rate) {
 751                         break;
 752                 }
 753                 clk_set++;
 754         }
 755         if(clk_set->rate == rate) {
 756                 pll_clk_set_rate(clk_set, pll_data->id);
 757                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 758         } else {
 759                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 760                 return -1;
 761         }
 762         return 0;
 763 }
 764
 765 static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
 766 {
 767         struct _pll_data *pll_data = c->pll;
 768         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 769         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 770
 771         while(clk_set->rate) {
 772                 if (clk_set->rate == rate) {
 773                         break;
 774                 }
 775                 clk_set++;
 776         }
 777         if(clk_set->rate == rate) {
 778                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 779                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 780         } else {
 781                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 782                 return -1;
 783         }
 784         return 0;
 785 }
 786 #define PLL_FREF_MIN (183*KHZ)
 787 #define PLL_FREF_MAX (1500*MHZ)
 788
 789 #define PLL_FVCO_MIN (300*MHZ)
 790 #define PLL_FVCO_MAX (1500*MHZ)
 791
 792 #define PLL_FOUT_MIN (18750*KHZ)
 793 #define PLL_FOUT_MAX (1500*MHZ)
 794
 795 #define PLL_NF_MAX (65536)
 796 #define PLL_NR_MAX (64)
 797 #define PLL_NO_MAX (64)
 798
 799 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 800 {
 801         u32 nr, nf, no, nonr;
 802         u32 n;
 803         u32 YFfenzi;
 804         u32 YFfenmu;
 805         unsigned long fref, fvco, fout;
 806         u32 gcd_val = 0;
 807
 808         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 809         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 810                 return 0;
 811         gcd_val = clk_gcd(fin_hz, fout_hz);
 812         YFfenzi = fout_hz / gcd_val;
 813         YFfenmu = fin_hz / gcd_val;
 814
 815         for(n = 1;; n++) {
 816                 nf = YFfenzi * n;
 817                 nonr = YFfenmu * n;
 818                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 819                         break;
 820                 for(no = 1; no <= PLL_NO_MAX; no++) {
 821                         if(!(no == 1 || !(no % 2)))
 822                                 continue;
 823
 824                         if(nonr % no)
 825                                 continue;
 826                         nr = nonr / no;
 827
 828                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 829                                 continue;
 830
 831                         fref = fin_hz / nr;
 832                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 833                                 continue;
 834
 835                         fvco = (fin_hz / nr) * nf;
 836                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 837                                 continue;
 838                         fout = fvco / no;
 839                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 840                                 continue;
 841                         *clk_nr = nr;
 842                         *clk_no = no;
 843                         *clk_nf = nf;
 844                         return 1;
 845
 846                 }
 847
 848         }
 849         return 0;
 850 }
 851
 852 static int pll_clk_mode(struct clk *clk, int on)
 853 {
 854         u8 pll_id = clk->pll->id;
 855         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 856         u32 dly = (nr * 500) / 24 + 1;
 857         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 858         if (on) {
 859                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 860                 rk30_clock_udelay(dly);
 861                 pll_wait_lock(pll_id);
 862                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 863         } else {
 864                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 865                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 866         }
 867         return 0;
 868 }
 869
 870 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 871 {
 872         struct _pll_data *pll_data = c->pll;
 873         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 874         struct pll_clk_set temp_clk_set;
 875         u32 clk_nr, clk_nf, clk_no;
 876
 877
 878         while(clk_set->rate) {
 879                 if (clk_set->rate == rate) {
 880                         break;
 881                 }
 882                 clk_set++;
 883         }
 884         if(clk_set->rate == rate) {
 885                 CLKDATA_DBG("cpll get a rate\n");
 886                 pll_clk_set_rate(clk_set, pll_data->id);
 887
 888         } else {
 889                 CLKDATA_DBG("cpll get auto calc a rate\n");
 890                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 891                         pr_err("cpll auto set rate error\n");
 892                         return -ENOENT;
 893                 }
 894                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 895                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 896                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 897                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 898                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 899
 900         }
 901         return 0;
 902 }
 903 static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
 904 {
 905         struct _pll_data *pll_data = c->pll;
 906         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 907         struct pll_clk_set temp_clk_set;
 908         u32 clk_nr, clk_nf, clk_no;
 909         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 910
 911         while(clk_set->rate) {
 912                 if (clk_set->rate == rate) {
 913                         break;
 914                 }
 915                 clk_set++;
 916         }
 917         if(clk_set->rate == rate) {
 918                 CLKDATA_DBG("cpll get a rate\n");
 919                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 920
 921         } else {
 922                 CLKDATA_DBG("cpll get auto calc a rate\n");
 923                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 924                         pr_err("cpll auto set rate error\n");
 925                         return -ENOENT;
 926                 }
 927                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 928                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 929                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 930                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 931                 plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
 932
 933         }
 934         return 0;
 935 }
 936
 937
 938 /* ******************fixed input clk ***********************************************/
 939 static struct clk xin24m = {
 940         .name           = "xin24m",
 941         .rate           = 24 * MHZ,
 942         .flags          = RATE_FIXED,
 943 };
 944
 945 static struct clk clk_12m = {
 946         .name           = "clk_12m",
 947         .parent         = &xin24m,
 948         .rate           = 12 * MHZ,
 949         .flags          = RATE_FIXED,
 950 };
 951
 952 /************************************pll func***************************/
 953 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 954                 struct apll_clk_set *tables) {
 955         const struct apll_clk_set *ps, *pt;
 956
 957         /* find the arm_pll we want. */
 958         ps = pt = tables;
 959         while (pt->rate) {
 960                 if (pt->rate == rate) {
 961                         ps = pt;
 962                         break;
 963                 }
 964                 // we are sorted, and ps->rate > pt->rate.
 965                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 966                         ps = pt;
 967                 if (pt->rate < rate)
 968                         break;
 969                 pt++;
 970         }
 971         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 972         return ps;
 973 }
 974 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 975 {
 976         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 977 }
 978 #if 1
 979 struct arm_clks_div_set {
 980         u32 rate;
 981         u32     clksel0;
 982         u32     clksel1;
 983 };
 984
 985 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 986 { \
 987         .rate    =_mhz,\
 988         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 989         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 990         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 991         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 992         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 993 }
 994 struct arm_clks_div_set arm_clk_div_tlb[] = {
 995         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 996         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 997         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 998         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 999         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
1000         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
1001         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
1002 };
1003 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
1004         int i = 0;
1005         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
1006                 if(arm_clk_div_tlb[i].rate >= rate)
1007                         return &arm_clk_div_tlb[i];
1008         }
1009         return NULL;
1010 }
1011
1012 #endif
1013
1014 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1015 {
1016         unsigned long flags;
1017         const struct apll_clk_set *ps;
1018         u32 pll_id = clk->pll->id;
1019         u32 temp_div;
1020         u32 old_aclk_div = 0, new_aclk_div;
1021
1022         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1023
1024         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1025         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1026
1027         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1028                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1029
1030         if(general_pll_clk.rate > clk->rate) {
1031                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1032         } else {
1033                 temp_div = 1;
1034         }
1035
1036         // ungating cpu gpll path
1037         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1038         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1039
1040         local_irq_save(flags);
1041         //div arm clk for gpll
1042
1043         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1044         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1045
1046         loops_per_jiffy = lpj_gpll / temp_div;
1047         smp_wmb();
1048
1049         /*if core src don't select gpll ,apll neet to enter slow mode */
1050         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1051
1052
1053         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
1054         dsb();
1055         dsb();
1056         dsb();
1057         dsb();
1058         dsb();
1059         dsb();
1060         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1061         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1062
1063         rk30_clock_udelay(1);
1064         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
1065
1066         pll_wait_lock(pll_id);
1067
1068         //return form slow
1069         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1070         //reparent to apll
1071
1072         if(new_aclk_div>=old_aclk_div) {
1073                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1074                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1075         }
1076
1077         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1078         if(old_aclk_div>new_aclk_div) {
1079                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1080                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1081         }
1082
1083         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1084
1085         loops_per_jiffy = ps->lpj;
1086         smp_wmb();
1087
1088         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1089
1090         local_irq_restore(flags);
1091
1092         //gate gpll path
1093         // FIXME
1094         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1095         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1096
1097         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1098                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1099                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1100                         cru_readl(CRU_CLKSELS_CON(1)));
1101         return 0;
1102 }
1103
1104 static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1105 {
1106         unsigned long flags;
1107         const struct apll_clk_set *ps;
1108         u32 pll_id = clk->pll->id;
1109         u32 temp_div;
1110         u32 old_aclk_div = 0, new_aclk_div;
1111         DVFS_DBG("%s: for rk3188 plus\n", __func__);
1112
1113         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1114
1115         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1116         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1117
1118         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1119                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1120
1121         if(general_pll_clk.rate > clk->rate) {
1122                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1123         } else {
1124                 temp_div = 1;
1125         }
1126
1127         // ungating cpu gpll path
1128         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1129         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1130
1131         local_irq_save(flags);
1132         //div arm clk for gpll
1133
1134         cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1135         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1136
1137         loops_per_jiffy = lpj_gpll / temp_div;
1138         smp_wmb();
1139
1140         /*if core src don't select gpll ,apll neet to enter slow mode */
1141         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1142
1143         //enter rest
1144         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
1145         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1146         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1147         cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
1148         rk30_clock_udelay(5);
1149
1150         //return form rest
1151         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
1152
1153         //wating lock state
1154         rk30_clock_udelay(ps->rst_dly);
1155         pll_wait_lock(pll_id);
1156
1157         if(new_aclk_div>=old_aclk_div) {
1158                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1159                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1160         }
1161
1162         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1163         if(old_aclk_div>new_aclk_div) {
1164                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1165                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1166         }
1167
1168         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1169
1170         loops_per_jiffy = ps->lpj;
1171         smp_wmb();
1172
1173         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1174
1175         local_irq_restore(flags);
1176
1177         //gate gpll path
1178         // FIXME
1179         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1180         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1181
1182         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1183                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1184                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1185                         cru_readl(CRU_CLKSELS_CON(1)));
1186         return 0;
1187 }
1188
1189 /************************************pll clocks***************************/
1190
1191 static const struct apll_clk_set apll_clks[] = {
1192         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1193         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1194         _APLL_SET_CLKS(2208, 1, 92, 1, 8,       81, 81, 21, 41, 21),
1195         _APLL_SET_CLKS(2184, 1, 91, 1, 8,       81, 81, 21, 41, 21),
1196         _APLL_SET_CLKS(2160, 1, 90, 1, 8,       81, 81, 21, 41, 21),
1197         _APLL_SET_CLKS(2136, 1, 89, 1, 8,       81, 81, 21, 41, 21),
1198         _APLL_SET_CLKS(2112, 1, 88, 1, 8,       81, 81, 21, 41, 21),
1199         _APLL_SET_CLKS(2088, 1, 87, 1, 8,       81, 81, 21, 41, 21),
1200         _APLL_SET_CLKS(2064, 1, 86, 1, 8,       81, 81, 21, 41, 21),
1201         _APLL_SET_CLKS(2040, 1, 85, 1, 8,       81, 81, 21, 41, 21),
1202         _APLL_SET_CLKS(2016, 1, 84, 1, 8,       81, 81, 21, 41, 21),
1203         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1204         _APLL_SET_CLKS(1968, 1, 82, 1, 8,       81, 81, 21, 41, 21),
1205         _APLL_SET_CLKS(1944, 1, 81, 1, 8,       81, 81, 21, 41, 21),
1206         _APLL_SET_CLKS(1920, 1, 80, 1, 8,       81, 81, 21, 41, 21),
1207         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1208         _APLL_SET_CLKS(1872, 1, 78, 1, 8,       81, 81, 21, 41, 21),
1209         _APLL_SET_CLKS(1848, 1, 77, 1, 8,       81, 81, 21, 41, 21),
1210         _APLL_SET_CLKS(1824, 1, 76, 1, 8,       81, 81, 21, 41, 21),
1211         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1212         _APLL_SET_CLKS(1776, 1, 74, 1, 8,       81, 81, 21, 41, 21),
1213         _APLL_SET_CLKS(1752, 1, 73, 1, 8,       81, 81, 21, 41, 21),
1214         _APLL_SET_CLKS(1728, 1, 72, 1, 8,       81, 81, 21, 41, 21),
1215         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1216         _APLL_SET_CLKS(1680, 1, 70, 1, 8,       41, 41, 21, 41, 21),
1217         _APLL_SET_CLKS(1656, 1, 69, 1, 8,       41, 41, 21, 41, 21),
1218         _APLL_SET_CLKS(1632, 1, 68, 1, 8,       41, 41, 21, 41, 21),
1219         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1220         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1221         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1222         _APLL_SET_CLKS(1488, 1, 62, 1, 8,       41, 41, 21, 41, 21),
1223         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1224         _APLL_SET_CLKS(1440, 1, 60, 1, 8,       41, 41, 21, 41, 21),
1225         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1226         _APLL_SET_CLKS(1392, 1, 58, 1, 8,       41, 41, 21, 41, 21),
1227         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1228         _APLL_SET_CLKS(1344, 1, 56, 1, 8,       41, 41, 21, 41, 21),
1229         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1230         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1231         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1232         _APLL_SET_CLKS(1248, 1, 52, 1, 8,       41, 41, 21, 41, 21),
1233         _APLL_SET_CLKS(1224, 1, 51, 1, 8,       41, 41, 21, 41, 21),
1234         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1235         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1236         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1237         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1238         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1239         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1240         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1241         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1242         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1243         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1244         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1245         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1246         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1247         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1248         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1249         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1250         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1251         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1252         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1253
1254 };
1255 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1256 static struct clk arm_pll_clk = {
1257         .name           = "arm_pll",
1258         .parent         = &xin24m,
1259         .mode           = pll_clk_mode,
1260         .recalc         = plls_clk_recalc,
1261         .set_rate       = arm_pll_clk_set_rate,
1262         .round_rate     = arm_pll_clk_round_rate,
1263         .pll            = &apll_data,
1264 };
1265
1266 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1267 {
1268         /* do nothing here */
1269         return 0;
1270 }
1271 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1272 static struct clk ddr_pll_clk = {
1273         .name           = "ddr_pll",
1274         .parent         = &xin24m,
1275         .recalc         = plls_clk_recalc,
1276         .set_rate       = ddr_pll_clk_set_rate,
1277         .pll            = &dpll_data,
1278 };
1279
1280 static const struct pll_clk_set cpll_clks[] = {
1281         _PLL_SET_CLKS(360000, 1,  60,   4),
1282         _PLL_SET_CLKS(408000, 1,  68,   4),
1283         _PLL_SET_CLKS(456000, 1,  76,   4),
1284         _PLL_SET_CLKS(504000, 1,  84,   4),
1285         _PLL_SET_CLKS(552000, 1,  46,   2),
1286         _PLL_SET_CLKS(600000, 1,  50,   2),
1287         _PLL_SET_CLKS(742500, 8,  495,  2),
1288         _PLL_SET_CLKS(768000, 1,  64,   2),
1289         _PLL_SET_CLKS(798000, 2,  133,  2),
1290         _PLL_SET_CLKS(1188000, 2, 99,   1),
1291         _PLL_SET_CLKS(     0, 4,  133,  1),
1292 };
1293 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1294 static struct clk codec_pll_clk = {
1295         .name           = "codec_pll",
1296         .parent         = &xin24m,
1297         .mode           = pll_clk_mode,
1298         .recalc         = plls_clk_recalc,
1299         .set_rate       = cpll_clk_set_rate,
1300         .pll            = &cpll_data,
1301 };
1302
1303 static const struct pll_clk_set gpll_clks[] = {
1304         _PLL_SET_CLKS(148500,   2,      99,     8),
1305         _PLL_SET_CLKS(297000,   2,      198,    8),
1306         _PLL_SET_CLKS(300000,   1,      50,     4),
1307         _PLL_SET_CLKS(594000,   2,      198,    4),
1308         _PLL_SET_CLKS(1188000,  2,      99,     1),
1309         _PLL_SET_CLKS(1200000,  1,      50,     1),
1310         _PLL_SET_CLKS(0,        0,       0,     0),
1311 };
1312 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1313 static struct clk general_pll_clk = {
1314         .name           = "general_pll",
1315         .parent         = &xin24m,
1316         .recalc         = plls_clk_recalc,
1317         .set_rate       = gpll_clk_set_rate,
1318         .pll            = &gpll_data
1319 };
1320 /********************************clocks***********************************/
1321 GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1322
1323 /* core and cpu setting */
1324 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1325 {
1326         CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1327         return 0;
1328 }
1329
1330 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1331 {
1332         CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1333         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1334 }
1335 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1336 {
1337         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1338         unsigned long rate = clk->parent->recalc(clk->parent) >> shift;
1339         //CLKDATA_DBG("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1340         return rate;
1341 }
1342 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1343 static struct clk clk_ddr = {
1344         .name           = "ddr",
1345         .parent         = &ddr_pll_clk,
1346         .recalc         = ddr_clk_recalc_rate,
1347         .set_rate       = ddr_clk_set_rate,
1348         .round_rate     = ddr_clk_round_rate,
1349         .gate_idx       = CLK_GATE_DDRPHY,
1350         .clksel_con     = CRU_CLKSELS_CON(26),
1351         CRU_DIV_SET(0x3, 0, 4),
1352         CRU_SRC_SET(1, 8),
1353         CRU_PARENTS_SET(clk_ddr_parents),
1354 };
1355 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1356 {
1357         int ret;
1358
1359         ret = clk_set_rate_nolock(c->parent, rate);
1360         if (ret) {
1361                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1362                 return ret;
1363         }
1364         //set arm pll div 1
1365         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1366         return 0;
1367 }
1368 static unsigned long clk_core_get_rate(struct clk *c)
1369 {
1370         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1371         //c->parent->rate=c->parent->recalc(c->parent);
1372         return c->parent->rate / div;
1373 }
1374 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1375 {
1376         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1377         return clk_round_rate_nolock(clk->parent, rate) / div;
1378 }
1379
1380 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1381 {
1382
1383         u32 temp_div;
1384         struct clk *old_prt;
1385
1386         if(clk->parent == new_prt)
1387                 return 0;
1388         if (unlikely(!clk->parents))
1389                 return -EINVAL;
1390         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1391         //arm
1392         old_prt = clk->parent;
1393
1394         if(clk->parents[0] == new_prt) {
1395                 new_prt->set_rate(new_prt, 300 * MHZ);
1396                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1397         } else if(clk->parents[1] == new_prt) {
1398
1399                 if(new_prt->rate > old_prt->rate) {
1400                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1401                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1402                 }
1403                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1404                 new_prt->set_rate(new_prt, 300 * MHZ);
1405         } else
1406                 return -1;
1407
1408
1409         return 0;
1410
1411 }
1412
1413 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1414 {
1415         u32 temp_div;
1416         u32 old_aclk_div = 0, new_aclk_div;
1417         struct arm_clks_div_set *temp_clk_div;
1418         unsigned long arm_gpll_rate, arm_gpll_lpj;
1419         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1420         arm_gpll_rate = c->parent->rate / temp_div;
1421
1422         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1423         if(!temp_clk_div)
1424                 temp_clk_div = &arm_clk_div_tlb[4];
1425
1426         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1427         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1428         if(c->rate >= rate) {
1429                 arm_gpll_lpj = lpj_gpll / temp_div;
1430                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1431         }
1432
1433         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1434         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1435                         CRU_CLKSELS_CON(0));
1436         if((c->rate < rate)) {
1437                 arm_gpll_lpj = lpj_gpll / temp_div;
1438                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1439         }
1440         return 0;
1441 }
1442 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1443 {
1444         return c->parent->rate;
1445 }
1446 static struct clk clk_core_gpll_path = {
1447         .name           = "cpu_gpll_path",
1448         .parent         = &general_pll_clk,
1449         .recalc         = arm_core_gpll_clk_get_rate,
1450         .set_rate       = core_gpll_clk_set_rate,
1451         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1452 };
1453
1454
1455 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1456
1457 static struct clk clk_core = {
1458         .name           = "core",
1459         .parent         = &arm_pll_clk,
1460         .set_rate       = clk_core_set_rate,
1461         .recalc         = clk_core_get_rate,
1462         .round_rate     = core_clk_round_rate,
1463         .set_parent     = core_clksel_set_parent,
1464         .clksel_con     = CRU_CLKSELS_CON(0),
1465         CRU_DIV_SET(0x1f, 9, 32),
1466         CRU_SRC_SET(1, 8),
1467         CRU_PARENTS_SET(clk_core_parents),
1468 };
1469 GATE_CLK(l2c, clk_core, CLK_L2C);
1470 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1471 static unsigned long aclk_recalc(struct clk *clk)
1472 {
1473         unsigned long rate;
1474         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1475
1476         BUG_ON(div > 5);
1477         if (div >= 5)
1478                 div = 8;
1479         rate = clk->parent->rate / div;
1480         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1481
1482         return rate;
1483 };
1484 static struct clk core_periph = {
1485         .name           = "core_periph",
1486         .parent         = &clk_core,
1487         .gate_idx       = CLK_GATE_CORE_PERIPH,
1488         .recalc         = clksel_recalc_shift_2,
1489         .clksel_con     = CRU_CLKSELS_CON(0),
1490         CRU_DIV_SET(0x3, 6, 16),
1491 };
1492 static struct clk aclk_core = {
1493         .name           = "aclk_core",
1494         .parent         = &clk_core,
1495         .gate_idx       = CLK_GATE_ACLK_CORE,
1496         .recalc         = aclk_recalc,
1497         .clksel_con     = CRU_CLKSELS_CON(1),
1498         CRU_DIV_SET(0x7, 3, 8),
1499 };
1500
1501 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1502 static struct clk clk_cpu_div = {
1503         .name           = "cpu_div",
1504         .parent         = &arm_pll_clk,
1505         .set_rate       = clksel_set_rate_freediv,
1506         .recalc         = clksel_recalc_div,
1507         .clksel_con     = CRU_CLKSELS_CON(0),
1508         CRU_DIV_SET(0x1f, 0, 32),
1509         CRU_SRC_SET(1, 5),
1510         CRU_PARENTS_SET(clk_cpu_div_parents),
1511 };
1512
1513 static struct clk aclk_cpu = {
1514         .name           = "aclk_cpu",
1515         .parent         = &clk_cpu_div,
1516         .gate_idx       = CLK_GATE_ACLK_CPU,
1517 };
1518
1519 static struct clk hclk_cpu = {
1520         .name           = "hclk_cpu",
1521         .parent         = &aclk_cpu,
1522         .gate_idx       = CLK_GATE_HCLK_CPU,
1523         .recalc         = clksel_recalc_shift,
1524         .set_rate       = clksel_set_rate_shift,
1525         .clksel_con     = CRU_CLKSELS_CON(1),
1526         CRU_DIV_SET(0x3, 8, 4),
1527
1528 };
1529
1530 static struct clk pclk_cpu = {
1531         .name           = "pclk_cpu",
1532         .parent         = &aclk_cpu,
1533         .gate_idx       = CLK_GATE_PCLK_CPU,
1534         .recalc         = clksel_recalc_shift,
1535         .set_rate       = clksel_set_rate_shift,
1536         .clksel_con     = CRU_CLKSELS_CON(1),
1537         CRU_DIV_SET(0x3, 12, 8),
1538 };
1539
1540 static struct clk ahb2apb_cpu = {
1541         .name           = "ahb2apb",
1542         .parent         = &hclk_cpu,
1543         .recalc         = clksel_recalc_shift,
1544         .set_rate       = clksel_set_rate_shift,
1545         .clksel_con     = CRU_CLKSELS_CON(1),
1546         CRU_DIV_SET(0x3, 14, 4),
1547 };
1548
1549
1550 static struct clk atclk_cpu = {
1551         .name           = "atclk_cpu",
1552         .parent         = &pclk_cpu,
1553         .gate_idx       = CLK_GATE_ATCLK_CPU,
1554 };
1555
1556 /* GPU setting */
1557 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1558 {
1559         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1560         return clkset_rate_freediv_autosel_parents(clk, max_rate);
1561 };
1562
1563 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1564
1565 static struct clk aclk_gpu = {
1566         .name           = "aclk_gpu",
1567         .mode           = gate_mode,
1568         .recalc         = clksel_recalc_div,
1569         .round_rate     = clk_freediv_round_autosel_parents_rate,
1570         .set_rate       = clkset_rate_freediv_autosel_parents,
1571         .clksel_con     = CRU_CLKSELS_CON(34),
1572         .gate_idx       = CLK_GATE_ACLK_GPU,
1573         CRU_DIV_SET(0x1f, 0, 32),
1574         CRU_SRC_SET(0x1, 7),
1575         CRU_PARENTS_SET(aclk_gpu_parents),
1576 };
1577
1578 /* vcodec setting */
1579 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1580 {
1581         unsigned long rate = clk->parent->rate / 4;
1582         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1583         return rate;
1584 }
1585
1586 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1587
1588 static struct clk aclk_vepu = {
1589         .name           = "aclk_vepu",
1590         .parent         = &codec_pll_clk,
1591         .mode           = gate_mode,
1592         .recalc         = clksel_recalc_div,
1593         .set_rate       = clkset_rate_freediv_autosel_parents,
1594         .clksel_con     = CRU_CLKSELS_CON(32),
1595         .gate_idx       = CLK_GATE_ACLK_VEPU,
1596         CRU_DIV_SET(0x1f, 0, 32),
1597         CRU_SRC_SET(0x1, 7),
1598         CRU_PARENTS_SET(aclk_vepu_parents),
1599 };
1600
1601 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1602
1603 static struct clk aclk_vdpu = {
1604         .name           = "aclk_vdpu",
1605         .mode           = gate_mode,
1606         .recalc         = clksel_recalc_div,
1607         .set_rate       = clkset_rate_freediv_autosel_parents,
1608         .clksel_con     = CRU_CLKSELS_CON(32),
1609         .gate_idx       = CLK_GATE_ACLK_VDPU,
1610         CRU_DIV_SET(0x1f, 8, 32),
1611         CRU_SRC_SET(0x1, 15),
1612         CRU_PARENTS_SET(aclk_vdpu_parents),
1613 };
1614 static struct clk hclk_vepu = {
1615         .name           = "hclk_vepu",
1616         .parent         = &aclk_vepu,
1617         .mode           = gate_mode,
1618         .recalc         = clksel_recalc_vpu_hclk,
1619         .gate_idx       = CLK_GATE_HCLK_VEPU,
1620 };
1621
1622 static struct clk hclk_vdpu = {
1623         .name           = "hclk_vdpu",
1624         .parent         = &aclk_vdpu,
1625         .mode           = gate_mode,
1626         .recalc         = clksel_recalc_vpu_hclk,
1627         .gate_idx       = CLK_GATE_HCLK_VDPU,
1628 };
1629
1630 /* aclk lcdc setting */
1631 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1632
1633 static struct clk aclk_lcdc0_pre = {
1634         .name           = "aclk_lcdc0_pre",
1635         .parent         = &codec_pll_clk,
1636         .mode           = gate_mode,
1637         .recalc         = clksel_recalc_div,
1638         .set_rate       = clkset_rate_freediv_autosel_parents,
1639         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1640         .clksel_con     = CRU_CLKSELS_CON(31),
1641         CRU_DIV_SET(0x1f, 0, 32),
1642         CRU_SRC_SET(0x1, 7),
1643         CRU_PARENTS_SET(aclk_lcdc0_parents),
1644 };
1645
1646 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1647
1648 static struct clk aclk_lcdc1_pre = {
1649         .name           = "aclk_lcdc1_pre",
1650         .parent         = &codec_pll_clk,
1651         .mode           = gate_mode,
1652         .recalc         = clksel_recalc_div,
1653         .set_rate       = clkset_rate_freediv_autosel_parents,
1654         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1655         .clksel_con     = CRU_CLKSELS_CON(31),
1656         CRU_DIV_SET(0x1f, 8, 32),
1657         CRU_SRC_SET(0x1, 15),
1658         CRU_PARENTS_SET(aclk_lcdc1_parents),
1659 };
1660
1661 /* aclk/hclk/pclk periph setting */
1662 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1663
1664 static struct clk aclk_periph = {
1665         .name           = "aclk_periph",
1666         .parent         = &general_pll_clk,
1667         .mode           = gate_mode,
1668         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1669         .recalc         = clksel_recalc_div,
1670         .set_rate       = clksel_set_rate_freediv,
1671         .clksel_con     = CRU_CLKSELS_CON(10),
1672         CRU_DIV_SET(0x1f, 0, 32),
1673         CRU_SRC_SET(1, 15),
1674         CRU_PARENTS_SET(aclk_periph_parents),
1675 };
1676 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1677
1678 static struct clk pclk_periph = {
1679         .name           = "pclk_periph",
1680         .parent         = &aclk_periph,
1681         .mode           = gate_mode,
1682         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1683         .recalc         = clksel_recalc_shift,
1684         .set_rate       = clksel_set_rate_shift,
1685         .clksel_con     = CRU_CLKSELS_CON(10),
1686         CRU_DIV_SET(0x3, 12, 8),
1687 };
1688
1689 static struct clk hclk_periph = {
1690         .name           = "hclk_periph",
1691         .parent         = &aclk_periph,
1692         .mode           = gate_mode,
1693         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1694         .recalc         = clksel_recalc_shift,
1695         .set_rate       = clksel_set_rate_shift,
1696         .clksel_con     = CRU_CLKSELS_CON(10),
1697         CRU_DIV_SET(0x3, 8, 4),
1698 };
1699 /* dclk lcdc setting */
1700 // FIXME
1701 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1702 {
1703         u32 div, old_div;
1704         int i;
1705         unsigned long new_rate;
1706         int ret = 0;
1707
1708         if(clk->rate == rate)
1709                 return 0;
1710         for(i = 0; i < 2; i++) {
1711                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1712                 new_rate = clk->parents[i]->rate / div;
1713                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1714                         break;
1715                 }
1716         }
1717         if(i >= 2) {
1718                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1719                 return -1;
1720         }
1721
1722         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1723
1724         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1725                         clk->div_shift, clk->div_mask) + 1;
1726         if(div > old_div)
1727                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1728
1729         if(clk->parents[i] != clk->parent) {
1730                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1731         }
1732
1733         if (ret) {
1734                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1735                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1736                 return ret;
1737         }
1738         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1739         return 0;
1740 }
1741
1742 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1743 {
1744         if (rate == 27 * MHZ)
1745                 return clkset_rate_freediv_autosel_parents(clk, rate);
1746         else
1747                 return clkset_rate_evendiv_autosel_parents(clk, rate);
1748
1749 #if 0
1750         int ret = 0;
1751         struct clk *parent;
1752         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1753                 parent = clk->parents[1];
1754                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1755         } else {
1756                 parent = clk->parents[0];
1757         }
1758         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1759         //clk->name,rate,parent->name,clk->parent->name);
1760
1761         if(parent != clk->parents[1]) {
1762                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1763                 if (ret) {
1764                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1765                         return ret;
1766                 }
1767         }
1768         if (clk->parent != parent) {
1769                 ret = clk_set_parent_nolock(clk, parent);
1770                 if (ret) {
1771                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1772                         return ret;
1773                 }
1774         }
1775         return ret;
1776 #endif
1777 }
1778
1779 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1780 static struct clk dclk_lcdc0 = {
1781         .name           = "dclk_lcdc0",
1782         .mode           = gate_mode,
1783         .set_rate       = dclk_lcdc_set_rate,
1784         .recalc         = clksel_recalc_div,
1785         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1786         .clksel_con     = CRU_CLKSELS_CON(27),
1787         CRU_SRC_SET(0x1, 0),
1788         CRU_DIV_SET(0xff, 8, 256),
1789         CRU_PARENTS_SET(dclk_lcdc0_parents),
1790 };
1791
1792 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1793 static struct clk dclk_lcdc1 = {
1794         .name           = "dclk_lcdc1",
1795         .mode           = gate_mode,
1796         .set_rate       = dclk_lcdc_set_rate,
1797         .recalc         = clksel_recalc_div,
1798         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1799         .clksel_con     = CRU_CLKSELS_CON(28),
1800         CRU_SRC_SET(0x1, 0),
1801         CRU_DIV_SET(0xff, 8, 256),
1802         CRU_PARENTS_SET(dclk_lcdc1_parents),
1803 };
1804
1805 /* cif setting */
1806 // FIXME
1807 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1808 static struct clk cif_out_pll = {
1809         .name           = "cif_out_pll",
1810         .parent         = &general_pll_clk,
1811         .clksel_con     = CRU_CLKSELS_CON(29),
1812         CRU_SRC_SET(0x1, 0),
1813         CRU_PARENTS_SET(cifout_sel_pll_parents),
1814 };
1815
1816 static struct clk cif0_out_div = {
1817         .name           = "cif0_out_div",
1818         .parent         = &cif_out_pll,
1819         .mode           = gate_mode,
1820         .recalc         = clksel_recalc_div,
1821         .set_rate       = clksel_set_rate_freediv,
1822         .gate_idx       = CLK_GATE_CIF0_OUT,
1823         .clksel_con     = CRU_CLKSELS_CON(29),
1824         CRU_DIV_SET(0x1f, 1, 32),
1825 };
1826
1827 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1828 {
1829         int ret = 0;
1830         struct clk *parent;
1831
1832         if (rate == 24 * MHZ) {
1833                 parent = clk->parents[1];
1834         } else {
1835                 parent = clk->parents[0];
1836                 ret = clk_set_rate_nolock(parent, rate);
1837                 if (ret)
1838                         return ret;
1839         }
1840         if (clk->parent != parent)
1841                 ret = clk_set_parent_nolock(clk, parent);
1842
1843         return ret;
1844 }
1845
1846 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1847 static struct clk cif0_out = {
1848         .name           = "cif0_out",
1849         .parent         = &cif0_out_div,
1850         .set_rate       = cif_out_set_rate,
1851         .clksel_con     = CRU_CLKSELS_CON(29),
1852         CRU_SRC_SET(0x1, 7),
1853         CRU_PARENTS_SET(cif0_out_parents),
1854 };
1855
1856 static struct clk pclkin_cif0 = {
1857         .name           = "pclkin_cif0",
1858         .mode           = gate_mode,
1859         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1860 };
1861
1862 static struct clk inv_cif0 = {
1863         .name           = "inv_cif0",
1864         .parent         = &pclkin_cif0,
1865 };
1866
1867 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1868 static struct clk cif0_in = {
1869         .name           = "cif0_in",
1870         .parent         = &pclkin_cif0,
1871         .clksel_con     = CRU_CLKSELS_CON(30),
1872         CRU_SRC_SET(0x1, 8),
1873         CRU_PARENTS_SET(cif0_in_parents),
1874 };
1875
1876 /* i2s/spdif setting */
1877 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1878 static struct clk clk_i2s_pll = {
1879         .name           = "i2s_pll",
1880         .parent         = &general_pll_clk,
1881         .clksel_con     = CRU_CLKSELS_CON(2),
1882         CRU_SRC_SET(0x1, 15),
1883         CRU_PARENTS_SET(clk_i2s_div_parents),
1884 };
1885
1886 static struct clk clk_i2s0_div = {
1887         .name           = "i2s0_div",
1888         .parent         = &clk_i2s_pll,
1889         .mode           = gate_mode,
1890         .recalc         = clksel_recalc_div,
1891         .set_rate       = clksel_set_rate_freediv,
1892         .round_rate     = clksel_freediv_round_rate,
1893         .gate_idx       = CLK_GATE_I2S0_SRC,
1894         .clksel_con     = CRU_CLKSELS_CON(3),
1895         CRU_DIV_SET(0x7f, 0, 64),
1896 };
1897
1898 static struct clk clk_spdif_div = {
1899         .name           = "spdif_div",
1900         .parent         = &clk_i2s_pll,
1901         .recalc         = clksel_recalc_div,
1902         .set_rate       = clksel_set_rate_freediv,
1903         .round_rate     = clksel_freediv_round_rate,
1904         .mode           = gate_mode,
1905         .gate_idx       = CLK_GATE_SPDIF_SRC,
1906         .clksel_con     = CRU_CLKSELS_CON(5),
1907         CRU_DIV_SET(0x7f, 0, 64),
1908 };
1909 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1910 {
1911         u32 numerator, denominator;
1912         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1913         //clk->parent->parent
1914         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1915                                 &numerator, &denominator) == 0) {
1916                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1917                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1918                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1919         } else {
1920                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1921                 return -ENOENT;
1922         }
1923         return 0;
1924 }
1925
1926 static struct clk clk_i2s0_frac_div = {
1927         .name           = "i2s0_frac_div",
1928         .parent         = &clk_i2s0_div,
1929         .mode           = gate_mode,
1930         .gate_idx       = CLK_GATE_I2S0_FRAC,
1931         .recalc         = clksel_recalc_frac,
1932         .set_rate       = clk_i2s_fracdiv_set_rate,
1933         .clksel_con     = CRU_CLKSELS_CON(7),
1934 };
1935
1936 static struct clk clk_spdif_frac_div = {
1937         .name           = "spdif_frac_div",
1938         .parent         = &clk_spdif_div,
1939         .mode           = gate_mode,
1940         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1941         .recalc         = clksel_recalc_frac,
1942         .set_rate       = clk_i2s_fracdiv_set_rate,
1943         .clksel_con     = CRU_CLKSELS_CON(9),
1944 };
1945
1946 #define I2S_SRC_DIV     (0x0)
1947 #define I2S_SRC_FRAC    (0x1)
1948 #define I2S_SRC_12M     (0x2)
1949
1950 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1951 {
1952         int ret = -EINVAL;
1953         struct clk *parent;
1954
1955         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1956                 parent = clk->parents[I2S_SRC_12M];
1957         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1958                 parent = clk->parents[I2S_SRC_DIV];
1959         } else {
1960                 parent = clk->parents[I2S_SRC_FRAC];
1961         }
1962
1963         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1964                         clk->name, rate, parent->name, clk->parent->name);
1965
1966         if(parent != clk->parents[I2S_SRC_12M]) {
1967                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1968                 if (ret) {
1969                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1970                         return ret;
1971                 }
1972         }
1973
1974         if (clk->parent != parent) {
1975                 ret = clk_set_parent_nolock(clk, parent);
1976                 if (ret) {
1977                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1978                         return ret;
1979                 }
1980         }
1981
1982         return ret;
1983 };
1984
1985 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
1986
1987 static struct clk clk_i2s0 = {
1988         .name           = "i2s0",
1989         .set_rate       = i2s_set_rate,
1990         .clksel_con     = CRU_CLKSELS_CON(3),
1991         CRU_SRC_SET(0x3, 8),
1992         CRU_PARENTS_SET(clk_i2s0_parents),
1993 };
1994
1995 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
1996
1997 static struct clk clk_spdif = {
1998         .name           = "spdif",
1999         .parent         = &clk_spdif_frac_div,
2000         .set_rate       = i2s_set_rate,
2001         .clksel_con = CRU_CLKSELS_CON(5),
2002         CRU_SRC_SET(0x3, 8),
2003         CRU_PARENTS_SET(clk_spdif_parents),
2004 };
2005
2006 /* otgphy setting */
2007 GATE_CLK(otgphy0, xin24m, OTGPHY0);
2008 GATE_CLK(otgphy1, xin24m, OTGPHY1);
2009
2010 static struct clk clk_otgphy0_480m = {
2011         .name           = "otgphy0_480m",
2012         .parent         = &clk_otgphy0,
2013 };
2014 static struct clk clk_otgphy1_480m = {
2015         .name           = "otgphy1_480m",
2016         .parent         = &clk_otgphy1,
2017 };
2018
2019 /* hsicphy setting */
2020 #ifdef ARCH_RK31
2021 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
2022 static struct clk clk_hsicphy_480m = {
2023         .name           = "hsicphy_480m",
2024         .parent         = &clk_otgphy0_480m,
2025         .clksel_con      = CRU_CLKSELS_CON(30),
2026         CRU_SRC_SET(0x3, 0),
2027         CRU_PARENTS_SET(clk_hsicphy_parents),
2028 };
2029 static struct clk clk_hsicphy_12m = {
2030         .name           = "hsicphy_12m",
2031         .parent         = &clk_hsicphy_480m,
2032         .clksel_con     = CRU_CLKSELS_CON(11),
2033         CRU_DIV_SET(0x3f, 8, 64),
2034 };
2035 #endif
2036
2037 /* mac and rmii setting */
2038 // FIXME
2039 static struct clk rmii_clkin = {
2040         .name           = "rmii_clkin",
2041 };
2042 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
2043 static struct clk clk_mac_pll_div = {
2044         .name           = "mac_pll_div",
2045         .parent         = &general_pll_clk,
2046         .mode           = gate_mode,
2047         .gate_idx       = CLK_GATE_MAC_SRC,
2048         .recalc         = clksel_recalc_div,
2049         .set_rate       = clksel_set_rate_freediv,
2050         .clksel_con     = CRU_CLKSELS_CON(21),
2051         CRU_DIV_SET(0x1f, 8, 32),
2052         CRU_SRC_SET(0x1, 0),
2053         CRU_PARENTS_SET(clk_mac_ref_div_parents),
2054 };
2055
2056 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
2057 {
2058         if(clk->parent == clk->parents[1]) {
2059                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
2060                 return -ENOENT;
2061         } else if(clk->parent == clk->parents[0]) {
2062                 return clk_set_rate_nolock(clk->parents[0], rate);
2063         }
2064         return -ENOENT;
2065 }
2066
2067 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
2068
2069 static struct clk clk_mac_ref = {
2070         .name           = "mac_ref",
2071         .parent         = &clk_mac_pll_div,
2072         .set_rate       = clksel_mac_ref_set_rate,
2073         .clksel_con     = CRU_CLKSELS_CON(21),
2074         CRU_SRC_SET(0x1, 4),
2075         CRU_PARENTS_SET(clk_mac_ref_parents),
2076 };
2077
2078 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
2079 {
2080         return clk_set_parent_nolock(clk->parent, parent);
2081 }
2082
2083 static struct clk clk_mii_tx = {
2084         .name           = "mii_tx",
2085         .parent         = &clk_mac_ref,
2086         //.set_parent   = clk_set_mii_tx_parent,
2087         .mode           = gate_mode,
2088         .gate_idx       = CLK_GATE_MAC_LBTEST,
2089 };
2090
2091 /* hsadc and saradc */
2092 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
2093 static struct clk clk_hsadc_pll_div = {
2094         .name           = "hsadc_pll_div",
2095         .parent         = &general_pll_clk,
2096         .mode           = gate_mode,
2097         .gate_idx       = CLK_GATE_HSADC_SRC,
2098         .recalc         = clksel_recalc_div,
2099         .round_rate     = clk_freediv_round_autosel_parents_rate,
2100         .set_rate       = clkset_rate_freediv_autosel_parents,
2101         //.round_rate   = clksel_freediv_round_rate,
2102         //.set_rate     = clksel_set_rate_freediv,
2103         .clksel_con = CRU_CLKSELS_CON(22),
2104         CRU_DIV_SET(0xff, 8, 256),
2105         CRU_SRC_SET(0x1, 0),
2106         CRU_PARENTS_SET(clk_hsadc_pll_parents),
2107 };
2108 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2109 {
2110         u32 numerator, denominator;
2111         //        clk_hsadc_pll_div->gpll/cpll
2112         //clk->parent->parent
2113         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2114                                 &numerator, &denominator) == 0) {
2115                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2116
2117                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2118
2119                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2120         } else {
2121                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2122                 return -ENOENT;
2123         }
2124         return 0;
2125 }
2126 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2127 {
2128         u32 numerator, denominator;
2129         u32 i, ret = 0;
2130         //        clk_hsadc_pll_div->gpll/cpll
2131         //clk->parent->parent
2132         for(i = 0; i < 2; i++) {
2133                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2134                                         &numerator, &denominator) == 0)
2135                         break;
2136         }
2137         if(i >= 2)
2138                 return -ENOENT;
2139
2140         if(clk->parent->parent != clk->parent->parents[i])
2141                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2142         if(ret == 0) {
2143                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2144
2145                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2146
2147                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2148         } else {
2149                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2150                 return -ENOENT;
2151         }
2152         return 0;
2153 }
2154
2155 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2156 {
2157         u32 numerator, denominator;
2158
2159         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2160         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2161                                 &numerator, &denominator) == 0)
2162                 return rate;
2163
2164         return 0;
2165 }
2166 static struct clk clk_hsadc_frac_div = {
2167         .name           = "hsadc_frac_div",
2168         .parent         = &clk_hsadc_pll_div,
2169         .mode           = gate_mode,
2170         .recalc         = clksel_recalc_frac,
2171         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2172         .round_rate     = clk_hsadc_fracdiv_round_rate,
2173         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
2174         .clksel_con     = CRU_CLKSELS_CON(23),
2175 };
2176
2177 #define HSADC_SRC_DIV 0x0
2178 #define HSADC_SRC_FRAC 0x1
2179 #define HSADC_SRC_EXT 0x2
2180 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2181 {
2182         int ret = -EINVAL;
2183         struct clk *parent;
2184
2185         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2186                 CLKDATA_DBG("hsadc clk is form ext\n");
2187                 return 0;
2188         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2189                 parent = clk->parents[HSADC_SRC_DIV];
2190         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2191                 parent = clk->parents[HSADC_SRC_FRAC];
2192         } else
2193                 parent = clk->parents[HSADC_SRC_DIV];
2194
2195         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2196                         clk->name, rate, parent->name, clk->parent->name);
2197
2198         ret = clk_set_rate_nolock(parent, rate);
2199         if (ret) {
2200                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2201                 return ret;
2202         }
2203         if (clk->parent != parent) {
2204                 ret = clk_set_parent_nolock(clk, parent);
2205                 if (ret) {
2206                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2207                         return ret;
2208                 }
2209         }
2210         return ret;
2211 }
2212
2213 static struct clk clk_hsadc_ext = {
2214         .name           = "hsadc_ext",
2215 };
2216
2217 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2218 static struct clk clk_hsadc_out = {
2219         .name           = "hsadc_out",
2220         .parent         = &clk_hsadc_pll_div,
2221         .set_rate       = clk_hsadc_set_rate,
2222         .clksel_con     = CRU_CLKSELS_CON(22),
2223         CRU_SRC_SET(0x3, 4),
2224         CRU_PARENTS_SET(clk_hsadc_out_parents),
2225 };
2226 static struct clk clk_hsadc_out_inv = {
2227         .name           = "hsadc_out_inv",
2228         .parent         = &clk_hsadc_out,
2229 };
2230
2231 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2232 static struct clk clk_hsadc = {
2233         .name           = "hsadc",
2234         .parent         = &clk_hsadc_out,
2235         .clksel_con     = CRU_CLKSELS_CON(22),
2236         CRU_SRC_SET(0x1, 7),
2237         CRU_PARENTS_SET(clk_hsadc_parents),
2238 };
2239
2240 static struct clk clk_saradc = {
2241         .name           = "saradc",
2242         .parent         = &xin24m,
2243         .mode           = gate_mode,
2244         .recalc         = clksel_recalc_div,
2245         .set_rate       = clksel_set_rate_freediv,
2246         .gate_idx       = CLK_GATE_SARADC_SRC,
2247         .clksel_con     = CRU_CLKSELS_CON(24),
2248         CRU_DIV_SET(0xff, 8, 256),
2249 };
2250
2251 /* smc setting */
2252 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2253 static struct clk clkn_smc = {
2254         .name           = "smc_inv",
2255         .parent         = &clk_smc,
2256 };
2257
2258 /* spi setting */
2259 static struct clk clk_spi0 = {
2260         .name           = "spi0",
2261         .parent         = &pclk_periph,
2262         .mode           = gate_mode,
2263         .recalc         = clksel_recalc_div,
2264         .set_rate       = clksel_set_rate_freediv,
2265         .gate_idx       = CLK_GATE_SPI0_SRC,
2266         .clksel_con     = CRU_CLKSELS_CON(25),
2267         CRU_DIV_SET(0x7f, 0, 128),
2268 };
2269
2270 static struct clk clk_spi1 = {
2271         .name           = "spi1",
2272         .parent         = &pclk_periph,
2273         .mode           = gate_mode,
2274         .recalc         = clksel_recalc_div,
2275         .set_rate       = clksel_set_rate_freediv,
2276         .gate_idx       = CLK_GATE_SPI1_SRC,
2277         .clksel_con     = CRU_CLKSELS_CON(25),
2278         CRU_DIV_SET(0x7f, 8, 128),
2279 };
2280
2281 /* sdmmc/sdio/emmc setting */
2282 static struct clk clk_sdmmc = {
2283         .name           = "sdmmc",
2284         .parent         = &hclk_periph,
2285         .mode           = gate_mode,
2286         .recalc         = clksel_recalc_div,
2287         .set_rate       = clksel_set_rate_even,
2288         .gate_idx       = CLK_GATE_MMC0_SRC,
2289         .clksel_con     = CRU_CLKSELS_CON(11),
2290         CRU_DIV_SET(0x3f, 0, 64),
2291 };
2292
2293 static struct clk clk_sdio = {
2294         .name           = "sdio",
2295         .parent         = &hclk_periph,
2296         .mode           = gate_mode,
2297         .recalc         = clksel_recalc_div,
2298         .set_rate       = clksel_set_rate_even,
2299         .gate_idx       = CLK_GATE_SDIO_SRC,
2300         .clksel_con     = CRU_CLKSELS_CON(12),
2301         CRU_DIV_SET(0x3f, 0, 64),
2302
2303 };
2304
2305 static struct clk clk_emmc = {
2306         .name           = "emmc",
2307         .parent         = &hclk_periph,
2308         .mode           = gate_mode,
2309         .recalc         = clksel_recalc_div,
2310         .set_rate       = clksel_set_rate_freediv,
2311         .gate_idx       = CLK_GATE_EMMC_SRC,
2312         .clksel_con     = CRU_CLKSELS_CON(12),
2313         CRU_DIV_SET(0x3f, 8, 64),
2314 };
2315
2316 /* uart setting */
2317 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2318 static struct clk clk_uart_pll = {
2319         .name           = "uart_pll",
2320         .parent         = &general_pll_clk,
2321         .clksel_con     = CRU_CLKSELS_CON(12),
2322         CRU_SRC_SET(0x1, 15),
2323         CRU_PARENTS_SET(clk_uart_src_parents),
2324 };
2325 static struct clk clk_uart0_div = {
2326         .name           = "uart0_div",
2327         .parent         = &clk_uart_pll,
2328         .mode           = gate_mode,
2329         .gate_idx       = CLK_GATE_UART0_SRC,
2330         .recalc         = clksel_recalc_div,
2331         .set_rate       = clksel_set_rate_freediv,
2332         .round_rate     = clksel_freediv_round_rate,
2333         .clksel_con     = CRU_CLKSELS_CON(13),
2334         CRU_DIV_SET(0x7f, 0, 64),
2335 };
2336 static struct clk clk_uart1_div = {
2337         .name           = "uart1_div",
2338         .parent         = &clk_uart_pll,
2339         .mode           = gate_mode,
2340         .gate_idx       = CLK_GATE_UART1_SRC,
2341         .recalc         = clksel_recalc_div,
2342         .round_rate     = clksel_freediv_round_rate,
2343         .set_rate       = clksel_set_rate_freediv,
2344         .clksel_con     = CRU_CLKSELS_CON(14),
2345         CRU_DIV_SET(0x7f, 0, 64),
2346 };
2347
2348 static struct clk clk_uart2_div = {
2349         .name           = "uart2_div",
2350         .parent         = &clk_uart_pll,
2351         .mode           = gate_mode,
2352         .gate_idx       = CLK_GATE_UART2_SRC,
2353         .recalc         = clksel_recalc_div,
2354         .round_rate     = clksel_freediv_round_rate,
2355         .set_rate       = clksel_set_rate_freediv,
2356         .clksel_con     = CRU_CLKSELS_CON(15),
2357         CRU_DIV_SET(0x7f, 0, 64),
2358 };
2359
2360 static struct clk clk_uart3_div = {
2361         .name           = "uart3_div",
2362         .parent         = &clk_uart_pll,
2363         .mode           = gate_mode,
2364         .gate_idx       = CLK_GATE_UART3_SRC,
2365         .recalc         = clksel_recalc_div,
2366         .round_rate     = clksel_freediv_round_rate,
2367         .set_rate       = clksel_set_rate_freediv,
2368         .clksel_con     = CRU_CLKSELS_CON(16),
2369         CRU_DIV_SET(0x7f, 0, 64),
2370 };
2371 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2372 {
2373         u32 numerator, denominator;
2374         //clk_uart0_div->clk_uart_pll->gpll/cpll
2375         //clk->parent->parent
2376         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2377                                 &numerator, &denominator) == 0) {
2378                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2379
2380                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2381
2382                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2383         } else {
2384                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2385                 return -ENOENT;
2386         }
2387         return 0;
2388 }
2389
2390 static struct clk clk_uart0_frac_div = {
2391         .name           = "uart0_frac_div",
2392         .parent         = &clk_uart0_div,
2393         .mode           = gate_mode,
2394         .recalc         = clksel_recalc_frac,
2395         .set_rate       = clk_uart_fracdiv_set_rate,
2396         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2397         .clksel_con     = CRU_CLKSELS_CON(17),
2398 };
2399 static struct clk clk_uart1_frac_div = {
2400         .name           = "uart1_frac_div",
2401         .parent         = &clk_uart1_div,
2402         .mode           = gate_mode,
2403         .recalc         = clksel_recalc_frac,
2404         .set_rate       = clk_uart_fracdiv_set_rate,
2405         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2406         .clksel_con     = CRU_CLKSELS_CON(18),
2407 };
2408 static struct clk clk_uart2_frac_div = {
2409         .name           = "uart2_frac_div",
2410         .mode           = gate_mode,
2411         .parent         = &clk_uart2_div,
2412         .recalc         = clksel_recalc_frac,
2413         .set_rate       = clk_uart_fracdiv_set_rate,
2414         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2415         .clksel_con     = CRU_CLKSELS_CON(19),
2416 };
2417 static struct clk clk_uart3_frac_div = {
2418         .name           = "uart3_frac_div",
2419         .parent         = &clk_uart3_div,
2420         .mode           = gate_mode,
2421         .recalc         = clksel_recalc_frac,
2422         .set_rate       = clk_uart_fracdiv_set_rate,
2423         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2424         .clksel_con     = CRU_CLKSELS_CON(20),
2425 };
2426
2427 #define UART_SRC_DIV 0
2428 #define UART_SRC_FRAC 1
2429 #define UART_SRC_24M 2
2430
2431 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2432 {
2433         int ret = 0;
2434         struct clk *parent;
2435
2436         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2437                 parent = clk->parents[UART_SRC_24M];
2438         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2439                 parent = clk->parents[UART_SRC_DIV];
2440         } else {
2441                 parent = clk->parents[UART_SRC_FRAC];
2442         }
2443
2444         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2445                         clk->name, rate, parent->name, clk->parent->name);
2446
2447         if(parent != clk->parents[UART_SRC_24M]) {
2448                 ret = clk_set_rate_nolock(parent, rate);
2449                 if (ret) {
2450                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2451                         return ret;
2452                 }
2453         }
2454
2455         if (clk->parent != parent) {
2456                 ret = clk_set_parent_nolock(clk, parent);
2457                 if (ret) {
2458                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2459                         return ret;
2460                 }
2461         }
2462
2463         return ret;
2464 }
2465
2466 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2467 static struct clk clk_uart0 = {
2468         .name           = "uart0",
2469         .set_rate       = clk_uart_set_rate,
2470         .clksel_con     = CRU_CLKSELS_CON(13),
2471         CRU_SRC_SET(0x3, 8),
2472         CRU_PARENTS_SET(clk_uart0_parents),
2473 };
2474
2475 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2476 static struct clk clk_uart1 = {
2477         .name           = "uart1",
2478         .set_rate       = clk_uart_set_rate,
2479         .clksel_con     = CRU_CLKSELS_CON(14),
2480         CRU_SRC_SET(0x3, 8),
2481         CRU_PARENTS_SET(clk_uart1_parents),
2482 };
2483
2484 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2485 static struct clk clk_uart2 = {
2486         .name           = "uart2",
2487         .set_rate       = clk_uart_set_rate,
2488         .clksel_con     = CRU_CLKSELS_CON(15),
2489         CRU_SRC_SET(0x3, 8),
2490         CRU_PARENTS_SET(clk_uart2_parents),
2491 };
2492 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2493 static struct clk clk_uart3 = {
2494         .name           = "uart3",
2495         .set_rate       = clk_uart_set_rate,
2496         .clksel_con     = CRU_CLKSELS_CON(16),
2497         CRU_SRC_SET(0x3, 8),
2498         CRU_PARENTS_SET(clk_uart3_parents),
2499 };
2500
2501 /* timer setting */
2502 GATE_CLK(timer0, xin24m, TIMER0);
2503 GATE_CLK(timer1, xin24m, TIMER1);
2504 GATE_CLK(timer2, xin24m, TIMER2);
2505 GATE_CLK(timer3, xin24m, TIMER3);
2506 GATE_CLK(timer4, xin24m, TIMER4);
2507 GATE_CLK(timer5, xin24m, TIMER5);
2508 GATE_CLK(timer6, xin24m, TIMER6);
2509
2510 /*********************power domain*******************************/
2511 #if 1
2512 #ifdef RK30_CLK_OFFBOARD_TEST
2513 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2514 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2515 #else
2516 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2517 #define _pmu_set_power_domain pmu_set_power_domain
2518 #endif
2519
2520 static int pd_video_mode(struct clk *clk, int on)
2521 {
2522         u32 gate[3];
2523         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2524         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2525         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2526         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2527         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2528         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2529         pmu_set_power_domain(PD_VIDEO, on);
2530         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2531         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2532         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2533         return 0;
2534 }
2535
2536 static struct clk pd_video = {
2537         .name   = "pd_video",
2538         .flags  = IS_PD,
2539         .mode   = pd_video_mode,
2540         .gate_idx       = PD_VIDEO,
2541 };
2542 static int pd_display_mode(struct clk *clk, int on)
2543 {
2544         u32 gate[10];
2545         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2546         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2547         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2548         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2549         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2550         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2551         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2552         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2553         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2554         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2555         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2556         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2557         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2558         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2559         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2560         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2561         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2562         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2563         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2564         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2565         pmu_set_power_domain(PD_VIO, on);
2566         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2567         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2568         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2569         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2570         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2571         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2572         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2573         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2574         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2575         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2576         return 0;
2577 }
2578
2579 static struct clk pd_display = {
2580         .name   = "pd_vio",
2581         .flags  = IS_PD,
2582         .mode   = pd_display_mode,
2583         .gate_idx       = PD_VIO,
2584 };
2585 static struct clk pd_lcdc0 = {
2586         .parent = &pd_display,
2587         .name   = "pd_lcdc0",
2588 };
2589 static struct clk pd_lcdc1 = {
2590         .parent = &pd_display,
2591         .name   = "pd_lcdc1",
2592 };
2593 static struct clk pd_cif0 = {
2594         .parent = &pd_display,
2595         .name   = "pd_cif0",
2596 };
2597 static struct clk pd_rga = {
2598         .parent = &pd_display,
2599         .name   = "pd_rga",
2600 };
2601 static struct clk pd_ipp = {
2602         .parent = &pd_display,
2603         .name   = "pd_ipp",
2604 };
2605 static struct clk pd_hdmi = {
2606         .parent = &pd_display,
2607         .name   = "pd_hdmi",
2608 };
2609
2610
2611 static int pd_gpu_mode(struct clk *clk, int on)
2612 {
2613         u32 gate[3];
2614         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2615         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2616         pmu_set_power_domain(PD_GPU, on);
2617         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2618         return 0;
2619 }
2620
2621 static struct clk pd_gpu = {
2622         .name   = "pd_gpu",
2623         .flags  = IS_PD,
2624         .mode   = pd_gpu_mode,
2625         .gate_idx       = PD_GPU,
2626 };
2627
2628 static int pm_off_mode(struct clk *clk, int on)
2629 {
2630         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2631         return 0;
2632 }
2633 static struct clk pd_peri = {
2634         .name   = "pd_peri",
2635         .flags  = IS_PD,
2636         .mode   = pm_off_mode,
2637         .gate_idx       = PD_PERI,
2638 };
2639
2640
2641 #define PD_CLK(name) \
2642 {\
2643         .dev_id = NULL,\
2644         .con_id = #name,\
2645         .clk = &name,\
2646 }
2647
2648 #endif
2649 /************************rk30 fixed div clock****************************************/
2650
2651 /*************************aclk_cpu***********************/
2652
2653 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2654 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2655 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2656
2657 /*************************hclk_cpu***********************/
2658
2659 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2660 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2661 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2662 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2663 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2664 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2665 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2666 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2667 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2668 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2669 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2670 GATE_CLK(hclk_imem0,    hclk_cpu,       HCLK_IMEM0);
2671 GATE_CLK(hclk_imem1,    hclk_cpu,       HCLK_IMEM1);
2672
2673 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2674 GATE_CLK(pclk_uart0,    ahb2apb_cpu, PCLK_UART0);
2675 GATE_CLK(pclk_uart1,    ahb2apb_cpu, PCLK_UART1);
2676 /*************************pclk_cpu***********************/
2677 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2678 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2679 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2680 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2681 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2682 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2683 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2684 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2685 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2686 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2687 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2688 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2689 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2690 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2691 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2692
2693 /*************************aclk_periph***********************/
2694
2695 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2696 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2697 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2698 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2699 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2700 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2701
2702 /*************************hclk_periph***********************/
2703 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2704 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2705 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2706 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2707 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2708 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2709 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2710 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2711 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2712 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2713 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2714 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2715 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2716 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2717 /*************************pclk_periph***********************/
2718 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2719 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2720 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2721 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2722 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2723 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2724 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2725 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2726 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2727 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2728 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2729 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2730 /*************************aclk_lcdc0***********************/
2731
2732 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2733 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2734 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2735 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2736
2737 /*************************aclk_lcdc0***********************/
2738
2739 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2740 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2741 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2742
2743
2744 #if 1
2745 #define CLK(dev, con, ck) \
2746 {\
2747         .dev_id = dev,\
2748         .con_id = con,\
2749         .clk = ck,\
2750 }
2751
2752
2753 #define CLK1(name) \
2754 {\
2755         .dev_id = NULL,\
2756         .con_id = #name,\
2757         .clk = &clk_##name,\
2758 }
2759
2760 #endif
2761
2762 static struct clk_lookup clks[] = {
2763         CLK(NULL, "xin24m", &xin24m),
2764         //CLK(NULL, "xin27m", &xin27m),
2765         CLK(NULL, "xin12m", &clk_12m),
2766         CLK(NULL, "arm_pll", &arm_pll_clk),
2767         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2768         CLK(NULL, "codec_pll", &codec_pll_clk),
2769         CLK(NULL, "general_pll", &general_pll_clk),
2770
2771         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2772         CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2773
2774         CLK(NULL, "ddr", &clk_ddr),
2775         CLK(NULL, "cpu", &clk_core),
2776         CLK1(l2c),
2777         CLK1(core_dbg),
2778         CLK("smp_twd", NULL, &core_periph),
2779         CLK(NULL, "aclk_core", &aclk_core),
2780
2781         CLK(NULL, "logic", &clk_cpu_div),
2782         CLK(NULL, "aclk_cpu", &aclk_cpu),
2783         CLK(NULL, "pclk_cpu", &pclk_cpu),
2784         CLK(NULL, "atclk_cpu", &atclk_cpu),
2785         CLK(NULL, "hclk_cpu", &hclk_cpu),
2786         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2787
2788         CLK(NULL, "gpu",        &aclk_gpu),
2789
2790         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2791         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2792         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2793         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2794
2795         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2796         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2797
2798         CLK(NULL, "aclk_periph", &aclk_periph),
2799         CLK(NULL, "pclk_periph", &pclk_periph),
2800         CLK(NULL, "hclk_periph", &hclk_periph),
2801
2802         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2803         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2804
2805         CLK(NULL, "cif_out_pll", &cif_out_pll),
2806         CLK(NULL, "cif0_out_div", &cif0_out_div),
2807         CLK(NULL, "cif0_out", &cif0_out),
2808
2809         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2810         CLK(NULL, "inv_cif0", &inv_cif0),
2811         CLK(NULL, "cif0_in", &cif0_in),
2812
2813         CLK1(i2s_pll),
2814         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2815         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2816         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2817
2818         // actually no i2s1
2819         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2820         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2821         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2822
2823
2824         CLK1(spdif_div),
2825         CLK1(spdif_frac_div),
2826         CLK1(spdif),
2827
2828         CLK1(otgphy0),
2829         CLK1(otgphy1),
2830         CLK1(otgphy0_480m),
2831         CLK1(otgphy1_480m),
2832         CLK1(hsicphy_480m),
2833         CLK1(hsicphy_12m),
2834
2835         CLK(NULL, "rmii_clkin", &rmii_clkin),
2836         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2837         CLK1(mac_ref),
2838         CLK1(mii_tx),
2839
2840         CLK1(hsadc_pll_div),
2841         CLK1(hsadc_frac_div),
2842         CLK1(hsadc_ext),
2843         CLK1(hsadc_out),
2844         CLK1(hsadc_out_inv),
2845         CLK1(hsadc),
2846
2847         CLK1(saradc),
2848
2849         CLK1(smc),
2850         CLK(NULL, "smc_inv",    &clkn_smc),
2851
2852         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2853         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2854
2855         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2856         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2857         CLK1(emmc),
2858
2859         CLK1(uart_pll),
2860         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2861         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2862         CLK("rk_serial.0", "uart", &clk_uart0),
2863         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2864         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2865         CLK("rk_serial.1", "uart", &clk_uart1),
2866         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2867         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2868         CLK("rk_serial.2", "uart", &clk_uart2),
2869         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2870         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2871         CLK("rk_serial.3", "uart", &clk_uart3),
2872
2873         CLK1(timer0),
2874         CLK1(timer1),
2875         CLK1(timer2),
2876         CLK1(timer3),
2877         CLK1(timer4),
2878         CLK1(timer5),
2879         CLK1(timer6),
2880
2881         /*************************aclk_cpu***********************/
2882         CLK1(dma1),
2883         CLK1(intmem),
2884         CLK1(aclk_strc_sys),
2885
2886         /*************************hclk_cpu***********************/
2887         CLK1(rom),
2888         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2889         // actually no i2s1
2890         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2891         CLK1(hclk_spdif),
2892         CLK1(hclk_cpubus),
2893         CLK1(hclk_ahb2apb),
2894         CLK1(hclk_vio_bus),
2895         CLK1(hclk_lcdc0),
2896         CLK1(hclk_lcdc1),
2897         CLK1(hclk_cif0),
2898         CLK1(hclk_ipp),
2899         CLK1(hclk_rga),
2900         CLK1(hclk_imem0),
2901         CLK1(hclk_imem1),
2902
2903         /*************************pclk_cpu***********************/
2904         CLK1(pwm01),
2905         CLK1(pclk_timer0),
2906         CLK1(pclk_timer2),
2907         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2908         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2909         CLK1(gpio0),
2910         CLK1(gpio1),
2911         CLK1(gpio2),
2912         CLK1(efuse),
2913         CLK1(tzpc),
2914         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2915         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2916         CLK1(pclk_ddrupctl),
2917         CLK1(pclk_ddrpubl),
2918         CLK1(dbg),
2919         CLK1(grf),
2920         CLK1(pmu),
2921
2922         /*************************aclk_periph***********************/
2923         CLK1(dma2),
2924         CLK1(aclk_smc),
2925         CLK1(aclk_gps),
2926         CLK1(aclk_peri_niu),
2927         CLK1(aclk_cpu_peri),
2928         CLK1(aclk_peri_axi_matrix),
2929
2930         /*************************hclk_periph***********************/
2931         CLK1(hclk_peri_axi_matrix),
2932         CLK1(hclk_peri_ahb_arbi),
2933         CLK1(hclk_emem_peri),
2934         CLK1(hclk_mac),
2935         CLK1(nandc),
2936         CLK1(hclk_usb_peri),
2937         CLK1(hclk_otg0),
2938         CLK1(hclk_otg1),
2939         CLK1(hclk_hsic),
2940         CLK1(hclk_hsadc),
2941         CLK1(hclk_pidfilter),
2942         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2943         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2944         CLK1(hclk_emmc),
2945
2946         /*************************pclk_periph***********************/
2947         CLK1(pclk_peri_axi_matrix),
2948         CLK1(pwm23),
2949         CLK1(wdt),
2950         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2951         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2952         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2953         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2954         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2955         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2956         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2957         CLK1(gpio3),
2958         CLK1(pclk_saradc),
2959
2960         /*************************aclk_lcdc0***********************/
2961         CLK1(aclk_vio0),
2962         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2963         CLK1(aclk_cif0),
2964         CLK1(aclk_ipp),
2965
2966         /*************************aclk_lcdc1***********************/
2967         CLK1(aclk_vio1),
2968         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2969         CLK1(aclk_rga),
2970         /************************power domain**********************/
2971
2972         PD_CLK(pd_peri),
2973         PD_CLK(pd_display),
2974         PD_CLK(pd_lcdc0),
2975         PD_CLK(pd_lcdc1),
2976         PD_CLK(pd_cif0),
2977         //PD_CLK(pd_cif1),
2978         PD_CLK(pd_rga),
2979         PD_CLK(pd_ipp),
2980         //PD_CLK(pd_video),
2981         PD_CLK(pd_gpu),
2982         //PD_CLK(pd_dbg),
2983 };
2984 static void __init rk30_init_enable_clocks(void)
2985 {
2986         #if 0
2987         //clk_enable_nolock(&xin24m);
2988         //clk_enable_nolock(&clk_12m);
2989         //clk_enable_nolock(&arm_pll_clk);
2990         //clk_enable_nolock(&ddr_pll_clk);
2991         //clk_enable_nolock(&codec_pll_clk);
2992         //clk_enable_nolock(&general_pll_clk);
2993         #endif
2994         clk_enable_nolock(&clk_ddr);
2995         //clk_enable_nolock(&clk_core);
2996         clk_enable_nolock(&clk_cpu_div);
2997         clk_enable_nolock(&clk_core_gpll_path);
2998         clk_enable_nolock(&clk_l2c);
2999         clk_enable_nolock(&clk_core_dbg);
3000         clk_enable_nolock(&core_periph);
3001         clk_enable_nolock(&aclk_core);
3002         //clk_enable_nolock(&aclk_cpu);
3003         //clk_enable_nolock(&pclk_cpu);
3004         clk_enable_nolock(&atclk_cpu);
3005         //clk_enable_nolock(&hclk_cpu);
3006         clk_enable_nolock(&ahb2apb_cpu);
3007         #if 0
3008          clk_enable_nolock(&clk_gpu);
3009          clk_enable_nolock(&aclk_gpu);
3010          clk_enable_nolock(&aclk_gpu_slv);
3011          clk_enable_nolock(&aclk_gpu_mst);
3012
3013          clk_enable_nolock(&aclk_vepu);
3014          clk_enable_nolock(&hclk_vepu);
3015          clk_enable_nolock(&aclk_vdpu);
3016          clk_enable_nolock(&hclk_vdpu);
3017
3018          clk_enable_nolock(&aclk_lcdc0_pre);
3019          clk_enable_nolock(&aclk_lcdc1_pre);
3020
3021          clk_enable_nolock(&aclk_periph);
3022         clk_enable_nolock(&pclk_periph);
3023         clk_enable_nolock(&hclk_periph);
3024         #endif
3025         #if 0
3026          clk_enable_nolock(&dclk_lcdc0);
3027          clk_enable_nolock(&dclk_lcdc1);
3028
3029          clk_enable_nolock(&cif_out_pll);
3030          clk_enable_nolock(&cif0_out_div);
3031
3032          clk_enable_nolock(&cif0_out);
3033          clk_enable_nolock(&pclkin_cif0);
3034          clk_enable_nolock(&inv_cif0);
3035          clk_enable_nolock(&cif0_in);
3036
3037          clk_enable_nolock(&clk_i2s_pll);
3038          clk_enable_nolock(&clk_i2s0_div);
3039          clk_enable_nolock(&clk_i2s0_frac_div);
3040          clk_enable_nolock(&clk_i2s0);
3041
3042           actually no i2s1
3043          clk_enable_nolock(&clk_i2s0_div);
3044          clk_enable_nolock(&clk_i2s0_frac_div);
3045          clk_enable_nolock(&clk_i2s0);
3046
3047         clk_enable_nolock(&clk_spdif_div);
3048         clk_enable_nolock(&clk_spdif_frac_div);
3049         clk_enable_nolock(&clk_spdif);
3050         #endif
3051         #if 0
3052         clk_enable_nolock(&clk_otgphy0);
3053         clk_enable_nolock(&clk_otgphy1);
3054         clk_enable_nolock(&clk_otgphy0_480m);
3055         clk_enable_nolock(&clk_otgphy1_480m);
3056         clk_enable_nolock(&clk_hsicphy_480m);
3057         clk_enable_nolock(&clk_hsicphy_12m);
3058         #endif
3059
3060         #if 0
3061         clk_enable_nolock(&rmii_clkin);
3062         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
3063         clk_enable_nolock(&clk_mac_ref);
3064         clk_enable_nolock(&clk_mii_tx);
3065         #endif
3066
3067         #if 0
3068         clk_enable_nolock(&clk_hsadc_pll_div);
3069         clk_enable_nolock(&clk_hsadc_frac_div);
3070         clk_enable_nolock(&clk_hsadc_ext);
3071         clk_enable_nolock(&clk_hsadc_out);
3072         clk_enable_nolock(&clk_hsadc_out_inv);
3073         clk_enable_nolock(&clk_hsadc);
3074
3075         clk_enable_nolock(&clk_saradc);
3076         #endif
3077         /*
3078         clk_enable_nolock(&clk_smc);
3079         clk_enable_nolock(&clkn_smc);
3080         */
3081         /*
3082         clk_enable_nolock(&clk_spi0);
3083         clk_enable_nolock(&clk_spi1);
3084         */
3085         /*
3086         clk_enable_nolock(&clk_sdmmc);
3087         clk_enable_nolock(&clk_sdio);
3088         clk_enable_nolock(&clk_emmc);
3089         */
3090         #if 0
3091         clk_enable_nolock(&clk_uart_pll);
3092         clk_enable_nolock(&clk_uart0_div);
3093         clk_enable_nolock(&clk_uart0_frac_div);
3094         clk_enable_nolock(&clk_uart0);
3095         clk_enable_nolock(&clk_uart1_div);
3096         clk_enable_nolock(&clk_uart1_frac_div);
3097         clk_enable_nolock(&clk_uart1);
3098         clk_enable_nolock(&clk_uart2_div);
3099         clk_enable_nolock(&clk_uart2_frac_div);
3100         clk_enable_nolock(&clk_uart2);
3101         clk_enable_nolock(&clk_uart3_div);
3102         clk_enable_nolock(&clk_uart3_frac_div);
3103         clk_enable_nolock(&clk_uart3);
3104         #endif
3105         #if CONFIG_RK_DEBUG_UART == 0
3106                 clk_enable_nolock(&clk_uart0);
3107                 clk_enable_nolock(&clk_pclk_uart0);
3108         #elif CONFIG_RK_DEBUG_UART == 1
3109                 clk_enable_nolock(&clk_uart1);
3110                 clk_enable_nolock(&clk_pclk_uart1);
3111
3112         #elif CONFIG_RK_DEBUG_UART == 2
3113                 clk_enable_nolock(&clk_uart2);
3114                 clk_enable_nolock(&clk_pclk_uart2);
3115
3116         #elif CONFIG_RK_DEBUG_UART == 3
3117                 clk_enable_nolock(&clk_uart3);
3118                 clk_enable_nolock(&clk_pclk_uart3);
3119
3120         #endif
3121         #if 0
3122         clk_enable_nolock(&clk_timer0);
3123         clk_enable_nolock(&clk_timer1);
3124         clk_enable_nolock(&clk_timer2);
3125         #endif
3126
3127         /*************************aclk_cpu***********************/
3128         clk_enable_nolock(&clk_dma1);
3129         clk_enable_nolock(&clk_intmem);
3130         clk_enable_nolock(&clk_aclk_strc_sys);
3131
3132         /*************************hclk_cpu***********************/
3133         clk_enable_nolock(&clk_rom);
3134         #if 0
3135         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3136         // actually no i2s1
3137         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3138         clk_enable_nolock(&clk_hclk_spdif);
3139         #endif
3140         clk_enable_nolock(&clk_hclk_cpubus);
3141         clk_enable_nolock(&clk_hclk_ahb2apb);
3142         clk_enable_nolock(&clk_hclk_vio_bus);
3143         #if 0
3144         clk_enable_nolock(&clk_hclk_lcdc0);
3145         clk_enable_nolock(&clk_hclk_lcdc1);
3146         clk_enable_nolock(&clk_hclk_cif0);
3147         clk_enable_nolock(&clk_hclk_ipp);
3148         clk_enable_nolock(&clk_hclk_rga);
3149         #endif
3150         clk_enable_nolock(&clk_hclk_imem0);
3151         clk_enable_nolock(&clk_hclk_imem1);
3152
3153         /*************************pclk_cpu***********************/
3154         #if 0
3155         clk_enable_nolock(&clk_pwm01);
3156         clk_enable_nolock(&clk_pclk_timer0);
3157         clk_enable_nolock(&clk_pclk_timer1);
3158         clk_enable_nolock(&clk_pclk_timer2);
3159         clk_enable_nolock(&clk_i2c0);
3160         clk_enable_nolock(&clk_i2c1);
3161         clk_enable_nolock(&clk_gpio0);
3162         clk_enable_nolock(&clk_gpio1);
3163         clk_enable_nolock(&clk_gpio2);
3164         clk_enable_nolock(&clk_efuse);
3165         #endif
3166         clk_enable_nolock(&clk_tzpc);
3167         //clk_enable_nolock(&clk_pclk_uart0);
3168         //clk_enable_nolock(&clk_pclk_uart1);
3169         clk_enable_nolock(&clk_pclk_ddrupctl);
3170         clk_enable_nolock(&clk_pclk_ddrpubl);
3171         clk_enable_nolock(&clk_dbg);
3172         clk_enable_nolock(&clk_grf);
3173         clk_enable_nolock(&clk_pmu);
3174
3175         /*************************aclk_periph***********************/
3176         clk_enable_nolock(&clk_dma2);
3177         clk_enable_nolock(&clk_aclk_smc);
3178         clk_enable_nolock(&clk_aclk_peri_niu);
3179         clk_enable_nolock(&clk_aclk_cpu_peri);
3180         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3181
3182         /*************************hclk_periph***********************/
3183         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3184         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3185         clk_enable_nolock(&clk_hclk_emem_peri);
3186         //clk_enable_nolock(&clk_hclk_mac);
3187         clk_enable_nolock(&clk_nandc);
3188         clk_enable_nolock(&clk_hclk_usb_peri);
3189         #if 0
3190         clk_enable_nolock(&clk_hclk_otg0);
3191         clk_enable_nolock(&clk_hclk_otg1);
3192         clk_enable_nolock(&clk_hclk_hsic);
3193         clk_enable_nolock(&clk_hclk_gps);
3194         clk_enable_nolock(&clk_hclk_hsadc);
3195         clk_enable_nolock(&clk_hclk_pidfilter);
3196         clk_enable_nolock(&clk_hclk_sdmmc);
3197         clk_enable_nolock(&clk_hclk_sdio);
3198         clk_enable_nolock(&clk_hclk_emmc);
3199         #endif
3200
3201         /*************************pclk_periph***********************/
3202         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3203         #if 0
3204         clk_enable_nolock(&clk_pwm23);
3205         clk_enable_nolock(&clk_wdt);
3206         clk_enable_nolock(&clk_pclk_spi0);
3207         clk_enable_nolock(&clk_pclk_spi1);
3208         clk_enable_nolock(&clk_pclk_uart2);
3209         clk_enable_nolock(&clk_pclk_uart3);
3210         #endif
3211         #if 0
3212         clk_enable_nolock(&clk_i2c2);
3213         clk_enable_nolock(&clk_i2c3);
3214         clk_enable_nolock(&clk_i2c4);
3215         clk_enable_nolock(&clk_gpio3);
3216         clk_enable_nolock(&clk_pclk_saradc);
3217         #endif
3218         /*************************aclk_lcdc0***********************/
3219 #if 1
3220         //clk_enable_nolock(&clk_aclk_vio0);
3221         //clk_enable_nolock(&clk_aclk_lcdc0);
3222         //clk_enable_nolock(&clk_aclk_cif0);
3223         //clk_enable_nolock(&clk_aclk_ipp);
3224 #endif
3225         /*************************aclk_lcdc1***********************/
3226 #if 1
3227         //clk_enable_nolock(&clk_aclk_vio1);
3228         //clk_enable_nolock(&clk_aclk_lcdc1);
3229         //clk_enable_nolock(&clk_aclk_rga);
3230 #endif
3231         /************************power domain**********************/
3232
3233 }
3234 static void periph_clk_set_init(void)
3235 {
3236         unsigned long aclk_p, hclk_p, pclk_p;
3237         unsigned long ppll_rate = general_pll_clk.rate;
3238         //aclk 148.5
3239
3240         /* general pll */
3241         switch (ppll_rate) {
3242                 case 148500* KHZ:
3243                         aclk_p = 148500 * KHZ;
3244                         hclk_p = aclk_p >> 1;
3245                         pclk_p = aclk_p >> 2;
3246                         break;
3247                 case 1188*MHZ:
3248                         aclk_p = aclk_p >> 3; // 0
3249                         hclk_p = aclk_p >> 1;
3250                         pclk_p = aclk_p >> 2;
3251
3252                 case 297 * MHZ:
3253                         aclk_p = ppll_rate >> 1;
3254                         hclk_p = aclk_p >> 0;
3255                         pclk_p = aclk_p >> 1;
3256                         break;
3257
3258                 case 300 * MHZ:
3259                         aclk_p = ppll_rate >> 1;
3260                         hclk_p = aclk_p >> 0;
3261                         pclk_p = aclk_p >> 1;
3262                         break;
3263                 case 594 * MHZ:
3264                         aclk_p = ppll_rate >> 2;
3265                         hclk_p = aclk_p >> 0;
3266                         pclk_p = aclk_p >> 1;
3267                         break;
3268                 default:
3269                         aclk_p = 150 * MHZ;
3270                         hclk_p = 150 * MHZ;
3271                         pclk_p = 75 * MHZ;
3272                         break;
3273         }
3274         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3275         clk_set_rate_nolock(&aclk_periph, aclk_p);
3276         clk_set_rate_nolock(&hclk_periph, hclk_p);
3277         clk_set_rate_nolock(&pclk_periph, pclk_p);
3278 }
3279
3280 static void cpu_axi_init(void)
3281 {
3282         unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3283         unsigned long gpll_rate = general_pll_clk.rate;
3284
3285         switch (gpll_rate) {
3286                 case 297 * MHZ:
3287                         cpu_div_rate = gpll_rate;
3288                         aclk_cpu_rate = cpu_div_rate >> 0;
3289                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3290                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3291                         break;
3292
3293                 case 594 * MHZ:
3294                         cpu_div_rate = gpll_rate >> 1;
3295                         aclk_cpu_rate = cpu_div_rate >> 0;
3296                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3297                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3298                         break;
3299                 default:
3300                         aclk_cpu_rate = 150 * MHZ;
3301                         hclk_cpu_rate = 150 * MHZ;
3302                         pclk_cpu_rate = 75 * MHZ;
3303                         break;
3304         }
3305         ahb2apb_cpu_rate = pclk_cpu_rate;
3306
3307         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3308         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3309         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3310         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3311         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3312         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3313 }
3314
3315 void rk30_clock_common_i2s_init(void)
3316 {
3317         unsigned long i2s_rate;
3318         //20 times
3319         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3320                 i2s_rate = 49152000;
3321         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3322                 i2s_rate = 24576000;
3323         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3324                 i2s_rate = 22579000;
3325         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3326                 i2s_rate = 12288000;
3327         } else {
3328                 i2s_rate = 49152000;
3329         }
3330
3331         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3332                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3333         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3334                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3335         } else {
3336                 if(general_pll_clk.rate > codec_pll_clk.rate)
3337                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3338                 else
3339                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3340         }
3341 }
3342
3343 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3344 {
3345
3346         //general
3347         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3348         //code pll
3349         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3350
3351         cpu_axi_init();
3352         clk_set_rate_nolock(&clk_core, 816 * MHZ);
3353         //periph clk
3354         periph_clk_set_init();
3355
3356         //i2s
3357         rk30_clock_common_i2s_init();
3358
3359         // spi
3360         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3361         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3362
3363         // uart
3364         if(rk30_clock_flags & CLK_FLG_UART_1_3M)
3365                 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3366         else
3367                 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3368         //mac
3369         if(!(gpll_rate % (50 * MHZ)))
3370                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3371         else if(!(ddr_pll_clk.rate % (50 * MHZ)))
3372                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3373         else
3374                 CLKDATA_ERR("mac can't get 50mhz\n");
3375
3376         //hsadc
3377         //auto pll sel
3378         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3379
3380         //lcdc0 lcd auto sel pll
3381         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3382         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3383
3384         //cif
3385         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3386
3387         //axi lcdc auto sel
3388         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3389         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3390         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3391         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3392
3393         //axi vepu auto sel
3394         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3395         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3396
3397         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3398         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3399         //gpu auto sel
3400         clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
3401         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3402
3403         clk_set_rate_nolock(&clk_uart0, 49500000);
3404         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3405         clk_set_rate_nolock(&clk_sdio, 24750000);
3406
3407 }
3408
3409 static struct clk def_ops_clk = {
3410         .get_parent = clksel_get_parent,
3411         .set_parent = clksel_set_parent,
3412 };
3413
3414 #ifdef CONFIG_PROC_FS
3415 struct clk_dump_ops dump_ops;
3416 #endif
3417 void rk_dump_clock_info(void);
3418 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3419 {
3420         struct clk_lookup *lk;
3421
3422         if (soc_is_rk3188plus()) {
3423                 arm_pll_clk.recalc = plus_plls_clk_recalc;
3424                 ddr_pll_clk.recalc = plus_plls_clk_recalc;
3425                 codec_pll_clk.recalc = plus_plls_clk_recalc;
3426                 general_pll_clk.recalc = plus_plls_clk_recalc;
3427
3428                 arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
3429                 codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
3430                 general_pll_clk.set_rate = plus_gpll_clk_set_rate;
3431         }
3432         clk_register_dump_ops(&dump_ops);
3433         clk_register_default_ops_clk(&def_ops_clk);
3434         rk30_clock_flags = flags;
3435         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3436 #ifdef RK30_CLK_OFFBOARD_TEST
3437                 rk30_clkdev_add(lk);
3438 #else
3439                 clkdev_add(lk);
3440 #endif
3441                 clk_register(lk->clk);
3442         }
3443         clk_recalculate_root_clocks_nolock();
3444
3445         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3446
3447         /*
3448          * Only enable those clocks we will need, let the drivers
3449          * enable other clocks as necessary
3450          */
3451         rk30_init_enable_clocks();
3452 #if 0
3453         // print loader config
3454         CLKDATA_DBG("%s clks register dbg start\n", __func__);
3455         rk_dump_clock_info();
3456         rk30_clk_dump_regs();
3457
3458         CLKDATA_DBG("%s clks register dbg end\n", __func__);
3459 #endif
3460         /*
3461          * Disable any unused clocks left on by the bootloader
3462          */
3463         //clk_disable_unused();
3464         rk30_clock_common_init(gpll, cpll);
3465         preset_lpj = loops_per_jiffy;
3466
3467         //gpio6_b7
3468         //regfile_writel(0xc0004000,0x10c);
3469         //cru_writel(0x07000000,CRU_MISC_CON);
3470
3471 }
3472 extern int rk3188_dvfs_init(void);
3473
3474 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3475 {
3476         DVFS_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
3477                         gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3478         _rk30_clock_data_init(gpll, cpll, flags);
3479         rk3188_dvfs_init();
3480 }
3481
3482 /*
3483  * You can override arm_clk rate with armclk= cmdline option.
3484  */
3485 static int __init armclk_setup(char *str)
3486 {
3487         get_option(&str, &armclk);
3488
3489         if (!armclk)
3490                 return 0;
3491         if (armclk < 10000)
3492                 armclk *= MHZ;
3493         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3494         return 0;
3495 }
3496 #ifndef RK30_CLK_OFFBOARD_TEST
3497 early_param("armclk", armclk_setup);
3498 #endif
3499
3500
3501 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3502 {
3503         struct clk *ck;
3504         int i;
3505         unsigned long rate = clk->rate;
3506         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3507         for (i = 0; i < deep; i++)
3508                 printk("    ");
3509
3510         printk("%-11s ", clk->name);
3511 #ifndef RK30_CLK_OFFBOARD_TEST
3512         if (clk->flags & IS_PD) {
3513                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3514         }
3515 #endif
3516         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3517                 int idx = clk->gate_idx;
3518                 u32 v;
3519                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3520                 printk("%s ", v ? "off" : "on ");
3521         }
3522
3523         if (clk->pll) {
3524                 u32 pll_mode;
3525                 u32 pll_id = clk->pll->id;
3526                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3527                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3528                         printk("slow   ");
3529                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3530                         printk("normal ");
3531                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3532                         printk("deep   ");
3533
3534                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3535                         printk("bypass ");
3536         } else if(clk == &clk_ddr) {
3537                 rate = clk->recalc(clk);
3538         }
3539
3540         if (rate >= MHZ) {
3541                 if (rate % MHZ)
3542                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3543                 else
3544                         printk("%ld MHz", rate / MHZ);
3545         } else if (rate >= KHZ) {
3546                 if (rate % KHZ)
3547                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3548                 else
3549                         printk("%ld KHz", rate / KHZ);
3550         } else {
3551                 printk("%ld Hz", rate);
3552         }
3553
3554         printk(" usecount = %d", clk->usecount);
3555
3556         if (clk->parent)
3557                 printk(" parent = %s", clk->parent->name);
3558
3559         printk("\n");
3560
3561         list_for_each_entry(ck, root_clocks, node) {
3562                 if (ck->parent == clk)
3563                         rk_dump_clock(ck, deep + 1, root_clocks);
3564         }
3565 }
3566
3567 #if 1
3568 struct list_head *get_rk_clocks_head(void);
3569
3570 void rk_dump_clock_info(void)
3571 {
3572         struct clk* clk;
3573         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3574                 if (!clk->parent)
3575                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3576         }
3577 }
3578 #endif
3579
3580 #ifdef CONFIG_PROC_FS
3581
3582 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3583 {
3584         struct clk *ck;
3585         int i;
3586         unsigned long rate = clk->rate;
3587         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3588         for (i = 0; i < deep; i++)
3589                 seq_printf(s, "    ");
3590
3591         seq_printf(s, "%-11s ", clk->name);
3592 #ifndef RK30_CLK_OFFBOARD_TEST
3593         if (clk->flags & IS_PD) {
3594                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3595         }
3596 #endif
3597         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3598                 int idx = clk->gate_idx;
3599                 u32 v;
3600                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3601                 seq_printf(s, "%s ", v ? "off" : "on ");
3602         }
3603
3604         if (clk->pll) {
3605                 u32 pll_mode;
3606                 u32 pll_id = clk->pll->id;
3607                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3608                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3609                         seq_printf(s, "slow   ");
3610                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3611                         seq_printf(s, "normal ");
3612                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3613                         seq_printf(s, "deep   ");
3614
3615                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3616                         seq_printf(s, "bypass ");
3617         } else if(clk == &clk_ddr) {
3618                 rate = clk->recalc(clk);
3619         }
3620
3621         if (rate >= MHZ) {
3622                 if (rate % MHZ)
3623                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3624                 else
3625                         seq_printf(s, "%ld MHz", rate / MHZ);
3626         } else if (rate >= KHZ) {
3627                 if (rate % KHZ)
3628                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3629                 else
3630                         seq_printf(s, "%ld KHz", rate / KHZ);
3631         } else {
3632                 seq_printf(s, "%ld Hz", rate);
3633         }
3634
3635         seq_printf(s, " usecount = %d", clk->usecount);
3636
3637         if (clk->parent)
3638                 seq_printf(s, " parent = %s", clk->parent->name);
3639
3640         seq_printf(s, "\n");
3641
3642         list_for_each_entry(ck, root_clocks, node) {
3643                 if (ck->parent == clk)
3644                         dump_clock(s, ck, deep + 1, root_clocks);
3645         }
3646 }
3647
3648 static void dump_regs(struct seq_file *s)
3649 {
3650         int i = 0;
3651         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3652         seq_printf(s, "\nPLLRegisters:\n");
3653         for(i = 0; i < END_PLL_ID; i++) {
3654                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3655                                 cru_readl(PLL_CONS(i, 0)),
3656                                 cru_readl(PLL_CONS(i, 1)),
3657                                 cru_readl(PLL_CONS(i, 2)),
3658                                 cru_readl(PLL_CONS(i, 3))
3659                           );
3660         }
3661         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3662
3663         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3664                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3665         }
3666         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3667                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3668         }
3669         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3670         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3671
3672         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3673                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3674         }
3675         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3676         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3677
3678 }
3679
3680 void rk30_clk_dump_regs(void)
3681 {
3682         int i = 0;
3683         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3684         printk("\nPLLRegisters:\n");
3685         for(i = 0; i < END_PLL_ID; i++) {
3686                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3687                                 cru_readl(PLL_CONS(i, 0)),
3688                                 cru_readl(PLL_CONS(i, 1)),
3689                                 cru_readl(PLL_CONS(i, 2)),
3690                                 cru_readl(PLL_CONS(i, 3))
3691                       );
3692         }
3693         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3694
3695         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3696                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3697         }
3698         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3699                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3700         }
3701         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3702         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3703
3704         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3705                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3706         }
3707         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3708         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3709
3710 }
3711
3712
3713 #ifdef CONFIG_PROC_FS
3714 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3715 struct clk_dump_ops dump_ops = {
3716         .dump_clk = dump_clock,
3717         .dump_regs = dump_regs,
3718 };
3719 #endif
3720
3721
3722 #endif /* CONFIG_PROC_FS */
3723
3724
3725
3726
3727 #ifdef RK30_CLK_OFFBOARD_TEST
3728 struct clk *test_get_parent(struct clk *clk) {
3729         return clk->parent;
3730 }
3731
3732 void i2s_test(void)
3733 {
3734         struct clk *i2s_clk = &clk_i2s0;
3735
3736         clk_enable_nolock(i2s_clk);
3737
3738         clk_set_rate_nolock(i2s_clk, 12288000);
3739         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3740         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3741         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3742         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3743         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3744
3745 }
3746
3747 void uart_test(void)
3748 {
3749         struct clk *uart_clk = &clk_uart0;
3750
3751         clk_enable_nolock(uart_clk);
3752
3753         clk_set_rate_nolock(uart_clk, 12288000);
3754         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3755         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3756         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3757         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3758         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3759
3760 }
3761 void hsadc_test(void)
3762 {
3763         struct clk *hsadc_clk = &clk_hsadc;
3764
3765         printk("******************hsadc_test**********************\n");
3766         clk_enable_nolock(hsadc_clk);
3767
3768         clk_set_rate_nolock(hsadc_clk, 12288000);
3769         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3770
3771
3772         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3773         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3774
3775         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3776
3777         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3778
3779         printk("******************hsadc out clock**********************\n");
3780
3781         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3782         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3783         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3784         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3785
3786
3787
3788 }
3789
3790 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3791 {
3792         //arm
3793         printk("*********arm_pll_clk***********\n");
3794         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3795
3796         printk("*********set clk_core parent***********\n");
3797         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3798         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3799
3800         //general
3801         printk("*********general_pll_clk***********\n");
3802         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3803
3804         //code pll
3805         printk("*********codec_pll_clk***********\n");
3806         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3807
3808
3809         printk("*********periph_clk_set_init***********\n");
3810         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3811         periph_clk_set_init();
3812
3813 #if 0 //
3814         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3815 #else
3816         printk("*********clk i2s***********\n");
3817         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3818         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3819         i2s_test();
3820 #endif
3821         // spi
3822         clk_enable_nolock(&clk_spi0);
3823         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3824         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3825         //saradc
3826         clk_enable_nolock(&clk_saradc);
3827         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3828         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3829         //sdio
3830         clk_enable_nolock(&clk_sdio);
3831         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3832         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3833         // uart
3834         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3835         uart_test();
3836         //mac
3837         printk("*********mac***********\n");
3838
3839         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3840         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3841
3842         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3843         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3844         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3845
3846         printk("*********mac mii set***********\n");
3847         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3848         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3849         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3850         //hsadc
3851         printk("*********hsadc 1***********\n");
3852         //auto pll
3853         hsadc_test();
3854         //lcdc
3855         clk_enable_nolock(&dclk_lcdc0);
3856
3857         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
3858         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
3859
3860         //cif
3861         clk_enable_nolock(&cif0_out);
3862
3863         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3864         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
3865
3866         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
3867         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3868
3869         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
3870         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3871         //cif_in
3872         clk_enable_nolock(&cif0_in);
3873         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
3874         //axi lcdc
3875         clk_enable_nolock(&aclk_lcdc0);
3876         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
3877         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
3878         //axi vepu
3879         clk_enable_nolock(&aclk_vepu);
3880         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3881         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
3882
3883         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
3884         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
3885
3886         printk("test end\n");
3887
3888         /* arm pll
3889            clk_set_rate_nolock(&arm_pll_clk, armclk);
3890            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
3891            */
3892         //
3893         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3894         //
3895         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3896         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3897
3898 }
3899
3900
3901
3902
3903
3904 static LIST_HEAD(rk30_clocks);
3905 static DEFINE_MUTEX(rk30_clocks_mutex);
3906
3907 static inline int __rk30clk_get(struct clk *clk)
3908 {
3909         return 1;
3910 }
3911 void rk30_clkdev_add(struct clk_lookup *cl)
3912 {
3913         mutex_lock(&rk30_clocks_mutex);
3914         list_add_tail(&cl->node, &rk30_clocks);
3915         mutex_unlock(&rk30_clocks_mutex);
3916 }
3917 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
3918         struct clk_lookup *p, *cl = NULL;
3919         int match, best = 0;
3920
3921         list_for_each_entry(p, &rk30_clocks, node) {
3922                 match = 0;
3923                 if (p->dev_id) {
3924                         if (!dev_id || strcmp(p->dev_id, dev_id))
3925                                 continue;
3926                         match += 2;
3927                 }
3928                 if (p->con_id) {
3929                         if (!con_id || strcmp(p->con_id, con_id))
3930                                 continue;
3931                         match += 1;
3932                 }
3933
3934                 if (match > best) {
3935                         cl = p;
3936                         if (match != 3)
3937                                 best = match;
3938                         else
3939                                 break;
3940                 }
3941         }
3942         return cl;
3943 }
3944
3945 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
3946         struct clk_lookup *cl;
3947
3948         mutex_lock(&rk30_clocks_mutex);
3949         cl = rk30_clk_find(dev_id, con_id);
3950         if (cl && !__rk30clk_get(cl->clk))
3951                 cl = NULL;
3952         mutex_unlock(&rk30_clocks_mutex);
3953
3954         return cl ? cl->clk : ERR_PTR(-ENOENT);
3955 }
3956 //EXPORT_SYMBOL(rk30_clk_get_sys);
3957
3958 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
3959         const char *dev_id = dev ? dev_name(dev) : NULL;
3960         return rk30_clk_get_sys(dev_id, con_id);
3961 }
3962 //EXPORT_SYMBOL(rk30_clk_get);
3963
3964
3965 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3966
3967 void rk30_clocks_test(void)
3968 {
3969         struct clk *test_gpll;
3970         test_gpll = rk30_clk_get(NULL, "general_pll");
3971         if(test_gpll) {
3972                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
3973                 printk("gpll rate=%lu\n", test_gpll->rate);
3974         }
3975         //while(1);
3976 }
3977
3978 void __init rk30_clock_init_test(void)
3979 {
3980
3981         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
3982         //while(1);
3983 }
3984
3985
3986 #endif
3987
3988