arch/arm/mach-rk3188/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include <mach/clock.h>
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29 #include <mach/ddr.h>
  30
  31 #define MHZ                     (1000UL * 1000UL)
  32 #define KHZ                     (1000UL)
  33 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  34 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
  35 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  36 void rk30_clk_dump_regs(void);
  37
  38 //flags bit
  39 //has extern 27mhz
  40 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  41 //max i2s rate
  42 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  43 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  44 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  45 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  46 //uart 1m\3m
  47 #define CLK_FLG_UART_1_3M                       (1<<5)
  48
  49 #define ARCH_RK31
  50
  51 struct apll_clk_set {
  52         unsigned long   rate;
  53         u32     pllcon0;
  54         u32     pllcon1;
  55         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  56         u32     rst_dly;//us
  57         u32     clksel0;
  58         u32     clksel1;
  59         unsigned long   lpj;
  60 };
  61 struct pll_clk_set {
  62         unsigned long   rate;
  63         u32     pllcon0;
  64         u32     pllcon1;
  65         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  66         unsigned long   rst_dly;//us
  67 };
  68
  69 #define SET_PLL_DATA(_pll_id,_table) \
  70 {\
  71         .id=(_pll_id),\
  72         .table=(_table),\
  73 }
  74
  75
  76 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  77 { \
  78         .rate   = (_mhz) * KHZ, \
  79         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  80         .pllcon1 = PLL_CLKF_SET(nf),\
  81         .rst_dly=((nr*500)/24+1),\
  82 }
  83
  84
  85 #define _APLL_SET_LPJ(_mhz) \
  86         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  87
  88
  89 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  90                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  91 { \
  92         .rate   = _mhz * MHZ, \
  93         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  94         .pllcon1 = PLL_CLKF_SET(nf),\
  95         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
  96         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
  97         _APLL_SET_LPJ(_mhz),\
  98         .rst_dly=((nr*500)/24+1),\
  99 }
 100
 101 #define CRU_DIV_SET(mask,shift,max) \
 102         .div_mask=(mask),\
 103 .div_shift=(shift),\
 104 .div_max=(max)
 105
 106
 107 #define CRU_SRC_SET(mask,shift ) \
 108         .src_mask=(mask),\
 109 .src_shift=(shift)
 110
 111 #define CRU_PARENTS_SET(parents_array) \
 112         .parents=(parents_array),\
 113 .parents_num=ARRAY_SIZE((parents_array))
 114
 115 #define CRU_GATE_MODE_SET(_func,_IDX) \
 116         .mode=_func,\
 117 .gate_idx=(_IDX)
 118
 119 struct clk_src_sel {
 120         struct clk      *parent;
 121         u8      value;//crt bit
 122         u8      flag;
 123         //selgate
 124 };
 125
 126 #define GATE_CLK(NAME,PARENT,ID) \
 127         static struct clk clk_##NAME = { \
 128                 .name           = #NAME, \
 129                 .parent         = &PARENT, \
 130                 .mode           = gate_mode, \
 131                 .gate_idx       = CLK_GATE_##ID, \
 132         }
 133 #ifdef RK30_CLK_OFFBOARD_TEST
 134 u32 TEST_GRF_REG[0x240];
 135 u32 TEST_CRU_REG[0x240];
 136 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 137
 138 u32 cru_writel_is_pr(u32 offset)
 139 {
 140         return (offset == 0x4000);
 141 }
 142 void cru_writel(u32 v, u32 offset)
 143 {
 144
 145         u32 mask_v = v >> 16;
 146         TEST_CRU_REG[offset/4] &= (~mask_v);
 147
 148         v &= (mask_v);
 149
 150         TEST_CRU_REG[offset/4] |= v;
 151         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 152
 153         if(cru_writel_is_pr(offset)) {
 154                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 155
 156         }
 157
 158 }
 159 void cru_writel_i2s(u32 v, u32 offset)
 160 {
 161         TEST_CRU_REG[offset/4] = v;
 162 }
 163 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 164
 165 #define regfile_readl(offset)   (0xffffffff)
 166 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 167 void rk30_clkdev_add(struct clk_lookup *cl);
 168 #else
 169 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 170 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 171 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 172 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 173
 174 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 175 #endif
 176
 177 #define DEBUG
 178 #ifdef DEBUG
 179 //#define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 180 //#define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 181 #define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
 182 #define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
 183 #else
 184 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 185 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 186 #endif
 187 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 188 #define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
 189
 190
 191 #define get_cru_bits(con,mask,shift)\
 192         ((cru_readl((con)) >> (shift)) & (mask))
 193
 194 #define set_cru_bits_w_msk(val,mask,shift,con)\
 195         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 196
 197
 198 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 199                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 200
 201
 202 static u32 rk30_clock_flags = 0;
 203 static struct clk codec_pll_clk;
 204 static struct clk general_pll_clk;
 205 static struct clk arm_pll_clk;
 206 static unsigned long lpj_gpll;
 207 static unsigned int __initdata armclk = 504 * MHZ;
 208
 209
 210 /************************clk recalc div rate*********************************/
 211
 212 //for free div
 213 static unsigned long clksel_recalc_div(struct clk *clk)
 214 {
 215         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 216
 217         unsigned long rate = clk->parent->rate / div;
 218         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 219         return rate;
 220 }
 221
 222 //for div 1 2 4 2^n
 223 static unsigned long clksel_recalc_shift(struct clk *clk)
 224 {
 225         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 226         unsigned long rate = clk->parent->rate >> shift;
 227         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 228         return rate;
 229 }
 230
 231
 232 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 233 {
 234         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 235         unsigned long rate = clk->parent->rate >> shift;
 236         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 237         return rate;
 238 }
 239
 240 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 241 {
 242         unsigned long rate = clk->parent->rate;
 243         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 244         return rate;
 245 }
 246 /********************************set div rate***********************************/
 247
 248 //for free div
 249 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 250 {
 251         u32 div;
 252         for (div = 0; div < clk->div_max; div++) {
 253                 u32 new_rate = clk->parent->rate / (div + 1);
 254                 if (new_rate <= rate) {
 255                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 256                         //clk->rate = new_rate;
 257                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 258                                         clk->name, rate, div + 1);
 259                         return 0;
 260                 }
 261         }
 262         return -ENOENT;
 263 }
 264
 265 //for div 1 2 4 2^n
 266 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 267 {
 268         u32 shift;
 269         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 270                 u32 new_rate = clk->parent->rate >> shift;
 271                 if (new_rate <= rate) {
 272                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 273                         clk->rate = new_rate;
 274                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 275                                         clk->name, rate, shift);
 276                         return 0;
 277                 }
 278         }
 279         return -ENOENT;
 280 }
 281
 282 //for div 2 4 2^n
 283 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 284 {
 285         u32 shift;
 286
 287         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 288                 u32 new_rate = clk->parent->rate >> shift;
 289                 if (new_rate <= rate) {
 290                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 291                         clk->rate = new_rate;
 292                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 293                                         clk->name, rate, shift);
 294                         return 0;
 295                 }
 296         }
 297         return -ENOENT;
 298 }
 299 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 300 {
 301         u32 div;
 302         unsigned long new_rate;
 303         for (div = 0; div < div_max; div++) {
 304                 new_rate = rate / (div + 1);
 305                 if (new_rate <= rate_out) {
 306                         return div + 1;
 307                 }
 308         }
 309         return div_max ? div_max : 1;
 310 }
 311 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 312         u32 div[2] = {0, 0};
 313         unsigned long new_rate[2] = {0, 0};
 314         u32 i;
 315
 316         if(clk->rate == rate)
 317                 return clk->parent;
 318         for(i = 0; i < 2; i++) {
 319                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 320                 new_rate[i] = clk->parents[i]->rate / div[i];
 321                 if(new_rate[i] == rate) {
 322                         *div_out = div[i];
 323                         return clk->parents[i];
 324                 }
 325         }
 326         if(new_rate[0] < new_rate[1])
 327                 i = 1;
 328         else
 329                 i = 0;
 330         *div_out = div[i];
 331         return clk->parents[i];
 332 }
 333
 334 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 335 {
 336         struct clk *p_clk;
 337         u32 div, old_div;
 338         int ret = 0;
 339         if(clk->rate == rate)
 340                 return 0;
 341         p_clk = get_freediv_parents_div(clk, rate, &div);
 342
 343         if(!p_clk)
 344                 return -ENOENT;
 345
 346         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 347         if (clk->parent != p_clk) {
 348                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 349
 350                 if(div > old_div) {
 351                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 352                 }
 353                 ret = clk_set_parent_nolock(clk, p_clk);
 354                 if(ret) {
 355                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 356                         return -ENOENT;
 357                 }
 358         }
 359         //set div
 360         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 361         return 0;
 362 }
 363
 364 //rate==div rate //hdmi
 365 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 366 {
 367         struct clk *p_clk;
 368         u32 div, old_div;
 369         int ret;
 370         p_clk = get_freediv_parents_div(clk, rate, &div);
 371
 372         if(!p_clk)
 373                 return -ENOENT;
 374
 375         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 376                 return -ENOENT;
 377
 378         if (clk->parent != p_clk) {
 379                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 380                                 clk->div_shift, clk->div_mask) + 1;
 381                 if(div > old_div) {
 382                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 383                 }
 384                 ret = clk_set_parent_nolock(clk, p_clk);
 385                 if (ret) {
 386                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 387                         return ret;
 388                 }
 389         }
 390         //set div
 391         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 392         return 0;
 393 }
 394
 395 /***************************round********************************/
 396
 397 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 398 {
 399         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 400 }
 401
 402 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 403 {
 404         u32 div;
 405         struct clk *p_clk;
 406         if(clk->rate == rate)
 407                 return clk->rate;
 408         p_clk = get_freediv_parents_div(clk, rate, &div);
 409         if(!p_clk)
 410                 return 0;
 411         return p_clk->rate / div;
 412 }
 413
 414 /**************************************others seting************************************/
 415
 416 static struct clk *clksel_get_parent(struct clk *clk) {
 417         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 418 }
 419 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 420 {
 421         u32 i;
 422         if (unlikely(!clk->parents))
 423                 return -EINVAL;
 424         for (i = 0; (i < clk->parents_num); i++) {
 425                 if (clk->parents[i] != parent)
 426                         continue;
 427                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 428                 return 0;
 429         }
 430         return -EINVAL;
 431 }
 432
 433 static int gate_mode(struct clk *clk, int on)
 434 {
 435         int idx = clk->gate_idx;
 436         if (idx >= CLK_GATE_MAX)
 437                 return -EINVAL;
 438         if(on) {
 439                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 440                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 441                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 442         } else {
 443                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 444                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 445                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 446         }
 447         return 0;
 448 }
 449 /*****************************frac set******************************************/
 450
 451 static unsigned long clksel_recalc_frac(struct clk *clk)
 452 {
 453         unsigned long rate;
 454         u64 rate64;
 455         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 456         if (r == 0) // FPGA ?
 457                 return clk->parent->rate;
 458         numerator = r >> 16;
 459         denominator = r & 0xFFFF;
 460         rate64 = (u64)clk->parent->rate * numerator;
 461         do_div(rate64, denominator);
 462         rate = rate64;
 463         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 464         return rate;
 465 }
 466
 467 static u32 clk_gcd(u32 numerator, u32 denominator)
 468 {
 469         u32 a, b;
 470
 471         if (!numerator || !denominator)
 472                 return 0;
 473         if (numerator > denominator) {
 474                 a = numerator;
 475                 b = denominator;
 476         } else {
 477                 a = denominator;
 478                 b = numerator;
 479         }
 480         while (b != 0) {
 481                 int r = b;
 482                 b = a % b;
 483                 a = r;
 484         }
 485
 486         return a;
 487 }
 488
 489 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 490                 u32 *numerator, u32 *denominator)
 491 {
 492         u32 gcd_vl;
 493         gcd_vl = clk_gcd(rate, rate_out);
 494         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 495
 496         if (!gcd_vl) {
 497                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 498                 return -ENOENT;
 499         }
 500
 501         *numerator = rate_out / gcd_vl;
 502         *denominator = rate / gcd_vl;
 503
 504         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 505                         *numerator, *denominator, *denominator / *numerator);
 506
 507         if (*numerator > 0xffff || *denominator > 0xffff ||
 508                         (*denominator / (*numerator)) < 20) {
 509                 CLKDATA_ERR("can't get a available nume and deno\n");
 510                 return -ENOENT;
 511         }
 512
 513         return 0;
 514
 515 }
 516 /* *********************pll **************************/
 517
 518 #define rk30_clock_udelay(a) udelay(a);
 519
 520 /*********************pll lock status**********************************/
 521 //#define GRF_SOC_CON0       0x15c
 522 static void pll_wait_lock(int pll_idx)
 523 {
 524         u32 pll_state[4] = {1, 0, 2, 3};
 525         u32 bit = 0x20u << pll_state[pll_idx];
 526         int delay = 24000000;
 527         while (delay > 0) {
 528                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 529                         break;
 530                 delay--;
 531         }
 532         if (delay == 0) {
 533                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 534                 while(1);
 535         }
 536 }
 537
 538
 539
 540 /***************************pll function**********************************/
 541 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 542 {
 543         unsigned long rate;
 544
 545         if (PLLS_IN_NORM(pll_id)) {
 546                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 547                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 548
 549
 550                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 551
 552                 /*
 553                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 554                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 555                    */
 556
 557
 558                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 559                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 560                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 561
 562                 do_div(rate64, PLL_NR(pll_con0));
 563                 do_div(rate64, PLL_NO(pll_con0));
 564
 565                 rate = rate64;
 566                 /*
 567                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 568                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 569                    */
 570         } else {
 571                 rate = parent_rate;
 572                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 573         }
 574         return rate;
 575 }
 576 static unsigned long plls_clk_recalc(struct clk *clk)
 577 {
 578         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 579 }
 580
 581 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 582 {
 583         //enter slowmode
 584         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 585         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 586         dsb();
 587         dsb();
 588         dsb();
 589         dsb();
 590         dsb();
 591         dsb();
 592         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 593         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 594
 595         rk30_clock_udelay(1);
 596         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 597
 598         pll_wait_lock(pll_id);
 599
 600         //return form slow
 601         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 602
 603         /*
 604            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 605            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 606            */
 607
 608         return 0;
 609 }
 610 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 611 {
 612         struct _pll_data *pll_data = c->pll;
 613         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 614
 615         while(clk_set->rate) {
 616                 if (clk_set->rate == rate) {
 617                         break;
 618                 }
 619                 clk_set++;
 620         }
 621         if(clk_set->rate == rate) {
 622                 pll_clk_set_rate(clk_set, pll_data->id);
 623                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 624         } else {
 625                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 626                 return -1;
 627         }
 628         return 0;
 629 }
 630
 631 #define PLL_FREF_MIN (183*KHZ)
 632 #define PLL_FREF_MAX (1500*MHZ)
 633
 634 #define PLL_FVCO_MIN (300*MHZ)
 635 #define PLL_FVCO_MAX (1500*MHZ)
 636
 637 #define PLL_FOUT_MIN (18750*KHZ)
 638 #define PLL_FOUT_MAX (1500*MHZ)
 639
 640 #define PLL_NF_MAX (65536)
 641 #define PLL_NR_MAX (64)
 642 #define PLL_NO_MAX (64)
 643
 644 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 645 {
 646         u32 nr, nf, no, nonr;
 647         u32 n;
 648         u32 YFfenzi;
 649         u32 YFfenmu;
 650         unsigned long fref, fvco, fout;
 651         u32 gcd_val = 0;
 652
 653         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 654         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 655                 return 0;
 656         gcd_val = clk_gcd(fin_hz, fout_hz);
 657         YFfenzi = fout_hz / gcd_val;
 658         YFfenmu = fin_hz / gcd_val;
 659
 660         for(n = 1;; n++) {
 661                 nf = YFfenzi * n;
 662                 nonr = YFfenmu * n;
 663                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 664                         break;
 665                 for(no = 1; no <= PLL_NO_MAX; no++) {
 666                         if(!(no == 1 || !(no % 2)))
 667                                 continue;
 668
 669                         if(nonr % no)
 670                                 continue;
 671                         nr = nonr / no;
 672
 673                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 674                                 continue;
 675
 676                         fref = fin_hz / nr;
 677                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 678                                 continue;
 679
 680                         fvco = (fin_hz / nr) * nf;
 681                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 682                                 continue;
 683                         fout = fvco / no;
 684                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 685                                 continue;
 686                         *clk_nr = nr;
 687                         *clk_no = no;
 688                         *clk_nf = nf;
 689                         return 1;
 690
 691                 }
 692
 693         }
 694         return 0;
 695 }
 696
 697 static int pll_clk_mode(struct clk *clk, int on)
 698 {
 699         u8 pll_id = clk->pll->id;
 700         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 701         u32 dly = (nr * 500) / 24 + 1;
 702         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 703         if (on) {
 704                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 705                 rk30_clock_udelay(dly);
 706                 pll_wait_lock(pll_id);
 707                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 708         } else {
 709                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 710                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 711         }
 712         return 0;
 713 }
 714
 715 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 716 {
 717         struct _pll_data *pll_data = c->pll;
 718         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 719         struct pll_clk_set temp_clk_set;
 720         u32 clk_nr, clk_nf, clk_no;
 721
 722
 723         while(clk_set->rate) {
 724                 if (clk_set->rate == rate) {
 725                         break;
 726                 }
 727                 clk_set++;
 728         }
 729         if(clk_set->rate == rate) {
 730                 CLKDATA_DBG("cpll get a rate\n");
 731                 pll_clk_set_rate(clk_set, pll_data->id);
 732
 733         } else {
 734                 CLKDATA_DBG("cpll get auto calc a rate\n");
 735                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 736                         pr_err("cpll auto set rate error\n");
 737                         return -ENOENT;
 738                 }
 739                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 740                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 741                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 742                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 743                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 744
 745         }
 746         return 0;
 747 }
 748
 749
 750 /* ******************fixed input clk ***********************************************/
 751 static struct clk xin24m = {
 752         .name           = "xin24m",
 753         .rate           = 24 * MHZ,
 754         .flags          = RATE_FIXED,
 755 };
 756
 757 static struct clk clk_12m = {
 758         .name           = "clk_12m",
 759         .parent         = &xin24m,
 760         .rate           = 12 * MHZ,
 761         .flags          = RATE_FIXED,
 762 };
 763
 764 /************************************pll func***************************/
 765 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 766                 struct apll_clk_set *tables) {
 767         const struct apll_clk_set *ps, *pt;
 768
 769         /* find the arm_pll we want. */
 770         ps = pt = tables;
 771         while (pt->rate) {
 772                 if (pt->rate == rate) {
 773                         ps = pt;
 774                         break;
 775                 }
 776                 // we are sorted, and ps->rate > pt->rate.
 777                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 778                         ps = pt;
 779                 if (pt->rate < rate)
 780                         break;
 781                 pt++;
 782         }
 783         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 784         return ps;
 785 }
 786 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 787 {
 788         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 789 }
 790 #if 1
 791 struct arm_clks_div_set {
 792         u32 rate;
 793         u32     clksel0;
 794         u32     clksel1;
 795 };
 796
 797 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 798 { \
 799         .rate    =_mhz,\
 800         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 801         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 802         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 803         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 804         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 805 }
 806 struct arm_clks_div_set arm_clk_div_tlb[] = {
 807         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 808         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 809         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 810         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 811         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
 812         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
 813         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
 814 };
 815 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
 816         int i = 0;
 817         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
 818                 if(arm_clk_div_tlb[i].rate >= rate)
 819                         return &arm_clk_div_tlb[i];
 820         }
 821         return NULL;
 822 }
 823
 824 #endif
 825
 826 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 827 {
 828         unsigned long flags;
 829         const struct apll_clk_set *ps;
 830         u32 pll_id = clk->pll->id;
 831         u32 temp_div;
 832         u32 old_aclk_div = 0, new_aclk_div;
 833
 834         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
 835
 836         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
 837         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
 838
 839         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
 840                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
 841
 842         if(general_pll_clk.rate > clk->rate) {
 843                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
 844         } else {
 845                 temp_div = 1;
 846         }
 847
 848         // ungating cpu gpll path
 849         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
 850         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 851
 852         local_irq_save(flags);
 853         //div arm clk for gpll
 854
 855         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
 856         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
 857
 858         loops_per_jiffy = lpj_gpll / temp_div;
 859         smp_wmb();
 860
 861         /*if core src don't select gpll ,apll neet to enter slow mode */
 862         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 863
 864
 865         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 866         dsb();
 867         dsb();
 868         dsb();
 869         dsb();
 870         dsb();
 871         dsb();
 872         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
 873         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
 874
 875         rk30_clock_udelay(1);
 876         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 877
 878         pll_wait_lock(pll_id);
 879
 880         //return form slow
 881         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 882         //reparent to apll
 883
 884         if(new_aclk_div>=old_aclk_div) {
 885                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 886                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 887         }
 888
 889         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
 890         if(old_aclk_div>new_aclk_div) {
 891                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 892                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 893         }
 894
 895         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
 896
 897         loops_per_jiffy = ps->lpj;
 898         smp_wmb();
 899
 900         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
 901
 902         local_irq_restore(flags);
 903
 904         //gate gpll path
 905         // FIXME
 906         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
 907         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 908
 909         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
 910                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
 911                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
 912                         cru_readl(CRU_CLKSELS_CON(1)));
 913         return 0;
 914 }
 915
 916
 917 /************************************pll clocks***************************/
 918
 919 static const struct apll_clk_set apll_clks[] = {
 920         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
 921         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
 922         _APLL_SET_CLKS(2208, 1, 92, 1, 8,       81, 81, 21, 41, 21),
 923         _APLL_SET_CLKS(2184, 1, 91, 1, 8,       81, 81, 21, 41, 21),
 924         _APLL_SET_CLKS(2160, 1, 90, 1, 8,       81, 81, 21, 41, 21),
 925         _APLL_SET_CLKS(2136, 1, 89, 1, 8,       81, 81, 21, 41, 21),
 926         _APLL_SET_CLKS(2112, 1, 88, 1, 8,       81, 81, 21, 41, 21),
 927         _APLL_SET_CLKS(2088, 1, 87, 1, 8,       81, 81, 21, 41, 21),
 928         _APLL_SET_CLKS(2064, 1, 86, 1, 8,       81, 81, 21, 41, 21),
 929         _APLL_SET_CLKS(2040, 1, 85, 1, 8,       81, 81, 21, 41, 21),
 930         _APLL_SET_CLKS(2016, 1, 84, 1, 8,       81, 81, 21, 41, 21),
 931         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
 932         _APLL_SET_CLKS(1968, 1, 82, 1, 8,       81, 81, 21, 41, 21),
 933         _APLL_SET_CLKS(1944, 1, 81, 1, 8,       81, 81, 21, 41, 21),
 934         _APLL_SET_CLKS(1920, 1, 80, 1, 8,       81, 81, 21, 41, 21),
 935         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
 936         _APLL_SET_CLKS(1872, 1, 78, 1, 8,       81, 81, 21, 41, 21),
 937         _APLL_SET_CLKS(1848, 1, 77, 1, 8,       81, 81, 21, 41, 21),
 938         _APLL_SET_CLKS(1824, 1, 76, 1, 8,       81, 81, 21, 41, 21),
 939         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
 940         _APLL_SET_CLKS(1776, 1, 74, 1, 8,       81, 81, 21, 41, 21),
 941         _APLL_SET_CLKS(1752, 1, 73, 1, 8,       81, 81, 21, 41, 21),
 942         _APLL_SET_CLKS(1728, 1, 72, 1, 8,       81, 81, 21, 41, 21),
 943         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
 944         _APLL_SET_CLKS(1680, 1, 70, 1, 8,       41, 41, 21, 41, 21),
 945         _APLL_SET_CLKS(1656, 1, 69, 1, 8,       41, 41, 21, 41, 21),
 946         _APLL_SET_CLKS(1632, 1, 68, 1, 8,       41, 41, 21, 41, 21),
 947         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
 948         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
 949         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
 950         _APLL_SET_CLKS(1488, 1, 62, 1, 8,       41, 41, 21, 41, 21),
 951         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
 952         _APLL_SET_CLKS(1440, 1, 60, 1, 8,       41, 41, 21, 41, 21),
 953         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
 954         _APLL_SET_CLKS(1392, 1, 58, 1, 8,       41, 41, 21, 41, 21),
 955         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
 956         _APLL_SET_CLKS(1344, 1, 56, 1, 8,       41, 41, 21, 41, 21),
 957         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
 958         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
 959         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
 960         _APLL_SET_CLKS(1248, 1, 52, 1, 8,       41, 41, 21, 41, 21),
 961         _APLL_SET_CLKS(1224, 1, 51, 1, 8,       41, 41, 21, 41, 21),
 962         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
 963         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
 964         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
 965         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
 966         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
 967         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
 968         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
 969         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
 970         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
 971         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
 972         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
 973         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
 974         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
 975         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
 976         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
 977         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
 978         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
 979         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
 980         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
 981
 982 };
 983 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
 984 static struct clk arm_pll_clk = {
 985         .name           = "arm_pll",
 986         .parent         = &xin24m,
 987         .mode           = pll_clk_mode,
 988         .recalc         = plls_clk_recalc,
 989         .set_rate       = arm_pll_clk_set_rate,
 990         .round_rate     = arm_pll_clk_round_rate,
 991         .pll            = &apll_data,
 992 };
 993
 994 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 995 {
 996         /* do nothing here */
 997         return 0;
 998 }
 999 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1000 static struct clk ddr_pll_clk = {
1001         .name           = "ddr_pll",
1002         .parent         = &xin24m,
1003         .recalc         = plls_clk_recalc,
1004         .set_rate       = ddr_pll_clk_set_rate,
1005         .pll            = &dpll_data,
1006 };
1007
1008 static const struct pll_clk_set cpll_clks[] = {
1009         _PLL_SET_CLKS(360000, 1,  60,   4),
1010         _PLL_SET_CLKS(408000, 1,  68,   4),
1011         _PLL_SET_CLKS(456000, 1,  76,   4),
1012         _PLL_SET_CLKS(504000, 1,  84,   4),
1013         _PLL_SET_CLKS(552000, 1,  46,   2),
1014         _PLL_SET_CLKS(600000, 1,  50,   2),
1015         _PLL_SET_CLKS(742500, 8,  495,  2),
1016         _PLL_SET_CLKS(768000, 1,  64,   2),
1017         _PLL_SET_CLKS(798000, 2,  133,  2),
1018         _PLL_SET_CLKS(1188000, 2, 99,   1),
1019         _PLL_SET_CLKS(     0, 4,  133,  1),
1020 };
1021 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1022 static struct clk codec_pll_clk = {
1023         .name           = "codec_pll",
1024         .parent         = &xin24m,
1025         .mode           = pll_clk_mode,
1026         .recalc         = plls_clk_recalc,
1027         .set_rate       = cpll_clk_set_rate,
1028         .pll            = &cpll_data,
1029 };
1030
1031 static const struct pll_clk_set gpll_clks[] = {
1032         _PLL_SET_CLKS(148500,   2,      99,     8),
1033         _PLL_SET_CLKS(297000,   2,      198,    8),
1034         _PLL_SET_CLKS(300000,   1,      50,     4),
1035         _PLL_SET_CLKS(594000,   2,      198,    4),
1036         _PLL_SET_CLKS(1188000,  2,      99,     1),
1037         _PLL_SET_CLKS(1200000,  1,      50,     1),
1038         _PLL_SET_CLKS(0,        0,       0,     0),
1039 };
1040 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1041 static struct clk general_pll_clk = {
1042         .name           = "general_pll",
1043         .parent         = &xin24m,
1044         .recalc         = plls_clk_recalc,
1045         .set_rate       = gpll_clk_set_rate,
1046         .pll            = &gpll_data
1047 };
1048 /********************************clocks***********************************/
1049 GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1050
1051 /* core and cpu setting */
1052 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1053 {
1054         CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1055         return 0;
1056 }
1057
1058 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1059 {
1060         CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1061         return ddr_set_pll(rate / MHZ, 0) * MHZ;
1062 }
1063 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1064 {
1065         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1066         unsigned long rate = clk->parent->recalc(clk->parent) >> shift;
1067         //CLKDATA_DBG("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1068         return rate;
1069 }
1070 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1071 static struct clk clk_ddr = {
1072         .name           = "ddr",
1073         .parent         = &ddr_pll_clk,
1074         .recalc         = ddr_clk_recalc_rate,
1075         .set_rate       = ddr_clk_set_rate,
1076         .round_rate     = ddr_clk_round_rate,
1077         .gate_idx       = CLK_GATE_DDRPHY,
1078         .clksel_con     = CRU_CLKSELS_CON(26),
1079         CRU_DIV_SET(0x3, 0, 4),
1080         CRU_SRC_SET(1, 8),
1081         CRU_PARENTS_SET(clk_ddr_parents),
1082 };
1083 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1084 {
1085         int ret;
1086
1087         ret = clk_set_rate_nolock(c->parent, rate);
1088         if (ret) {
1089                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1090                 return ret;
1091         }
1092         //set arm pll div 1
1093         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1094         return 0;
1095 }
1096 static unsigned long clk_core_get_rate(struct clk *c)
1097 {
1098         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1099         //c->parent->rate=c->parent->recalc(c->parent);
1100         return c->parent->rate / div;
1101 }
1102 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1103 {
1104         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1105         return clk_round_rate_nolock(clk->parent, rate) / div;
1106 }
1107
1108 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1109 {
1110
1111         u32 temp_div;
1112         struct clk *old_prt;
1113
1114         if(clk->parent == new_prt)
1115                 return 0;
1116         if (unlikely(!clk->parents))
1117                 return -EINVAL;
1118         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1119         //arm
1120         old_prt = clk->parent;
1121
1122         if(clk->parents[0] == new_prt) {
1123                 new_prt->set_rate(new_prt, 300 * MHZ);
1124                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1125         } else if(clk->parents[1] == new_prt) {
1126
1127                 if(new_prt->rate > old_prt->rate) {
1128                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1129                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1130                 }
1131                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1132                 new_prt->set_rate(new_prt, 300 * MHZ);
1133         } else
1134                 return -1;
1135
1136
1137         return 0;
1138
1139 }
1140
1141 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1142 {
1143         u32 temp_div;
1144         u32 old_aclk_div = 0, new_aclk_div;
1145         struct arm_clks_div_set *temp_clk_div;
1146         unsigned long arm_gpll_rate, arm_gpll_lpj;
1147         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1148         arm_gpll_rate = c->parent->rate / temp_div;
1149
1150         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1151         if(!temp_clk_div)
1152                 temp_clk_div = &arm_clk_div_tlb[4];
1153
1154         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1155         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1156         if(c->rate >= rate) {
1157                 arm_gpll_lpj = lpj_gpll / temp_div;
1158                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1159         }
1160
1161         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1162         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1163                         CRU_CLKSELS_CON(0));
1164         if((c->rate < rate)) {
1165                 arm_gpll_lpj = lpj_gpll / temp_div;
1166                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1167         }
1168         return 0;
1169 }
1170 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1171 {
1172         return c->parent->rate;
1173 }
1174 static struct clk clk_core_gpll_path = {
1175         .name           = "cpu_gpll_path",
1176         .parent         = &general_pll_clk,
1177         .recalc         = arm_core_gpll_clk_get_rate,
1178         .set_rate       = core_gpll_clk_set_rate,
1179         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1180 };
1181
1182
1183 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1184
1185 static struct clk clk_core = {
1186         .name           = "core",
1187         .parent         = &arm_pll_clk,
1188         .set_rate       = clk_core_set_rate,
1189         .recalc         = clk_core_get_rate,
1190         .round_rate     = core_clk_round_rate,
1191         .set_parent     = core_clksel_set_parent,
1192         .clksel_con     = CRU_CLKSELS_CON(0),
1193         CRU_DIV_SET(0x1f, 9, 32),
1194         CRU_SRC_SET(1, 8),
1195         CRU_PARENTS_SET(clk_core_parents),
1196 };
1197 GATE_CLK(l2c, clk_core, CLK_L2C);
1198 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1199 static unsigned long aclk_recalc(struct clk *clk)
1200 {
1201         unsigned long rate;
1202         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1203
1204         BUG_ON(div > 5);
1205         if (div >= 5)
1206                 div = 8;
1207         rate = clk->parent->rate / div;
1208         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1209
1210         return rate;
1211 };
1212 static struct clk core_periph = {
1213         .name           = "core_periph",
1214         .parent         = &clk_core,
1215         .gate_idx       = CLK_GATE_CORE_PERIPH,
1216         .recalc         = clksel_recalc_shift_2,
1217         .clksel_con     = CRU_CLKSELS_CON(0),
1218         CRU_DIV_SET(0x3, 6, 16),
1219 };
1220 static struct clk aclk_core = {
1221         .name           = "aclk_core",
1222         .parent         = &clk_core,
1223         .gate_idx       = CLK_GATE_ACLK_CORE,
1224         .recalc         = aclk_recalc,
1225         .clksel_con     = CRU_CLKSELS_CON(1),
1226         CRU_DIV_SET(0x7, 3, 8),
1227 };
1228
1229 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1230 static struct clk clk_cpu_div = {
1231         .name           = "cpu_div",
1232         .parent         = &arm_pll_clk,
1233         .set_rate       = clksel_set_rate_freediv,
1234         .recalc         = clksel_recalc_div,
1235         .clksel_con     = CRU_CLKSELS_CON(0),
1236         CRU_DIV_SET(0x1f, 0, 32),
1237         CRU_SRC_SET(1, 5),
1238         CRU_PARENTS_SET(clk_cpu_div_parents),
1239 };
1240
1241 static struct clk aclk_cpu = {
1242         .name           = "aclk_cpu",
1243         .parent         = &clk_cpu_div,
1244         .gate_idx       = CLK_GATE_ACLK_CPU,
1245 };
1246
1247 static struct clk hclk_cpu = {
1248         .name           = "hclk_cpu",
1249         .parent         = &aclk_cpu,
1250         .gate_idx       = CLK_GATE_HCLK_CPU,
1251         .recalc         = clksel_recalc_shift,
1252         .set_rate       = clksel_set_rate_shift,
1253         .clksel_con     = CRU_CLKSELS_CON(1),
1254         CRU_DIV_SET(0x3, 8, 4),
1255
1256 };
1257
1258 static struct clk pclk_cpu = {
1259         .name           = "pclk_cpu",
1260         .parent         = &aclk_cpu,
1261         .gate_idx       = CLK_GATE_PCLK_CPU,
1262         .recalc         = clksel_recalc_shift,
1263         .set_rate       = clksel_set_rate_shift,
1264         .clksel_con     = CRU_CLKSELS_CON(1),
1265         CRU_DIV_SET(0x3, 12, 8),
1266 };
1267
1268 static struct clk ahb2apb_cpu = {
1269         .name           = "ahb2apb",
1270         .parent         = &hclk_cpu,
1271         .recalc         = clksel_recalc_shift,
1272         .set_rate       = clksel_set_rate_shift,
1273         .clksel_con     = CRU_CLKSELS_CON(1),
1274         CRU_DIV_SET(0x3, 14, 4),
1275 };
1276
1277
1278 static struct clk atclk_cpu = {
1279         .name           = "atclk_cpu",
1280         .parent         = &pclk_cpu,
1281         .gate_idx       = CLK_GATE_ATCLK_CPU,
1282 };
1283
1284 /* GPU setting */
1285 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1286 {
1287         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1288         return clkset_rate_freediv_autosel_parents(clk, max_rate);
1289 };
1290
1291 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1292
1293 static struct clk aclk_gpu = {
1294         .name           = "aclk_gpu",
1295         .mode           = gate_mode,
1296         .recalc         = clksel_recalc_div,
1297         .round_rate     = clk_freediv_round_autosel_parents_rate,
1298         .set_rate       = clksel_set_rate_freediv,
1299         .clksel_con     = CRU_CLKSELS_CON(34),
1300         .gate_idx       = CLK_GATE_ACLK_GPU,
1301         CRU_DIV_SET(0x1f, 0, 32),
1302         CRU_SRC_SET(0x1, 7),
1303         CRU_PARENTS_SET(aclk_gpu_parents),
1304 };
1305
1306 /* vcodec setting */
1307 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1308 {
1309         unsigned long rate = clk->parent->rate / 4;
1310         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1311         return rate;
1312 }
1313
1314 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1315
1316 static struct clk aclk_vepu = {
1317         .name           = "aclk_vepu",
1318         .parent         = &codec_pll_clk,
1319         .mode           = gate_mode,
1320         .recalc         = clksel_recalc_div,
1321         .set_rate       = clkset_rate_freediv_autosel_parents,
1322         .clksel_con     = CRU_CLKSELS_CON(32),
1323         .gate_idx       = CLK_GATE_ACLK_VEPU,
1324         CRU_DIV_SET(0x1f, 0, 32),
1325         CRU_SRC_SET(0x1, 7),
1326         CRU_PARENTS_SET(aclk_vepu_parents),
1327 };
1328
1329 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1330
1331 static struct clk aclk_vdpu = {
1332         .name           = "aclk_vdpu",
1333         .mode           = gate_mode,
1334         .recalc         = clksel_recalc_div,
1335         .set_rate       = clkset_rate_freediv_autosel_parents,
1336         .clksel_con     = CRU_CLKSELS_CON(32),
1337         .gate_idx       = CLK_GATE_ACLK_VDPU,
1338         CRU_DIV_SET(0x1f, 8, 32),
1339         CRU_SRC_SET(0x1, 15),
1340         CRU_PARENTS_SET(aclk_vdpu_parents),
1341 };
1342 static struct clk hclk_vepu = {
1343         .name           = "hclk_vepu",
1344         .parent         = &aclk_vepu,
1345         .mode           = gate_mode,
1346         .recalc         = clksel_recalc_vpu_hclk,
1347         .gate_idx       = CLK_GATE_HCLK_VEPU,
1348 };
1349
1350 static struct clk hclk_vdpu = {
1351         .name           = "hclk_vdpu",
1352         .parent         = &aclk_vdpu,
1353         .mode           = gate_mode,
1354         .recalc         = clksel_recalc_vpu_hclk,
1355         .gate_idx       = CLK_GATE_HCLK_VDPU,
1356 };
1357
1358 /* aclk lcdc setting */
1359 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1360
1361 static struct clk aclk_lcdc0_pre = {
1362         .name           = "aclk_lcdc0_pre",
1363         .parent         = &codec_pll_clk,
1364         .mode           = gate_mode,
1365         .recalc         = clksel_recalc_div,
1366         .set_rate       = clkset_rate_freediv_autosel_parents,
1367         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1368         .clksel_con     = CRU_CLKSELS_CON(31),
1369         CRU_DIV_SET(0x1f, 0, 32),
1370         CRU_SRC_SET(0x1, 7),
1371         CRU_PARENTS_SET(aclk_lcdc0_parents),
1372 };
1373
1374 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1375
1376 static struct clk aclk_lcdc1_pre = {
1377         .name           = "aclk_lcdc1_pre",
1378         .parent         = &codec_pll_clk,
1379         .mode           = gate_mode,
1380         .recalc         = clksel_recalc_div,
1381         .set_rate       = clkset_rate_freediv_autosel_parents,
1382         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1383         .clksel_con     = CRU_CLKSELS_CON(31),
1384         CRU_DIV_SET(0x1f, 8, 32),
1385         CRU_SRC_SET(0x1, 15),
1386         CRU_PARENTS_SET(aclk_lcdc1_parents),
1387 };
1388
1389 /* aclk/hclk/pclk periph setting */
1390 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1391
1392 static struct clk aclk_periph = {
1393         .name           = "aclk_periph",
1394         .parent         = &general_pll_clk,
1395         .mode           = gate_mode,
1396         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1397         .recalc         = clksel_recalc_div,
1398         .set_rate       = clksel_set_rate_freediv,
1399         .clksel_con     = CRU_CLKSELS_CON(10),
1400         CRU_DIV_SET(0x1f, 0, 32),
1401         CRU_SRC_SET(1, 15),
1402         CRU_PARENTS_SET(aclk_periph_parents),
1403 };
1404 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1405
1406 static struct clk pclk_periph = {
1407         .name           = "pclk_periph",
1408         .parent         = &aclk_periph,
1409         .mode           = gate_mode,
1410         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1411         .recalc         = clksel_recalc_shift,
1412         .set_rate       = clksel_set_rate_shift,
1413         .clksel_con     = CRU_CLKSELS_CON(10),
1414         CRU_DIV_SET(0x3, 12, 8),
1415 };
1416
1417 static struct clk hclk_periph = {
1418         .name           = "hclk_periph",
1419         .parent         = &aclk_periph,
1420         .mode           = gate_mode,
1421         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1422         .recalc         = clksel_recalc_shift,
1423         .set_rate       = clksel_set_rate_shift,
1424         .clksel_con     = CRU_CLKSELS_CON(10),
1425         CRU_DIV_SET(0x3, 8, 4),
1426 };
1427 /* dclk lcdc setting */
1428 // FIXME
1429 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1430 {
1431         u32 div, old_div;
1432         int i;
1433         unsigned long new_rate;
1434         int ret = 0;
1435
1436         if(clk->rate == rate)
1437                 return 0;
1438         for(i = 0; i < 2; i++) {
1439                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1440                 new_rate = clk->parents[i]->rate / div;
1441                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1442                         break;
1443                 }
1444         }
1445         if(i >= 2) {
1446                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1447                 return -1;
1448         }
1449
1450         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1451
1452         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1453                         clk->div_shift, clk->div_mask) + 1;
1454         if(div > old_div)
1455                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1456
1457         if(clk->parents[i] != clk->parent) {
1458                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1459         }
1460
1461         if (ret) {
1462                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1463                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1464                 return ret;
1465         }
1466         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1467         return 0;
1468 }
1469
1470 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1471 {
1472         int ret = 0;
1473         struct clk *parent;
1474
1475         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1476                 parent = clk->parents[1];
1477                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1478         } else {
1479                 parent = clk->parents[0];
1480         }
1481         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1482         //clk->name,rate,parent->name,clk->parent->name);
1483
1484         if(parent != clk->parents[1]) {
1485                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1486                 if (ret) {
1487                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1488                         return ret;
1489                 }
1490         }
1491         if (clk->parent != parent) {
1492                 ret = clk_set_parent_nolock(clk, parent);
1493                 if (ret) {
1494                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1495                         return ret;
1496                 }
1497         }
1498         return ret;
1499 }
1500
1501 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1502 static struct clk dclk_lcdc0 = {
1503         .name           = "dclk_lcdc0",
1504         .mode           = gate_mode,
1505         .set_rate       = clkset_rate_freediv_autosel_parents,
1506         .recalc         = clksel_recalc_div,
1507         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1508         .clksel_con     = CRU_CLKSELS_CON(27),
1509         CRU_SRC_SET(0x1, 0),
1510         CRU_DIV_SET(0xff, 8, 256),
1511         CRU_PARENTS_SET(dclk_lcdc0_parents),
1512 };
1513
1514 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1515 static struct clk dclk_lcdc1 = {
1516         .name           = "dclk_lcdc1",
1517         .mode           = gate_mode,
1518         .set_rate       = clkset_rate_freediv_autosel_parents,
1519         .recalc         = clksel_recalc_div,
1520         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1521         .clksel_con     = CRU_CLKSELS_CON(28),
1522         CRU_SRC_SET(0x1, 0),
1523         CRU_DIV_SET(0xff, 8, 256),
1524         CRU_PARENTS_SET(dclk_lcdc1_parents),
1525 };
1526
1527 /* cif setting */
1528 // FIXME
1529 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1530 static struct clk cif_out_pll = {
1531         .name           = "cif_out_pll",
1532         .parent         = &general_pll_clk,
1533         .clksel_con     = CRU_CLKSELS_CON(29),
1534         CRU_SRC_SET(0x1, 0),
1535         CRU_PARENTS_SET(cifout_sel_pll_parents),
1536 };
1537
1538 static struct clk cif0_out_div = {
1539         .name           = "cif0_out_div",
1540         .parent         = &cif_out_pll,
1541         .mode           = gate_mode,
1542         .recalc         = clksel_recalc_div,
1543         .set_rate       = clksel_set_rate_freediv,
1544         .gate_idx       = CLK_GATE_CIF0_OUT,
1545         .clksel_con     = CRU_CLKSELS_CON(29),
1546         CRU_DIV_SET(0x1f, 1, 32),
1547 };
1548
1549 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1550 {
1551         int ret = 0;
1552         struct clk *parent;
1553
1554         if (rate == 24 * MHZ) {
1555                 parent = clk->parents[1];
1556         } else {
1557                 parent = clk->parents[0];
1558                 ret = clk_set_rate_nolock(parent, rate);
1559                 if (ret)
1560                         return ret;
1561         }
1562         if (clk->parent != parent)
1563                 ret = clk_set_parent_nolock(clk, parent);
1564
1565         return ret;
1566 }
1567
1568 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1569 static struct clk cif0_out = {
1570         .name           = "cif0_out",
1571         .parent         = &cif0_out_div,
1572         .set_rate       = cif_out_set_rate,
1573         .clksel_con     = CRU_CLKSELS_CON(29),
1574         CRU_SRC_SET(0x1, 7),
1575         CRU_PARENTS_SET(cif0_out_parents),
1576 };
1577
1578 static struct clk pclkin_cif0 = {
1579         .name           = "pclkin_cif0",
1580         .mode           = gate_mode,
1581         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1582 };
1583
1584 static struct clk inv_cif0 = {
1585         .name           = "inv_cif0",
1586         .parent         = &pclkin_cif0,
1587 };
1588
1589 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1590 static struct clk cif0_in = {
1591         .name           = "cif0_in",
1592         .parent         = &pclkin_cif0,
1593         .clksel_con     = CRU_CLKSELS_CON(30),
1594         CRU_SRC_SET(0x1, 8),
1595         CRU_PARENTS_SET(cif0_in_parents),
1596 };
1597
1598 /* i2s/spdif setting */
1599 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1600 static struct clk clk_i2s_pll = {
1601         .name           = "i2s_pll",
1602         .parent         = &general_pll_clk,
1603         .clksel_con     = CRU_CLKSELS_CON(2),
1604         CRU_SRC_SET(0x1, 15),
1605         CRU_PARENTS_SET(clk_i2s_div_parents),
1606 };
1607
1608 static struct clk clk_i2s0_div = {
1609         .name           = "i2s0_div",
1610         .parent         = &clk_i2s_pll,
1611         .mode           = gate_mode,
1612         .recalc         = clksel_recalc_div,
1613         .set_rate       = clksel_set_rate_freediv,
1614         .round_rate     = clksel_freediv_round_rate,
1615         .gate_idx       = CLK_GATE_I2S0_SRC,
1616         .clksel_con     = CRU_CLKSELS_CON(3),
1617         CRU_DIV_SET(0x7f, 0, 64),
1618 };
1619
1620 static struct clk clk_spdif_div = {
1621         .name           = "spdif_div",
1622         .parent         = &clk_i2s_pll,
1623         .recalc         = clksel_recalc_div,
1624         .set_rate       = clksel_set_rate_freediv,
1625         .round_rate     = clksel_freediv_round_rate,
1626         .mode           = gate_mode,
1627         .gate_idx       = CLK_GATE_SPDIF_SRC,
1628         .clksel_con     = CRU_CLKSELS_CON(5),
1629         CRU_DIV_SET(0x7f, 0, 64),
1630 };
1631 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1632 {
1633         u32 numerator, denominator;
1634         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1635         //clk->parent->parent
1636         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1637                                 &numerator, &denominator) == 0) {
1638                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1639                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1640                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1641         } else {
1642                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1643                 return -ENOENT;
1644         }
1645         return 0;
1646 }
1647
1648 static struct clk clk_i2s0_frac_div = {
1649         .name           = "i2s0_frac_div",
1650         .parent         = &clk_i2s0_div,
1651         .mode           = gate_mode,
1652         .gate_idx       = CLK_GATE_I2S0_FRAC,
1653         .recalc         = clksel_recalc_frac,
1654         .set_rate       = clk_i2s_fracdiv_set_rate,
1655         .clksel_con     = CRU_CLKSELS_CON(7),
1656 };
1657
1658 static struct clk clk_spdif_frac_div = {
1659         .name           = "spdif_frac_div",
1660         .parent         = &clk_spdif_div,
1661         .mode           = gate_mode,
1662         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1663         .recalc         = clksel_recalc_frac,
1664         .set_rate       = clk_i2s_fracdiv_set_rate,
1665         .clksel_con     = CRU_CLKSELS_CON(9),
1666 };
1667
1668 #define I2S_SRC_DIV     (0x0)
1669 #define I2S_SRC_FRAC    (0x1)
1670 #define I2S_SRC_12M     (0x2)
1671
1672 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1673 {
1674         int ret = -EINVAL;
1675         struct clk *parent;
1676
1677         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1678                 parent = clk->parents[I2S_SRC_12M];
1679         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1680                 parent = clk->parents[I2S_SRC_DIV];
1681         } else {
1682                 parent = clk->parents[I2S_SRC_FRAC];
1683         }
1684
1685         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1686                         clk->name, rate, parent->name, clk->parent->name);
1687
1688         if(parent != clk->parents[I2S_SRC_12M]) {
1689                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1690                 if (ret) {
1691                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1692                         return ret;
1693                 }
1694         }
1695
1696         if (clk->parent != parent) {
1697                 ret = clk_set_parent_nolock(clk, parent);
1698                 if (ret) {
1699                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1700                         return ret;
1701                 }
1702         }
1703
1704         return ret;
1705 };
1706
1707 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
1708
1709 static struct clk clk_i2s0 = {
1710         .name           = "i2s0",
1711         .set_rate       = i2s_set_rate,
1712         .clksel_con     = CRU_CLKSELS_CON(3),
1713         CRU_SRC_SET(0x3, 8),
1714         CRU_PARENTS_SET(clk_i2s0_parents),
1715 };
1716
1717 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
1718
1719 static struct clk clk_spdif = {
1720         .name           = "spdif",
1721         .parent         = &clk_spdif_frac_div,
1722         .set_rate       = i2s_set_rate,
1723         .clksel_con = CRU_CLKSELS_CON(5),
1724         CRU_SRC_SET(0x3, 8),
1725         CRU_PARENTS_SET(clk_spdif_parents),
1726 };
1727
1728 /* otgphy setting */
1729 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1730 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1731
1732 static struct clk clk_otgphy0_480m = {
1733         .name           = "otgphy0_480m",
1734         .parent         = &clk_otgphy0,
1735 };
1736 static struct clk clk_otgphy1_480m = {
1737         .name           = "otgphy1_480m",
1738         .parent         = &clk_otgphy1,
1739 };
1740
1741 /* hsicphy setting */
1742 #ifdef ARCH_RK31
1743 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
1744 static struct clk clk_hsicphy_480m = {
1745         .name           = "hsicphy_480m",
1746         .parent         = &clk_otgphy0_480m,
1747         .clksel_con      = CRU_CLKSELS_CON(30),
1748         CRU_SRC_SET(0x3, 0),
1749         CRU_PARENTS_SET(clk_hsicphy_parents),
1750 };
1751 static struct clk clk_hsicphy_12m = {
1752         .name           = "hsicphy_12m",
1753         .parent         = &clk_hsicphy_480m,
1754         .clksel_con     = CRU_CLKSELS_CON(11),
1755         CRU_DIV_SET(0x3f, 8, 64),
1756 };
1757 #endif
1758
1759 /* mac and rmii setting */
1760 // FIXME
1761 static struct clk rmii_clkin = {
1762         .name           = "rmii_clkin",
1763 };
1764 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
1765 static struct clk clk_mac_pll_div = {
1766         .name           = "mac_pll_div",
1767         .parent         = &general_pll_clk,
1768         .mode           = gate_mode,
1769         .gate_idx       = CLK_GATE_MAC_SRC,
1770         .recalc         = clksel_recalc_div,
1771         .set_rate       = clksel_set_rate_freediv,
1772         .clksel_con     = CRU_CLKSELS_CON(21),
1773         CRU_DIV_SET(0x1f, 8, 32),
1774         CRU_SRC_SET(0x1, 0),
1775         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1776 };
1777
1778 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1779 {
1780         if(clk->parent == clk->parents[1]) {
1781                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1782                 return -ENOENT;
1783         } else if(clk->parent == clk->parents[0]) {
1784                 return clk_set_rate_nolock(clk->parents[0], rate);
1785         }
1786         return -ENOENT;
1787 }
1788
1789 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
1790
1791 static struct clk clk_mac_ref = {
1792         .name           = "mac_ref",
1793         .parent         = &clk_mac_pll_div,
1794         .set_rate       = clksel_mac_ref_set_rate,
1795         .clksel_con     = CRU_CLKSELS_CON(21),
1796         CRU_SRC_SET(0x1, 4),
1797         CRU_PARENTS_SET(clk_mac_ref_parents),
1798 };
1799
1800 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1801 {
1802         return clk_set_parent_nolock(clk->parent, parent);
1803 }
1804
1805 static struct clk clk_mii_tx = {
1806         .name           = "mii_tx",
1807         .parent         = &clk_mac_ref,
1808         //.set_parent   = clk_set_mii_tx_parent,
1809         .mode           = gate_mode,
1810         .gate_idx       = CLK_GATE_MAC_LBTEST,
1811 };
1812
1813 /* hsadc and saradc */
1814 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
1815 static struct clk clk_hsadc_pll_div = {
1816         .name           = "hsadc_pll_div",
1817         .parent         = &general_pll_clk,
1818         .mode           = gate_mode,
1819         .gate_idx       = CLK_GATE_HSADC_SRC,
1820         .recalc         = clksel_recalc_div,
1821         .round_rate     = clk_freediv_round_autosel_parents_rate,
1822         .set_rate       = clkset_rate_freediv_autosel_parents,
1823         //.round_rate   = clksel_freediv_round_rate,
1824         //.set_rate     = clksel_set_rate_freediv,
1825         .clksel_con = CRU_CLKSELS_CON(22),
1826         CRU_DIV_SET(0xff, 8, 256),
1827         CRU_SRC_SET(0x1, 0),
1828         CRU_PARENTS_SET(clk_hsadc_pll_parents),
1829 };
1830 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
1831 {
1832         u32 numerator, denominator;
1833         //        clk_hsadc_pll_div->gpll/cpll
1834         //clk->parent->parent
1835         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1836                                 &numerator, &denominator) == 0) {
1837                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1838
1839                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1840
1841                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1842         } else {
1843                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1844                 return -ENOENT;
1845         }
1846         return 0;
1847 }
1848 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
1849 {
1850         u32 numerator, denominator;
1851         u32 i, ret = 0;
1852         //        clk_hsadc_pll_div->gpll/cpll
1853         //clk->parent->parent
1854         for(i = 0; i < 2; i++) {
1855                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
1856                                         &numerator, &denominator) == 0)
1857                         break;
1858         }
1859         if(i >= 2)
1860                 return -ENOENT;
1861
1862         if(clk->parent->parent != clk->parent->parents[i])
1863                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
1864         if(ret == 0) {
1865                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
1866
1867                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1868
1869                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
1870         } else {
1871                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1872                 return -ENOENT;
1873         }
1874         return 0;
1875 }
1876
1877 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
1878 {
1879         u32 numerator, denominator;
1880
1881         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
1882         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1883                                 &numerator, &denominator) == 0)
1884                 return rate;
1885
1886         return 0;
1887 }
1888 static struct clk clk_hsadc_frac_div = {
1889         .name           = "hsadc_frac_div",
1890         .parent         = &clk_hsadc_pll_div,
1891         .mode           = gate_mode,
1892         .recalc         = clksel_recalc_frac,
1893         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
1894         .round_rate     = clk_hsadc_fracdiv_round_rate,
1895         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
1896         .clksel_con     = CRU_CLKSELS_CON(23),
1897 };
1898
1899 #define HSADC_SRC_DIV 0x0
1900 #define HSADC_SRC_FRAC 0x1
1901 #define HSADC_SRC_EXT 0x2
1902 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
1903 {
1904         int ret = -EINVAL;
1905         struct clk *parent;
1906
1907         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
1908                 CLKDATA_DBG("hsadc clk is form ext\n");
1909                 return 0;
1910         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
1911                 parent = clk->parents[HSADC_SRC_DIV];
1912         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
1913                 parent = clk->parents[HSADC_SRC_FRAC];
1914         } else
1915                 parent = clk->parents[HSADC_SRC_DIV];
1916
1917         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1918                         clk->name, rate, parent->name, clk->parent->name);
1919
1920         ret = clk_set_rate_nolock(parent, rate);
1921         if (ret) {
1922                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
1923                 return ret;
1924         }
1925         if (clk->parent != parent) {
1926                 ret = clk_set_parent_nolock(clk, parent);
1927                 if (ret) {
1928                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
1929                         return ret;
1930                 }
1931         }
1932         return ret;
1933 }
1934
1935 static struct clk clk_hsadc_ext = {
1936         .name           = "hsadc_ext",
1937 };
1938
1939 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
1940 static struct clk clk_hsadc_out = {
1941         .name           = "hsadc_out",
1942         .parent         = &clk_hsadc_pll_div,
1943         .set_rate       = clk_hsadc_set_rate,
1944         .clksel_con     = CRU_CLKSELS_CON(22),
1945         CRU_SRC_SET(0x3, 4),
1946         CRU_PARENTS_SET(clk_hsadc_out_parents),
1947 };
1948 static struct clk clk_hsadc_out_inv = {
1949         .name           = "hsadc_out_inv",
1950         .parent         = &clk_hsadc_out,
1951 };
1952
1953 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
1954 static struct clk clk_hsadc = {
1955         .name           = "hsadc",
1956         .parent         = &clk_hsadc_out,
1957         .clksel_con     = CRU_CLKSELS_CON(22),
1958         CRU_SRC_SET(0x1, 7),
1959         CRU_PARENTS_SET(clk_hsadc_parents),
1960 };
1961
1962 static struct clk clk_saradc = {
1963         .name           = "saradc",
1964         .parent         = &xin24m,
1965         .mode           = gate_mode,
1966         .recalc         = clksel_recalc_div,
1967         .set_rate       = clksel_set_rate_freediv,
1968         .gate_idx       = CLK_GATE_SARADC_SRC,
1969         .clksel_con     = CRU_CLKSELS_CON(24),
1970         CRU_DIV_SET(0xff, 8, 256),
1971 };
1972
1973 /* smc setting */
1974 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
1975 static struct clk clkn_smc = {
1976         .name           = "smc_inv",
1977         .parent         = &clk_smc,
1978 };
1979
1980 /* spi setting */
1981 static struct clk clk_spi0 = {
1982         .name           = "spi0",
1983         .parent         = &pclk_periph,
1984         .mode           = gate_mode,
1985         .recalc         = clksel_recalc_div,
1986         .set_rate       = clksel_set_rate_freediv,
1987         .gate_idx       = CLK_GATE_SPI0_SRC,
1988         .clksel_con     = CRU_CLKSELS_CON(25),
1989         CRU_DIV_SET(0x7f, 0, 128),
1990 };
1991
1992 static struct clk clk_spi1 = {
1993         .name           = "spi1",
1994         .parent         = &pclk_periph,
1995         .mode           = gate_mode,
1996         .recalc         = clksel_recalc_div,
1997         .set_rate       = clksel_set_rate_freediv,
1998         .gate_idx       = CLK_GATE_SPI1_SRC,
1999         .clksel_con     = CRU_CLKSELS_CON(25),
2000         CRU_DIV_SET(0x7f, 8, 128),
2001 };
2002
2003 /* sdmmc/sdio/emmc setting */
2004 static struct clk clk_sdmmc = {
2005         .name           = "sdmmc",
2006         .parent         = &hclk_periph,
2007         .mode           = gate_mode,
2008         .recalc         = clksel_recalc_div,
2009         .set_rate       = clksel_set_rate_freediv,
2010         .gate_idx       = CLK_GATE_MMC0_SRC,
2011         .clksel_con     = CRU_CLKSELS_CON(11),
2012         CRU_DIV_SET(0x3f, 0, 64),
2013 };
2014
2015 static struct clk clk_sdio = {
2016         .name           = "sdio",
2017         .parent         = &hclk_periph,
2018         .mode           = gate_mode,
2019         .recalc         = clksel_recalc_div,
2020         .set_rate       = clksel_set_rate_freediv,
2021         .gate_idx       = CLK_GATE_SDIO_SRC,
2022         .clksel_con     = CRU_CLKSELS_CON(12),
2023         CRU_DIV_SET(0x3f, 0, 64),
2024
2025 };
2026
2027 static struct clk clk_emmc = {
2028         .name           = "emmc",
2029         .parent         = &hclk_periph,
2030         .mode           = gate_mode,
2031         .recalc         = clksel_recalc_div,
2032         .set_rate       = clksel_set_rate_freediv,
2033         .gate_idx       = CLK_GATE_EMMC_SRC,
2034         .clksel_con     = CRU_CLKSELS_CON(12),
2035         CRU_DIV_SET(0x3f, 8, 64),
2036 };
2037
2038 /* uart setting */
2039 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2040 static struct clk clk_uart_pll = {
2041         .name           = "uart_pll",
2042         .parent         = &general_pll_clk,
2043         .clksel_con     = CRU_CLKSELS_CON(12),
2044         CRU_SRC_SET(0x1, 15),
2045         CRU_PARENTS_SET(clk_uart_src_parents),
2046 };
2047 static struct clk clk_uart0_div = {
2048         .name           = "uart0_div",
2049         .parent         = &clk_uart_pll,
2050         .mode           = gate_mode,
2051         .gate_idx       = CLK_GATE_UART0_SRC,
2052         .recalc         = clksel_recalc_div,
2053         .set_rate       = clksel_set_rate_freediv,
2054         .round_rate     = clksel_freediv_round_rate,
2055         .clksel_con     = CRU_CLKSELS_CON(13),
2056         CRU_DIV_SET(0x7f, 0, 64),
2057 };
2058 static struct clk clk_uart1_div = {
2059         .name           = "uart1_div",
2060         .parent         = &clk_uart_pll,
2061         .mode           = gate_mode,
2062         .gate_idx       = CLK_GATE_UART1_SRC,
2063         .recalc         = clksel_recalc_div,
2064         .round_rate     = clksel_freediv_round_rate,
2065         .set_rate       = clksel_set_rate_freediv,
2066         .clksel_con     = CRU_CLKSELS_CON(14),
2067         CRU_DIV_SET(0x7f, 0, 64),
2068 };
2069
2070 static struct clk clk_uart2_div = {
2071         .name           = "uart2_div",
2072         .parent         = &clk_uart_pll,
2073         .mode           = gate_mode,
2074         .gate_idx       = CLK_GATE_UART2_SRC,
2075         .recalc         = clksel_recalc_div,
2076         .round_rate     = clksel_freediv_round_rate,
2077         .set_rate       = clksel_set_rate_freediv,
2078         .clksel_con     = CRU_CLKSELS_CON(15),
2079         CRU_DIV_SET(0x7f, 0, 64),
2080 };
2081
2082 static struct clk clk_uart3_div = {
2083         .name           = "uart3_div",
2084         .parent         = &clk_uart_pll,
2085         .mode           = gate_mode,
2086         .gate_idx       = CLK_GATE_UART3_SRC,
2087         .recalc         = clksel_recalc_div,
2088         .round_rate     = clksel_freediv_round_rate,
2089         .set_rate       = clksel_set_rate_freediv,
2090         .clksel_con     = CRU_CLKSELS_CON(16),
2091         CRU_DIV_SET(0x7f, 0, 64),
2092 };
2093 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2094 {
2095         u32 numerator, denominator;
2096         //clk_uart0_div->clk_uart_pll->gpll/cpll
2097         //clk->parent->parent
2098         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2099                                 &numerator, &denominator) == 0) {
2100                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2101
2102                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2103
2104                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2105         } else {
2106                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2107                 return -ENOENT;
2108         }
2109         return 0;
2110 }
2111
2112 static struct clk clk_uart0_frac_div = {
2113         .name           = "uart0_frac_div",
2114         .parent         = &clk_uart0_div,
2115         .mode           = gate_mode,
2116         .recalc         = clksel_recalc_frac,
2117         .set_rate       = clk_uart_fracdiv_set_rate,
2118         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2119         .clksel_con     = CRU_CLKSELS_CON(17),
2120 };
2121 static struct clk clk_uart1_frac_div = {
2122         .name           = "uart1_frac_div",
2123         .parent         = &clk_uart1_div,
2124         .mode           = gate_mode,
2125         .recalc         = clksel_recalc_frac,
2126         .set_rate       = clk_uart_fracdiv_set_rate,
2127         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2128         .clksel_con     = CRU_CLKSELS_CON(18),
2129 };
2130 static struct clk clk_uart2_frac_div = {
2131         .name           = "uart2_frac_div",
2132         .mode           = gate_mode,
2133         .parent         = &clk_uart2_div,
2134         .recalc         = clksel_recalc_frac,
2135         .set_rate       = clk_uart_fracdiv_set_rate,
2136         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2137         .clksel_con     = CRU_CLKSELS_CON(19),
2138 };
2139 static struct clk clk_uart3_frac_div = {
2140         .name           = "uart3_frac_div",
2141         .parent         = &clk_uart3_div,
2142         .mode           = gate_mode,
2143         .recalc         = clksel_recalc_frac,
2144         .set_rate       = clk_uart_fracdiv_set_rate,
2145         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2146         .clksel_con     = CRU_CLKSELS_CON(20),
2147 };
2148
2149 #define UART_SRC_DIV 0
2150 #define UART_SRC_FRAC 1
2151 #define UART_SRC_24M 2
2152
2153 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2154 {
2155         int ret = 0;
2156         struct clk *parent;
2157
2158         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2159                 parent = clk->parents[UART_SRC_24M];
2160         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2161                 parent = clk->parents[UART_SRC_DIV];
2162         } else {
2163                 parent = clk->parents[UART_SRC_FRAC];
2164         }
2165
2166         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2167                         clk->name, rate, parent->name, clk->parent->name);
2168
2169         if(parent != clk->parents[UART_SRC_24M]) {
2170                 ret = clk_set_rate_nolock(parent, rate);
2171                 if (ret) {
2172                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2173                         return ret;
2174                 }
2175         }
2176
2177         if (clk->parent != parent) {
2178                 ret = clk_set_parent_nolock(clk, parent);
2179                 if (ret) {
2180                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2181                         return ret;
2182                 }
2183         }
2184
2185         return ret;
2186 }
2187
2188 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2189 static struct clk clk_uart0 = {
2190         .name           = "uart0",
2191         .set_rate       = clk_uart_set_rate,
2192         .clksel_con     = CRU_CLKSELS_CON(13),
2193         CRU_SRC_SET(0x3, 8),
2194         CRU_PARENTS_SET(clk_uart0_parents),
2195 };
2196
2197 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2198 static struct clk clk_uart1 = {
2199         .name           = "uart1",
2200         .set_rate       = clk_uart_set_rate,
2201         .clksel_con     = CRU_CLKSELS_CON(14),
2202         CRU_SRC_SET(0x3, 8),
2203         CRU_PARENTS_SET(clk_uart1_parents),
2204 };
2205
2206 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2207 static struct clk clk_uart2 = {
2208         .name           = "uart2",
2209         .set_rate       = clk_uart_set_rate,
2210         .clksel_con     = CRU_CLKSELS_CON(15),
2211         CRU_SRC_SET(0x3, 8),
2212         CRU_PARENTS_SET(clk_uart2_parents),
2213 };
2214 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2215 static struct clk clk_uart3 = {
2216         .name           = "uart3",
2217         .set_rate       = clk_uart_set_rate,
2218         .clksel_con     = CRU_CLKSELS_CON(16),
2219         CRU_SRC_SET(0x3, 8),
2220         CRU_PARENTS_SET(clk_uart3_parents),
2221 };
2222
2223 /* timer setting */
2224 GATE_CLK(timer0, xin24m, TIMER0);
2225 GATE_CLK(timer1, xin24m, TIMER1);
2226 GATE_CLK(timer2, xin24m, TIMER2);
2227 GATE_CLK(timer3, xin24m, TIMER3);
2228 GATE_CLK(timer4, xin24m, TIMER4);
2229 GATE_CLK(timer5, xin24m, TIMER5);
2230 GATE_CLK(timer6, xin24m, TIMER6);
2231
2232 /*********************power domain*******************************/
2233 #if 1
2234 #ifdef RK30_CLK_OFFBOARD_TEST
2235 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2236 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2237 #else
2238 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2239 #define _pmu_set_power_domain pmu_set_power_domain
2240 #endif
2241
2242 static int pd_video_mode(struct clk *clk, int on)
2243 {
2244         u32 gate[3];
2245         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2246         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2247         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2248         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2249         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2250         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2251         pmu_set_power_domain(PD_VIDEO, on);
2252         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2253         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2254         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2255         return 0;
2256 }
2257
2258 static struct clk pd_video = {
2259         .name   = "pd_video",
2260         .flags  = IS_PD,
2261         .mode   = pd_video_mode,
2262         .gate_idx       = PD_VIDEO,
2263 };
2264 static int pd_display_mode(struct clk *clk, int on)
2265 {
2266         u32 gate[10];
2267         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2268         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2269         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2270         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2271         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2272         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2273         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2274         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2275         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2276         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2277         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2278         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2279         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2280         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2281         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2282         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2283         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2284         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2285         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2286         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2287         pmu_set_power_domain(PD_VIO, on);
2288         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2289         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2290         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2291         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2292         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2293         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2294         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2295         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2296         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2297         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2298         return 0;
2299 }
2300
2301 static struct clk pd_display = {
2302         .name   = "pd_vio",
2303         .flags  = IS_PD,
2304         .mode   = pd_display_mode,
2305         .gate_idx       = PD_VIO,
2306 };
2307 static struct clk pd_lcdc0 = {
2308         .parent = &pd_display,
2309         .name   = "pd_lcdc0",
2310 };
2311 static struct clk pd_lcdc1 = {
2312         .parent = &pd_display,
2313         .name   = "pd_lcdc1",
2314 };
2315 static struct clk pd_cif0 = {
2316         .parent = &pd_display,
2317         .name   = "pd_cif0",
2318 };
2319 static struct clk pd_rga = {
2320         .parent = &pd_display,
2321         .name   = "pd_rga",
2322 };
2323 static struct clk pd_ipp = {
2324         .parent = &pd_display,
2325         .name   = "pd_ipp",
2326 };
2327 static struct clk pd_hdmi = {
2328         .parent = &pd_display,
2329         .name   = "pd_hdmi",
2330 };
2331
2332
2333 static int pd_gpu_mode(struct clk *clk, int on)
2334 {
2335         u32 gate[3];
2336         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2337         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2338         pmu_set_power_domain(PD_GPU, on);
2339         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2340         return 0;
2341 }
2342
2343 static struct clk pd_gpu = {
2344         .name   = "pd_gpu",
2345         .flags  = IS_PD,
2346         .mode   = pd_gpu_mode,
2347         .gate_idx       = PD_GPU,
2348 };
2349
2350 static int pm_off_mode(struct clk *clk, int on)
2351 {
2352         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2353         return 0;
2354 }
2355 static struct clk pd_peri = {
2356         .name   = "pd_peri",
2357         .flags  = IS_PD,
2358         .mode   = pm_off_mode,
2359         .gate_idx       = PD_PERI,
2360 };
2361
2362
2363 #define PD_CLK(name) \
2364 {\
2365         .dev_id = NULL,\
2366         .con_id = #name,\
2367         .clk = &name,\
2368 }
2369
2370 #endif
2371 /************************rk30 fixed div clock****************************************/
2372
2373 /*************************aclk_cpu***********************/
2374
2375 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2376 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2377 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2378
2379 /*************************hclk_cpu***********************/
2380
2381 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2382 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2383 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2384 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2385 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2386 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2387 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2388 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2389 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2390 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2391 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2392 GATE_CLK(hclk_imem0,    hclk_cpu,       HCLK_IMEM0);
2393 GATE_CLK(hclk_imem1,    hclk_cpu,       HCLK_IMEM1);
2394
2395 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2396 GATE_CLK(pclk_uart0,    ahb2apb_cpu, PCLK_UART0);
2397 GATE_CLK(pclk_uart1,    ahb2apb_cpu, PCLK_UART1);
2398 /*************************pclk_cpu***********************/
2399 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2400 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2401 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2402 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2403 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2404 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2405 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2406 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2407 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2408 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2409 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2410 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2411 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2412 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2413 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2414
2415 /*************************aclk_periph***********************/
2416
2417 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2418 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2419 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2420 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2421 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2422 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2423
2424 /*************************hclk_periph***********************/
2425 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2426 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2427 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2428 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2429 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2430 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2431 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2432 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2433 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2434 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2435 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2436 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2437 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2438 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2439 /*************************pclk_periph***********************/
2440 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2441 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2442 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2443 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2444 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2445 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2446 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2447 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2448 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2449 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2450 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2451 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2452 /*************************aclk_lcdc0***********************/
2453
2454 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2455 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2456 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2457 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2458
2459 /*************************aclk_lcdc0***********************/
2460
2461 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2462 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2463 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2464
2465
2466 #if 1
2467 #define CLK(dev, con, ck) \
2468 {\
2469         .dev_id = dev,\
2470         .con_id = con,\
2471         .clk = ck,\
2472 }
2473
2474
2475 #define CLK1(name) \
2476 {\
2477         .dev_id = NULL,\
2478         .con_id = #name,\
2479         .clk = &clk_##name,\
2480 }
2481
2482 #endif
2483
2484 static struct clk_lookup clks[] = {
2485         CLK(NULL, "xin24m", &xin24m),
2486         //CLK(NULL, "xin27m", &xin27m),
2487         CLK(NULL, "xin12m", &clk_12m),
2488         CLK(NULL, "arm_pll", &arm_pll_clk),
2489         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2490         CLK(NULL, "codec_pll", &codec_pll_clk),
2491         CLK(NULL, "general_pll", &general_pll_clk),
2492
2493         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2494         CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2495
2496         CLK(NULL, "ddr", &clk_ddr),
2497         CLK(NULL, "cpu", &clk_core),
2498         CLK1(l2c),
2499         CLK1(core_dbg),
2500         CLK("smp_twd", NULL, &core_periph),
2501         CLK(NULL, "aclk_core", &aclk_core),
2502
2503         CLK(NULL, "logic", &clk_cpu_div),
2504         CLK(NULL, "aclk_cpu", &aclk_cpu),
2505         CLK(NULL, "pclk_cpu", &pclk_cpu),
2506         CLK(NULL, "atclk_cpu", &atclk_cpu),
2507         CLK(NULL, "hclk_cpu", &hclk_cpu),
2508         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2509
2510         CLK(NULL, "gpu",        &aclk_gpu),
2511
2512         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2513         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2514         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2515         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2516
2517         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2518         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2519
2520         CLK(NULL, "aclk_periph", &aclk_periph),
2521         CLK(NULL, "pclk_periph", &pclk_periph),
2522         CLK(NULL, "hclk_periph", &hclk_periph),
2523
2524         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2525         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2526
2527         CLK(NULL, "cif_out_pll", &cif_out_pll),
2528         CLK(NULL, "cif0_out_div", &cif0_out_div),
2529         CLK(NULL, "cif0_out", &cif0_out),
2530
2531         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2532         CLK(NULL, "inv_cif0", &inv_cif0),
2533         CLK(NULL, "cif0_in", &cif0_in),
2534
2535         CLK1(i2s_pll),
2536         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2537         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2538         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2539
2540         // actually no i2s1
2541         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2542         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2543         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2544
2545
2546         CLK1(spdif_div),
2547         CLK1(spdif_frac_div),
2548         CLK1(spdif),
2549
2550         CLK1(otgphy0),
2551         CLK1(otgphy1),
2552         CLK1(otgphy0_480m),
2553         CLK1(otgphy1_480m),
2554         CLK1(hsicphy_480m),
2555         CLK1(hsicphy_12m),
2556
2557         CLK(NULL, "rmii_clkin", &rmii_clkin),
2558         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2559         CLK1(mac_ref),
2560         CLK1(mii_tx),
2561
2562         CLK1(hsadc_pll_div),
2563         CLK1(hsadc_frac_div),
2564         CLK1(hsadc_ext),
2565         CLK1(hsadc_out),
2566         CLK1(hsadc_out_inv),
2567         CLK1(hsadc),
2568
2569         CLK1(saradc),
2570
2571         CLK1(smc),
2572         CLK(NULL, "smc_inv",    &clkn_smc),
2573
2574         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2575         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2576
2577         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2578         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2579         CLK1(emmc),
2580
2581         CLK1(uart_pll),
2582         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2583         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2584         CLK("rk_serial.0", "uart", &clk_uart0),
2585         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2586         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2587         CLK("rk_serial.1", "uart", &clk_uart1),
2588         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2589         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2590         CLK("rk_serial.2", "uart", &clk_uart2),
2591         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2592         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2593         CLK("rk_serial.3", "uart", &clk_uart3),
2594
2595         CLK1(timer0),
2596         CLK1(timer1),
2597         CLK1(timer2),
2598         CLK1(timer3),
2599         CLK1(timer4),
2600         CLK1(timer5),
2601         CLK1(timer6),
2602
2603         /*************************aclk_cpu***********************/
2604         CLK1(dma1),
2605         CLK1(intmem),
2606         CLK1(aclk_strc_sys),
2607
2608         /*************************hclk_cpu***********************/
2609         CLK1(rom),
2610         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2611         // actually no i2s1
2612         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2613         CLK1(hclk_spdif),
2614         CLK1(hclk_cpubus),
2615         CLK1(hclk_ahb2apb),
2616         CLK1(hclk_vio_bus),
2617         CLK1(hclk_lcdc0),
2618         CLK1(hclk_lcdc1),
2619         CLK1(hclk_cif0),
2620         CLK1(hclk_ipp),
2621         CLK1(hclk_rga),
2622         CLK1(hclk_imem0),
2623         CLK1(hclk_imem1),
2624
2625         /*************************pclk_cpu***********************/
2626         CLK1(pwm01),
2627         CLK1(pclk_timer0),
2628         CLK1(pclk_timer2),
2629         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2630         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2631         CLK1(gpio0),
2632         CLK1(gpio1),
2633         CLK1(gpio2),
2634         CLK1(efuse),
2635         CLK1(tzpc),
2636         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2637         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2638         CLK1(pclk_ddrupctl),
2639         CLK1(pclk_ddrpubl),
2640         CLK1(dbg),
2641         CLK1(grf),
2642         CLK1(pmu),
2643
2644         /*************************aclk_periph***********************/
2645         CLK1(dma2),
2646         CLK1(aclk_smc),
2647         CLK1(aclk_gps),
2648         CLK1(aclk_peri_niu),
2649         CLK1(aclk_cpu_peri),
2650         CLK1(aclk_peri_axi_matrix),
2651
2652         /*************************hclk_periph***********************/
2653         CLK1(hclk_peri_axi_matrix),
2654         CLK1(hclk_peri_ahb_arbi),
2655         CLK1(hclk_emem_peri),
2656         CLK1(hclk_mac),
2657         CLK1(nandc),
2658         CLK1(hclk_usb_peri),
2659         CLK1(hclk_otg0),
2660         CLK1(hclk_otg1),
2661         CLK1(hclk_hsic),
2662         CLK1(hclk_hsadc),
2663         CLK1(hclk_pidfilter),
2664         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2665         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2666         CLK1(hclk_emmc),
2667
2668         /*************************pclk_periph***********************/
2669         CLK1(pclk_peri_axi_matrix),
2670         CLK1(pwm23),
2671         CLK1(wdt),
2672         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2673         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2674         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2675         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2676         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2677         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2678         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2679         CLK1(gpio3),
2680         CLK1(pclk_saradc),
2681
2682         /*************************aclk_lcdc0***********************/
2683         CLK1(aclk_vio0),
2684         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2685         CLK1(aclk_cif0),
2686         CLK1(aclk_ipp),
2687
2688         /*************************aclk_lcdc1***********************/
2689         CLK1(aclk_vio1),
2690         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2691         CLK1(aclk_rga),
2692         /************************power domain**********************/
2693
2694         PD_CLK(pd_peri),
2695         PD_CLK(pd_display),
2696         PD_CLK(pd_lcdc0),
2697         PD_CLK(pd_lcdc1),
2698         PD_CLK(pd_cif0),
2699         //PD_CLK(pd_cif1),
2700         PD_CLK(pd_rga),
2701         PD_CLK(pd_ipp),
2702         //PD_CLK(pd_video),
2703         PD_CLK(pd_gpu),
2704         //PD_CLK(pd_dbg),
2705 };
2706 static void __init rk30_init_enable_clocks(void)
2707 {
2708         #if 0
2709         //clk_enable_nolock(&xin24m);
2710         //clk_enable_nolock(&clk_12m);
2711         //clk_enable_nolock(&arm_pll_clk);
2712         //clk_enable_nolock(&ddr_pll_clk);
2713         //clk_enable_nolock(&codec_pll_clk);
2714         //clk_enable_nolock(&general_pll_clk);
2715         #endif
2716         clk_enable_nolock(&clk_ddr);
2717         //clk_enable_nolock(&clk_core);
2718         clk_enable_nolock(&clk_cpu_div);
2719         clk_enable_nolock(&clk_core_gpll_path);
2720         clk_enable_nolock(&clk_l2c);
2721         clk_enable_nolock(&clk_core_dbg);
2722         clk_enable_nolock(&core_periph);
2723         clk_enable_nolock(&aclk_core);
2724         //clk_enable_nolock(&aclk_cpu);
2725         //clk_enable_nolock(&pclk_cpu);
2726         clk_enable_nolock(&atclk_cpu);
2727         //clk_enable_nolock(&hclk_cpu);
2728         clk_enable_nolock(&ahb2apb_cpu);
2729         #if 0
2730          clk_enable_nolock(&clk_gpu);
2731          clk_enable_nolock(&aclk_gpu);
2732          clk_enable_nolock(&aclk_gpu_slv);
2733          clk_enable_nolock(&aclk_gpu_mst);
2734
2735          clk_enable_nolock(&aclk_vepu);
2736          clk_enable_nolock(&hclk_vepu);
2737          clk_enable_nolock(&aclk_vdpu);
2738          clk_enable_nolock(&hclk_vdpu);
2739
2740          clk_enable_nolock(&aclk_lcdc0_pre);
2741          clk_enable_nolock(&aclk_lcdc1_pre);
2742
2743          clk_enable_nolock(&aclk_periph);
2744         clk_enable_nolock(&pclk_periph);
2745         clk_enable_nolock(&hclk_periph);
2746         #endif
2747         #if 0
2748          clk_enable_nolock(&dclk_lcdc0);
2749          clk_enable_nolock(&dclk_lcdc1);
2750
2751          clk_enable_nolock(&cif_out_pll);
2752          clk_enable_nolock(&cif0_out_div);
2753
2754          clk_enable_nolock(&cif0_out);
2755          clk_enable_nolock(&pclkin_cif0);
2756          clk_enable_nolock(&inv_cif0);
2757          clk_enable_nolock(&cif0_in);
2758
2759          clk_enable_nolock(&clk_i2s_pll);
2760          clk_enable_nolock(&clk_i2s0_div);
2761          clk_enable_nolock(&clk_i2s0_frac_div);
2762          clk_enable_nolock(&clk_i2s0);
2763
2764           actually no i2s1
2765          clk_enable_nolock(&clk_i2s0_div);
2766          clk_enable_nolock(&clk_i2s0_frac_div);
2767          clk_enable_nolock(&clk_i2s0);
2768
2769         clk_enable_nolock(&clk_spdif_div);
2770         clk_enable_nolock(&clk_spdif_frac_div);
2771         clk_enable_nolock(&clk_spdif);
2772         #endif
2773         #if 0
2774         clk_enable_nolock(&clk_otgphy0);
2775         clk_enable_nolock(&clk_otgphy1);
2776         clk_enable_nolock(&clk_otgphy0_480m);
2777         clk_enable_nolock(&clk_otgphy1_480m);
2778         clk_enable_nolock(&clk_hsicphy_480m);
2779         clk_enable_nolock(&clk_hsicphy_12m);
2780         #endif
2781
2782         #if 0
2783         clk_enable_nolock(&rmii_clkin);
2784         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
2785         clk_enable_nolock(&clk_mac_ref);
2786         clk_enable_nolock(&clk_mii_tx);
2787         #endif
2788
2789         #if 0
2790         clk_enable_nolock(&clk_hsadc_pll_div);
2791         clk_enable_nolock(&clk_hsadc_frac_div);
2792         clk_enable_nolock(&clk_hsadc_ext);
2793         clk_enable_nolock(&clk_hsadc_out);
2794         clk_enable_nolock(&clk_hsadc_out_inv);
2795         clk_enable_nolock(&clk_hsadc);
2796
2797         clk_enable_nolock(&clk_saradc);
2798         #endif
2799         /*
2800         clk_enable_nolock(&clk_smc);
2801         clk_enable_nolock(&clkn_smc);
2802         */
2803         /*
2804         clk_enable_nolock(&clk_spi0);
2805         clk_enable_nolock(&clk_spi1);
2806         */
2807         /*
2808         clk_enable_nolock(&clk_sdmmc);
2809         clk_enable_nolock(&clk_sdio);
2810         clk_enable_nolock(&clk_emmc);
2811         */
2812         #if 0
2813         clk_enable_nolock(&clk_uart_pll);
2814         clk_enable_nolock(&clk_uart0_div);
2815         clk_enable_nolock(&clk_uart0_frac_div);
2816         clk_enable_nolock(&clk_uart0);
2817         clk_enable_nolock(&clk_uart1_div);
2818         clk_enable_nolock(&clk_uart1_frac_div);
2819         clk_enable_nolock(&clk_uart1);
2820         clk_enable_nolock(&clk_uart2_div);
2821         clk_enable_nolock(&clk_uart2_frac_div);
2822         clk_enable_nolock(&clk_uart2);
2823         clk_enable_nolock(&clk_uart3_div);
2824         clk_enable_nolock(&clk_uart3_frac_div);
2825         clk_enable_nolock(&clk_uart3);
2826         #endif
2827         #if CONFIG_RK_DEBUG_UART == 0
2828                 clk_enable_nolock(&clk_uart0);
2829                 clk_enable_nolock(&clk_pclk_uart0);
2830         #elif CONFIG_RK_DEBUG_UART == 1
2831                 clk_enable_nolock(&clk_uart1);
2832                 clk_enable_nolock(&clk_pclk_uart1);
2833
2834         #elif CONFIG_RK_DEBUG_UART == 2
2835                 clk_enable_nolock(&clk_uart2);
2836                 clk_enable_nolock(&clk_pclk_uart2);
2837
2838         #elif CONFIG_RK_DEBUG_UART == 3
2839                 clk_enable_nolock(&clk_uart3);
2840                 clk_enable_nolock(&clk_pclk_uart3);
2841
2842         #endif
2843         #if 0
2844         clk_enable_nolock(&clk_timer0);
2845         clk_enable_nolock(&clk_timer1);
2846         clk_enable_nolock(&clk_timer2);
2847         #endif
2848
2849         /*************************aclk_cpu***********************/
2850         clk_enable_nolock(&clk_dma1);
2851         clk_enable_nolock(&clk_intmem);
2852         clk_enable_nolock(&clk_aclk_strc_sys);
2853
2854         /*************************hclk_cpu***********************/
2855         clk_enable_nolock(&clk_rom);
2856         #if 0
2857         clk_enable_nolock(&clk_hclk_i2s0_2ch);
2858         // actually no i2s1
2859         clk_enable_nolock(&clk_hclk_i2s0_2ch);
2860         clk_enable_nolock(&clk_hclk_spdif);
2861         #endif
2862         clk_enable_nolock(&clk_hclk_cpubus);
2863         clk_enable_nolock(&clk_hclk_ahb2apb);
2864         clk_enable_nolock(&clk_hclk_vio_bus);
2865         #if 0
2866         clk_enable_nolock(&clk_hclk_lcdc0);
2867         clk_enable_nolock(&clk_hclk_lcdc1);
2868         clk_enable_nolock(&clk_hclk_cif0);
2869         clk_enable_nolock(&clk_hclk_ipp);
2870         clk_enable_nolock(&clk_hclk_rga);
2871         #endif
2872         clk_enable_nolock(&clk_hclk_imem0);
2873         clk_enable_nolock(&clk_hclk_imem1);
2874
2875         /*************************pclk_cpu***********************/
2876         #if 0
2877         clk_enable_nolock(&clk_pwm01);
2878         clk_enable_nolock(&clk_pclk_timer0);
2879         clk_enable_nolock(&clk_pclk_timer1);
2880         clk_enable_nolock(&clk_pclk_timer2);
2881         clk_enable_nolock(&clk_i2c0);
2882         clk_enable_nolock(&clk_i2c1);
2883         clk_enable_nolock(&clk_gpio0);
2884         clk_enable_nolock(&clk_gpio1);
2885         clk_enable_nolock(&clk_gpio2);
2886         clk_enable_nolock(&clk_efuse);
2887         #endif
2888         clk_enable_nolock(&clk_tzpc);
2889         //clk_enable_nolock(&clk_pclk_uart0);
2890         //clk_enable_nolock(&clk_pclk_uart1);
2891         clk_enable_nolock(&clk_pclk_ddrupctl);
2892         clk_enable_nolock(&clk_pclk_ddrpubl);
2893         clk_enable_nolock(&clk_dbg);
2894         clk_enable_nolock(&clk_grf);
2895         clk_enable_nolock(&clk_pmu);
2896
2897         /*************************aclk_periph***********************/
2898         clk_enable_nolock(&clk_dma2);
2899         clk_enable_nolock(&clk_aclk_smc);
2900         clk_enable_nolock(&clk_aclk_peri_niu);
2901         clk_enable_nolock(&clk_aclk_cpu_peri);
2902         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
2903
2904         /*************************hclk_periph***********************/
2905         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
2906         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
2907         clk_enable_nolock(&clk_hclk_emem_peri);
2908         //clk_enable_nolock(&clk_hclk_mac);
2909         //clk_enable_nolock(&clk_nandc);
2910         clk_enable_nolock(&clk_hclk_usb_peri);
2911         #if 0
2912         clk_enable_nolock(&clk_hclk_otg0);
2913         clk_enable_nolock(&clk_hclk_otg1);
2914         clk_enable_nolock(&clk_hclk_hsic);
2915         clk_enable_nolock(&clk_hclk_gps);
2916         clk_enable_nolock(&clk_hclk_hsadc);
2917         clk_enable_nolock(&clk_hclk_pidfilter);
2918         clk_enable_nolock(&clk_hclk_sdmmc);
2919         clk_enable_nolock(&clk_hclk_sdio);
2920         clk_enable_nolock(&clk_hclk_emmc);
2921         #endif
2922
2923         /*************************pclk_periph***********************/
2924         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
2925         #if 0
2926         clk_enable_nolock(&clk_pwm23);
2927         clk_enable_nolock(&clk_wdt);
2928         clk_enable_nolock(&clk_pclk_spi0);
2929         clk_enable_nolock(&clk_pclk_spi1);
2930         clk_enable_nolock(&clk_pclk_uart2);
2931         clk_enable_nolock(&clk_pclk_uart3);
2932         #endif
2933         #if 0
2934         clk_enable_nolock(&clk_i2c2);
2935         clk_enable_nolock(&clk_i2c3);
2936         clk_enable_nolock(&clk_i2c4);
2937         clk_enable_nolock(&clk_gpio3);
2938         clk_enable_nolock(&clk_pclk_saradc);
2939         #endif
2940         /*************************aclk_lcdc0***********************/
2941 #if 1
2942         //clk_enable_nolock(&clk_aclk_vio0);
2943         //clk_enable_nolock(&clk_aclk_lcdc0);
2944         //clk_enable_nolock(&clk_aclk_cif0);
2945         //clk_enable_nolock(&clk_aclk_ipp);
2946 #endif
2947         /*************************aclk_lcdc1***********************/
2948 #if 1
2949         //clk_enable_nolock(&clk_aclk_vio1);
2950         //clk_enable_nolock(&clk_aclk_lcdc1);
2951         //clk_enable_nolock(&clk_aclk_rga);
2952 #endif
2953         /************************power domain**********************/
2954
2955 }
2956 static void periph_clk_set_init(void)
2957 {
2958         unsigned long aclk_p, hclk_p, pclk_p;
2959         unsigned long ppll_rate = general_pll_clk.rate;
2960         //aclk 148.5
2961
2962         /* general pll */
2963         switch (ppll_rate) {
2964                 case 148500* KHZ:
2965                         aclk_p = 148500 * KHZ;
2966                         hclk_p = aclk_p >> 1;
2967                         pclk_p = aclk_p >> 2;
2968                         break;
2969                 case 1188*MHZ:
2970                         aclk_p = aclk_p >> 3; // 0
2971                         hclk_p = aclk_p >> 1;
2972                         pclk_p = aclk_p >> 2;
2973
2974                 case 297 * MHZ:
2975                         aclk_p = ppll_rate >> 1;
2976                         hclk_p = aclk_p >> 0;
2977                         pclk_p = aclk_p >> 1;
2978                         break;
2979
2980                 case 300 * MHZ:
2981                         aclk_p = ppll_rate >> 1;
2982                         hclk_p = aclk_p >> 0;
2983                         pclk_p = aclk_p >> 1;
2984                         break;
2985                 case 594 * MHZ:
2986                         aclk_p = ppll_rate >> 2;
2987                         hclk_p = aclk_p >> 0;
2988                         pclk_p = aclk_p >> 1;
2989                         break;
2990                 default:
2991                         aclk_p = 150 * MHZ;
2992                         hclk_p = 150 * MHZ;
2993                         pclk_p = 75 * MHZ;
2994                         break;
2995         }
2996         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
2997         clk_set_rate_nolock(&aclk_periph, aclk_p);
2998         clk_set_rate_nolock(&hclk_periph, hclk_p);
2999         clk_set_rate_nolock(&pclk_periph, pclk_p);
3000 }
3001
3002 static void cpu_axi_init(void)
3003 {
3004         unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3005         unsigned long gpll_rate = general_pll_clk.rate;
3006
3007         switch (gpll_rate) {
3008                 case 297 * MHZ:
3009                         cpu_div_rate = gpll_rate;
3010                         aclk_cpu_rate = cpu_div_rate >> 0;
3011                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3012                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3013                         break;
3014
3015                 case 594 * MHZ:
3016                         cpu_div_rate = gpll_rate >> 1;
3017                         aclk_cpu_rate = cpu_div_rate >> 0;
3018                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3019                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3020                         break;
3021                 default:
3022                         aclk_cpu_rate = 150 * MHZ;
3023                         hclk_cpu_rate = 150 * MHZ;
3024                         pclk_cpu_rate = 75 * MHZ;
3025                         break;
3026         }
3027         ahb2apb_cpu_rate = pclk_cpu_rate;
3028
3029         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3030         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3031         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3032         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3033         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3034         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3035 }
3036
3037 void rk30_clock_common_i2s_init(void)
3038 {
3039         unsigned long i2s_rate;
3040         //20 times
3041         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3042                 i2s_rate = 49152000;
3043         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3044                 i2s_rate = 24576000;
3045         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3046                 i2s_rate = 22579000;
3047         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3048                 i2s_rate = 12288000;
3049         } else {
3050                 i2s_rate = 49152000;
3051         }
3052
3053         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3054                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3055         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3056                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3057         } else {
3058                 if(general_pll_clk.rate > codec_pll_clk.rate)
3059                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3060                 else
3061                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3062         }
3063 }
3064
3065 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3066 {
3067
3068         //general
3069         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3070         //code pll
3071         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3072
3073         cpu_axi_init();
3074         clk_set_rate_nolock(&clk_core, 312 * MHZ);
3075         //periph clk
3076         periph_clk_set_init();
3077
3078         //i2s
3079         rk30_clock_common_i2s_init();
3080
3081         // spi
3082         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3083         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3084
3085         // uart
3086         if(rk30_clock_flags & CLK_FLG_UART_1_3M)
3087                 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3088         else
3089                 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3090         //mac
3091         if(!(gpll_rate % (50 * MHZ)))
3092                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3093         else if(!(ddr_pll_clk.rate % (50 * MHZ)))
3094                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3095         else
3096                 CLKDATA_ERR("mac can't get 50mhz\n");
3097
3098         //hsadc
3099         //auto pll sel
3100         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3101
3102         //lcdc0 lcd auto sel pll
3103         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3104         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3105
3106         //cif
3107         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3108
3109         //axi lcdc auto sel
3110         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3111         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3112         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3113         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3114
3115         //axi vepu auto sel
3116         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3117         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3118
3119         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3120         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3121         //gpu auto sel
3122         clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
3123         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3124
3125         clk_set_rate_nolock(&clk_uart0, 49500000);
3126
3127 }
3128
3129 static struct clk def_ops_clk = {
3130         .get_parent = clksel_get_parent,
3131         .set_parent = clksel_set_parent,
3132 };
3133
3134 #ifdef CONFIG_PROC_FS
3135 struct clk_dump_ops dump_ops;
3136 #endif
3137 void rk_dump_clock_info(void);
3138
3139 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3140 {
3141         struct clk_lookup *lk;
3142
3143         clk_register_dump_ops(&dump_ops);
3144         clk_register_default_ops_clk(&def_ops_clk);
3145         rk30_clock_flags = flags;
3146         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3147 #ifdef RK30_CLK_OFFBOARD_TEST
3148                 rk30_clkdev_add(lk);
3149 #else
3150                 clkdev_add(lk);
3151 #endif
3152                 clk_register(lk->clk);
3153         }
3154         clk_recalculate_root_clocks_nolock();
3155
3156         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3157
3158         /*
3159          * Only enable those clocks we will need, let the drivers
3160          * enable other clocks as necessary
3161          */
3162         rk30_init_enable_clocks();
3163 #if 1
3164         // print loader config
3165         CLKDATA_DBG("%s clks register dbg start\n", __func__);
3166         rk_dump_clock_info();
3167         rk30_clk_dump_regs();
3168
3169         CLKDATA_DBG("%s clks register dbg end\n", __func__);
3170 #endif
3171         /*
3172          * Disable any unused clocks left on by the bootloader
3173          */
3174         //clk_disable_unused();
3175         rk30_clock_common_init(gpll, cpll);
3176         preset_lpj = loops_per_jiffy;
3177
3178         //gpio6_b7
3179         //regfile_writel(0xc0004000,0x10c);
3180         //cru_writel(0x07000000,CRU_MISC_CON);
3181
3182 }
3183
3184 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3185 {
3186         _rk30_clock_data_init(gpll, cpll, flags);
3187         rk30_dvfs_init();
3188 }
3189
3190 /*
3191  * You can override arm_clk rate with armclk= cmdline option.
3192  */
3193 static int __init armclk_setup(char *str)
3194 {
3195         get_option(&str, &armclk);
3196
3197         if (!armclk)
3198                 return 0;
3199         if (armclk < 10000)
3200                 armclk *= MHZ;
3201         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3202         return 0;
3203 }
3204 #ifndef RK30_CLK_OFFBOARD_TEST
3205 early_param("armclk", armclk_setup);
3206 #endif
3207
3208
3209 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3210 {
3211         struct clk *ck;
3212         int i;
3213         unsigned long rate = clk->rate;
3214         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3215         for (i = 0; i < deep; i++)
3216                 printk("    ");
3217
3218         printk("%-11s ", clk->name);
3219 #ifndef RK30_CLK_OFFBOARD_TEST
3220         if (clk->flags & IS_PD) {
3221                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3222         }
3223 #endif
3224         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3225                 int idx = clk->gate_idx;
3226                 u32 v;
3227                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3228                 printk("%s ", v ? "off" : "on ");
3229         }
3230
3231         if (clk->pll) {
3232                 u32 pll_mode;
3233                 u32 pll_id = clk->pll->id;
3234                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3235                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3236                         printk("slow   ");
3237                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3238                         printk("normal ");
3239                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3240                         printk("deep   ");
3241
3242                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3243                         printk("bypass ");
3244         } else if(clk == &clk_ddr) {
3245                 rate = clk->recalc(clk);
3246         }
3247
3248         if (rate >= MHZ) {
3249                 if (rate % MHZ)
3250                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3251                 else
3252                         printk("%ld MHz", rate / MHZ);
3253         } else if (rate >= KHZ) {
3254                 if (rate % KHZ)
3255                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3256                 else
3257                         printk("%ld KHz", rate / KHZ);
3258         } else {
3259                 printk("%ld Hz", rate);
3260         }
3261
3262         printk(" usecount = %d", clk->usecount);
3263
3264         if (clk->parent)
3265                 printk(" parent = %s", clk->parent->name);
3266
3267         printk("\n");
3268
3269         list_for_each_entry(ck, root_clocks, node) {
3270                 if (ck->parent == clk)
3271                         rk_dump_clock(ck, deep + 1, root_clocks);
3272         }
3273 }
3274
3275 #if 1
3276 struct list_head *get_rk_clocks_head(void);
3277
3278 void rk_dump_clock_info(void)
3279 {
3280         struct clk* clk;
3281         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3282                 if (!clk->parent)
3283                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3284         }
3285 }
3286 #endif
3287
3288 #ifdef CONFIG_PROC_FS
3289
3290 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3291 {
3292         struct clk *ck;
3293         int i;
3294         unsigned long rate = clk->rate;
3295         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3296         for (i = 0; i < deep; i++)
3297                 seq_printf(s, "    ");
3298
3299         seq_printf(s, "%-11s ", clk->name);
3300 #ifndef RK30_CLK_OFFBOARD_TEST
3301         if (clk->flags & IS_PD) {
3302                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3303         }
3304 #endif
3305         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3306                 int idx = clk->gate_idx;
3307                 u32 v;
3308                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3309                 seq_printf(s, "%s ", v ? "off" : "on ");
3310         }
3311
3312         if (clk->pll) {
3313                 u32 pll_mode;
3314                 u32 pll_id = clk->pll->id;
3315                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3316                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3317                         seq_printf(s, "slow   ");
3318                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3319                         seq_printf(s, "normal ");
3320                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3321                         seq_printf(s, "deep   ");
3322
3323                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3324                         seq_printf(s, "bypass ");
3325         } else if(clk == &clk_ddr) {
3326                 rate = clk->recalc(clk);
3327         }
3328
3329         if (rate >= MHZ) {
3330                 if (rate % MHZ)
3331                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3332                 else
3333                         seq_printf(s, "%ld MHz", rate / MHZ);
3334         } else if (rate >= KHZ) {
3335                 if (rate % KHZ)
3336                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3337                 else
3338                         seq_printf(s, "%ld KHz", rate / KHZ);
3339         } else {
3340                 seq_printf(s, "%ld Hz", rate);
3341         }
3342
3343         seq_printf(s, " usecount = %d", clk->usecount);
3344
3345         if (clk->parent)
3346                 seq_printf(s, " parent = %s", clk->parent->name);
3347
3348         seq_printf(s, "\n");
3349
3350         list_for_each_entry(ck, root_clocks, node) {
3351                 if (ck->parent == clk)
3352                         dump_clock(s, ck, deep + 1, root_clocks);
3353         }
3354 }
3355
3356 static void dump_regs(struct seq_file *s)
3357 {
3358         int i = 0;
3359         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3360         seq_printf(s, "\nPLLRegisters:\n");
3361         for(i = 0; i < END_PLL_ID; i++) {
3362                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3363                                 cru_readl(PLL_CONS(i, 0)),
3364                                 cru_readl(PLL_CONS(i, 1)),
3365                                 cru_readl(PLL_CONS(i, 2)),
3366                                 cru_readl(PLL_CONS(i, 3))
3367                           );
3368         }
3369         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3370
3371         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3372                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3373         }
3374         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3375                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3376         }
3377         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3378         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3379
3380         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3381                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3382         }
3383         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3384         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3385
3386 }
3387
3388 void rk30_clk_dump_regs(void)
3389 {
3390         int i = 0;
3391         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3392         printk("\nPLLRegisters:\n");
3393         for(i = 0; i < END_PLL_ID; i++) {
3394                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3395                                 cru_readl(PLL_CONS(i, 0)),
3396                                 cru_readl(PLL_CONS(i, 1)),
3397                                 cru_readl(PLL_CONS(i, 2)),
3398                                 cru_readl(PLL_CONS(i, 3))
3399                       );
3400         }
3401         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3402
3403         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3404                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3405         }
3406         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3407                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3408         }
3409         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3410         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3411
3412         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3413                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3414         }
3415         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3416         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3417
3418 }
3419
3420
3421 #ifdef CONFIG_PROC_FS
3422 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3423 struct clk_dump_ops dump_ops = {
3424         .dump_clk = dump_clock,
3425         .dump_regs = dump_regs,
3426 };
3427 #endif
3428
3429
3430 #endif /* CONFIG_PROC_FS */
3431
3432
3433
3434
3435 #ifdef RK30_CLK_OFFBOARD_TEST
3436 struct clk *test_get_parent(struct clk *clk) {
3437         return clk->parent;
3438 }
3439
3440 void i2s_test(void)
3441 {
3442         struct clk *i2s_clk = &clk_i2s0;
3443
3444         clk_enable_nolock(i2s_clk);
3445
3446         clk_set_rate_nolock(i2s_clk, 12288000);
3447         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3448         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3449         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3450         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3451         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3452
3453 }
3454
3455 void uart_test(void)
3456 {
3457         struct clk *uart_clk = &clk_uart0;
3458
3459         clk_enable_nolock(uart_clk);
3460
3461         clk_set_rate_nolock(uart_clk, 12288000);
3462         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3463         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3464         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3465         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3466         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3467
3468 }
3469 void hsadc_test(void)
3470 {
3471         struct clk *hsadc_clk = &clk_hsadc;
3472
3473         printk("******************hsadc_test**********************\n");
3474         clk_enable_nolock(hsadc_clk);
3475
3476         clk_set_rate_nolock(hsadc_clk, 12288000);
3477         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3478
3479
3480         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3481         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3482
3483         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3484
3485         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3486
3487         printk("******************hsadc out clock**********************\n");
3488
3489         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3490         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3491         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3492         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3493
3494
3495
3496 }
3497
3498 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3499 {
3500         //arm
3501         printk("*********arm_pll_clk***********\n");
3502         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3503
3504         printk("*********set clk_core parent***********\n");
3505         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3506         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3507
3508         //general
3509         printk("*********general_pll_clk***********\n");
3510         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3511
3512         //code pll
3513         printk("*********codec_pll_clk***********\n");
3514         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3515
3516
3517         printk("*********periph_clk_set_init***********\n");
3518         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3519         periph_clk_set_init();
3520
3521 #if 0 //
3522         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3523 #else
3524         printk("*********clk i2s***********\n");
3525         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3526         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3527         i2s_test();
3528 #endif
3529         // spi
3530         clk_enable_nolock(&clk_spi0);
3531         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3532         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3533         //saradc
3534         clk_enable_nolock(&clk_saradc);
3535         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3536         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3537         //sdio
3538         clk_enable_nolock(&clk_sdio);
3539         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3540         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3541         // uart
3542         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3543         uart_test();
3544         //mac
3545         printk("*********mac***********\n");
3546
3547         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3548         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3549
3550         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3551         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3552         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3553
3554         printk("*********mac mii set***********\n");
3555         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3556         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3557         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3558         //hsadc
3559         printk("*********hsadc 1***********\n");
3560         //auto pll
3561         hsadc_test();
3562         //lcdc
3563         clk_enable_nolock(&dclk_lcdc0);
3564
3565         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
3566         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
3567
3568         //cif
3569         clk_enable_nolock(&cif0_out);
3570
3571         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3572         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
3573
3574         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
3575         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3576
3577         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
3578         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3579         //cif_in
3580         clk_enable_nolock(&cif0_in);
3581         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
3582         //axi lcdc
3583         clk_enable_nolock(&aclk_lcdc0);
3584         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
3585         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
3586         //axi vepu
3587         clk_enable_nolock(&aclk_vepu);
3588         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3589         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
3590
3591         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
3592         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
3593
3594         printk("test end\n");
3595
3596         /* arm pll
3597            clk_set_rate_nolock(&arm_pll_clk, armclk);
3598            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
3599            */
3600         //
3601         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3602         //
3603         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3604         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3605
3606 }
3607
3608
3609
3610
3611
3612 static LIST_HEAD(rk30_clocks);
3613 static DEFINE_MUTEX(rk30_clocks_mutex);
3614
3615 static inline int __rk30clk_get(struct clk *clk)
3616 {
3617         return 1;
3618 }
3619 void rk30_clkdev_add(struct clk_lookup *cl)
3620 {
3621         mutex_lock(&rk30_clocks_mutex);
3622         list_add_tail(&cl->node, &rk30_clocks);
3623         mutex_unlock(&rk30_clocks_mutex);
3624 }
3625 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
3626         struct clk_lookup *p, *cl = NULL;
3627         int match, best = 0;
3628
3629         list_for_each_entry(p, &rk30_clocks, node) {
3630                 match = 0;
3631                 if (p->dev_id) {
3632                         if (!dev_id || strcmp(p->dev_id, dev_id))
3633                                 continue;
3634                         match += 2;
3635                 }
3636                 if (p->con_id) {
3637                         if (!con_id || strcmp(p->con_id, con_id))
3638                                 continue;
3639                         match += 1;
3640                 }
3641
3642                 if (match > best) {
3643                         cl = p;
3644                         if (match != 3)
3645                                 best = match;
3646                         else
3647                                 break;
3648                 }
3649         }
3650         return cl;
3651 }
3652
3653 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
3654         struct clk_lookup *cl;
3655
3656         mutex_lock(&rk30_clocks_mutex);
3657         cl = rk30_clk_find(dev_id, con_id);
3658         if (cl && !__rk30clk_get(cl->clk))
3659                 cl = NULL;
3660         mutex_unlock(&rk30_clocks_mutex);
3661
3662         return cl ? cl->clk : ERR_PTR(-ENOENT);
3663 }
3664 //EXPORT_SYMBOL(rk30_clk_get_sys);
3665
3666 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
3667         const char *dev_id = dev ? dev_name(dev) : NULL;
3668         return rk30_clk_get_sys(dev_id, con_id);
3669 }
3670 //EXPORT_SYMBOL(rk30_clk_get);
3671
3672
3673 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3674
3675 void rk30_clocks_test(void)
3676 {
3677         struct clk *test_gpll;
3678         test_gpll = rk30_clk_get(NULL, "general_pll");
3679         if(test_gpll) {
3680                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
3681                 printk("gpll rate=%lu\n", test_gpll->rate);
3682         }
3683         //while(1);
3684 }
3685
3686 void __init rk30_clock_init_test(void)
3687 {
3688
3689         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
3690         //while(1);
3691 }
3692
3693
3694 #endif
3695
3696