arch/arm/mach-rk3188/clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <plat/efuse.h>
  25 #include <mach/cru.h>
  26 #include <mach/iomux.h>
  27 #include <mach/clock.h>
  28 #include <mach/pmu.h>
  29 #include <mach/dvfs.h>
  30 #include <mach/ddr.h>
  31 #include <mach/cpu.h>
  32
  33 #define MHZ                     (1000UL * 1000UL)
  34 #define KHZ                     (1000UL)
  35 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  36 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
  37 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  38 void rk30_clk_dump_regs(void);
  39
  40 //flags bit
  41 //has extern 27mhz
  42 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  43 //max i2s rate
  44 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  45 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  46 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  47 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  48 //uart 1m\3m
  49 #define CLK_FLG_UART_1_3M                       (1<<5)
  50
  51 #define ARCH_RK31
  52
  53 struct apll_clk_set {
  54         unsigned long   rate;
  55         u32     pllcon0;
  56         u32     pllcon1;
  57         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  58         u32     rst_dly;//us
  59         u32     clksel0;
  60         u32     clksel1;
  61         unsigned long   lpj;
  62 };
  63 struct pll_clk_set {
  64         unsigned long   rate;
  65         u32     pllcon0;
  66         u32     pllcon1;
  67         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  68         unsigned long   rst_dly;//us
  69 };
  70
  71 #define SET_PLL_DATA(_pll_id,_table) \
  72 {\
  73         .id=(_pll_id),\
  74         .table=(_table),\
  75 }
  76
  77
  78 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  79 { \
  80         .rate   = (_mhz) * KHZ, \
  81         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  82         .pllcon1 = PLL_CLKF_SET(nf),\
  83         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  84         .rst_dly=((nr*500)/24+1),\
  85 }
  86
  87
  88 #define _APLL_SET_LPJ(_mhz) \
  89         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  90
  91
  92 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  93                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  94 { \
  95         .rate   = _mhz * MHZ, \
  96         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  97         .pllcon1 = PLL_CLKF_SET(nf),\
  98         .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
  99         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
 100         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
 101         _APLL_SET_LPJ(_mhz),\
 102         .rst_dly=((nr*500)/24+1),\
 103 }
 104
 105 #define CRU_DIV_SET(mask,shift,max) \
 106         .div_mask=(mask),\
 107 .div_shift=(shift),\
 108 .div_max=(max)
 109
 110
 111 #define CRU_SRC_SET(mask,shift ) \
 112         .src_mask=(mask),\
 113 .src_shift=(shift)
 114
 115 #define CRU_PARENTS_SET(parents_array) \
 116         .parents=(parents_array),\
 117 .parents_num=ARRAY_SIZE((parents_array))
 118
 119 #define CRU_GATE_MODE_SET(_func,_IDX) \
 120         .mode=_func,\
 121 .gate_idx=(_IDX)
 122
 123 struct clk_src_sel {
 124         struct clk      *parent;
 125         u8      value;//crt bit
 126         u8      flag;
 127         //selgate
 128 };
 129
 130 #define GATE_CLK(NAME,PARENT,ID) \
 131         static struct clk clk_##NAME = { \
 132                 .name           = #NAME, \
 133                 .parent         = &PARENT, \
 134                 .mode           = gate_mode, \
 135                 .gate_idx       = CLK_GATE_##ID, \
 136         }
 137 #ifdef RK30_CLK_OFFBOARD_TEST
 138 u32 TEST_GRF_REG[0x240];
 139 u32 TEST_CRU_REG[0x240];
 140 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 141
 142 u32 cru_writel_is_pr(u32 offset)
 143 {
 144         return (offset == 0x4000);
 145 }
 146 void cru_writel(u32 v, u32 offset)
 147 {
 148
 149         u32 mask_v = v >> 16;
 150         TEST_CRU_REG[offset/4] &= (~mask_v);
 151
 152         v &= (mask_v);
 153
 154         TEST_CRU_REG[offset/4] |= v;
 155         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 156
 157         if(cru_writel_is_pr(offset)) {
 158                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 159
 160         }
 161
 162 }
 163 void cru_writel_i2s(u32 v, u32 offset)
 164 {
 165         TEST_CRU_REG[offset/4] = v;
 166 }
 167 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 168
 169 #define regfile_readl(offset)   (0xffffffff)
 170 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 171 void rk30_clkdev_add(struct clk_lookup *cl);
 172 #else
 173 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 174 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 175 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 176 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 177
 178 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 179 #endif
 180
 181 //#define DEBUG
 182 #ifdef DEBUG
 183 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 184 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 185 //#define CLKDATA_DBG(fmt, args...) printk("CLKDATA_DBG:\t"fmt, ##args)
 186 //#define CLKDATA_LOG(fmt, args...) printk("CLKDATA_LOG:\t"fmt, ##args)
 187 #else
 188 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 189 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 190 #endif
 191 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 192 #define CLKDATA_WARNING(fmt, args...) printk("CLKDATA_WANING:\t"fmt, ##args)
 193
 194
 195 #define get_cru_bits(con,mask,shift)\
 196         ((cru_readl((con)) >> (shift)) & (mask))
 197
 198 #define set_cru_bits_w_msk(val,mask,shift,con)\
 199         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 200
 201
 202 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 203                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 204
 205
 206 static u32 rk30_clock_flags = 0;
 207 static struct clk codec_pll_clk;
 208 static struct clk general_pll_clk;
 209 static struct clk arm_pll_clk;
 210 static unsigned long lpj_gpll;
 211 static unsigned int __initdata armclk = 504 * MHZ;
 212
 213
 214 /************************clk recalc div rate*********************************/
 215
 216 //for free div
 217 static unsigned long clksel_recalc_div(struct clk *clk)
 218 {
 219         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 220
 221         unsigned long rate = clk->parent->rate / div;
 222         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 223         return rate;
 224 }
 225
 226 //for div 1 2 4 2^n
 227 static unsigned long clksel_recalc_shift(struct clk *clk)
 228 {
 229         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 230         unsigned long rate = clk->parent->rate >> shift;
 231         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 232         return rate;
 233 }
 234
 235
 236 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 237 {
 238         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 239         unsigned long rate = clk->parent->rate >> shift;
 240         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 241         return rate;
 242 }
 243
 244 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 245 {
 246         unsigned long rate = clk->parent->rate;
 247         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 248         return rate;
 249 }
 250 /********************************set div rate***********************************/
 251
 252 //for free div
 253 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 254 {
 255         u32 div;
 256         for (div = 0; div < clk->div_max; div++) {
 257                 u32 new_rate = clk->parent->rate / (div + 1);
 258                 if (new_rate <= rate) {
 259                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 260                         //clk->rate = new_rate;
 261                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 262                                         clk->name, rate, div + 1);
 263                         return 0;
 264                 }
 265         }
 266         return -ENOENT;
 267 }
 268
 269 //for div 1 2 4 2^n
 270 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 271 {
 272         u32 shift;
 273         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 274                 u32 new_rate = clk->parent->rate >> shift;
 275                 if (new_rate <= rate) {
 276                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 277                         clk->rate = new_rate;
 278                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 279                                         clk->name, rate, shift);
 280                         return 0;
 281                 }
 282         }
 283         return -ENOENT;
 284 }
 285
 286 //for div 2 4 2^n
 287 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 288 {
 289         u32 shift;
 290
 291         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 292                 u32 new_rate = clk->parent->rate >> shift;
 293                 if (new_rate <= rate) {
 294                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 295                         clk->rate = new_rate;
 296                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 297                                         clk->name, rate, shift);
 298                         return 0;
 299                 }
 300         }
 301         return -ENOENT;
 302 }
 303
 304 //for div 1 2 4 2*n
 305 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 306 {
 307         u32 div;
 308         for (div = 2; div < clk->div_max; div += 2) {
 309                 u32 new_rate = clk->parent->rate / div;
 310                 if (new_rate <= rate) {
 311                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 312                         clk->rate = new_rate;
 313                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 314                                         __func__, clk->name, rate, div);
 315                         return 0;
 316                 }
 317         }
 318         return -ENOENT;
 319 }
 320 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 321 {
 322         u32 div;
 323         unsigned long new_rate;
 324         for (div = 0; div < div_max; div++) {
 325                 new_rate = rate / (div + 1);
 326                 if (new_rate <= rate_out) {
 327                         return div + 1;
 328                 }
 329         }
 330         return div_max ? div_max : 1;
 331 }
 332 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 333 {
 334         u32 div;
 335         unsigned long new_rate;
 336         for (div = 1; div < div_max; div += 2) {
 337                 new_rate = rate / (div + 1);
 338                 if (new_rate <= rate_out) {
 339                         return div + 1;
 340                 }
 341         }
 342         return div_max ? div_max : 1;
 343 }
 344 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 345         u32 div[2] = {0, 0};
 346         unsigned long new_rate[2] = {0, 0};
 347         u32 i;
 348
 349         if(clk->rate == rate)
 350                 return clk->parent;
 351         for(i = 0; i < 2; i++) {
 352                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 353                 new_rate[i] = clk->parents[i]->rate / div[i];
 354                 if(new_rate[i] == rate) {
 355                         *div_out = div[i];
 356                         return clk->parents[i];
 357                 }
 358         }
 359         if(new_rate[0] < new_rate[1])
 360                 i = 1;
 361         else
 362                 i = 0;
 363         *div_out = div[i];
 364         return clk->parents[i];
 365 }
 366 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 367         u32 div[2] = {0, 0};
 368         unsigned long new_rate[2] = {0, 0};
 369         u32 i;
 370
 371         if(clk->rate == rate)
 372                 return clk->parent;
 373         for(i = 0; i < 2; i++) {
 374                 div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 375                 new_rate[i] = clk->parents[i]->rate / div[i];
 376                 if(new_rate[i] == rate) {
 377                         *div_out = div[i];
 378                         return clk->parents[i];
 379                 }
 380         }
 381         if(new_rate[0] < new_rate[1])
 382                 i = 1;
 383         else
 384                 i = 0;
 385         *div_out = div[i];
 386         return clk->parents[i];
 387 }
 388
 389 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 390 {
 391         struct clk *p_clk;
 392         u32 div, old_div;
 393         int ret = 0;
 394         if(clk->rate == rate)
 395                 return 0;
 396         p_clk = get_freediv_parents_div(clk, rate, &div);
 397
 398         if(!p_clk)
 399                 return -ENOENT;
 400
 401         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 402         if (clk->parent != p_clk) {
 403                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 404
 405                 if(div > old_div) {
 406                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 407                 }
 408                 ret = clk_set_parent_nolock(clk, p_clk);
 409                 if(ret) {
 410                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 411                         return -ENOENT;
 412                 }
 413         }
 414         //set div
 415         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 416         return 0;
 417 }
 418 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 419 {
 420         struct clk *p_clk;
 421         u32 div, old_div;
 422         int ret = 0;
 423         if(clk->rate == rate)
 424                 return 0;
 425         p_clk = get_evendiv_parents_div(clk, rate, &div);
 426
 427         if(!p_clk)
 428                 return -ENOENT;
 429
 430         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 431         if (clk->parent != p_clk) {
 432                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 433
 434                 if(div > old_div) {
 435                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 436                 }
 437                 ret = clk_set_parent_nolock(clk, p_clk);
 438                 if(ret) {
 439                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 440                         return -ENOENT;
 441                 }
 442         }
 443         //set div
 444         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 445         return 0;
 446 }
 447
 448 //rate==div rate //hdmi
 449 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 450 {
 451         struct clk *p_clk;
 452         u32 div, old_div;
 453         int ret;
 454         p_clk = get_freediv_parents_div(clk, rate, &div);
 455
 456         if(!p_clk)
 457                 return -ENOENT;
 458
 459         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 460                 return -ENOENT;
 461
 462         if (clk->parent != p_clk) {
 463                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 464                                 clk->div_shift, clk->div_mask) + 1;
 465                 if(div > old_div) {
 466                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 467                 }
 468                 ret = clk_set_parent_nolock(clk, p_clk);
 469                 if (ret) {
 470                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 471                         return ret;
 472                 }
 473         }
 474         //set div
 475         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 476         return 0;
 477 }
 478
 479 /***************************round********************************/
 480
 481 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 482 {
 483         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 484 }
 485
 486 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 487 {
 488         u32 div;
 489         struct clk *p_clk;
 490         if(clk->rate == rate)
 491                 return clk->rate;
 492         p_clk = get_freediv_parents_div(clk, rate, &div);
 493         if(!p_clk)
 494                 return 0;
 495         return p_clk->rate / div;
 496 }
 497
 498 /**************************************others seting************************************/
 499
 500 static struct clk *clksel_get_parent(struct clk *clk) {
 501         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 502 }
 503 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 504 {
 505         u32 i;
 506         if (unlikely(!clk->parents))
 507                 return -EINVAL;
 508         for (i = 0; (i < clk->parents_num); i++) {
 509                 if (clk->parents[i] != parent)
 510                         continue;
 511                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 512                 return 0;
 513         }
 514         return -EINVAL;
 515 }
 516
 517 static int gate_mode(struct clk *clk, int on)
 518 {
 519         int idx = clk->gate_idx;
 520         if (idx >= CLK_GATE_MAX)
 521                 return -EINVAL;
 522         if(on) {
 523                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 524                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 525                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 526         } else {
 527                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 528                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 529                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 530         }
 531         return 0;
 532 }
 533 /*****************************frac set******************************************/
 534
 535 static unsigned long clksel_recalc_frac(struct clk *clk)
 536 {
 537         unsigned long rate;
 538         u64 rate64;
 539         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 540         if (r == 0) // FPGA ?
 541                 return clk->parent->rate;
 542         numerator = r >> 16;
 543         denominator = r & 0xFFFF;
 544         rate64 = (u64)clk->parent->rate * numerator;
 545         do_div(rate64, denominator);
 546         rate = rate64;
 547         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 548         return rate;
 549 }
 550
 551 static u32 clk_gcd(u32 numerator, u32 denominator)
 552 {
 553         u32 a, b;
 554
 555         if (!numerator || !denominator)
 556                 return 0;
 557         if (numerator > denominator) {
 558                 a = numerator;
 559                 b = denominator;
 560         } else {
 561                 a = denominator;
 562                 b = numerator;
 563         }
 564         while (b != 0) {
 565                 int r = b;
 566                 b = a % b;
 567                 a = r;
 568         }
 569
 570         return a;
 571 }
 572
 573 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 574                 u32 *numerator, u32 *denominator)
 575 {
 576         u32 gcd_vl;
 577         gcd_vl = clk_gcd(rate, rate_out);
 578         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 579
 580         if (!gcd_vl) {
 581                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 582                 return -ENOENT;
 583         }
 584
 585         *numerator = rate_out / gcd_vl;
 586         *denominator = rate / gcd_vl;
 587
 588         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 589                         *numerator, *denominator, *denominator / *numerator);
 590
 591         if (*numerator > 0xffff || *denominator > 0xffff ||
 592                         (*denominator / (*numerator)) < 20) {
 593                 CLKDATA_ERR("can't get a available nume and deno\n");
 594                 return -ENOENT;
 595         }
 596
 597         return 0;
 598
 599 }
 600 /* *********************pll **************************/
 601
 602 #define rk30_clock_udelay(a) udelay(a);
 603
 604 /*********************pll lock status**********************************/
 605 //#define GRF_SOC_CON0       0x15c
 606 static void pll_wait_lock(int pll_idx)
 607 {
 608         u32 pll_state[4] = {1, 0, 2, 3};
 609         u32 bit = 0x20u << pll_state[pll_idx];
 610         int delay = 24000000;
 611         while (delay > 0) {
 612                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 613                         break;
 614                 delay--;
 615         }
 616         if (delay == 0) {
 617                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 618                 while(1);
 619         }
 620 }
 621
 622
 623
 624 /***************************pll function**********************************/
 625 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 626 {
 627         unsigned long rate;
 628
 629         if (PLLS_IN_NORM(pll_id)) {
 630                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 631                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 632
 633
 634                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 635
 636                 /*
 637                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 638                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 639                    */
 640
 641
 642                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 643                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 644                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 645
 646                 do_div(rate64, PLL_NR(pll_con0));
 647                 do_div(rate64, PLL_NO(pll_con0));
 648
 649                 rate = rate64;
 650                 /*
 651                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 652                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 653                    */
 654         } else {
 655                 rate = parent_rate;
 656                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 657         }
 658         return rate;
 659 }
 660 static unsigned long plls_clk_recalc(struct clk *clk)
 661 {
 662         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 663 }
 664 static unsigned long plus_pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 665 {
 666         unsigned long rate;
 667
 668         if (PLLS_IN_NORM(pll_id)) {
 669                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 670                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 671
 672                 u64 rate64 = (u64)parent_rate * PLUS_PLL_NF(pll_con1);
 673
 674                 do_div(rate64, PLUS_PLL_NR(pll_con0));
 675                 do_div(rate64, PLUS_PLL_NO(pll_con0));
 676
 677                 rate = rate64;
 678         } else {
 679                 rate = parent_rate;
 680                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 681         }
 682         return rate;
 683 }
 684 static unsigned long plus_plls_clk_recalc(struct clk *clk)
 685 {
 686         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 687         return plus_pll_clk_recalc(clk->pll->id, clk->parent->rate);
 688 }
 689
 690 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 691 {
 692         //enter slowmode
 693         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 694         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 695         dsb();
 696         dsb();
 697         dsb();
 698         dsb();
 699         dsb();
 700         dsb();
 701         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 702         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 703
 704         rk30_clock_udelay(1);
 705         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 706
 707         pll_wait_lock(pll_id);
 708
 709         //return form slow
 710         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 711
 712         /*
 713            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 714            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 715            */
 716
 717         return 0;
 718 }
 719
 720 static int plus_pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 721 {
 722         //enter slowmode
 723         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 724
 725         //enter rest
 726         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
 727         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 728         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 729         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id, 2));
 730         rk30_clock_udelay(5);
 731
 732         //return form rest
 733         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
 734
 735         //wating lock state
 736         rk30_clock_udelay(clk_set->rst_dly);
 737         pll_wait_lock(pll_id);
 738
 739         //return form slow
 740         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 741
 742         return 0;
 743 }
 744
 745 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 746 {
 747         struct _pll_data *pll_data = c->pll;
 748         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 749
 750         while(clk_set->rate) {
 751                 if (clk_set->rate == rate) {
 752                         break;
 753                 }
 754                 clk_set++;
 755         }
 756         if(clk_set->rate == rate) {
 757                 pll_clk_set_rate(clk_set, pll_data->id);
 758                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 759         } else {
 760                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 761                 return -1;
 762         }
 763         return 0;
 764 }
 765
 766 static int plus_gpll_clk_set_rate(struct clk *c, unsigned long rate)
 767 {
 768         struct _pll_data *pll_data = c->pll;
 769         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 770         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 771
 772         while(clk_set->rate) {
 773                 if (clk_set->rate == rate) {
 774                         break;
 775                 }
 776                 clk_set++;
 777         }
 778         if(clk_set->rate == rate) {
 779                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 780                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 781         } else {
 782                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 783                 return -1;
 784         }
 785         return 0;
 786 }
 787 #define PLL_FREF_MIN (183*KHZ)
 788 #define PLL_FREF_MAX (1500*MHZ)
 789
 790 #define PLL_FVCO_MIN (300*MHZ)
 791 #define PLL_FVCO_MAX (1500*MHZ)
 792
 793 #define PLL_FOUT_MIN (18750*KHZ)
 794 #define PLL_FOUT_MAX (1500*MHZ)
 795
 796 #define PLL_NF_MAX (65536)
 797 #define PLL_NR_MAX (64)
 798 #define PLL_NO_MAX (64)
 799
 800 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 801 {
 802         u32 nr, nf, no, nonr;
 803         u32 n;
 804         u32 YFfenzi;
 805         u32 YFfenmu;
 806         unsigned long fref, fvco, fout;
 807         u32 gcd_val = 0;
 808
 809         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 810         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 811                 return 0;
 812         gcd_val = clk_gcd(fin_hz, fout_hz);
 813         YFfenzi = fout_hz / gcd_val;
 814         YFfenmu = fin_hz / gcd_val;
 815
 816         for(n = 1;; n++) {
 817                 nf = YFfenzi * n;
 818                 nonr = YFfenmu * n;
 819                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 820                         break;
 821                 for(no = 1; no <= PLL_NO_MAX; no++) {
 822                         if(!(no == 1 || !(no % 2)))
 823                                 continue;
 824
 825                         if(nonr % no)
 826                                 continue;
 827                         nr = nonr / no;
 828
 829                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 830                                 continue;
 831
 832                         fref = fin_hz / nr;
 833                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 834                                 continue;
 835
 836                         fvco = (fin_hz / nr) * nf;
 837                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 838                                 continue;
 839                         fout = fvco / no;
 840                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 841                                 continue;
 842                         *clk_nr = nr;
 843                         *clk_no = no;
 844                         *clk_nf = nf;
 845                         return 1;
 846
 847                 }
 848
 849         }
 850         return 0;
 851 }
 852
 853 static int pll_clk_mode(struct clk *clk, int on)
 854 {
 855         u8 pll_id = clk->pll->id;
 856         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 857         u32 dly = (nr * 500) / 24 + 1;
 858         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 859         if (on) {
 860                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 861                 rk30_clock_udelay(dly);
 862                 pll_wait_lock(pll_id);
 863                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 864         } else {
 865                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 866                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 867         }
 868         return 0;
 869 }
 870
 871 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 872 {
 873         struct _pll_data *pll_data = c->pll;
 874         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 875         struct pll_clk_set temp_clk_set;
 876         u32 clk_nr, clk_nf, clk_no;
 877
 878         if(rate == 24 * MHZ) {
 879                 cru_writel(PLL_MODE_SLOW(pll_data->id), CRU_MODE_CON);
 880                 cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll_data->id, 3));
 881                 return 0;
 882         }
 883         while(clk_set->rate) {
 884                 if (clk_set->rate == rate) {
 885                         break;
 886                 }
 887                 clk_set++;
 888         }
 889         if(clk_set->rate == rate) {
 890                 CLKDATA_DBG("cpll get a rate\n");
 891                 pll_clk_set_rate(clk_set, pll_data->id);
 892
 893         } else {
 894                 CLKDATA_DBG("cpll get auto calc a rate\n");
 895                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 896                         pr_err("cpll auto set rate error\n");
 897                         return -ENOENT;
 898                 }
 899                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 900                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 901                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 902                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 903                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 904
 905         }
 906         return 0;
 907 }
 908 static int plus_cpll_clk_set_rate(struct clk *c, unsigned long rate)
 909 {
 910         struct _pll_data *pll_data = c->pll;
 911         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 912         struct pll_clk_set temp_clk_set;
 913         u32 clk_nr, clk_nf, clk_no;
 914         DVFS_DBG("%s: for rk3188 plus\n", __func__);
 915
 916         while(clk_set->rate) {
 917                 if (clk_set->rate == rate) {
 918                         break;
 919                 }
 920                 clk_set++;
 921         }
 922         if(clk_set->rate == rate) {
 923                 CLKDATA_DBG("cpll get a rate\n");
 924                 plus_pll_clk_set_rate(clk_set, pll_data->id);
 925
 926         } else {
 927                 CLKDATA_DBG("cpll get auto calc a rate\n");
 928                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 929                         pr_err("cpll auto set rate error\n");
 930                         return -ENOENT;
 931                 }
 932                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 933                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 934                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 935                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 936                 plus_pll_clk_set_rate(&temp_clk_set, pll_data->id);
 937
 938         }
 939         return 0;
 940 }
 941
 942
 943 /* ******************fixed input clk ***********************************************/
 944 static struct clk xin24m = {
 945         .name           = "xin24m",
 946         .rate           = 24 * MHZ,
 947         .flags          = RATE_FIXED,
 948 };
 949
 950 static struct clk clk_12m = {
 951         .name           = "clk_12m",
 952         .parent         = &xin24m,
 953         .rate           = 12 * MHZ,
 954         .flags          = RATE_FIXED,
 955 };
 956
 957 /************************************pll func***************************/
 958 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 959                 struct apll_clk_set *tables) {
 960         const struct apll_clk_set *ps, *pt;
 961
 962         /* find the arm_pll we want. */
 963         ps = pt = tables;
 964         while (pt->rate) {
 965                 if (pt->rate == rate) {
 966                         ps = pt;
 967                         break;
 968                 }
 969                 // we are sorted, and ps->rate > pt->rate.
 970                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 971                         ps = pt;
 972                 if (pt->rate < rate)
 973                         break;
 974                 pt++;
 975         }
 976         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 977         return ps;
 978 }
 979 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 980 {
 981         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 982 }
 983 #if 1
 984 struct arm_clks_div_set {
 985         u32 rate;
 986         u32     clksel0;
 987         u32     clksel1;
 988 };
 989
 990 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 991 { \
 992         .rate    =_mhz,\
 993         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 994         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 995         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 996         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 997         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 998 }
 999 struct arm_clks_div_set arm_clk_div_tlb[] = {
1000         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
1001         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
1002         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
1003         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
1004         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
1005         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
1006         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
1007 };
1008 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
1009         int i = 0;
1010         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
1011                 if(arm_clk_div_tlb[i].rate >= rate)
1012                         return &arm_clk_div_tlb[i];
1013         }
1014         return NULL;
1015 }
1016
1017 #endif
1018
1019 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1020 {
1021         unsigned long flags;
1022         const struct apll_clk_set *ps;
1023         u32 pll_id = clk->pll->id;
1024         u32 temp_div;
1025         u32 old_aclk_div = 0, new_aclk_div;
1026
1027         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1028
1029         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1030         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1031
1032         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1033                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1034
1035         if(general_pll_clk.rate > clk->rate) {
1036                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1037         } else {
1038                 temp_div = 1;
1039         }
1040
1041         // ungating cpu gpll path
1042         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1043         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1044
1045         local_irq_save(flags);
1046         //div arm clk for gpll
1047
1048         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1049         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1050
1051         loops_per_jiffy = lpj_gpll / temp_div;
1052         smp_wmb();
1053
1054         /*if core src don't select gpll ,apll neet to enter slow mode */
1055         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1056
1057
1058         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
1059         dsb();
1060         dsb();
1061         dsb();
1062         dsb();
1063         dsb();
1064         dsb();
1065         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1066         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1067
1068         rk30_clock_udelay(1);
1069         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
1070
1071         pll_wait_lock(pll_id);
1072
1073         //return form slow
1074         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1075         //reparent to apll
1076
1077         if(new_aclk_div>=old_aclk_div) {
1078                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1079                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1080         }
1081
1082         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1083         if(old_aclk_div>new_aclk_div) {
1084                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1085                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1086         }
1087
1088         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1089
1090         loops_per_jiffy = ps->lpj;
1091         smp_wmb();
1092
1093         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1094
1095         local_irq_restore(flags);
1096
1097         //gate gpll path
1098         // FIXME
1099         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1100         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1101
1102         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1103                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1104                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1105                         cru_readl(CRU_CLKSELS_CON(1)));
1106         return 0;
1107 }
1108
1109 static int plus_arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1110 {
1111         unsigned long flags;
1112         const struct apll_clk_set *ps;
1113         u32 pll_id = clk->pll->id;
1114         u32 temp_div;
1115         u32 old_aclk_div = 0, new_aclk_div;
1116         DVFS_DBG("%s: for rk3188 plus\n", __func__);
1117
1118         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
1119
1120         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1121         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
1122
1123         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
1124                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
1125
1126         if(general_pll_clk.rate > clk->rate) {
1127                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
1128         } else {
1129                 temp_div = 1;
1130         }
1131
1132         // ungating cpu gpll path
1133         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
1134         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1135
1136         local_irq_save(flags);
1137         //div arm clk for gpll
1138
1139         cru_writel(CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
1140         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
1141
1142         loops_per_jiffy = lpj_gpll / temp_div;
1143         smp_wmb();
1144
1145         /*if core src don't select gpll ,apll neet to enter slow mode */
1146         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1147
1148         //enter rest
1149         cru_writel(PLL_RESET_W_MSK | PLL_RESET, PLL_CONS(pll_id, 3));
1150         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
1151         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
1152         cru_writel(ps->pllcon2, PLL_CONS(pll_id, 2));
1153         rk30_clock_udelay(5);
1154
1155         //return form rest
1156         cru_writel(PLL_RESET_W_MSK | PLL_RESET_RESUME, PLL_CONS(pll_id, 3));
1157
1158         //wating lock state
1159         rk30_clock_udelay(ps->rst_dly);
1160         pll_wait_lock(pll_id);
1161
1162         if(new_aclk_div>=old_aclk_div) {
1163                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1164                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1165         }
1166
1167         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1168         if(old_aclk_div>new_aclk_div) {
1169                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
1170                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
1171         }
1172
1173         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
1174
1175         loops_per_jiffy = ps->lpj;
1176         smp_wmb();
1177
1178         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1179
1180         local_irq_restore(flags);
1181
1182         //gate gpll path
1183         // FIXME
1184         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1185         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1186
1187         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1188                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1189                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1190                         cru_readl(CRU_CLKSELS_CON(1)));
1191         return 0;
1192 }
1193
1194 /************************************pll clocks***************************/
1195
1196 static const struct apll_clk_set apll_clks[] = {
1197         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1198         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1199         _APLL_SET_CLKS(2208, 1, 92, 1, 8,       81, 81, 21, 41, 21),
1200         _APLL_SET_CLKS(2184, 1, 91, 1, 8,       81, 81, 21, 41, 21),
1201         _APLL_SET_CLKS(2160, 1, 90, 1, 8,       81, 81, 21, 41, 21),
1202         _APLL_SET_CLKS(2136, 1, 89, 1, 8,       81, 81, 21, 41, 21),
1203         _APLL_SET_CLKS(2112, 1, 88, 1, 8,       81, 81, 21, 41, 21),
1204         _APLL_SET_CLKS(2088, 1, 87, 1, 8,       81, 81, 21, 41, 21),
1205         _APLL_SET_CLKS(2064, 1, 86, 1, 8,       81, 81, 21, 41, 21),
1206         _APLL_SET_CLKS(2040, 1, 85, 1, 8,       81, 81, 21, 41, 21),
1207         _APLL_SET_CLKS(2016, 1, 84, 1, 8,       81, 81, 21, 41, 21),
1208         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1209         _APLL_SET_CLKS(1968, 1, 82, 1, 8,       81, 81, 21, 41, 21),
1210         _APLL_SET_CLKS(1944, 1, 81, 1, 8,       81, 81, 21, 41, 21),
1211         _APLL_SET_CLKS(1920, 1, 80, 1, 8,       81, 81, 21, 41, 21),
1212         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1213         _APLL_SET_CLKS(1872, 1, 78, 1, 8,       81, 81, 21, 41, 21),
1214         _APLL_SET_CLKS(1848, 1, 77, 1, 8,       81, 81, 21, 41, 21),
1215         _APLL_SET_CLKS(1824, 1, 76, 1, 8,       81, 81, 21, 41, 21),
1216         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1217         _APLL_SET_CLKS(1776, 1, 74, 1, 8,       81, 81, 21, 41, 21),
1218         _APLL_SET_CLKS(1752, 1, 73, 1, 8,       81, 81, 21, 41, 21),
1219         _APLL_SET_CLKS(1728, 1, 72, 1, 8,       81, 81, 21, 41, 21),
1220         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1221         _APLL_SET_CLKS(1680, 1, 70, 1, 8,       41, 41, 21, 41, 21),
1222         _APLL_SET_CLKS(1656, 1, 69, 1, 8,       41, 41, 21, 41, 21),
1223         _APLL_SET_CLKS(1632, 1, 68, 1, 8,       41, 41, 21, 41, 21),
1224         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1225         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1226         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1227         _APLL_SET_CLKS(1488, 1, 62, 1, 8,       41, 41, 21, 41, 21),
1228         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1229         _APLL_SET_CLKS(1440, 1, 60, 1, 8,       41, 41, 21, 41, 21),
1230         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1231         _APLL_SET_CLKS(1392, 1, 58, 1, 8,       41, 41, 21, 41, 21),
1232         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1233         _APLL_SET_CLKS(1344, 1, 56, 1, 8,       41, 41, 21, 41, 21),
1234         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1235         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1236         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1237         _APLL_SET_CLKS(1248, 1, 52, 1, 8,       41, 41, 21, 41, 21),
1238         _APLL_SET_CLKS(1224, 1, 51, 1, 8,       41, 41, 21, 41, 21),
1239         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1240         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1241         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1242         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1243         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1244         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1245         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1246         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1247         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1248         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1249         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1250         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1251         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1252         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1253         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1254         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1255         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1256         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1257         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1258
1259 };
1260 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1261 static struct clk arm_pll_clk = {
1262         .name           = "arm_pll",
1263         .parent         = &xin24m,
1264         .mode           = pll_clk_mode,
1265         .recalc         = plls_clk_recalc,
1266         .set_rate       = arm_pll_clk_set_rate,
1267         .round_rate     = arm_pll_clk_round_rate,
1268         .pll            = &apll_data,
1269 };
1270
1271 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1272 {
1273         /* do nothing here */
1274         return 0;
1275 }
1276 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1277 static struct clk ddr_pll_clk = {
1278         .name           = "ddr_pll",
1279         .parent         = &xin24m,
1280         .recalc         = plls_clk_recalc,
1281         .set_rate       = ddr_pll_clk_set_rate,
1282         .pll            = &dpll_data,
1283 };
1284
1285 static const struct pll_clk_set cpll_clks[] = {
1286         _PLL_SET_CLKS(360000, 1,  60,   4),
1287         _PLL_SET_CLKS(408000, 1,  68,   4),
1288         _PLL_SET_CLKS(456000, 1,  76,   4),
1289         _PLL_SET_CLKS(504000, 1,  84,   4),
1290         _PLL_SET_CLKS(552000, 1,  46,   2),
1291         _PLL_SET_CLKS(600000, 1,  50,   2),
1292         _PLL_SET_CLKS(742500, 8,  495,  2),
1293         _PLL_SET_CLKS(768000, 1,  64,   2),
1294         _PLL_SET_CLKS(798000, 2,  133,  2),
1295         _PLL_SET_CLKS(1188000, 2, 99,   1),
1296         _PLL_SET_CLKS(     0, 4,  133,  1),
1297 };
1298 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1299 static struct clk codec_pll_clk = {
1300         .name           = "codec_pll",
1301         .parent         = &xin24m,
1302         .mode           = pll_clk_mode,
1303         .recalc         = plls_clk_recalc,
1304         .set_rate       = cpll_clk_set_rate,
1305         .pll            = &cpll_data,
1306 };
1307
1308 static const struct pll_clk_set gpll_clks[] = {
1309         _PLL_SET_CLKS(148500,   2,      99,     8),
1310         _PLL_SET_CLKS(297000,   2,      198,    8),
1311         _PLL_SET_CLKS(300000,   1,      50,     4),
1312         _PLL_SET_CLKS(594000,   2,      198,    4),
1313         _PLL_SET_CLKS(891000,   8,      594,    2),
1314         _PLL_SET_CLKS(1188000,  2,      99,     1),
1315         _PLL_SET_CLKS(1200000,  1,      50,     1),
1316         _PLL_SET_CLKS(0,        0,       0,     0),
1317 };
1318 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1319 static struct clk general_pll_clk = {
1320         .name           = "general_pll",
1321         .parent         = &xin24m,
1322         .recalc         = plls_clk_recalc,
1323         .set_rate       = gpll_clk_set_rate,
1324         .pll            = &gpll_data
1325 };
1326 /********************************clocks***********************************/
1327 //GATE_CLK(ddr_gpll_path, general_pll_clk, DDR_GPLL);
1328 static struct clk clk_ddr_gpll_path = {
1329         .name           = "ddr_gpll_path",
1330         .parent         = &general_pll_clk,
1331         .recalc         = clksel_recalc_parent_rate,
1332         .gate_idx       = CLK_GATE_DDR_GPLL,
1333         .mode           = gate_mode,
1334 };
1335
1336 /* core and cpu setting */
1337 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1338 {
1339         CLKDATA_DBG("%s do nothing for ddr set rate\n", __func__);
1340         return 0;
1341 }
1342
1343 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1344 {
1345         CLKDATA_DBG("%s do nothing for ddr round rate\n", __func__);
1346         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1347 }
1348 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1349 {
1350         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1351         unsigned long rate = 0;
1352         clk->parent = clk->get_parent(clk);
1353         rate = clk->parent->recalc(clk->parent) >> shift;
1354         CLKDATA_DBG("%s new clock rate is %lu (shift %u), parent=%s, rate=%lu\n",
1355                         clk->name, rate, shift, clk->parent->name, clk->parent->rate);
1356         return rate;
1357 }
1358 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &clk_ddr_gpll_path};
1359 static struct clk clk_ddr = {
1360         .name           = "ddr",
1361         .parent         = &ddr_pll_clk,
1362         .get_parent     = clksel_get_parent,
1363         .set_parent     = clksel_set_parent,
1364         .recalc         = ddr_clk_recalc_rate,
1365         .set_rate       = ddr_clk_set_rate,
1366         .round_rate     = ddr_clk_round_rate,
1367         .gate_idx       = CLK_GATE_DDRPHY,
1368         .clksel_con     = CRU_CLKSELS_CON(26),
1369         CRU_DIV_SET(0x3, 0, 4),
1370         CRU_SRC_SET(1, 8),
1371         CRU_PARENTS_SET(clk_ddr_parents),
1372 };
1373 static int clk_core_set_rate(struct clk *c, unsigned long rate)
1374 {
1375         int ret;
1376
1377         ret = clk_set_rate_nolock(c->parent, rate);
1378         if (ret) {
1379                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1380                 return ret;
1381         }
1382         //set arm pll div 1
1383         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1384         return 0;
1385 }
1386 static unsigned long clk_core_get_rate(struct clk *c)
1387 {
1388         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1389         //c->parent->rate=c->parent->recalc(c->parent);
1390         return c->parent->rate / div;
1391 }
1392 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1393 {
1394         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1395         return clk_round_rate_nolock(clk->parent, rate) / div;
1396 }
1397
1398 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1399 {
1400
1401         u32 temp_div;
1402         struct clk *old_prt;
1403
1404         if(clk->parent == new_prt)
1405                 return 0;
1406         if (unlikely(!clk->parents))
1407                 return -EINVAL;
1408         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1409         //arm
1410         old_prt = clk->parent;
1411
1412         if(clk->parents[0] == new_prt) {
1413                 new_prt->set_rate(new_prt, 300 * MHZ);
1414                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1415         } else if(clk->parents[1] == new_prt) {
1416
1417                 if(new_prt->rate > old_prt->rate) {
1418                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1419                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1420                 }
1421                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1422                 new_prt->set_rate(new_prt, 300 * MHZ);
1423         } else
1424                 return -1;
1425
1426
1427         return 0;
1428
1429 }
1430
1431 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1432 {
1433         u32 temp_div;
1434         u32 old_aclk_div = 0, new_aclk_div;
1435         struct arm_clks_div_set *temp_clk_div;
1436         unsigned long arm_gpll_rate, arm_gpll_lpj;
1437         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1438         arm_gpll_rate = c->parent->rate / temp_div;
1439
1440         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1441         if(!temp_clk_div)
1442                 temp_clk_div = &arm_clk_div_tlb[4];
1443
1444         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1445         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1446         if(c->rate >= rate) {
1447                 arm_gpll_lpj = lpj_gpll / temp_div;
1448                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1449         }
1450
1451         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1452         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1453                         CRU_CLKSELS_CON(0));
1454         if((c->rate < rate)) {
1455                 arm_gpll_lpj = lpj_gpll / temp_div;
1456                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1457         }
1458         return 0;
1459 }
1460 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1461 {
1462         return c->parent->rate;
1463 }
1464 static struct clk clk_core_gpll_path = {
1465         .name           = "cpu_gpll_path",
1466         .parent         = &general_pll_clk,
1467         .recalc         = arm_core_gpll_clk_get_rate,
1468         .set_rate       = core_gpll_clk_set_rate,
1469         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1470 };
1471
1472
1473 static struct clk *clk_core_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1474
1475 static struct clk clk_core = {
1476         .name           = "core",
1477         .parent         = &arm_pll_clk,
1478         .set_rate       = clk_core_set_rate,
1479         .recalc         = clk_core_get_rate,
1480         .round_rate     = core_clk_round_rate,
1481         .set_parent     = core_clksel_set_parent,
1482         .clksel_con     = CRU_CLKSELS_CON(0),
1483         CRU_DIV_SET(0x1f, 9, 32),
1484         CRU_SRC_SET(1, 8),
1485         CRU_PARENTS_SET(clk_core_parents),
1486 };
1487 GATE_CLK(l2c, clk_core, CLK_L2C);
1488 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1489 static unsigned long aclk_recalc(struct clk *clk)
1490 {
1491         unsigned long rate;
1492         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1493
1494         BUG_ON(div > 5);
1495         if (div >= 5)
1496                 div = 8;
1497         rate = clk->parent->rate / div;
1498         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1499
1500         return rate;
1501 };
1502 static struct clk core_periph = {
1503         .name           = "core_periph",
1504         .parent         = &clk_core,
1505         .gate_idx       = CLK_GATE_CORE_PERIPH,
1506         .recalc         = clksel_recalc_shift_2,
1507         .clksel_con     = CRU_CLKSELS_CON(0),
1508         CRU_DIV_SET(0x3, 6, 16),
1509 };
1510 static struct clk aclk_core = {
1511         .name           = "aclk_core",
1512         .parent         = &clk_core,
1513         .gate_idx       = CLK_GATE_ACLK_CORE,
1514         .recalc         = aclk_recalc,
1515         .clksel_con     = CRU_CLKSELS_CON(1),
1516         CRU_DIV_SET(0x7, 3, 8),
1517 };
1518
1519 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1520 static struct clk clk_cpu_div = {
1521         .name           = "cpu_div",
1522         .parent         = &arm_pll_clk,
1523         .set_rate       = clksel_set_rate_freediv,
1524         .recalc         = clksel_recalc_div,
1525         .clksel_con     = CRU_CLKSELS_CON(0),
1526         CRU_DIV_SET(0x1f, 0, 32),
1527         CRU_SRC_SET(1, 5),
1528         CRU_PARENTS_SET(clk_cpu_div_parents),
1529 };
1530
1531 static struct clk aclk_cpu = {
1532         .name           = "aclk_cpu",
1533         .parent         = &clk_cpu_div,
1534         .gate_idx       = CLK_GATE_ACLK_CPU,
1535 };
1536
1537 static struct clk hclk_cpu = {
1538         .name           = "hclk_cpu",
1539         .parent         = &aclk_cpu,
1540         .gate_idx       = CLK_GATE_HCLK_CPU,
1541         .recalc         = clksel_recalc_shift,
1542         .set_rate       = clksel_set_rate_shift,
1543         .clksel_con     = CRU_CLKSELS_CON(1),
1544         CRU_DIV_SET(0x3, 8, 4),
1545
1546 };
1547
1548 static struct clk pclk_cpu = {
1549         .name           = "pclk_cpu",
1550         .parent         = &aclk_cpu,
1551         .gate_idx       = CLK_GATE_PCLK_CPU,
1552         .recalc         = clksel_recalc_shift,
1553         .set_rate       = clksel_set_rate_shift,
1554         .clksel_con     = CRU_CLKSELS_CON(1),
1555         CRU_DIV_SET(0x3, 12, 8),
1556 };
1557
1558 static struct clk ahb2apb_cpu = {
1559         .name           = "ahb2apb",
1560         .parent         = &hclk_cpu,
1561         .recalc         = clksel_recalc_shift,
1562         .set_rate       = clksel_set_rate_shift,
1563         .clksel_con     = CRU_CLKSELS_CON(1),
1564         CRU_DIV_SET(0x3, 14, 4),
1565 };
1566
1567
1568 static struct clk atclk_cpu = {
1569         .name           = "atclk_cpu",
1570         .parent         = &pclk_cpu,
1571         .gate_idx       = CLK_GATE_ATCLK_CPU,
1572 };
1573
1574 /* GPU setting */
1575 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1576 {
1577         unsigned long max_rate = rate / 100 * 105;      /* +5% */
1578         return clkset_rate_freediv_autosel_parents(clk, max_rate);
1579 };
1580
1581 static struct clk *aclk_gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1582
1583 static struct clk aclk_gpu = {
1584         .name           = "aclk_gpu",
1585         .mode           = gate_mode,
1586         .recalc         = clksel_recalc_div,
1587         .round_rate     = clk_freediv_round_autosel_parents_rate,
1588         .set_rate       = clkset_rate_freediv_autosel_parents,
1589         .clksel_con     = CRU_CLKSELS_CON(34),
1590         .gate_idx       = CLK_GATE_ACLK_GPU,
1591         CRU_DIV_SET(0x1f, 0, 32),
1592         CRU_SRC_SET(0x1, 7),
1593         CRU_PARENTS_SET(aclk_gpu_parents),
1594 };
1595
1596 /* vcodec setting */
1597 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1598 {
1599         unsigned long rate = clk->parent->rate / 4;
1600         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1601         return rate;
1602 }
1603
1604 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1605
1606 static struct clk aclk_vepu = {
1607         .name           = "aclk_vepu",
1608         .parent         = &codec_pll_clk,
1609         .mode           = gate_mode,
1610         .recalc         = clksel_recalc_div,
1611         .set_rate       = clkset_rate_freediv_autosel_parents,
1612         .clksel_con     = CRU_CLKSELS_CON(32),
1613         .gate_idx       = CLK_GATE_ACLK_VEPU,
1614         CRU_DIV_SET(0x1f, 0, 32),
1615         CRU_SRC_SET(0x1, 7),
1616         CRU_PARENTS_SET(aclk_vepu_parents),
1617 };
1618
1619 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1620
1621 static struct clk aclk_vdpu = {
1622         .name           = "aclk_vdpu",
1623         .mode           = gate_mode,
1624         .recalc         = clksel_recalc_div,
1625         .set_rate       = clkset_rate_freediv_autosel_parents,
1626         .clksel_con     = CRU_CLKSELS_CON(32),
1627         .gate_idx       = CLK_GATE_ACLK_VDPU,
1628         CRU_DIV_SET(0x1f, 8, 32),
1629         CRU_SRC_SET(0x1, 15),
1630         CRU_PARENTS_SET(aclk_vdpu_parents),
1631 };
1632 static struct clk hclk_vepu = {
1633         .name           = "hclk_vepu",
1634         .parent         = &aclk_vepu,
1635         .mode           = gate_mode,
1636         .recalc         = clksel_recalc_vpu_hclk,
1637         .gate_idx       = CLK_GATE_HCLK_VEPU,
1638 };
1639
1640 static struct clk hclk_vdpu = {
1641         .name           = "hclk_vdpu",
1642         .parent         = &aclk_vdpu,
1643         .mode           = gate_mode,
1644         .recalc         = clksel_recalc_vpu_hclk,
1645         .gate_idx       = CLK_GATE_HCLK_VDPU,
1646 };
1647
1648 /* aclk lcdc setting */
1649 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1650
1651 static struct clk aclk_lcdc0_pre = {
1652         .name           = "aclk_lcdc0_pre",
1653         .parent         = &codec_pll_clk,
1654         .mode           = gate_mode,
1655         .recalc         = clksel_recalc_div,
1656         .set_rate       = clkset_rate_freediv_autosel_parents,
1657         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1658         .clksel_con     = CRU_CLKSELS_CON(31),
1659         CRU_DIV_SET(0x1f, 0, 32),
1660         CRU_SRC_SET(0x1, 7),
1661         CRU_PARENTS_SET(aclk_lcdc0_parents),
1662 };
1663
1664 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1665
1666 static struct clk aclk_lcdc1_pre = {
1667         .name           = "aclk_lcdc1_pre",
1668         .parent         = &codec_pll_clk,
1669         .mode           = gate_mode,
1670         .recalc         = clksel_recalc_div,
1671         .set_rate       = clkset_rate_freediv_autosel_parents,
1672         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1673         .clksel_con     = CRU_CLKSELS_CON(31),
1674         CRU_DIV_SET(0x1f, 8, 32),
1675         CRU_SRC_SET(0x1, 15),
1676         CRU_PARENTS_SET(aclk_lcdc1_parents),
1677 };
1678
1679 /* aclk/hclk/pclk periph setting */
1680 static struct clk *aclk_periph_parents[2] = {&codec_pll_clk, &general_pll_clk};
1681
1682 static struct clk aclk_periph = {
1683         .name           = "aclk_periph",
1684         .parent         = &general_pll_clk,
1685         .mode           = gate_mode,
1686         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1687         .recalc         = clksel_recalc_div,
1688         .set_rate       = clksel_set_rate_freediv,
1689         .clksel_con     = CRU_CLKSELS_CON(10),
1690         CRU_DIV_SET(0x1f, 0, 32),
1691         CRU_SRC_SET(1, 15),
1692         CRU_PARENTS_SET(aclk_periph_parents),
1693 };
1694 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1695
1696 static struct clk pclk_periph = {
1697         .name           = "pclk_periph",
1698         .parent         = &aclk_periph,
1699         .mode           = gate_mode,
1700         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1701         .recalc         = clksel_recalc_shift,
1702         .set_rate       = clksel_set_rate_shift,
1703         .clksel_con     = CRU_CLKSELS_CON(10),
1704         CRU_DIV_SET(0x3, 12, 8),
1705 };
1706
1707 static struct clk hclk_periph = {
1708         .name           = "hclk_periph",
1709         .parent         = &aclk_periph,
1710         .mode           = gate_mode,
1711         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1712         .recalc         = clksel_recalc_shift,
1713         .set_rate       = clksel_set_rate_shift,
1714         .clksel_con     = CRU_CLKSELS_CON(10),
1715         CRU_DIV_SET(0x3, 8, 4),
1716 };
1717 /* dclk lcdc setting */
1718 // FIXME
1719 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1720 {
1721         u32 div, old_div;
1722         int i;
1723         unsigned long new_rate;
1724         int ret = 0;
1725
1726         if(clk->rate == rate)
1727                 return 0;
1728         for(i = 0; i < 2; i++) {
1729                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1730                 new_rate = clk->parents[i]->rate / div;
1731                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1732                         break;
1733                 }
1734         }
1735         if(i >= 2) {
1736                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1737                 return -1;
1738         }
1739
1740         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1741
1742         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1743                         clk->div_shift, clk->div_mask) + 1;
1744         if(div > old_div)
1745                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1746
1747         if(clk->parents[i] != clk->parent) {
1748                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1749         }
1750
1751         if (ret) {
1752                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1753                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1754                 return ret;
1755         }
1756         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1757         return 0;
1758 }
1759
1760 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1761 {
1762         if (rate == 27 * MHZ)
1763                 return clkset_rate_freediv_autosel_parents(clk, rate);
1764         else
1765                 return clkset_rate_evendiv_autosel_parents(clk, rate);
1766
1767 #if 0
1768         int ret = 0;
1769         struct clk *parent;
1770         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1771                 parent = clk->parents[1];
1772                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1773         } else {
1774                 parent = clk->parents[0];
1775         }
1776         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1777         //clk->name,rate,parent->name,clk->parent->name);
1778
1779         if(parent != clk->parents[1]) {
1780                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1781                 if (ret) {
1782                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1783                         return ret;
1784                 }
1785         }
1786         if (clk->parent != parent) {
1787                 ret = clk_set_parent_nolock(clk, parent);
1788                 if (ret) {
1789                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1790                         return ret;
1791                 }
1792         }
1793         return ret;
1794 #endif
1795 }
1796
1797 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1798 static struct clk dclk_lcdc0 = {
1799         .name           = "dclk_lcdc0",
1800         .mode           = gate_mode,
1801         .set_rate       = dclk_lcdc_set_rate,
1802         .recalc         = clksel_recalc_div,
1803         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1804         .clksel_con     = CRU_CLKSELS_CON(27),
1805         CRU_SRC_SET(0x1, 0),
1806         CRU_DIV_SET(0xff, 8, 256),
1807         CRU_PARENTS_SET(dclk_lcdc0_parents),
1808 };
1809
1810 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1811 static struct clk dclk_lcdc1 = {
1812         .name           = "dclk_lcdc1",
1813         .mode           = gate_mode,
1814         .set_rate       = dclk_lcdc_set_rate,
1815         .recalc         = clksel_recalc_div,
1816         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1817         .clksel_con     = CRU_CLKSELS_CON(28),
1818         CRU_SRC_SET(0x1, 0),
1819         CRU_DIV_SET(0xff, 8, 256),
1820         CRU_PARENTS_SET(dclk_lcdc1_parents),
1821 };
1822
1823 /* cif setting */
1824 // FIXME
1825 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1826 static struct clk cif_out_pll = {
1827         .name           = "cif_out_pll",
1828         .parent         = &general_pll_clk,
1829         .clksel_con     = CRU_CLKSELS_CON(29),
1830         CRU_SRC_SET(0x1, 0),
1831         CRU_PARENTS_SET(cifout_sel_pll_parents),
1832 };
1833
1834 static struct clk cif0_out_div = {
1835         .name           = "cif0_out_div",
1836         .parent         = &cif_out_pll,
1837         .mode           = gate_mode,
1838         .recalc         = clksel_recalc_div,
1839         .set_rate       = clksel_set_rate_freediv,
1840         .gate_idx       = CLK_GATE_CIF0_OUT,
1841         .clksel_con     = CRU_CLKSELS_CON(29),
1842         CRU_DIV_SET(0x1f, 1, 32),
1843 };
1844
1845 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1846 {
1847         int ret = 0;
1848         struct clk *parent;
1849
1850         if (rate == 24 * MHZ) {
1851                 parent = clk->parents[1];
1852         } else {
1853                 parent = clk->parents[0];
1854                 ret = clk_set_rate_nolock(parent, rate);
1855                 if (ret)
1856                         return ret;
1857         }
1858         if (clk->parent != parent)
1859                 ret = clk_set_parent_nolock(clk, parent);
1860
1861         return ret;
1862 }
1863
1864 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1865 static struct clk cif0_out = {
1866         .name           = "cif0_out",
1867         .parent         = &cif0_out_div,
1868         .set_rate       = cif_out_set_rate,
1869         .clksel_con     = CRU_CLKSELS_CON(29),
1870         CRU_SRC_SET(0x1, 7),
1871         CRU_PARENTS_SET(cif0_out_parents),
1872 };
1873
1874 static struct clk pclkin_cif0 = {
1875         .name           = "pclkin_cif0",
1876         .mode           = gate_mode,
1877         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1878 };
1879
1880 static struct clk inv_cif0 = {
1881         .name           = "inv_cif0",
1882         .parent         = &pclkin_cif0,
1883 };
1884
1885 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1886 static struct clk cif0_in = {
1887         .name           = "cif0_in",
1888         .parent         = &pclkin_cif0,
1889         .clksel_con     = CRU_CLKSELS_CON(30),
1890         CRU_SRC_SET(0x1, 8),
1891         CRU_PARENTS_SET(cif0_in_parents),
1892 };
1893
1894 /* i2s/spdif setting */
1895 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1896 static struct clk clk_i2s_pll = {
1897         .name           = "i2s_pll",
1898         .parent         = &general_pll_clk,
1899         .clksel_con     = CRU_CLKSELS_CON(2),
1900         CRU_SRC_SET(0x1, 15),
1901         CRU_PARENTS_SET(clk_i2s_div_parents),
1902 };
1903
1904 static struct clk clk_i2s0_div = {
1905         .name           = "i2s0_div",
1906         .parent         = &clk_i2s_pll,
1907         .mode           = gate_mode,
1908         .recalc         = clksel_recalc_div,
1909         .set_rate       = clksel_set_rate_freediv,
1910         .round_rate     = clksel_freediv_round_rate,
1911         .gate_idx       = CLK_GATE_I2S0_SRC,
1912         .clksel_con     = CRU_CLKSELS_CON(3),
1913         CRU_DIV_SET(0x7f, 0, 64),
1914 };
1915
1916 static struct clk clk_spdif_div = {
1917         .name           = "spdif_div",
1918         .parent         = &clk_i2s_pll,
1919         .recalc         = clksel_recalc_div,
1920         .set_rate       = clksel_set_rate_freediv,
1921         .round_rate     = clksel_freediv_round_rate,
1922         .mode           = gate_mode,
1923         .gate_idx       = CLK_GATE_SPDIF_SRC,
1924         .clksel_con     = CRU_CLKSELS_CON(5),
1925         CRU_DIV_SET(0x7f, 0, 64),
1926 };
1927 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1928 {
1929         u32 numerator, denominator;
1930         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1931         //clk->parent->parent
1932         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1933                                 &numerator, &denominator) == 0) {
1934                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1935                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1936                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1937         } else {
1938                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1939                 return -ENOENT;
1940         }
1941         return 0;
1942 }
1943
1944 static struct clk clk_i2s0_frac_div = {
1945         .name           = "i2s0_frac_div",
1946         .parent         = &clk_i2s0_div,
1947         .mode           = gate_mode,
1948         .gate_idx       = CLK_GATE_I2S0_FRAC,
1949         .recalc         = clksel_recalc_frac,
1950         .set_rate       = clk_i2s_fracdiv_set_rate,
1951         .clksel_con     = CRU_CLKSELS_CON(7),
1952 };
1953
1954 static struct clk clk_spdif_frac_div = {
1955         .name           = "spdif_frac_div",
1956         .parent         = &clk_spdif_div,
1957         .mode           = gate_mode,
1958         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1959         .recalc         = clksel_recalc_frac,
1960         .set_rate       = clk_i2s_fracdiv_set_rate,
1961         .clksel_con     = CRU_CLKSELS_CON(9),
1962 };
1963
1964 #define I2S_SRC_DIV     (0x0)
1965 #define I2S_SRC_FRAC    (0x1)
1966 #define I2S_SRC_12M     (0x2)
1967
1968 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1969 {
1970         int ret = -EINVAL;
1971         struct clk *parent;
1972
1973         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1974                 parent = clk->parents[I2S_SRC_12M];
1975         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1976                 parent = clk->parents[I2S_SRC_DIV];
1977         } else {
1978                 parent = clk->parents[I2S_SRC_FRAC];
1979         }
1980
1981         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1982                         clk->name, rate, parent->name, clk->parent->name);
1983
1984         if(parent != clk->parents[I2S_SRC_12M]) {
1985                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1986                 if (ret) {
1987                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1988                         return ret;
1989                 }
1990         }
1991
1992         if (clk->parent != parent) {
1993                 ret = clk_set_parent_nolock(clk, parent);
1994                 if (ret) {
1995                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1996                         return ret;
1997                 }
1998         }
1999
2000         return ret;
2001 };
2002
2003 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
2004
2005 static struct clk clk_i2s0 = {
2006         .name           = "i2s0",
2007         .set_rate       = i2s_set_rate,
2008         .clksel_con     = CRU_CLKSELS_CON(3),
2009         CRU_SRC_SET(0x3, 8),
2010         CRU_PARENTS_SET(clk_i2s0_parents),
2011 };
2012
2013 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
2014
2015 static struct clk clk_spdif = {
2016         .name           = "spdif",
2017         .parent         = &clk_spdif_frac_div,
2018         .set_rate       = i2s_set_rate,
2019         .clksel_con = CRU_CLKSELS_CON(5),
2020         CRU_SRC_SET(0x3, 8),
2021         CRU_PARENTS_SET(clk_spdif_parents),
2022 };
2023
2024 /* otgphy setting */
2025 GATE_CLK(otgphy0, xin24m, OTGPHY0);
2026 GATE_CLK(otgphy1, xin24m, OTGPHY1);
2027
2028 static struct clk clk_otgphy0_480m = {
2029         .name           = "otgphy0_480m",
2030         .parent         = &clk_otgphy0,
2031 };
2032 static struct clk clk_otgphy1_480m = {
2033         .name           = "otgphy1_480m",
2034         .parent         = &clk_otgphy1,
2035 };
2036
2037 /* hsicphy setting */
2038 #ifdef ARCH_RK31
2039 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
2040 static struct clk clk_hsicphy_480m = {
2041         .name           = "hsicphy_480m",
2042         .parent         = &clk_otgphy0_480m,
2043         .clksel_con      = CRU_CLKSELS_CON(30),
2044         CRU_SRC_SET(0x3, 0),
2045         CRU_PARENTS_SET(clk_hsicphy_parents),
2046 };
2047 static struct clk clk_hsicphy_12m = {
2048         .name           = "hsicphy_12m",
2049         .parent         = &clk_hsicphy_480m,
2050         .clksel_con     = CRU_CLKSELS_CON(11),
2051         CRU_DIV_SET(0x3f, 8, 64),
2052 };
2053 #endif
2054
2055 /* mac and rmii setting */
2056 // FIXME
2057 static struct clk rmii_clkin = {
2058         .name           = "rmii_clkin",
2059 };
2060 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
2061 static struct clk clk_mac_pll_div = {
2062         .name           = "mac_pll_div",
2063         .parent         = &general_pll_clk,
2064         .mode           = gate_mode,
2065         .gate_idx       = CLK_GATE_MAC_SRC,
2066         .recalc         = clksel_recalc_div,
2067         .set_rate       = clksel_set_rate_freediv,
2068         .clksel_con     = CRU_CLKSELS_CON(21),
2069         CRU_DIV_SET(0x1f, 8, 32),
2070         CRU_SRC_SET(0x1, 0),
2071         CRU_PARENTS_SET(clk_mac_ref_div_parents),
2072 };
2073
2074 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
2075 {
2076         if(clk->parent == clk->parents[1]) {
2077                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
2078                 return -ENOENT;
2079         } else if(clk->parent == clk->parents[0]) {
2080                 return clk_set_rate_nolock(clk->parents[0], rate);
2081         }
2082         return -ENOENT;
2083 }
2084
2085 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
2086
2087 static struct clk clk_mac_ref = {
2088         .name           = "mac_ref",
2089         .parent         = &clk_mac_pll_div,
2090         .set_rate       = clksel_mac_ref_set_rate,
2091         .clksel_con     = CRU_CLKSELS_CON(21),
2092         CRU_SRC_SET(0x1, 4),
2093         CRU_PARENTS_SET(clk_mac_ref_parents),
2094 };
2095
2096 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
2097 {
2098         return clk_set_parent_nolock(clk->parent, parent);
2099 }
2100
2101 static struct clk clk_mii_tx = {
2102         .name           = "mii_tx",
2103         .parent         = &clk_mac_ref,
2104         //.set_parent   = clk_set_mii_tx_parent,
2105         .mode           = gate_mode,
2106         .gate_idx       = CLK_GATE_MAC_LBTEST,
2107 };
2108
2109 /* hsadc and saradc */
2110 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
2111 static struct clk clk_hsadc_pll_div = {
2112         .name           = "hsadc_pll_div",
2113         .parent         = &general_pll_clk,
2114         .mode           = gate_mode,
2115         .gate_idx       = CLK_GATE_HSADC_SRC,
2116         .recalc         = clksel_recalc_div,
2117         .round_rate     = clk_freediv_round_autosel_parents_rate,
2118         .set_rate       = clkset_rate_freediv_autosel_parents,
2119         //.round_rate   = clksel_freediv_round_rate,
2120         //.set_rate     = clksel_set_rate_freediv,
2121         .clksel_con = CRU_CLKSELS_CON(22),
2122         CRU_DIV_SET(0xff, 8, 256),
2123         CRU_SRC_SET(0x1, 0),
2124         CRU_PARENTS_SET(clk_hsadc_pll_parents),
2125 };
2126 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2127 {
2128         u32 numerator, denominator;
2129         //        clk_hsadc_pll_div->gpll/cpll
2130         //clk->parent->parent
2131         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2132                                 &numerator, &denominator) == 0) {
2133                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2134
2135                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2136
2137                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2138         } else {
2139                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2140                 return -ENOENT;
2141         }
2142         return 0;
2143 }
2144 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2145 {
2146         u32 numerator, denominator;
2147         u32 i, ret = 0;
2148         //        clk_hsadc_pll_div->gpll/cpll
2149         //clk->parent->parent
2150         for(i = 0; i < 2; i++) {
2151                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2152                                         &numerator, &denominator) == 0)
2153                         break;
2154         }
2155         if(i >= 2)
2156                 return -ENOENT;
2157
2158         if(clk->parent->parent != clk->parent->parents[i])
2159                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2160         if(ret == 0) {
2161                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2162
2163                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2164
2165                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2166         } else {
2167                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2168                 return -ENOENT;
2169         }
2170         return 0;
2171 }
2172
2173 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2174 {
2175         u32 numerator, denominator;
2176
2177         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2178         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2179                                 &numerator, &denominator) == 0)
2180                 return rate;
2181
2182         return 0;
2183 }
2184 static struct clk clk_hsadc_frac_div = {
2185         .name           = "hsadc_frac_div",
2186         .parent         = &clk_hsadc_pll_div,
2187         .mode           = gate_mode,
2188         .recalc         = clksel_recalc_frac,
2189         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2190         .round_rate     = clk_hsadc_fracdiv_round_rate,
2191         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
2192         .clksel_con     = CRU_CLKSELS_CON(23),
2193 };
2194
2195 #define HSADC_SRC_DIV 0x0
2196 #define HSADC_SRC_FRAC 0x1
2197 #define HSADC_SRC_EXT 0x2
2198 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2199 {
2200         int ret = -EINVAL;
2201         struct clk *parent;
2202
2203         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2204                 CLKDATA_DBG("hsadc clk is form ext\n");
2205                 return 0;
2206         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2207                 parent = clk->parents[HSADC_SRC_DIV];
2208         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2209                 parent = clk->parents[HSADC_SRC_FRAC];
2210         } else
2211                 parent = clk->parents[HSADC_SRC_DIV];
2212
2213         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2214                         clk->name, rate, parent->name, clk->parent->name);
2215
2216         ret = clk_set_rate_nolock(parent, rate);
2217         if (ret) {
2218                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2219                 return ret;
2220         }
2221         if (clk->parent != parent) {
2222                 ret = clk_set_parent_nolock(clk, parent);
2223                 if (ret) {
2224                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2225                         return ret;
2226                 }
2227         }
2228         return ret;
2229 }
2230
2231 static struct clk clk_hsadc_ext = {
2232         .name           = "hsadc_ext",
2233 };
2234
2235 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2236 static struct clk clk_hsadc_out = {
2237         .name           = "hsadc_out",
2238         .parent         = &clk_hsadc_pll_div,
2239         .set_rate       = clk_hsadc_set_rate,
2240         .clksel_con     = CRU_CLKSELS_CON(22),
2241         CRU_SRC_SET(0x3, 4),
2242         CRU_PARENTS_SET(clk_hsadc_out_parents),
2243 };
2244 static struct clk clk_hsadc_out_inv = {
2245         .name           = "hsadc_out_inv",
2246         .parent         = &clk_hsadc_out,
2247 };
2248
2249 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2250 static struct clk clk_hsadc = {
2251         .name           = "hsadc",
2252         .parent         = &clk_hsadc_out,
2253         .clksel_con     = CRU_CLKSELS_CON(22),
2254         CRU_SRC_SET(0x1, 7),
2255         CRU_PARENTS_SET(clk_hsadc_parents),
2256 };
2257
2258 static struct clk clk_saradc = {
2259         .name           = "saradc",
2260         .parent         = &xin24m,
2261         .mode           = gate_mode,
2262         .recalc         = clksel_recalc_div,
2263         .set_rate       = clksel_set_rate_freediv,
2264         .gate_idx       = CLK_GATE_SARADC_SRC,
2265         .clksel_con     = CRU_CLKSELS_CON(24),
2266         CRU_DIV_SET(0xff, 8, 256),
2267 };
2268
2269 /* smc setting */
2270 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2271 static struct clk clkn_smc = {
2272         .name           = "smc_inv",
2273         .parent         = &clk_smc,
2274 };
2275
2276 /* spi setting */
2277 static struct clk clk_spi0 = {
2278         .name           = "spi0",
2279         .parent         = &pclk_periph,
2280         .mode           = gate_mode,
2281         .recalc         = clksel_recalc_div,
2282         .set_rate       = clksel_set_rate_freediv,
2283         .gate_idx       = CLK_GATE_SPI0_SRC,
2284         .clksel_con     = CRU_CLKSELS_CON(25),
2285         CRU_DIV_SET(0x7f, 0, 128),
2286 };
2287
2288 static struct clk clk_spi1 = {
2289         .name           = "spi1",
2290         .parent         = &pclk_periph,
2291         .mode           = gate_mode,
2292         .recalc         = clksel_recalc_div,
2293         .set_rate       = clksel_set_rate_freediv,
2294         .gate_idx       = CLK_GATE_SPI1_SRC,
2295         .clksel_con     = CRU_CLKSELS_CON(25),
2296         CRU_DIV_SET(0x7f, 8, 128),
2297 };
2298
2299 /* sdmmc/sdio/emmc setting */
2300 static struct clk clk_sdmmc = {
2301         .name           = "sdmmc",
2302         .parent         = &hclk_periph,
2303         .mode           = gate_mode,
2304         .recalc         = clksel_recalc_div,
2305         .set_rate       = clksel_set_rate_even,
2306         .gate_idx       = CLK_GATE_MMC0_SRC,
2307         .clksel_con     = CRU_CLKSELS_CON(11),
2308         CRU_DIV_SET(0x3f, 0, 64),
2309 };
2310
2311 static struct clk clk_sdio = {
2312         .name           = "sdio",
2313         .parent         = &hclk_periph,
2314         .mode           = gate_mode,
2315         .recalc         = clksel_recalc_div,
2316         .set_rate       = clksel_set_rate_even,
2317         .gate_idx       = CLK_GATE_SDIO_SRC,
2318         .clksel_con     = CRU_CLKSELS_CON(12),
2319         CRU_DIV_SET(0x3f, 0, 64),
2320
2321 };
2322
2323 static struct clk clk_emmc = {
2324         .name           = "emmc",
2325         .parent         = &hclk_periph,
2326         .mode           = gate_mode,
2327         .recalc         = clksel_recalc_div,
2328         .set_rate       = clksel_set_rate_freediv,
2329         .gate_idx       = CLK_GATE_EMMC_SRC,
2330         .clksel_con     = CRU_CLKSELS_CON(12),
2331         CRU_DIV_SET(0x3f, 8, 64),
2332 };
2333
2334 /* uart setting */
2335 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2336 static struct clk clk_uart_pll = {
2337         .name           = "uart_pll",
2338         .parent         = &general_pll_clk,
2339         .clksel_con     = CRU_CLKSELS_CON(12),
2340         CRU_SRC_SET(0x1, 15),
2341         CRU_PARENTS_SET(clk_uart_src_parents),
2342 };
2343 static struct clk clk_uart0_div = {
2344         .name           = "uart0_div",
2345         .parent         = &clk_uart_pll,
2346         .mode           = gate_mode,
2347         .gate_idx       = CLK_GATE_UART0_SRC,
2348         .recalc         = clksel_recalc_div,
2349         .set_rate       = clksel_set_rate_freediv,
2350         .round_rate     = clksel_freediv_round_rate,
2351         .clksel_con     = CRU_CLKSELS_CON(13),
2352         CRU_DIV_SET(0x7f, 0, 64),
2353 };
2354 static struct clk clk_uart1_div = {
2355         .name           = "uart1_div",
2356         .parent         = &clk_uart_pll,
2357         .mode           = gate_mode,
2358         .gate_idx       = CLK_GATE_UART1_SRC,
2359         .recalc         = clksel_recalc_div,
2360         .round_rate     = clksel_freediv_round_rate,
2361         .set_rate       = clksel_set_rate_freediv,
2362         .clksel_con     = CRU_CLKSELS_CON(14),
2363         CRU_DIV_SET(0x7f, 0, 64),
2364 };
2365
2366 static struct clk clk_uart2_div = {
2367         .name           = "uart2_div",
2368         .parent         = &clk_uart_pll,
2369         .mode           = gate_mode,
2370         .gate_idx       = CLK_GATE_UART2_SRC,
2371         .recalc         = clksel_recalc_div,
2372         .round_rate     = clksel_freediv_round_rate,
2373         .set_rate       = clksel_set_rate_freediv,
2374         .clksel_con     = CRU_CLKSELS_CON(15),
2375         CRU_DIV_SET(0x7f, 0, 64),
2376 };
2377
2378 static struct clk clk_uart3_div = {
2379         .name           = "uart3_div",
2380         .parent         = &clk_uart_pll,
2381         .mode           = gate_mode,
2382         .gate_idx       = CLK_GATE_UART3_SRC,
2383         .recalc         = clksel_recalc_div,
2384         .round_rate     = clksel_freediv_round_rate,
2385         .set_rate       = clksel_set_rate_freediv,
2386         .clksel_con     = CRU_CLKSELS_CON(16),
2387         CRU_DIV_SET(0x7f, 0, 64),
2388 };
2389 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2390 {
2391         u32 numerator, denominator;
2392         //clk_uart0_div->clk_uart_pll->gpll/cpll
2393         //clk->parent->parent
2394         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2395                                 &numerator, &denominator) == 0) {
2396                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2397
2398                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2399
2400                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2401         } else {
2402                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2403                 return -ENOENT;
2404         }
2405         return 0;
2406 }
2407
2408 static struct clk clk_uart0_frac_div = {
2409         .name           = "uart0_frac_div",
2410         .parent         = &clk_uart0_div,
2411         .mode           = gate_mode,
2412         .recalc         = clksel_recalc_frac,
2413         .set_rate       = clk_uart_fracdiv_set_rate,
2414         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2415         .clksel_con     = CRU_CLKSELS_CON(17),
2416 };
2417 static struct clk clk_uart1_frac_div = {
2418         .name           = "uart1_frac_div",
2419         .parent         = &clk_uart1_div,
2420         .mode           = gate_mode,
2421         .recalc         = clksel_recalc_frac,
2422         .set_rate       = clk_uart_fracdiv_set_rate,
2423         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2424         .clksel_con     = CRU_CLKSELS_CON(18),
2425 };
2426 static struct clk clk_uart2_frac_div = {
2427         .name           = "uart2_frac_div",
2428         .mode           = gate_mode,
2429         .parent         = &clk_uart2_div,
2430         .recalc         = clksel_recalc_frac,
2431         .set_rate       = clk_uart_fracdiv_set_rate,
2432         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2433         .clksel_con     = CRU_CLKSELS_CON(19),
2434 };
2435 static struct clk clk_uart3_frac_div = {
2436         .name           = "uart3_frac_div",
2437         .parent         = &clk_uart3_div,
2438         .mode           = gate_mode,
2439         .recalc         = clksel_recalc_frac,
2440         .set_rate       = clk_uart_fracdiv_set_rate,
2441         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2442         .clksel_con     = CRU_CLKSELS_CON(20),
2443 };
2444
2445 #define UART_SRC_DIV 0
2446 #define UART_SRC_FRAC 1
2447 #define UART_SRC_24M 2
2448
2449 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2450 {
2451         int ret = 0;
2452         struct clk *parent;
2453
2454         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2455                 parent = clk->parents[UART_SRC_24M];
2456         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2457                 parent = clk->parents[UART_SRC_DIV];
2458         } else {
2459                 parent = clk->parents[UART_SRC_FRAC];
2460         }
2461
2462         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2463                         clk->name, rate, parent->name, clk->parent->name);
2464
2465         if(parent != clk->parents[UART_SRC_24M]) {
2466                 ret = clk_set_rate_nolock(parent, rate);
2467                 if (ret) {
2468                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2469                         return ret;
2470                 }
2471         }
2472
2473         if (clk->parent != parent) {
2474                 ret = clk_set_parent_nolock(clk, parent);
2475                 if (ret) {
2476                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2477                         return ret;
2478                 }
2479         }
2480
2481         return ret;
2482 }
2483
2484 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2485 static struct clk clk_uart0 = {
2486         .name           = "uart0",
2487         .set_rate       = clk_uart_set_rate,
2488         .clksel_con     = CRU_CLKSELS_CON(13),
2489         CRU_SRC_SET(0x3, 8),
2490         CRU_PARENTS_SET(clk_uart0_parents),
2491 };
2492
2493 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2494 static struct clk clk_uart1 = {
2495         .name           = "uart1",
2496         .set_rate       = clk_uart_set_rate,
2497         .clksel_con     = CRU_CLKSELS_CON(14),
2498         CRU_SRC_SET(0x3, 8),
2499         CRU_PARENTS_SET(clk_uart1_parents),
2500 };
2501
2502 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2503 static struct clk clk_uart2 = {
2504         .name           = "uart2",
2505         .set_rate       = clk_uart_set_rate,
2506         .clksel_con     = CRU_CLKSELS_CON(15),
2507         CRU_SRC_SET(0x3, 8),
2508         CRU_PARENTS_SET(clk_uart2_parents),
2509 };
2510 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2511 static struct clk clk_uart3 = {
2512         .name           = "uart3",
2513         .set_rate       = clk_uart_set_rate,
2514         .clksel_con     = CRU_CLKSELS_CON(16),
2515         CRU_SRC_SET(0x3, 8),
2516         CRU_PARENTS_SET(clk_uart3_parents),
2517 };
2518
2519 /* timer setting */
2520 GATE_CLK(timer0, xin24m, TIMER0);
2521 GATE_CLK(timer1, xin24m, TIMER1);
2522 GATE_CLK(timer2, xin24m, TIMER2);
2523 GATE_CLK(timer3, xin24m, TIMER3);
2524 GATE_CLK(timer4, xin24m, TIMER4);
2525 GATE_CLK(timer5, xin24m, TIMER5);
2526 GATE_CLK(timer6, xin24m, TIMER6);
2527
2528 /*********************power domain*******************************/
2529 #if 1
2530 #ifdef RK30_CLK_OFFBOARD_TEST
2531 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2532 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2533 #else
2534 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2535 #define _pmu_set_power_domain pmu_set_power_domain
2536 #endif
2537
2538 static int pd_video_mode(struct clk *clk, int on)
2539 {
2540         u32 gate[3];
2541         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2542         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2543         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2544         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2545         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2546         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2547         pmu_set_power_domain(PD_VIDEO, on);
2548         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2549         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2550         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2551         return 0;
2552 }
2553
2554 static struct clk pd_video = {
2555         .name   = "pd_video",
2556         .flags  = IS_PD,
2557         .mode   = pd_video_mode,
2558         .gate_idx       = PD_VIDEO,
2559 };
2560 static int pd_display_mode(struct clk *clk, int on)
2561 {
2562         u32 gate[10];
2563         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2564         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2565         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2566         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2567         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2568         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2569         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2570         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2571         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2572         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2573         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2574         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2575         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2576         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2577         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2578         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2579         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2580         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2581         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2582         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2583         pmu_set_power_domain(PD_VIO, on);
2584         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2585         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2586         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2587         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2588         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2589         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2590         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2591         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2592         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2593         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2594         return 0;
2595 }
2596
2597 static struct clk pd_display = {
2598         .name   = "pd_vio",
2599         .flags  = IS_PD,
2600         .mode   = pd_display_mode,
2601         .gate_idx       = PD_VIO,
2602 };
2603 static struct clk pd_lcdc0 = {
2604         .parent = &pd_display,
2605         .name   = "pd_lcdc0",
2606 };
2607 static struct clk pd_lcdc1 = {
2608         .parent = &pd_display,
2609         .name   = "pd_lcdc1",
2610 };
2611 static struct clk pd_cif0 = {
2612         .parent = &pd_display,
2613         .name   = "pd_cif0",
2614 };
2615 static struct clk pd_rga = {
2616         .parent = &pd_display,
2617         .name   = "pd_rga",
2618 };
2619 static struct clk pd_ipp = {
2620         .parent = &pd_display,
2621         .name   = "pd_ipp",
2622 };
2623 static struct clk pd_hdmi = {
2624         .parent = &pd_display,
2625         .name   = "pd_hdmi",
2626 };
2627
2628
2629 static int pd_gpu_mode(struct clk *clk, int on)
2630 {
2631         u32 gate[3];
2632         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2633         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2634         pmu_set_power_domain(PD_GPU, on);
2635         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2636         return 0;
2637 }
2638
2639 static struct clk pd_gpu = {
2640         .name   = "pd_gpu",
2641         .flags  = IS_PD,
2642         .mode   = pd_gpu_mode,
2643         .gate_idx       = PD_GPU,
2644 };
2645
2646 static int pm_off_mode(struct clk *clk, int on)
2647 {
2648         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2649         return 0;
2650 }
2651 static struct clk pd_peri = {
2652         .name   = "pd_peri",
2653         .flags  = IS_PD,
2654         .mode   = pm_off_mode,
2655         .gate_idx       = PD_PERI,
2656 };
2657
2658
2659 #define PD_CLK(name) \
2660 {\
2661         .dev_id = NULL,\
2662         .con_id = #name,\
2663         .clk = &name,\
2664 }
2665
2666 #endif
2667 /************************rk30 fixed div clock****************************************/
2668
2669 /*************************aclk_cpu***********************/
2670
2671 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2672 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2673 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2674
2675 /*************************hclk_cpu***********************/
2676
2677 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2678 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2679 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2680 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2681 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2682 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2683 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2684 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2685 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2686 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2687 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2688 GATE_CLK(hclk_imem0,    hclk_cpu,       HCLK_IMEM0);
2689 GATE_CLK(hclk_imem1,    hclk_cpu,       HCLK_IMEM1);
2690
2691 /*************************ahb2apb_cpu(pclk_cpu_h2p)***********************/
2692 GATE_CLK(pclk_uart0,    ahb2apb_cpu, PCLK_UART0);
2693 GATE_CLK(pclk_uart1,    ahb2apb_cpu, PCLK_UART1);
2694 /*************************pclk_cpu***********************/
2695 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2696 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2697 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2698 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2699 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2700 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2701 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2702 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2703 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2704 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2705 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2706 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2707 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2708 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2709 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2710
2711 /*************************aclk_periph***********************/
2712
2713 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2714 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2715 GATE_CLK(aclk_gps, aclk_periph, ACLK_GPS);
2716 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2717 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2718 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2719
2720 /*************************hclk_periph***********************/
2721 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2722 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2723 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2724 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2725 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2726 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2727 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2728 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2729 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2730 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2731 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2732 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2733 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2734 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2735 /*************************pclk_periph***********************/
2736 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2737 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2738 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2739 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2740 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2741 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2742 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2743 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2744 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2745 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2746 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2747 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2748 /*************************aclk_lcdc0***********************/
2749
2750 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2751 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2752 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2753 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2754
2755 /*************************aclk_lcdc0***********************/
2756
2757 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2758 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2759 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2760
2761
2762 #if 1
2763 #define CLK(dev, con, ck) \
2764 {\
2765         .dev_id = dev,\
2766         .con_id = con,\
2767         .clk = ck,\
2768 }
2769
2770
2771 #define CLK1(name) \
2772 {\
2773         .dev_id = NULL,\
2774         .con_id = #name,\
2775         .clk = &clk_##name,\
2776 }
2777
2778 #endif
2779
2780 static struct clk_lookup clks[] = {
2781         CLK(NULL, "xin24m", &xin24m),
2782         //CLK(NULL, "xin27m", &xin27m),
2783         CLK(NULL, "xin12m", &clk_12m),
2784         CLK(NULL, "arm_pll", &arm_pll_clk),
2785         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2786         CLK(NULL, "codec_pll", &codec_pll_clk),
2787         CLK(NULL, "general_pll", &general_pll_clk),
2788
2789         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2790         CLK(NULL, "ddr_gpll", &clk_ddr_gpll_path),
2791
2792         CLK(NULL, "ddr", &clk_ddr),
2793         CLK(NULL, "cpu", &clk_core),
2794         CLK1(l2c),
2795         CLK1(core_dbg),
2796         CLK("smp_twd", NULL, &core_periph),
2797         CLK(NULL, "aclk_core", &aclk_core),
2798
2799         CLK(NULL, "logic", &clk_cpu_div),
2800         CLK(NULL, "aclk_cpu", &aclk_cpu),
2801         CLK(NULL, "pclk_cpu", &pclk_cpu),
2802         CLK(NULL, "atclk_cpu", &atclk_cpu),
2803         CLK(NULL, "hclk_cpu", &hclk_cpu),
2804         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2805
2806         CLK(NULL, "gpu",        &aclk_gpu),
2807
2808         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2809         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2810         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2811         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2812
2813         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2814         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2815
2816         CLK(NULL, "aclk_periph", &aclk_periph),
2817         CLK(NULL, "pclk_periph", &pclk_periph),
2818         CLK(NULL, "hclk_periph", &hclk_periph),
2819
2820         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2821         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2822
2823         CLK(NULL, "cif_out_pll", &cif_out_pll),
2824         CLK(NULL, "cif0_out_div", &cif0_out_div),
2825         CLK(NULL, "cif0_out", &cif0_out),
2826
2827         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2828         CLK(NULL, "inv_cif0", &inv_cif0),
2829         CLK(NULL, "cif0_in", &cif0_in),
2830
2831         CLK1(i2s_pll),
2832         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2833         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2834         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2835
2836         // actually no i2s1
2837         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2838         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2839         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2840
2841
2842         CLK1(spdif_div),
2843         CLK1(spdif_frac_div),
2844         CLK1(spdif),
2845
2846         CLK1(otgphy0),
2847         CLK1(otgphy1),
2848         CLK1(otgphy0_480m),
2849         CLK1(otgphy1_480m),
2850         CLK1(hsicphy_480m),
2851         CLK1(hsicphy_12m),
2852
2853         CLK(NULL, "rmii_clkin", &rmii_clkin),
2854         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2855         CLK1(mac_ref),
2856         CLK1(mii_tx),
2857
2858         CLK1(hsadc_pll_div),
2859         CLK1(hsadc_frac_div),
2860         CLK1(hsadc_ext),
2861         CLK1(hsadc_out),
2862         CLK1(hsadc_out_inv),
2863         CLK1(hsadc),
2864
2865         CLK1(saradc),
2866
2867         CLK1(smc),
2868         CLK(NULL, "smc_inv",    &clkn_smc),
2869
2870         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2871         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2872
2873         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2874         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2875         CLK1(emmc),
2876
2877         CLK1(uart_pll),
2878         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2879         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2880         CLK("rk_serial.0", "uart", &clk_uart0),
2881         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2882         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2883         CLK("rk_serial.1", "uart", &clk_uart1),
2884         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2885         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2886         CLK("rk_serial.2", "uart", &clk_uart2),
2887         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2888         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2889         CLK("rk_serial.3", "uart", &clk_uart3),
2890
2891         CLK1(timer0),
2892         CLK1(timer1),
2893         CLK1(timer2),
2894         CLK1(timer3),
2895         CLK1(timer4),
2896         CLK1(timer5),
2897         CLK1(timer6),
2898
2899         /*************************aclk_cpu***********************/
2900         CLK1(dma1),
2901         CLK1(intmem),
2902         CLK1(aclk_strc_sys),
2903
2904         /*************************hclk_cpu***********************/
2905         CLK1(rom),
2906         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2907         // actually no i2s1
2908         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2909         CLK1(hclk_spdif),
2910         CLK1(hclk_cpubus),
2911         CLK1(hclk_ahb2apb),
2912         CLK1(hclk_vio_bus),
2913         CLK1(hclk_lcdc0),
2914         CLK1(hclk_lcdc1),
2915         CLK1(hclk_cif0),
2916         CLK1(hclk_ipp),
2917         CLK1(hclk_rga),
2918         CLK1(hclk_imem0),
2919         CLK1(hclk_imem1),
2920
2921         /*************************pclk_cpu***********************/
2922         CLK1(pwm01),
2923         CLK1(pclk_timer0),
2924         CLK1(pclk_timer2),
2925         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2926         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2927         CLK1(gpio0),
2928         CLK1(gpio1),
2929         CLK1(gpio2),
2930         CLK1(efuse),
2931         CLK1(tzpc),
2932         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2933         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2934         CLK1(pclk_ddrupctl),
2935         CLK1(pclk_ddrpubl),
2936         CLK1(dbg),
2937         CLK1(grf),
2938         CLK1(pmu),
2939
2940         /*************************aclk_periph***********************/
2941         CLK1(dma2),
2942         CLK1(aclk_smc),
2943         CLK1(aclk_gps),
2944         CLK1(aclk_peri_niu),
2945         CLK1(aclk_cpu_peri),
2946         CLK1(aclk_peri_axi_matrix),
2947
2948         /*************************hclk_periph***********************/
2949         CLK1(hclk_peri_axi_matrix),
2950         CLK1(hclk_peri_ahb_arbi),
2951         CLK1(hclk_emem_peri),
2952         CLK1(hclk_mac),
2953         CLK1(nandc),
2954         CLK1(hclk_usb_peri),
2955         CLK1(hclk_otg0),
2956         CLK1(hclk_otg1),
2957         CLK1(hclk_hsic),
2958         CLK1(hclk_hsadc),
2959         CLK1(hclk_pidfilter),
2960         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2961         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2962         CLK1(hclk_emmc),
2963
2964         /*************************pclk_periph***********************/
2965         CLK1(pclk_peri_axi_matrix),
2966         CLK1(pwm23),
2967         CLK1(wdt),
2968         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2969         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2970         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2971         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2972         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2973         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2974         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2975         CLK1(gpio3),
2976         CLK1(pclk_saradc),
2977
2978         /*************************aclk_lcdc0***********************/
2979         CLK1(aclk_vio0),
2980         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2981         CLK1(aclk_cif0),
2982         CLK1(aclk_ipp),
2983
2984         /*************************aclk_lcdc1***********************/
2985         CLK1(aclk_vio1),
2986         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2987         CLK1(aclk_rga),
2988         /************************power domain**********************/
2989
2990         PD_CLK(pd_peri),
2991         PD_CLK(pd_display),
2992         PD_CLK(pd_lcdc0),
2993         PD_CLK(pd_lcdc1),
2994         PD_CLK(pd_cif0),
2995         //PD_CLK(pd_cif1),
2996         PD_CLK(pd_rga),
2997         PD_CLK(pd_ipp),
2998         //PD_CLK(pd_video),
2999         PD_CLK(pd_gpu),
3000         //PD_CLK(pd_dbg),
3001 };
3002 static void __init rk30_init_enable_clocks(void)
3003 {
3004         #if 0
3005         //clk_enable_nolock(&xin24m);
3006         //clk_enable_nolock(&clk_12m);
3007         //clk_enable_nolock(&arm_pll_clk);
3008         //clk_enable_nolock(&ddr_pll_clk);
3009         //clk_enable_nolock(&codec_pll_clk);
3010         //clk_enable_nolock(&general_pll_clk);
3011         #endif
3012         clk_enable_nolock(&clk_ddr);
3013         //clk_enable_nolock(&clk_core);
3014         clk_enable_nolock(&clk_cpu_div);
3015         clk_enable_nolock(&clk_core_gpll_path);
3016         clk_enable_nolock(&clk_l2c);
3017         clk_enable_nolock(&clk_core_dbg);
3018         clk_enable_nolock(&core_periph);
3019         clk_enable_nolock(&aclk_core);
3020         //clk_enable_nolock(&aclk_cpu);
3021         //clk_enable_nolock(&pclk_cpu);
3022         clk_enable_nolock(&atclk_cpu);
3023         //clk_enable_nolock(&hclk_cpu);
3024         clk_enable_nolock(&ahb2apb_cpu);
3025         #if 0
3026          clk_enable_nolock(&clk_gpu);
3027          clk_enable_nolock(&aclk_gpu);
3028          clk_enable_nolock(&aclk_gpu_slv);
3029          clk_enable_nolock(&aclk_gpu_mst);
3030
3031          clk_enable_nolock(&aclk_vepu);
3032          clk_enable_nolock(&hclk_vepu);
3033          clk_enable_nolock(&aclk_vdpu);
3034          clk_enable_nolock(&hclk_vdpu);
3035
3036          clk_enable_nolock(&aclk_lcdc0_pre);
3037          clk_enable_nolock(&aclk_lcdc1_pre);
3038
3039          clk_enable_nolock(&aclk_periph);
3040         clk_enable_nolock(&pclk_periph);
3041         clk_enable_nolock(&hclk_periph);
3042         #endif
3043         #if 0
3044          clk_enable_nolock(&dclk_lcdc0);
3045          clk_enable_nolock(&dclk_lcdc1);
3046
3047          clk_enable_nolock(&cif_out_pll);
3048          clk_enable_nolock(&cif0_out_div);
3049
3050          clk_enable_nolock(&cif0_out);
3051          clk_enable_nolock(&pclkin_cif0);
3052          clk_enable_nolock(&inv_cif0);
3053          clk_enable_nolock(&cif0_in);
3054
3055          clk_enable_nolock(&clk_i2s_pll);
3056          clk_enable_nolock(&clk_i2s0_div);
3057          clk_enable_nolock(&clk_i2s0_frac_div);
3058          clk_enable_nolock(&clk_i2s0);
3059
3060           actually no i2s1
3061          clk_enable_nolock(&clk_i2s0_div);
3062          clk_enable_nolock(&clk_i2s0_frac_div);
3063          clk_enable_nolock(&clk_i2s0);
3064
3065         clk_enable_nolock(&clk_spdif_div);
3066         clk_enable_nolock(&clk_spdif_frac_div);
3067         clk_enable_nolock(&clk_spdif);
3068         #endif
3069         #if 0
3070         clk_enable_nolock(&clk_otgphy0);
3071         clk_enable_nolock(&clk_otgphy1);
3072         clk_enable_nolock(&clk_otgphy0_480m);
3073         clk_enable_nolock(&clk_otgphy1_480m);
3074         clk_enable_nolock(&clk_hsicphy_480m);
3075         clk_enable_nolock(&clk_hsicphy_12m);
3076         #endif
3077
3078         #if 0
3079         clk_enable_nolock(&rmii_clkin);
3080         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
3081         clk_enable_nolock(&clk_mac_ref);
3082         clk_enable_nolock(&clk_mii_tx);
3083         #endif
3084
3085         #if 0
3086         clk_enable_nolock(&clk_hsadc_pll_div);
3087         clk_enable_nolock(&clk_hsadc_frac_div);
3088         clk_enable_nolock(&clk_hsadc_ext);
3089         clk_enable_nolock(&clk_hsadc_out);
3090         clk_enable_nolock(&clk_hsadc_out_inv);
3091         clk_enable_nolock(&clk_hsadc);
3092
3093         clk_enable_nolock(&clk_saradc);
3094         #endif
3095         /*
3096         clk_enable_nolock(&clk_smc);
3097         clk_enable_nolock(&clkn_smc);
3098         */
3099         /*
3100         clk_enable_nolock(&clk_spi0);
3101         clk_enable_nolock(&clk_spi1);
3102         */
3103         /*
3104         clk_enable_nolock(&clk_sdmmc);
3105         clk_enable_nolock(&clk_sdio);
3106         clk_enable_nolock(&clk_emmc);
3107         */
3108         #if 0
3109         clk_enable_nolock(&clk_uart_pll);
3110         clk_enable_nolock(&clk_uart0_div);
3111         clk_enable_nolock(&clk_uart0_frac_div);
3112         clk_enable_nolock(&clk_uart0);
3113         clk_enable_nolock(&clk_uart1_div);
3114         clk_enable_nolock(&clk_uart1_frac_div);
3115         clk_enable_nolock(&clk_uart1);
3116         clk_enable_nolock(&clk_uart2_div);
3117         clk_enable_nolock(&clk_uart2_frac_div);
3118         clk_enable_nolock(&clk_uart2);
3119         clk_enable_nolock(&clk_uart3_div);
3120         clk_enable_nolock(&clk_uart3_frac_div);
3121         clk_enable_nolock(&clk_uart3);
3122         #endif
3123         #if CONFIG_RK_DEBUG_UART == 0
3124                 clk_enable_nolock(&clk_uart0);
3125                 clk_enable_nolock(&clk_pclk_uart0);
3126         #elif CONFIG_RK_DEBUG_UART == 1
3127                 clk_enable_nolock(&clk_uart1);
3128                 clk_enable_nolock(&clk_pclk_uart1);
3129
3130         #elif CONFIG_RK_DEBUG_UART == 2
3131                 clk_enable_nolock(&clk_uart2);
3132                 clk_enable_nolock(&clk_pclk_uart2);
3133
3134         #elif CONFIG_RK_DEBUG_UART == 3
3135                 clk_enable_nolock(&clk_uart3);
3136                 clk_enable_nolock(&clk_pclk_uart3);
3137
3138         #endif
3139         #if 0
3140         clk_enable_nolock(&clk_timer0);
3141         clk_enable_nolock(&clk_timer1);
3142         clk_enable_nolock(&clk_timer2);
3143         #endif
3144
3145         /*************************aclk_cpu***********************/
3146         clk_enable_nolock(&clk_dma1);
3147         clk_enable_nolock(&clk_intmem);
3148         clk_enable_nolock(&clk_aclk_strc_sys);
3149
3150         /*************************hclk_cpu***********************/
3151         clk_enable_nolock(&clk_rom);
3152         #if 0
3153         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3154         // actually no i2s1
3155         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3156         clk_enable_nolock(&clk_hclk_spdif);
3157         #endif
3158         clk_enable_nolock(&clk_hclk_cpubus);
3159         clk_enable_nolock(&clk_hclk_ahb2apb);
3160         clk_enable_nolock(&clk_hclk_vio_bus);
3161         #if 0
3162         clk_enable_nolock(&clk_hclk_lcdc0);
3163         clk_enable_nolock(&clk_hclk_lcdc1);
3164         clk_enable_nolock(&clk_hclk_cif0);
3165         clk_enable_nolock(&clk_hclk_ipp);
3166         clk_enable_nolock(&clk_hclk_rga);
3167         #endif
3168         clk_enable_nolock(&clk_hclk_imem0);
3169         clk_enable_nolock(&clk_hclk_imem1);
3170
3171         /*************************pclk_cpu***********************/
3172         #if 0
3173         clk_enable_nolock(&clk_pwm01);
3174         clk_enable_nolock(&clk_pclk_timer0);
3175         clk_enable_nolock(&clk_pclk_timer1);
3176         clk_enable_nolock(&clk_pclk_timer2);
3177         clk_enable_nolock(&clk_i2c0);
3178         clk_enable_nolock(&clk_i2c1);
3179         clk_enable_nolock(&clk_gpio0);
3180         clk_enable_nolock(&clk_gpio1);
3181         clk_enable_nolock(&clk_gpio2);
3182         clk_enable_nolock(&clk_efuse);
3183         #endif
3184         clk_enable_nolock(&clk_tzpc);
3185         //clk_enable_nolock(&clk_pclk_uart0);
3186         //clk_enable_nolock(&clk_pclk_uart1);
3187         clk_enable_nolock(&clk_pclk_ddrupctl);
3188         clk_enable_nolock(&clk_pclk_ddrpubl);
3189         clk_enable_nolock(&clk_dbg);
3190         clk_enable_nolock(&clk_grf);
3191         clk_enable_nolock(&clk_pmu);
3192
3193         /*************************aclk_periph***********************/
3194         clk_enable_nolock(&clk_dma2);
3195         clk_enable_nolock(&clk_aclk_smc);
3196         clk_enable_nolock(&clk_aclk_peri_niu);
3197         clk_enable_nolock(&clk_aclk_cpu_peri);
3198         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3199
3200         /*************************hclk_periph***********************/
3201         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3202         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3203         clk_enable_nolock(&clk_hclk_emem_peri);
3204         //clk_enable_nolock(&clk_hclk_mac);
3205         clk_enable_nolock(&clk_nandc);
3206         clk_enable_nolock(&clk_hclk_usb_peri);
3207         #if 0
3208         clk_enable_nolock(&clk_hclk_otg0);
3209         clk_enable_nolock(&clk_hclk_otg1);
3210         clk_enable_nolock(&clk_hclk_hsic);
3211         clk_enable_nolock(&clk_hclk_gps);
3212         clk_enable_nolock(&clk_hclk_hsadc);
3213         clk_enable_nolock(&clk_hclk_pidfilter);
3214         clk_enable_nolock(&clk_hclk_sdmmc);
3215         clk_enable_nolock(&clk_hclk_sdio);
3216         clk_enable_nolock(&clk_hclk_emmc);
3217         #endif
3218
3219         /*************************pclk_periph***********************/
3220         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3221         #if 0
3222         clk_enable_nolock(&clk_pwm23);
3223         clk_enable_nolock(&clk_wdt);
3224         clk_enable_nolock(&clk_pclk_spi0);
3225         clk_enable_nolock(&clk_pclk_spi1);
3226         clk_enable_nolock(&clk_pclk_uart2);
3227         clk_enable_nolock(&clk_pclk_uart3);
3228         #endif
3229         #if 0
3230         clk_enable_nolock(&clk_i2c2);
3231         clk_enable_nolock(&clk_i2c3);
3232         clk_enable_nolock(&clk_i2c4);
3233         clk_enable_nolock(&clk_gpio3);
3234         clk_enable_nolock(&clk_pclk_saradc);
3235         #endif
3236         /*************************aclk_lcdc0***********************/
3237 #if 1
3238         //clk_enable_nolock(&clk_aclk_vio0);
3239         //clk_enable_nolock(&clk_aclk_lcdc0);
3240         //clk_enable_nolock(&clk_aclk_cif0);
3241         //clk_enable_nolock(&clk_aclk_ipp);
3242 #endif
3243         /*************************aclk_lcdc1***********************/
3244 #if 1
3245         //clk_enable_nolock(&clk_aclk_vio1);
3246         //clk_enable_nolock(&clk_aclk_lcdc1);
3247         //clk_enable_nolock(&clk_aclk_rga);
3248 #endif
3249         /************************power domain**********************/
3250
3251 }
3252 static void periph_clk_set_init(void)
3253 {
3254         unsigned long aclk_p, hclk_p, pclk_p;
3255         unsigned long ppll_rate = general_pll_clk.rate;
3256         //aclk 148.5
3257
3258         /* general pll */
3259         switch (ppll_rate) {
3260                 case 148500 * KHZ:
3261                         aclk_p = 148500 * KHZ;
3262                         hclk_p = aclk_p >> 1;
3263                         pclk_p = aclk_p >> 2;
3264                         break;
3265                 case 297 * MHZ:
3266                         aclk_p = ppll_rate >> 1;
3267                         hclk_p = aclk_p >> 0;
3268                         pclk_p = aclk_p >> 1;
3269                         break;
3270                 case 300 * MHZ:
3271                         aclk_p = ppll_rate >> 1;
3272                         hclk_p = aclk_p >> 0;
3273                         pclk_p = aclk_p >> 1;
3274                         break;
3275                 case 594 * MHZ:
3276                         aclk_p = ppll_rate >> 2;
3277                         hclk_p = aclk_p >> 0;
3278                         pclk_p = aclk_p >> 1;
3279                         break;
3280                 case 891 * MHZ:
3281                         aclk_p = ppll_rate / 6;
3282                         hclk_p = aclk_p >> 0;
3283                         pclk_p = aclk_p >> 1;
3284                         break;
3285                 case 1188 * MHZ:
3286                         aclk_p = ppll_rate >> 3;
3287                         hclk_p = aclk_p >> 0;
3288                         pclk_p = aclk_p >> 1;
3289                         break;
3290
3291                 default:
3292                         aclk_p = 150 * MHZ;
3293                         hclk_p = 150 * MHZ;
3294                         pclk_p = 75 * MHZ;
3295                         break;
3296         }
3297         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3298         clk_set_rate_nolock(&aclk_periph, aclk_p);
3299         clk_set_rate_nolock(&hclk_periph, hclk_p);
3300         clk_set_rate_nolock(&pclk_periph, pclk_p);
3301 }
3302
3303 static void cpu_axi_init(void)
3304 {
3305         unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3306         unsigned long gpll_rate = general_pll_clk.rate;
3307
3308         switch (gpll_rate) {
3309                 case 297 * MHZ:
3310                         cpu_div_rate = gpll_rate;
3311                         aclk_cpu_rate = cpu_div_rate >> 0;
3312                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3313                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3314                         break;
3315
3316                 case 594 * MHZ:
3317                         cpu_div_rate = gpll_rate >> 1;
3318                         aclk_cpu_rate = cpu_div_rate >> 0;
3319                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3320                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3321                         break;
3322
3323                 case 891 * MHZ:
3324                         cpu_div_rate = gpll_rate / 3;
3325                         aclk_cpu_rate = cpu_div_rate >> 0;
3326                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3327                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3328                         break;
3329
3330                 case 1188 * MHZ:
3331                         cpu_div_rate = gpll_rate >> 2;
3332                         aclk_cpu_rate = cpu_div_rate >> 0;
3333                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3334                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3335                         break;
3336
3337                 default:
3338                         aclk_cpu_rate = 150 * MHZ;
3339                         hclk_cpu_rate = 150 * MHZ;
3340                         pclk_cpu_rate = 75 * MHZ;
3341                         break;
3342         }
3343         ahb2apb_cpu_rate = pclk_cpu_rate;
3344
3345         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3346         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3347         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3348         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3349         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3350         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3351 }
3352
3353 void rk30_clock_common_i2s_init(void)
3354 {
3355         unsigned long i2s_rate;
3356         //20 times
3357         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3358                 i2s_rate = 49152000;
3359         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3360                 i2s_rate = 24576000;
3361         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3362                 i2s_rate = 22579000;
3363         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3364                 i2s_rate = 12288000;
3365         } else {
3366                 i2s_rate = 49152000;
3367         }
3368
3369         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3370                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3371         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3372                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3373         } else {
3374                 if(general_pll_clk.rate > codec_pll_clk.rate)
3375                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3376                 else
3377                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3378         }
3379 }
3380
3381 static void inline clock_set_div(struct clk *clk,u32 div)
3382 {
3383         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3384 }
3385
3386 static void inline clock_set_max_div(struct clk *clk)
3387 {
3388         set_cru_bits_w_msk(clk->div_max - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
3389 }
3390
3391 static void div_clk_for_pll_init(void)
3392 {
3393         clock_set_max_div(&clk_cpu_div);
3394         clock_set_max_div(&aclk_vdpu);
3395         clock_set_max_div(&aclk_vepu);
3396         clock_set_max_div(&aclk_gpu);
3397         clock_set_max_div(&aclk_lcdc0_pre);
3398         clock_set_max_div(&aclk_lcdc1_pre);
3399         clock_set_max_div(&aclk_periph);
3400         clock_set_max_div(&dclk_lcdc0);
3401         clock_set_max_div(&dclk_lcdc1);
3402         clock_set_max_div(&cif0_out_div);
3403         clock_set_max_div(&clk_i2s0_div);
3404         clock_set_max_div(&clk_spdif_div);
3405         clock_set_max_div(&clk_uart0_div);
3406         clock_set_max_div(&clk_uart1_div);
3407         clock_set_max_div(&clk_uart2_div);
3408         clock_set_max_div(&clk_uart3_div);
3409         clock_set_max_div(&clk_hsicphy_12m);
3410         clock_set_max_div(&clk_hsadc_pll_div);
3411         clock_set_max_div(&clk_saradc);
3412 }
3413
3414 /************************************for cpll runing checking****************************************/
3415 static u8 pll_flag = 0;
3416 static int pll_get_flag(void)
3417 {
3418         u8 data_buf[32 + 1];
3419         efuse_readregs(0, 32, data_buf);
3420
3421         printk("pll_flag = 0x%02x\n", data_buf[22]);
3422         return data_buf[22] & 0x3;
3423 }
3424
3425 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3426 {
3427         div_clk_for_pll_init();
3428         //general
3429         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3430         //code pll
3431         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3432
3433         cpu_axi_init();
3434         clk_set_rate_nolock(&clk_core, 816 * MHZ);
3435         //periph clk
3436         periph_clk_set_init();
3437
3438         //i2s
3439         rk30_clock_common_i2s_init();
3440
3441         // spi
3442         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3443         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3444
3445         // uart
3446         if((rk30_clock_flags & CLK_FLG_UART_1_3M) && (cpll_rate != 24 * MHZ))
3447                 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3448         else
3449                 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3450         //mac
3451         if(!(gpll_rate % (50 * MHZ))) {
3452                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3453
3454         } else if((!(ddr_pll_clk.rate % (50 * MHZ))) && (ddr_pll_clk.rate != 24 * MHZ) && ((pll_flag & 0x2) == 0)) {
3455                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3456
3457         } else {
3458                 CLKDATA_DBG("mac can't get 50mhz, set to gpll\n");
3459                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3460         }
3461
3462         //hsadc
3463         //auto pll sel
3464         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3465
3466         //lcdc0 lcd auto sel pll
3467         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3468         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3469
3470         //cif
3471         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3472
3473         //axi lcdc auto sel
3474         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3475         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3476         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3477         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3478
3479         //axi vepu auto sel
3480         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3481         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3482
3483         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3484         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3485         //gpu auto sel
3486         clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
3487         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3488
3489         clk_set_rate_nolock(&clk_uart0, 49500000);
3490         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3491         clk_set_rate_nolock(&clk_sdio, 24750000);
3492 }
3493
3494 static struct clk def_ops_clk = {
3495         .get_parent = clksel_get_parent,
3496         .set_parent = clksel_set_parent,
3497 };
3498
3499 #ifdef CONFIG_PROC_FS
3500 struct clk_dump_ops dump_ops;
3501 #endif
3502 void rk_dump_clock_info(void);
3503 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3504 {
3505         struct clk_lookup *lk;
3506
3507         if (soc_is_rk3188plus()) {
3508                 arm_pll_clk.recalc = plus_plls_clk_recalc;
3509                 ddr_pll_clk.recalc = plus_plls_clk_recalc;
3510                 codec_pll_clk.recalc = plus_plls_clk_recalc;
3511                 general_pll_clk.recalc = plus_plls_clk_recalc;
3512
3513                 arm_pll_clk.set_rate = plus_arm_pll_clk_set_rate;
3514                 codec_pll_clk.set_rate = plus_cpll_clk_set_rate;
3515                 general_pll_clk.set_rate = plus_gpll_clk_set_rate;
3516         }
3517
3518         pll_flag = pll_get_flag();
3519         if (0 != pll_flag) {
3520                 CLKDATA_DBG("CPLL=%lu, GPLL=%lu;CPLL CAN NOT LOCK, SET CPLL BY PASS, USE GPLL REPLACE CPLL\n",
3521                                 cpll, gpll);
3522                 cpll = 24 * MHZ;
3523                 gpll = 891 * MHZ;
3524         }
3525
3526         clk_register_dump_ops(&dump_ops);
3527         clk_register_default_ops_clk(&def_ops_clk);
3528         rk30_clock_flags = flags;
3529         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3530 #ifdef RK30_CLK_OFFBOARD_TEST
3531                 rk30_clkdev_add(lk);
3532 #else
3533                 clkdev_add(lk);
3534 #endif
3535                 clk_register(lk->clk);
3536         }
3537         clk_recalculate_root_clocks_nolock();
3538
3539         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3540
3541         /*
3542          * Only enable those clocks we will need, let the drivers
3543          * enable other clocks as necessary
3544          */
3545
3546         rk30_init_enable_clocks();
3547 #if 0
3548         // print loader config
3549         CLKDATA_DBG("%s clks register dbg start\n", __func__);
3550         rk_dump_clock_info();
3551         rk30_clk_dump_regs();
3552
3553         CLKDATA_DBG("%s clks register dbg end\n", __func__);
3554 #endif
3555         /*
3556          * Disable any unused clocks left on by the bootloader
3557          */
3558         //clk_disable_unused();
3559         rk30_clock_common_init(gpll, cpll);
3560         preset_lpj = loops_per_jiffy;
3561
3562         //gpio6_b7
3563         //regfile_writel(0xc0004000,0x10c);
3564         //cru_writel(0x07000000,CRU_MISC_CON);
3565
3566 }
3567 extern int rk3188_dvfs_init(void);
3568
3569 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3570 {
3571         CLKDATA_DBG("clock: gpll %lu cpll %lu flags 0x%x con2 0x%x/0x%x\n",
3572                         gpll, cpll, flags, cru_readl(PLL_CONS(DPLL_ID, 2)), cru_readl(PLL_CONS(CPLL_ID, 2)));
3573         _rk30_clock_data_init(gpll, cpll, flags);
3574         rk3188_dvfs_init();
3575 }
3576
3577 /*
3578  * You can override arm_clk rate with armclk= cmdline option.
3579  */
3580 static int __init armclk_setup(char *str)
3581 {
3582         get_option(&str, &armclk);
3583
3584         if (!armclk)
3585                 return 0;
3586         if (armclk < 10000)
3587                 armclk *= MHZ;
3588         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3589         return 0;
3590 }
3591 #ifndef RK30_CLK_OFFBOARD_TEST
3592 early_param("armclk", armclk_setup);
3593 #endif
3594
3595
3596 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3597 {
3598         struct clk *ck;
3599         int i;
3600         unsigned long rate = clk->rate;
3601         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3602         for (i = 0; i < deep; i++)
3603                 printk("    ");
3604
3605         printk("%-11s ", clk->name);
3606 #ifndef RK30_CLK_OFFBOARD_TEST
3607         if (clk->flags & IS_PD) {
3608                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3609         }
3610 #endif
3611         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3612                 int idx = clk->gate_idx;
3613                 u32 v;
3614                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3615                 printk("%s ", v ? "off" : "on ");
3616         }
3617
3618         if (clk->pll) {
3619                 u32 pll_mode;
3620                 u32 pll_id = clk->pll->id;
3621                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3622                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3623                         printk("slow   ");
3624                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3625                         printk("normal ");
3626                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3627                         printk("deep   ");
3628
3629                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3630                         printk("bypass ");
3631         } else if(clk == &clk_ddr) {
3632                 rate = clk->recalc(clk);
3633         }
3634
3635         if (rate >= MHZ) {
3636                 if (rate % MHZ)
3637                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3638                 else
3639                         printk("%ld MHz", rate / MHZ);
3640         } else if (rate >= KHZ) {
3641                 if (rate % KHZ)
3642                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3643                 else
3644                         printk("%ld KHz", rate / KHZ);
3645         } else {
3646                 printk("%ld Hz", rate);
3647         }
3648
3649         printk(" usecount = %d", clk->usecount);
3650
3651         if (clk->parent)
3652                 printk(" parent = %s", clk->parent->name);
3653
3654         printk("\n");
3655
3656         list_for_each_entry(ck, root_clocks, node) {
3657                 if (ck->parent == clk)
3658                         rk_dump_clock(ck, deep + 1, root_clocks);
3659         }
3660 }
3661
3662 #if 1
3663 struct list_head *get_rk_clocks_head(void);
3664
3665 void rk_dump_clock_info(void)
3666 {
3667         struct clk* clk;
3668         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3669                 if (!clk->parent)
3670                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3671         }
3672 }
3673 #endif
3674
3675 #ifdef CONFIG_PROC_FS
3676
3677 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3678 {
3679         struct clk *ck;
3680         int i;
3681         unsigned long rate = clk->rate;
3682         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3683         for (i = 0; i < deep; i++)
3684                 seq_printf(s, "    ");
3685
3686         seq_printf(s, "%-11s ", clk->name);
3687 #ifndef RK30_CLK_OFFBOARD_TEST
3688         if (clk->flags & IS_PD) {
3689                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3690         }
3691 #endif
3692         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3693                 int idx = clk->gate_idx;
3694                 u32 v;
3695                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3696                 seq_printf(s, "%s ", v ? "off" : "on ");
3697         }
3698
3699         if (clk->pll) {
3700                 u32 pll_mode;
3701                 u32 pll_id = clk->pll->id;
3702                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3703                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3704                         seq_printf(s, "slow   ");
3705                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3706                         seq_printf(s, "normal ");
3707                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3708                         seq_printf(s, "deep   ");
3709
3710                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3711                         seq_printf(s, "bypass ");
3712         } else if(clk == &clk_ddr) {
3713                 rate = clk->recalc(clk);
3714         }
3715
3716         if (rate >= MHZ) {
3717                 if (rate % MHZ)
3718                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3719                 else
3720                         seq_printf(s, "%ld MHz", rate / MHZ);
3721         } else if (rate >= KHZ) {
3722                 if (rate % KHZ)
3723                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3724                 else
3725                         seq_printf(s, "%ld KHz", rate / KHZ);
3726         } else {
3727                 seq_printf(s, "%ld Hz", rate);
3728         }
3729
3730         seq_printf(s, " usecount = %d", clk->usecount);
3731
3732         if (clk->parent)
3733                 seq_printf(s, " parent = %s", clk->parent->name);
3734
3735         seq_printf(s, "\n");
3736
3737         list_for_each_entry(ck, root_clocks, node) {
3738                 if (ck->parent == clk)
3739                         dump_clock(s, ck, deep + 1, root_clocks);
3740         }
3741 }
3742
3743 static void dump_regs(struct seq_file *s)
3744 {
3745         int i = 0;
3746         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3747         seq_printf(s, "\nPLLRegisters:\n");
3748         for(i = 0; i < END_PLL_ID; i++) {
3749                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3750                                 cru_readl(PLL_CONS(i, 0)),
3751                                 cru_readl(PLL_CONS(i, 1)),
3752                                 cru_readl(PLL_CONS(i, 2)),
3753                                 cru_readl(PLL_CONS(i, 3))
3754                           );
3755         }
3756         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3757
3758         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3759                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3760         }
3761         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3762                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3763         }
3764         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3765         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3766
3767         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3768                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3769         }
3770         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3771         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3772
3773 }
3774
3775 void rk30_clk_dump_regs(void)
3776 {
3777         int i = 0;
3778         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3779         printk("\nPLLRegisters:\n");
3780         for(i = 0; i < END_PLL_ID; i++) {
3781                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3782                                 cru_readl(PLL_CONS(i, 0)),
3783                                 cru_readl(PLL_CONS(i, 1)),
3784                                 cru_readl(PLL_CONS(i, 2)),
3785                                 cru_readl(PLL_CONS(i, 3))
3786                       );
3787         }
3788         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3789
3790         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3791                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3792         }
3793         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3794                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3795         }
3796         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3797         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3798
3799         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3800                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3801         }
3802         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3803         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3804
3805 }
3806
3807
3808 #ifdef CONFIG_PROC_FS
3809 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3810 struct clk_dump_ops dump_ops = {
3811         .dump_clk = dump_clock,
3812         .dump_regs = dump_regs,
3813 };
3814 #endif
3815
3816
3817 #endif /* CONFIG_PROC_FS */
3818
3819
3820
3821
3822 #ifdef RK30_CLK_OFFBOARD_TEST
3823 struct clk *test_get_parent(struct clk *clk) {
3824         return clk->parent;
3825 }
3826
3827 void i2s_test(void)
3828 {
3829         struct clk *i2s_clk = &clk_i2s0;
3830
3831         clk_enable_nolock(i2s_clk);
3832
3833         clk_set_rate_nolock(i2s_clk, 12288000);
3834         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3835         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3836         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3837         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3838         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3839
3840 }
3841
3842 void uart_test(void)
3843 {
3844         struct clk *uart_clk = &clk_uart0;
3845
3846         clk_enable_nolock(uart_clk);
3847
3848         clk_set_rate_nolock(uart_clk, 12288000);
3849         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3850         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3851         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3852         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3853         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3854
3855 }
3856 void hsadc_test(void)
3857 {
3858         struct clk *hsadc_clk = &clk_hsadc;
3859
3860         printk("******************hsadc_test**********************\n");
3861         clk_enable_nolock(hsadc_clk);
3862
3863         clk_set_rate_nolock(hsadc_clk, 12288000);
3864         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3865
3866
3867         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3868         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3869
3870         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3871
3872         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3873
3874         printk("******************hsadc out clock**********************\n");
3875
3876         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3877         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3878         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3879         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3880
3881
3882
3883 }
3884
3885 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3886 {
3887         //arm
3888         printk("*********arm_pll_clk***********\n");
3889         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3890
3891         printk("*********set clk_core parent***********\n");
3892         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3893         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3894
3895         //general
3896         printk("*********general_pll_clk***********\n");
3897         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3898
3899         //code pll
3900         printk("*********codec_pll_clk***********\n");
3901         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3902
3903
3904         printk("*********periph_clk_set_init***********\n");
3905         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3906         periph_clk_set_init();
3907
3908 #if 0 //
3909         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3910 #else
3911         printk("*********clk i2s***********\n");
3912         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3913         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3914         i2s_test();
3915 #endif
3916         // spi
3917         clk_enable_nolock(&clk_spi0);
3918         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3919         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3920         //saradc
3921         clk_enable_nolock(&clk_saradc);
3922         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3923         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3924         //sdio
3925         clk_enable_nolock(&clk_sdio);
3926         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3927         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3928         // uart
3929         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3930         uart_test();
3931         //mac
3932         printk("*********mac***********\n");
3933
3934         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3935         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3936
3937         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3938         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3939         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3940
3941         printk("*********mac mii set***********\n");
3942         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3943         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3944         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3945         //hsadc
3946         printk("*********hsadc 1***********\n");
3947         //auto pll
3948         hsadc_test();
3949         //lcdc
3950         clk_enable_nolock(&dclk_lcdc0);
3951
3952         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
3953         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
3954
3955         //cif
3956         clk_enable_nolock(&cif0_out);
3957
3958         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3959         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
3960
3961         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
3962         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3963
3964         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
3965         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3966         //cif_in
3967         clk_enable_nolock(&cif0_in);
3968         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
3969         //axi lcdc
3970         clk_enable_nolock(&aclk_lcdc0);
3971         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
3972         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
3973         //axi vepu
3974         clk_enable_nolock(&aclk_vepu);
3975         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3976         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
3977
3978         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
3979         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
3980
3981         printk("test end\n");
3982
3983         /* arm pll
3984            clk_set_rate_nolock(&arm_pll_clk, armclk);
3985            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
3986            */
3987         //
3988         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3989         //
3990         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3991         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3992
3993 }
3994
3995
3996
3997
3998
3999 static LIST_HEAD(rk30_clocks);
4000 static DEFINE_MUTEX(rk30_clocks_mutex);
4001
4002 static inline int __rk30clk_get(struct clk *clk)
4003 {
4004         return 1;
4005 }
4006 void rk30_clkdev_add(struct clk_lookup *cl)
4007 {
4008         mutex_lock(&rk30_clocks_mutex);
4009         list_add_tail(&cl->node, &rk30_clocks);
4010         mutex_unlock(&rk30_clocks_mutex);
4011 }
4012 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
4013         struct clk_lookup *p, *cl = NULL;
4014         int match, best = 0;
4015
4016         list_for_each_entry(p, &rk30_clocks, node) {
4017                 match = 0;
4018                 if (p->dev_id) {
4019                         if (!dev_id || strcmp(p->dev_id, dev_id))
4020                                 continue;
4021                         match += 2;
4022                 }
4023                 if (p->con_id) {
4024                         if (!con_id || strcmp(p->con_id, con_id))
4025                                 continue;
4026                         match += 1;
4027                 }
4028
4029                 if (match > best) {
4030                         cl = p;
4031                         if (match != 3)
4032                                 best = match;
4033                         else
4034                                 break;
4035                 }
4036         }
4037         return cl;
4038 }
4039
4040 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
4041         struct clk_lookup *cl;
4042
4043         mutex_lock(&rk30_clocks_mutex);
4044         cl = rk30_clk_find(dev_id, con_id);
4045         if (cl && !__rk30clk_get(cl->clk))
4046                 cl = NULL;
4047         mutex_unlock(&rk30_clocks_mutex);
4048
4049         return cl ? cl->clk : ERR_PTR(-ENOENT);
4050 }
4051 //EXPORT_SYMBOL(rk30_clk_get_sys);
4052
4053 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
4054         const char *dev_id = dev ? dev_name(dev) : NULL;
4055         return rk30_clk_get_sys(dev_id, con_id);
4056 }
4057 //EXPORT_SYMBOL(rk30_clk_get);
4058
4059
4060 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
4061
4062 void rk30_clocks_test(void)
4063 {
4064         struct clk *test_gpll;
4065         test_gpll = rk30_clk_get(NULL, "general_pll");
4066         if(test_gpll) {
4067                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
4068                 printk("gpll rate=%lu\n", test_gpll->rate);
4069         }
4070         //while(1);
4071 }
4072
4073 void __init rk30_clock_init_test(void)
4074 {
4075
4076         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
4077         //while(1);
4078 }
4079
4080
4081 #endif
4082
4083