arch/arm/mach-rk3188/include/mach/board.h

   1 #ifndef __MACH_BOARD_H
   2 #define __MACH_BOARD_H
   3
   4 #include <linux/device.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/i2c.h>
   7 #include <linux/types.h>
   8 #include <linux/timer.h>
   9 #include <linux/notifier.h>
  10 #include <asm/setup.h>
  11 #include <plat/board.h>
  12 #include <mach/sram.h>
  13 #include <linux/i2c-gpio.h>
  14
  15
  16 void __init rk30_map_common_io(void);
  17 void __init rk30_init_irq(void);
  18 void __init rk30_map_io(void);
  19 struct machine_desc;
  20 void __init rk30_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
  21 void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags);
  22
  23 #ifdef CONFIG_RK30_PWM_REGULATOR
  24 void  rk30_pwm_suspend_voltage_set(void);
  25 void  rk30_pwm_resume_voltage_set(void);
  26 void __sramfunc rk30_pwm_logic_suspend_voltage(void);
  27  void __sramfunc rk30_pwm_logic_resume_voltage(void);
  28 #endif
  29
  30 extern struct sys_timer rk30_timer;
  31
  32 enum _periph_pll {
  33         periph_pll_1485mhz = 148500000,
  34         periph_pll_297mhz = 297000000,
  35         periph_pll_300mhz = 300000000,
  36         periph_pll_384mhz = 384000000,
  37         periph_pll_594mhz = 594000000,
  38         periph_pll_1188mhz = 1188000000, /* for box*/
  39 };
  40 enum _codec_pll {
  41         codec_pll_360mhz = 360000000, /* for HDMI */
  42         codec_pll_408mhz = 408000000,
  43         codec_pll_456mhz = 456000000,
  44         codec_pll_504mhz = 504000000,
  45         codec_pll_552mhz = 552000000, /* for HDMI */
  46         codec_pll_594mhz = 594000000, /* for HDMI */
  47         codec_pll_600mhz = 600000000,
  48         codec_pll_742_5khz = 742500000,
  49         codec_pll_768mhz = 768000000,
  50         codec_pll_798mhz = 798000000,
  51         codec_pll_1188mhz = 1188000000,
  52         codec_pll_1200mhz = 1200000000,
  53 };
  54
  55 //has extern 27mhz
  56 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  57 //max i2s rate
  58 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  59 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  60 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  61 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  62 //uart 1m\3m
  63 #define CLK_FLG_UART_1_3M                       (1<<5)
  64 #define CLK_CPU_HPCLK_11                                (1<<6)
  65
  66
  67 #ifdef CONFIG_RK29_VMAC
  68
  69 #define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
  70 #define periph_pll_default periph_pll_300mhz
  71 #define codec_pll_default codec_pll_1188mhz
  72
  73 #else
  74
  75
  76 #define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
  77
  78 #define codec_pll_default codec_pll_594mhz
  79 #define periph_pll_default periph_pll_384mhz
  80 #endif
  81
  82
  83
  84
  85
  86
  87 #endif