arch/arm/mach-rk3188/include/mach/cru-rk3188.h

   1 enum rk_plls_id {
   2         APLL_ID = 0,
   3         DPLL_ID,
   4         CPLL_ID,
   5         GPLL_ID,
   6         END_PLL_ID,
   7 };
   8
   9 /*****cru reg offset*****/
  10
  11 #define CRU_MODE_CON            0x40
  12 #define CRU_CLKSEL_CON          0x44
  13 #define CRU_CLKGATE_CON         0xd0
  14 #define CRU_GLB_SRST_FST        0x100
  15 #define CRU_GLB_SRST_SND        0x104
  16 #define CRU_SOFTRST_CON         0x110
  17
  18 #define PLL_CONS(id, i)         ((id) * 0x10 + ((i) * 4))
  19
  20 #define CRU_CLKSELS_CON_CNT     (35)
  21 #define CRU_CLKSELS_CON(i)      (CRU_CLKSEL_CON + ((i) * 4))
  22
  23 #define CRU_CLKGATES_CON_CNT    (10)
  24 #define CRU_CLKGATES_CON(i)     (CRU_CLKGATE_CON + ((i) * 4))
  25
  26 #define CRU_SOFTRSTS_CON_CNT    (9)
  27 #define CRU_SOFTRSTS_CON(i)     (CRU_SOFTRST_CON + ((i) * 4))
  28
  29 #define CRU_MISC_CON            (0x134)
  30 #define CRU_GLB_CNT_TH          (0x140)
  31
  32 /********************************************************************/
  33 #define CRU_GET_REG_BITS_VAL(reg,bits_shift, msk)       (((reg) >> (bits_shift))&(msk))
  34 #define CRU_W_MSK(bits_shift, msk)      ((msk) << ((bits_shift) + 16))
  35 #define CRU_SET_BITS(val,bits_shift, msk)       (((val)&(msk)) << (bits_shift))
  36
  37 #define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
  38
  39 /*******************PLL CON0 BITS***************************/
  40
  41 #define PLL_CLKFACTOR_SET(val, shift, msk) \
  42         ((((val) - 1) & (msk)) << (shift))
  43
  44 #define PLL_CLKFACTOR_GET(reg, shift, msk) \
  45         ((((reg) >> (shift)) & (msk)) + 1)
  46
  47 #define PLL_OD_MSK              (0x3f)
  48 #define PLL_OD_SHIFT            (0x0)
  49
  50 #define PLL_CLKOD(val)          PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
  51 #define PLL_NO(reg)             PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
  52
  53 #define PLL_NO_SHIFT(reg)       PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
  54
  55 #define PLL_CLKOD_SET(val)      (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
  56
  57 #define PLL_NR_MSK              (0x3f)
  58 #define PLL_NR_SHIFT            (8)
  59 #define PLL_CLKR(val)           PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
  60 #define PLL_NR(reg)             PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
  61
  62 #define PLL_CLKR_SET(val)       (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
  63
  64 #define PLUS_PLL_OD_MSK         (0xf)
  65 #define PLUS_PLL_NO(reg)        (PLL_NO(reg) & PLUS_PLL_OD_MSK)
  66
  67 #define PLUS_PLL_NR_MSK         (0x3f)
  68 #define PLUS_PLL_NR(reg)        (PLL_NO(reg) & PLUS_PLL_NR_MSK)
  69
  70 #define PLUS_PLL_CLKR_SET(val)  PLL_CLKR_SET(val & PLUS_PLL_NR_MSK)
  71 #define PLUS_PLL_CLKOD_SET(val) PLL_CLKOD_SET(val & PLUS_PLL_OD_MSK)
  72 /*******************PLL CON1 BITS***************************/
  73
  74 #define PLL_NF_MSK              (0xffff)
  75 #define PLL_NF_SHIFT            (0)
  76 #define PLL_CLKF(val)           PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
  77 #define PLL_NF(reg)             PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
  78 #define PLL_CLKF_SET(val)       (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
  79
  80 #define PLUS_PLL_NF_MSK         (0x1ff)
  81 #define PLUS_PLL_NF(reg)        (PLL_NF(reg) & PLUS_PLL_NF_MSK)
  82 #define PLUS_PLL_CLKF_SET(val)  PLL_CLKF_SET(val & PLUS_PLL_NF_MSK)
  83 /*******************PLL CON2 BITS***************************/
  84
  85 #define PLL_BWADJ_MSK           (0xfff)
  86 #define PLL_BWADJ_SHIFT         (0)
  87 #define PLL_CLK_BWADJ_SET(val)  ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
  88
  89 /*******************PLL CON3 BITS***************************/
  90
  91 #define PLL_RESET_MSK           (1 << 5)
  92 #define PLL_RESET_W_MSK         (PLL_RESET_MSK << 16)
  93 #define PLL_RESET               (1 << 5)
  94 #define PLL_RESET_RESUME        (0 << 5)
  95
  96 #define PLL_BYPASS_MSK          (1 << 0)
  97 #define PLL_BYPASS              (1 << 0)
  98 #define PLL_NO_BYPASS           (0 << 0)
  99
 100 #define PLL_PWR_DN_MSK          (1 << 1)
 101 #define PLL_PWR_DN_W_MSK        (PLL_PWR_DN_MSK << 16)
 102 #define PLL_PWR_DN              (1 << 1)
 103 #define PLL_PWR_ON              (0 << 1)
 104
 105 #define PLL_STANDBY_MSK         (1 << 2)
 106 #define PLL_STANDBY             (1 << 2)
 107 #define PLL_NO_STANDBY          (0 << 2)
 108 /*******************CLKSEL0 BITS***************************/
 109 //core preiph div
 110 #define CORE_PERIPH_W_MSK       (3 << 22)
 111 #define CORE_PERIPH_MSK         (3 << 6)
 112 #define CORE_PERIPH_2           (0 << 6)
 113 #define CORE_PERIPH_4           (1 << 6)
 114 #define CORE_PERIPH_8           (2 << 6)
 115 #define CORE_PERIPH_16          (3 << 6)
 116 //arm clk pll sel
 117 #define CORE_SEL_PLL_MSK        (1 << 8)
 118 #define CORE_SEL_PLL_W_MSK      (1 << 24)
 119 #define CORE_SEL_APLL           (0 << 8)
 120 #define CORE_SEL_GPLL           (1 << 8)
 121
 122 #define CORE_CLK_DIV_W_MSK      (0x1F << 25)
 123 #define CORE_CLK_DIV_MSK        (0x1F << 9)
 124 #define CORE_CLK_DIV(i)         (((i) - 1) & 0x1F)
 125
 126 #define CPU_SEL_PLL_MSK         (1 << 5)
 127 #define CPU_SEL_PLL_W_MSK       (1 << 21)
 128 #define CPU_SEL_APLL            (0 << 5)
 129 #define CPU_SEL_GPLL            (1 << 5)
 130
 131 #define CPU_CLK_DIV_W_MSK       (0x1F << 16)
 132 #define CPU_CLK_DIV_MSK         (0x1F)
 133 #define CPU_CLK_DIV(i)          (((i) - 1) & 0x1F)
 134
 135 /*******************CLKSEL1 BITS***************************/
 136 //aclk div
 137 #define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
 138
 139 #define CORE_ACLK_W_MSK         (7 << 19)
 140 #define CORE_ACLK_MSK           (7 << 3)
 141 #define CORE_ACLK_11            (0 << 3)
 142 #define CORE_ACLK_21            (1 << 3)
 143 #define CORE_ACLK_31            (2 << 3)
 144 #define CORE_ACLK_41            (3 << 3)
 145 #define CORE_ACLK_81            (4 << 3)
 146 //hclk div
 147 #define ACLK_HCLK_W_MSK         (3 << 24)
 148 #define ACLK_HCLK_MSK           (3 << 8)
 149 #define ACLK_HCLK_11            (0 << 8)
 150 #define ACLK_HCLK_21            (1 << 8)
 151 #define ACLK_HCLK_41            (2 << 8)
 152 // pclk div
 153 #define ACLK_PCLK_W_MSK         (3 << 28)
 154 #define ACLK_PCLK_MSK           (3 << 12)
 155 #define ACLK_PCLK_11            (0 << 12)
 156 #define ACLK_PCLK_21            (1 << 12)
 157 #define ACLK_PCLK_41            (2 << 12)
 158 #define ACLK_PCLK_81            (3 << 12)
 159 // ahb2apb div
 160 #define AHB2APB_W_MSK           (3 << 30)
 161 #define AHB2APB_MSK             (3 << 14)
 162 #define AHB2APB_11              (0 << 14)
 163 #define AHB2APB_21              (1 << 14)
 164 #define AHB2APB_41              (2 << 14)
 165
 166 /*******************MODE BITS***************************/
 167
 168 #define PLL_MODE_MSK(id)        (0x3 << ((id) * 4))
 169 #define PLL_MODE_SLOW(id)       ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
 170 #define PLL_MODE_NORM(id)       ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
 171 #define PLL_MODE_DEEP(id)       ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
 172
 173 /*******************clksel10***************************/
 174
 175 #define PERI_ACLK_DIV_MASK 0x1f
 176 #define PERI_ACLK_DIV_W_MSK     (PERI_ACLK_DIV_MASK << 16)
 177 #define PERI_ACLK_DIV(i)        (((i) - 1) & PERI_ACLK_DIV_MASK)
 178 #define PERI_ACLK_DIV_OFF 0
 179
 180 #define PERI_HCLK_DIV_MASK 0x3
 181 #define PERI_HCLK_DIV_OFF 8
 182
 183 #define PERI_PCLK_DIV_MASK 0x3
 184 #define PERI_PCLK_DIV_OFF 12
 185
 186 /*******************gate BITS***************************/
 187
 188 #define CLK_GATE_CLKID(i)       (16 * (i))
 189 #define CLK_GATE_CLKID_CONS(i)  CRU_CLKGATES_CON((i) / 16)
 190
 191 #define CLK_GATE(i)             (1 << ((i)%16))
 192 #define CLK_UN_GATE(i)          (0)
 193
 194 #define CLK_GATE_W_MSK(i)       (1 << (((i) % 16) + 16))
 195
 196 enum cru_clk_gate {
 197         /* SCU CLK GATE 0 CON */
 198         CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
 199         CLK_GATE_CPU_GPLL_PATH,
 200         CLK_GATE_DDRPHY,
 201         CLK_GATE_ACLK_CPU,
 202
 203         CLK_GATE_HCLK_CPU,
 204         CLK_GATE_PCLK_CPU,
 205         CLK_GATE_ATCLK_CPU,
 206         CLK_GATE_ACLK_CORE,
 207
 208         CLK_GATE_0RES8,
 209         CLK_GATE_I2S0_SRC,
 210         CLK_GATE_I2S0_FRAC,
 211         CLK_GATE_0RES11,
 212
 213         CLK_GATE_0RES12,
 214         CLK_GATE_SPDIF_SRC,
 215         CLK_GATE_SPDIF_FRAC,
 216         CLK_GATE_TESTCLK,
 217
 218         CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
 219         CLK_GATE_TIMER1,
 220         CLK_GATE_TIMER3,
 221         CLK_GATE_JTAG,
 222
 223         CLK_GATE_ACLK_LCDC1_SRC,
 224         CLK_GATE_OTGPHY0,
 225         CLK_GATE_OTGPHY1,
 226         CLK_GATE_DDR_GPLL,
 227
 228         CLK_GATE_UART0_SRC,
 229         CLK_GATE_UART0_FRAC_SRC,
 230         CLK_GATE_UART1_SRC,
 231         CLK_GATE_UART1_FRAC_SRC,
 232
 233         CLK_GATE_UART2_SRC,
 234         CLK_GATE_UART2_FRAC_SRC,
 235         CLK_GATE_UART3_SRC,
 236         CLK_GATE_UART3_FRAC_SRC,
 237
 238         CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
 239         CLK_GATE_ACLK_PERIPH,
 240         CLK_GATE_HCLK_PERIPH,
 241         CLK_GATE_PCLK_PERIPH,
 242
 243         CLK_GATE_SMC_SRC,
 244         CLK_GATE_MAC_SRC,
 245         CLK_GATE_HSADC_SRC,
 246         CLK_GATE_HSADC_FRAC_SRC,
 247
 248         CLK_GATE_SARADC_SRC,
 249         CLK_GATE_SPI0_SRC,
 250         CLK_GATE_SPI1_SRC,
 251         CLK_GATE_MMC0_SRC,
 252
 253         CLK_GATE_MAC_LBTEST,
 254         CLK_GATE_SDIO_SRC,
 255         CLK_GATE_EMMC_SRC,
 256         CLK_GATE_2RES15,
 257
 258         CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
 259         CLK_GATE_DCLK_LCDC0_SRC,
 260         CLK_GATE_DCLK_LCDC1_SRC,
 261         CLK_GATE_PCLKIN_CIF0,
 262
 263         CLK_GATE_TIMER2,
 264         CLK_GATE_TIMER4,
 265         CLK_GATE_HSICPHY_SRC,
 266         CLK_GATE_CIF0_OUT,
 267
 268         CLK_GATE_TIMER5,
 269         CLK_GATE_ACLK_VEPU,
 270         CLK_GATE_HCLK_VEPU,
 271         CLK_GATE_ACLK_VDPU,
 272
 273         CLK_GATE_HCLK_VDPU,
 274         CLK_GATE_3RES13,
 275         CLK_GATE_TIMER6,
 276         CLK_GATE_ACLK_GPU_SRC,
 277
 278         CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
 279         CLK_GATE_PCLK_PERI_AXI_MATRIX,
 280         CLK_GATE_ACLK_CPU_PERI,
 281         CLK_GATE_ACLK_PERI_AXI_MATRIX,
 282
 283         CLK_GATE_ACLK_PEI_NIU,
 284         CLK_GATE_HCLK_USB_PERI,
 285         CLK_GATE_HCLK_PERI_AHB_ARBI,
 286         CLK_GATE_HCLK_EMEM_PERI,
 287
 288         CLK_GATE_HCLK_CPUBUS,
 289         CLK_GATE_HCLK_AHB2APB,
 290         CLK_GATE_ACLK_STRC_SYS,
 291         CLK_GATE_4RES11,
 292
 293         CLK_GATE_ACLK_INTMEM,
 294         CLK_GATE_4RES13,
 295         CLK_GATE_HCLK_IMEM1,
 296         CLK_GATE_HCLK_IMEM0,
 297
 298         CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
 299         CLK_GATE_ACLK_DMAC2,
 300         CLK_GATE_PCLK_EFUSE,
 301         CLK_GATE_PCLK_TZPC,
 302
 303         CLK_GATE_PCLK_GRF,
 304         CLK_GATE_PCLK_PMU,
 305         CLK_GATE_HCLK_ROM,
 306         CLK_GATE_PCLK_DDRUPCTL,
 307
 308         CLK_GATE_ACLK_SMC,
 309         CLK_GATE_HCLK_NANDC,
 310         CLK_GATE_HCLK_SDMMC0,
 311         CLK_GATE_HCLK_SDIO,
 312
 313         CLK_GATE_HCLK_EMMC,
 314         CLK_GATE_HCLK_OTG0,
 315         CLK_GATE_5RES14,
 316         CLK_GATE_5RES15,
 317
 318         CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
 319         CLK_GATE_HCLK_LCDC0,
 320         CLK_GATE_HCLK_LCDC1,
 321         CLK_GATE_ACLK_LCDC1,
 322
 323         CLK_GATE_HCLK_CIF0,
 324         CLK_GATE_ACLK_CIF0,
 325         CLK_GATE_6RES6,
 326         CLK_GATE_6RES7,
 327
 328         CLK_GATE_ACLK_IPP,
 329         CLK_GATE_HCLK_IPP,
 330         CLK_GATE_HCLK_RGA,
 331         CLK_GATE_ACLK_RGA,
 332
 333         CLK_GATE_HCLK_VIO_BUS,
 334         CLK_GATE_ACLK_VIO0,
 335         CLK_GATE_6RES14,
 336         CLK_GATE_6RES15,
 337
 338         CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
 339         CLK_GATE_HCLK_SPDIF,
 340         CLK_GATE_HCLK_I2S0_2CH,
 341         CLK_GATE_HCLK_OTG1,
 342
 343         CLK_GATE_HCLK_HSIC,
 344         CLK_GATE_HCLK_HSADC,
 345         CLK_GATE_HCLK_PIDF,
 346         CLK_GATE_PCLK_TIMER0,
 347
 348         CLK_GATE_7RES8,
 349         CLK_GATE_PCLK_TIMER2,   //same as RK3066B, diff list's mistake
 350         CLK_GATE_PCLK_PWM01,
 351         CLK_GATE_PCLK_PWM23,
 352
 353         CLK_GATE_PCLK_SPI0,
 354         CLK_GATE_PCLK_SPI1,
 355         CLK_GATE_PCLK_SARADC,
 356         CLK_GATE_PCLK_WDT,
 357
 358         CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
 359         CLK_GATE_PCLK_UART1,
 360         CLK_GATE_PCLK_UART2,
 361         CLK_GATE_PCLK_UART3,
 362
 363         CLK_GATE_PCLK_I2C0,
 364         CLK_GATE_PCLK_I2C1,
 365         CLK_GATE_PCLK_I2C2,
 366         CLK_GATE_PCLK_I2C3,
 367
 368         CLK_GATE_PCLK_I2C4,
 369         CLK_GATE_PCLK_GPIO0,
 370         CLK_GATE_PCLK_GPIO1,
 371         CLK_GATE_PCLK_GPIO2,
 372
 373         CLK_GATE_PCLK_GPIO3,
 374         CLK_GATE_ACLK_GPS,
 375         CLK_GATE_8RES14,
 376         CLK_GATE_8RES15,
 377
 378         CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
 379         CLK_GATE_PCLK_DBG,
 380         CLK_GATE_CLK_TRACE,
 381         CLK_GATE_ATCLK,
 382
 383         CLK_GATE_CLK_L2C,
 384         CLK_GATE_ACLK_VIO1,
 385         CLK_GATE_PCLK_PUBL,
 386         CLK_GATE_ACLK_GPU,
 387
 388         CLK_GATE_9RES8,
 389         CLK_GATE_9RES9,
 390         CLK_GATE_9RES10,
 391         CLK_GATE_9RES11,
 392
 393         CLK_GATE_9RES12,
 394         CLK_GATE_9RES13,
 395         CLK_GATE_9RES14,
 396         CLK_GATE_9RES15,
 397
 398         CLK_GATE_MAX,
 399 };
 400
 401 /* for compatible with rk30xx */
 402 #define CLK_GATE_ACLK_CIF1      CLK_GATE_ACLK_CIF0
 403 #define CLK_GATE_ACLK_INTMEM0   CLK_GATE_CLK_L2C
 404 #define CLK_GATE_ACLK_INTMEM1   CLK_GATE_ACLK_INTMEM0
 405 #define CLK_GATE_ACLK_INTMEM2   CLK_GATE_ACLK_INTMEM0
 406 #define CLK_GATE_ACLK_INTMEM3   CLK_GATE_ACLK_INTMEM0
 407
 408 #define SOFT_RST_ID(i)          (16 * (i))
 409
 410 enum cru_soft_reset {
 411         SOFT_RST_PTM_CORE2 = SOFT_RST_ID(0),
 412         SOFT_RST_PTM_CORE3,
 413         SOFT_RST_MCORE,
 414         SOFT_RST_CORE0,
 415
 416         SOFT_RST_CORE1,
 417         SOFT_RST_CORE2,
 418         SOFT_RST_CORE3,
 419         SOFT_RST_MCORE_DBG,
 420
 421         SOFT_RST_CORE0_DBG,
 422         SOFT_RST_CORE1_DBG,
 423         SOFT_RST_CORE2_DBG,
 424         SOFT_RST_CORE3_DBG,
 425
 426         SOFT_RST_CORE0_WDT,
 427         SOFT_RST_CORE1_WDT,
 428         SOFT_RST_STRC_SYS_AXI,
 429         SOFT_RST_L2C,
 430
 431         SOFT_RST_TIMER2 = SOFT_RST_ID(1),
 432         SOFT_RST_CPUSYS_AHB,
 433         SOFT_RST_1RES2,
 434         SOFT_RST_AHB2APB,
 435
 436         SOFT_RST_DMA1,
 437         SOFT_RST_INTMEM,
 438         SOFT_RST_ROM,
 439         SOFT_RST_TIMER4,
 440
 441         SOFT_RST_I2S,
 442         SOFT_RST_TIMER5,
 443         SOFT_RST_SPDIF,
 444         SOFT_RST_TIMER0,
 445
 446         SOFT_RST_TIMER1,
 447         SOFT_RST_TIMER3,
 448         SOFT_RST_EFUSE_APB,
 449         SOFT_RST_TIMER6,
 450
 451         SOFT_RST_GPIO0 = SOFT_RST_ID(2),
 452         SOFT_RST_GPIO1,
 453         SOFT_RST_GPIO2,
 454         SOFT_RST_GPIO3,
 455
 456         SOFT_RST_PTM3,
 457         SOFT_RST_PTM3_ATB,
 458         SOFT_RST_2RES6,
 459         SOFT_RST_UART0,
 460
 461         SOFT_RST_UART1,
 462         SOFT_RST_UART2,
 463         SOFT_RST_UART3,
 464         SOFT_RST_I2C0,
 465
 466         SOFT_RST_I2C1,
 467         SOFT_RST_I2C2,
 468         SOFT_RST_I2C3,
 469         SOFT_RST_I2C4,
 470
 471         SOFT_RST_PWM0 = SOFT_RST_ID(3),
 472         SOFT_RST_PWM1,
 473         SOFT_RST_DAP_PO,
 474         SOFT_RST_DAP,
 475
 476         SOFT_RST_DAP_SYS,
 477         SOFT_RST_TPIU_ATB,
 478         SOFT_RST_PMU_APB,
 479         SOFT_RST_GRF,
 480
 481         SOFT_RST_PMU,
 482         SOFT_RST_PERIPHSYS_AXI,
 483         SOFT_RST_PERIPHSYS_AHB,
 484         SOFT_RST_PERIPHSYS_APB,
 485
 486         SOFT_RST_PERIPH_NIU,
 487         SOFT_RST_CPU_PERI,
 488         SOFT_RST_EMEM_PERI,
 489         SOFT_RST_USB_PERI,
 490
 491         SOFT_RST_DMA2 = SOFT_RST_ID(4),
 492         SOFT_RST_SMC,
 493         SOFT_RST_MAC,
 494         SOFT_RST_GPS,
 495
 496         SOFT_RST_NANDC,
 497         SOFT_RST_USBOTG0,
 498         SOFT_RST_USBPHY0,
 499         SOFT_RST_OTGC0,
 500
 501         SOFT_RST_USBOTG1,
 502         SOFT_RST_USBPHY1,
 503         SOFT_RST_OTGC1,
 504         SOFT_RST_HSICPHY,
 505
 506         SOFT_RST_HSADC,
 507         SOFT_RST_PIDFILTER,
 508         SOFT_RST_TIMER_APB,
 509         SOFT_RST_DDRMSCH,
 510
 511         SOFT_RST_TZPC = SOFT_RST_ID(5),
 512         SOFT_RST_MMC0,
 513         SOFT_RST_SDIO,
 514         SOFT_RST_EMMC,
 515
 516         SOFT_RST_SPI0,
 517         SOFT_RST_SPI1,
 518         SOFT_RST_WDT,
 519         SOFT_RST_SARADC,
 520
 521         SOFT_RST_DDRPHY,
 522         SOFT_RST_DDRPHY_APB,
 523         SOFT_RST_DDRCTRL,
 524         SOFT_RST_DDRCTRL_APB,
 525
 526         SOFT_RST_PTM2,
 527         SOFT_RST_DDRPHY_CTL,
 528         SOFT_RST_CORE2_WDT,
 529         SOFT_RST_CORE3_WDT,
 530
 531         SOFT_RST_6RES0 = SOFT_RST_ID(6),
 532         SOFT_RST_6RES1,
 533         SOFT_RST_VIO0_AXI,
 534         SOFT_RST_VIO_BUS_AHB,
 535
 536         SOFT_RST_LCDC0_AXI,
 537         SOFT_RST_LCDC0_AHB,
 538         SOFT_RST_LCDC0_DCLK,
 539         SOFT_RST_LCDC1_AXI,
 540
 541         SOFT_RST_LCDC1_AHB,
 542         SOFT_RST_LCDC1_DCLK,
 543         SOFT_RST_IPP_AXI,
 544         SOFT_RST_IPP_AHB,
 545
 546         SOFT_RST_RGA_AXI,
 547         SOFT_RST_RGA_AHB,
 548         SOFT_RST_CIF0,
 549         SOFT_RST_PTM2_ATB,//SOFT_RST_6RES15, NO CIF1
 550
 551         SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
 552         SOFT_RST_VCODEC_AHB,
 553         SOFT_RST_VIO1_AXI,
 554         SOFT_RST_CPU_VCODEC,
 555
 556         SOFT_RST_VCODEC_NIU_AXI,
 557         SOFT_RST_HSIC_AHB,
 558         SOFT_RST_CTI2,
 559         SOFT_RST_CTI2_APB,
 560
 561         SOFT_RST_GPU_CORE,
 562         SOFT_RST_GPU_BRIDGE_AXI,
 563         SOFT_RST_GPU_NIU_AXI,
 564         SOFT_RST_CTI3,
 565
 566         SOFT_RST_CTI3_APB,
 567         SOFT_RST_TFUN_ATB,
 568         SOFT_RST_TFUN_APB,
 569         SOFT_RST_CTI4_APB,
 570
 571         SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
 572         SOFT_RST_TRACE,
 573         SOFT_RST_CORE_DBG,
 574         SOFT_RST_DBG_APB,
 575
 576         SOFT_RST_CTI0,
 577         SOFT_RST_CTI0_APB,
 578         SOFT_RST_CTI1,
 579         SOFT_RST_CTI1_APB,
 580
 581         SOFT_RST_PTM_CORE0,
 582         SOFT_RST_PTM_CORE1,
 583         SOFT_RST_PTM0,
 584         SOFT_RST_PTM0_ATB,
 585
 586         SOFT_RST_PTM1,
 587         SOFT_RST_PTM1_ATB,
 588         SOFT_RST_CTM,
 589         SOFT_RST_TS,
 590
 591         SOFT_RST_MAX,
 592 };
 593
 594 /*****cru reg end*****/
 595
 596 static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
 597 {
 598         const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
 599         u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
 600         writel_relaxed(val, reg);
 601         dsb();
 602 }