9 /*****cru reg offset*****/
11 #define CRU_MODE_CON 0x40
12 #define CRU_CLKSEL_CON 0x44
13 #define CRU_CLKGATE_CON 0xd0
14 #define CRU_GLB_SRST_FST 0x100
15 #define CRU_GLB_SRST_SND 0x104
16 #define CRU_SOFTRST_CON 0x110
18 #define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
20 #define CRU_CLKSELS_CON_CNT (35)
21 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
23 #define CRU_CLKGATES_CON_CNT (10)
24 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
26 #define CRU_SOFTRSTS_CON_CNT (9)
27 #define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
29 #define CRU_MISC_CON (0x134)
30 #define CRU_GLB_CNT_TH (0x140)
32 /********************************************************************/
33 #define CRU_GET_REG_BITS_VAL(reg,bits_shift, msk) (((reg) >> (bits_shift))&(msk))
34 #define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
35 #define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
37 #define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
39 /*******************PLL CON0 BITS***************************/
41 #define PLL_CLKFACTOR_SET(val, shift, msk) \
42 ((((val) - 1) & (msk)) << (shift))
44 #define PLL_CLKFACTOR_GET(reg, shift, msk) \
45 ((((reg) >> (shift)) & (msk)) + 1)
47 #define PLL_OD_MSK (0x3f)
48 #define PLL_OD_SHIFT (0x0)
50 #define PLL_CLKOD(val) PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
51 #define PLL_NO(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
53 #define PLL_NO_SHIFT(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
55 #define PLL_CLKOD_SET(val) (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
57 #define PLL_NR_MSK (0x3f)
58 #define PLL_NR_SHIFT (8)
59 #define PLL_CLKR(val) PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
60 #define PLL_NR(reg) PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
62 #define PLL_CLKR_SET(val) (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
64 #define PLUS_PLL_OD_MSK (0xf)
65 #define PLUS_PLL_NO(reg) (PLL_NO(reg) & PLUS_PLL_OD_MSK)
67 #define PLUS_PLL_NR_MSK (0x3f)
68 #define PLUS_PLL_NR(reg) (PLL_NO(reg) & PLUS_PLL_NR_MSK)
70 #define PLUS_PLL_CLKR_SET(val) PLL_CLKR_SET(val & PLUS_PLL_NR_MSK)
71 #define PLUS_PLL_CLKOD_SET(val) PLL_CLKOD_SET(val & PLUS_PLL_OD_MSK)
72 /*******************PLL CON1 BITS***************************/
74 #define PLL_NF_MSK (0xffff)
75 #define PLL_NF_SHIFT (0)
76 #define PLL_CLKF(val) PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
77 #define PLL_NF(reg) PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
78 #define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
80 #define PLUS_PLL_NF_MSK (0x1ff)
81 #define PLUS_PLL_NF(reg) (PLL_NF(reg) & PLUS_PLL_NF_MSK)
82 #define PLUS_PLL_CLKF_SET(val) PLL_CLKF_SET(val & PLUS_PLL_NF_MSK)
83 /*******************PLL CON2 BITS***************************/
85 #define PLL_BWADJ_MSK (0xfff)
86 #define PLL_BWADJ_SHIFT (0)
87 #define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
89 /*******************PLL CON3 BITS***************************/
91 #define PLL_RESET_MSK (1 << 5)
92 #define PLL_RESET_W_MSK (PLL_RESET_MSK << 16)
93 #define PLL_RESET (1 << 5)
94 #define PLL_RESET_RESUME (0 << 5)
96 #define PLL_BYPASS_MSK (1 << 0)
97 #define PLL_BYPASS (1 << 0)
98 #define PLL_NO_BYPASS (0 << 0)
100 #define PLL_PWR_DN_MSK (1 << 1)
101 #define PLL_PWR_DN_W_MSK (PLL_PWR_DN_MSK << 16)
102 #define PLL_PWR_DN (1 << 1)
103 #define PLL_PWR_ON (0 << 1)
105 #define PLL_STANDBY_MSK (1 << 2)
106 #define PLL_STANDBY (1 << 2)
107 #define PLL_NO_STANDBY (0 << 2)
108 /*******************CLKSEL0 BITS***************************/
110 #define CORE_PERIPH_W_MSK (3 << 22)
111 #define CORE_PERIPH_MSK (3 << 6)
112 #define CORE_PERIPH_2 (0 << 6)
113 #define CORE_PERIPH_4 (1 << 6)
114 #define CORE_PERIPH_8 (2 << 6)
115 #define CORE_PERIPH_16 (3 << 6)
117 #define CORE_SEL_PLL_MSK (1 << 8)
118 #define CORE_SEL_PLL_W_MSK (1 << 24)
119 #define CORE_SEL_APLL (0 << 8)
120 #define CORE_SEL_GPLL (1 << 8)
122 #define CORE_CLK_DIV_W_MSK (0x1F << 25)
123 #define CORE_CLK_DIV_MSK (0x1F << 9)
124 #define CORE_CLK_DIV(i) (((i) - 1) & 0x1F)
126 #define CPU_SEL_PLL_MSK (1 << 5)
127 #define CPU_SEL_PLL_W_MSK (1 << 21)
128 #define CPU_SEL_APLL (0 << 5)
129 #define CPU_SEL_GPLL (1 << 5)
131 #define CPU_CLK_DIV_W_MSK (0x1F << 16)
132 #define CPU_CLK_DIV_MSK (0x1F)
133 #define CPU_CLK_DIV(i) (((i) - 1) & 0x1F)
135 /*******************CLKSEL1 BITS***************************/
137 #define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
139 #define CORE_ACLK_W_MSK (7 << 19)
140 #define CORE_ACLK_MSK (7 << 3)
141 #define CORE_ACLK_11 (0 << 3)
142 #define CORE_ACLK_21 (1 << 3)
143 #define CORE_ACLK_31 (2 << 3)
144 #define CORE_ACLK_41 (3 << 3)
145 #define CORE_ACLK_81 (4 << 3)
147 #define ACLK_HCLK_W_MSK (3 << 24)
148 #define ACLK_HCLK_MSK (3 << 8)
149 #define ACLK_HCLK_11 (0 << 8)
150 #define ACLK_HCLK_21 (1 << 8)
151 #define ACLK_HCLK_41 (2 << 8)
153 #define ACLK_PCLK_W_MSK (3 << 28)
154 #define ACLK_PCLK_MSK (3 << 12)
155 #define ACLK_PCLK_11 (0 << 12)
156 #define ACLK_PCLK_21 (1 << 12)
157 #define ACLK_PCLK_41 (2 << 12)
158 #define ACLK_PCLK_81 (3 << 12)
160 #define AHB2APB_W_MSK (3 << 30)
161 #define AHB2APB_MSK (3 << 14)
162 #define AHB2APB_11 (0 << 14)
163 #define AHB2APB_21 (1 << 14)
164 #define AHB2APB_41 (2 << 14)
166 /*******************MODE BITS***************************/
168 #define PLL_MODE_MSK(id) (0x3 << ((id) * 4))
169 #define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
170 #define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
171 #define PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
173 /*******************clksel10***************************/
175 #define PERI_ACLK_DIV_MASK 0x1f
176 #define PERI_ACLK_DIV_W_MSK (PERI_ACLK_DIV_MASK << 16)
177 #define PERI_ACLK_DIV(i) (((i) - 1) & PERI_ACLK_DIV_MASK)
178 #define PERI_ACLK_DIV_OFF 0
180 #define PERI_HCLK_DIV_MASK 0x3
181 #define PERI_HCLK_DIV_OFF 8
183 #define PERI_PCLK_DIV_MASK 0x3
184 #define PERI_PCLK_DIV_OFF 12
186 /*******************gate BITS***************************/
188 #define CLK_GATE_CLKID(i) (16 * (i))
189 #define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
191 #define CLK_GATE(i) (1 << ((i)%16))
192 #define CLK_UN_GATE(i) (0)
194 #define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
197 /* SCU CLK GATE 0 CON */
198 CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
199 CLK_GATE_CPU_GPLL_PATH,
218 CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
223 CLK_GATE_ACLK_LCDC1_SRC,
229 CLK_GATE_UART0_FRAC_SRC,
231 CLK_GATE_UART1_FRAC_SRC,
234 CLK_GATE_UART2_FRAC_SRC,
236 CLK_GATE_UART3_FRAC_SRC,
238 CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
239 CLK_GATE_ACLK_PERIPH,
240 CLK_GATE_HCLK_PERIPH,
241 CLK_GATE_PCLK_PERIPH,
246 CLK_GATE_HSADC_FRAC_SRC,
258 CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
259 CLK_GATE_DCLK_LCDC0_SRC,
260 CLK_GATE_DCLK_LCDC1_SRC,
261 CLK_GATE_PCLKIN_CIF0,
265 CLK_GATE_HSICPHY_SRC,
276 CLK_GATE_ACLK_GPU_SRC,
278 CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
279 CLK_GATE_PCLK_PERI_AXI_MATRIX,
280 CLK_GATE_ACLK_CPU_PERI,
281 CLK_GATE_ACLK_PERI_AXI_MATRIX,
283 CLK_GATE_ACLK_PEI_NIU,
284 CLK_GATE_HCLK_USB_PERI,
285 CLK_GATE_HCLK_PERI_AHB_ARBI,
286 CLK_GATE_HCLK_EMEM_PERI,
288 CLK_GATE_HCLK_CPUBUS,
289 CLK_GATE_HCLK_AHB2APB,
290 CLK_GATE_ACLK_STRC_SYS,
293 CLK_GATE_ACLK_INTMEM,
298 CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
306 CLK_GATE_PCLK_DDRUPCTL,
310 CLK_GATE_HCLK_SDMMC0,
318 CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
333 CLK_GATE_HCLK_VIO_BUS,
338 CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
340 CLK_GATE_HCLK_I2S0_2CH,
346 CLK_GATE_PCLK_TIMER0,
349 CLK_GATE_PCLK_TIMER2, //same as RK3066B, diff list's mistake
355 CLK_GATE_PCLK_SARADC,
358 CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
378 CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
401 /* for compatible with rk30xx */
402 #define CLK_GATE_ACLK_CIF1 CLK_GATE_ACLK_CIF0
403 #define CLK_GATE_ACLK_INTMEM0 CLK_GATE_CLK_L2C
404 #define CLK_GATE_ACLK_INTMEM1 CLK_GATE_ACLK_INTMEM0
405 #define CLK_GATE_ACLK_INTMEM2 CLK_GATE_ACLK_INTMEM0
406 #define CLK_GATE_ACLK_INTMEM3 CLK_GATE_ACLK_INTMEM0
408 #define SOFT_RST_ID(i) (16 * (i))
410 enum cru_soft_reset {
411 SOFT_RST_PTM_CORE2 = SOFT_RST_ID(0),
428 SOFT_RST_STRC_SYS_AXI,
431 SOFT_RST_TIMER2 = SOFT_RST_ID(1),
451 SOFT_RST_GPIO0 = SOFT_RST_ID(2),
471 SOFT_RST_PWM0 = SOFT_RST_ID(3),
482 SOFT_RST_PERIPHSYS_AXI,
483 SOFT_RST_PERIPHSYS_AHB,
484 SOFT_RST_PERIPHSYS_APB,
491 SOFT_RST_DMA2 = SOFT_RST_ID(4),
511 SOFT_RST_TZPC = SOFT_RST_ID(5),
524 SOFT_RST_DDRCTRL_APB,
531 SOFT_RST_6RES0 = SOFT_RST_ID(6),
534 SOFT_RST_VIO_BUS_AHB,
549 SOFT_RST_PTM2_ATB,//SOFT_RST_6RES15, NO CIF1
551 SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
556 SOFT_RST_VCODEC_NIU_AXI,
562 SOFT_RST_GPU_BRIDGE_AXI,
563 SOFT_RST_GPU_NIU_AXI,
571 SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
594 /*****cru reg end*****/
596 static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
598 const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
599 u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
600 writel_relaxed(val, reg);