arch/arm/mach-rockchip/cpu_axi.h

   1 #ifndef __CPU_AXI_H
   2 #define __CPU_AXI_H
   3
   4 #define CPU_AXI_QOS_PRIORITY    0x08
   5 #define CPU_AXI_QOS_MODE        0x0c
   6 #define CPU_AXI_QOS_BANDWIDTH   0x10
   7 #define CPU_AXI_QOS_SATURATION  0x14
   8 #define CPU_AXI_QOS_EXTCONTROL  0x18
   9
  10 #define CPU_AXI_QOS_MODE_NONE           0
  11 #define CPU_AXI_QOS_MODE_FIXED          1
  12 #define CPU_AXI_QOS_MODE_LIMITER        2
  13 #define CPU_AXI_QOS_MODE_REGULATOR      3
  14
  15 #define CPU_AXI_QOS_PRIORITY_LEVEL(h, l)        ((((h) & 3) << 2) | ((l) & 3))
  16 #define CPU_AXI_SET_QOS_PRIORITY(h, l, base) \
  17         writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), base + CPU_AXI_QOS_PRIORITY)
  18
  19 #define CPU_AXI_SET_QOS_MODE(mode, base) \
  20         writel_relaxed((mode) & 3, base + CPU_AXI_QOS_MODE)
  21
  22 #define CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base) \
  23         writel_relaxed((bandwidth) & 0x7ff, base + CPU_AXI_QOS_BANDWIDTH)
  24
  25 #define CPU_AXI_SET_QOS_SATURATION(saturation, base) \
  26         writel_relaxed((saturation) & 0x3ff, base + CPU_AXI_QOS_SATURATION)
  27
  28 #define CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base) \
  29         writel_relaxed((extcontrol) & 7, base + CPU_AXI_QOS_EXTCONTROL)
  30
  31 #define CPU_AXI_QOS_NUM_REGS 5
  32 #define CPU_AXI_SAVE_QOS(array, base) do { \
  33         array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
  34         array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
  35         array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
  36         array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
  37         array[4] = readl_relaxed(base + CPU_AXI_QOS_EXTCONTROL); \
  38 } while (0)
  39 #define CPU_AXI_RESTORE_QOS(array, base) do { \
  40         writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
  41         writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
  42         writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
  43         writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
  44         writel_relaxed(array[4], base + CPU_AXI_QOS_EXTCONTROL); \
  45 } while (0)
  46
  47 #define RK3188_CPU_AXI_DMAC_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x1000)
  48 #define RK3188_CPU_AXI_CPU0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x2000)
  49 #define RK3188_CPU_AXI_CPU1R_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2080)
  50 #define RK3188_CPU_AXI_CPU1W_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2100)
  51 #define RK3188_CPU_AXI_PERI_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x4000)
  52 #define RK3188_CPU_AXI_GPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x5000)
  53 #define RK3188_CPU_AXI_VPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x6000)
  54 #define RK3188_CPU_AXI_LCDC0_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7000)
  55 #define RK3188_CPU_AXI_CIF0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7080)
  56 #define RK3188_CPU_AXI_IPP_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7100)
  57 #define RK3188_CPU_AXI_LCDC1_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7180)
  58 #define RK3188_CPU_AXI_CIF1_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7200)
  59 #define RK3188_CPU_AXI_RGA_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7280)
  60
  61 /* service core */
  62 #define RK3288_SERVICE_CORE_VIRT                RK_CPU_AXI_BUS_VIRT
  63 #define RK3288_CPU_AXI_CPUM_R_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x80)
  64 #define RK3288_CPU_AXI_CPUM_W_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x100)
  65 #define RK3288_CPU_AXI_CPUP_QOS_VIRT            (RK3288_SERVICE_CORE_VIRT + 0x0)
  66 /* service dmac */
  67 #define RK3288_SERVICE_DMAC_VIRT                (RK3288_SERVICE_CORE_VIRT + RK3288_SERVICE_CORE_SIZE)
  68 #define RK3288_CPU_AXI_BUS_DMAC_QOS_VIRT        (RK3288_SERVICE_DMAC_VIRT + 0x0)
  69 #define RK3288_CPU_AXI_CCP_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x180)
  70 #define RK3288_CPU_AXI_CRYPTO_QOS_VIRT          (RK3288_SERVICE_DMAC_VIRT + 0x100)
  71 #define RK3288_CPU_AXI_CCS_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x200)
  72 #define RK3288_CPU_AXI_HOST_QOS_VIRT            (RK3288_SERVICE_DMAC_VIRT + 0x80)
  73 /* service gpu */
  74 #define RK3288_SERVICE_GPU_VIRT                 (RK3288_SERVICE_DMAC_VIRT + RK3288_SERVICE_DMAC_SIZE)
  75 #define RK3288_CPU_AXI_GPU_R_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x0)
  76 #define RK3288_CPU_AXI_GPU_W_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x80)
  77 /* service peri */
  78 #define RK3288_SERVICE_PERI_VIRT                (RK3288_SERVICE_GPU_VIRT + RK3288_SERVICE_GPU_SIZE)
  79 #define RK3288_CPU_AXI_PERI_QOS_VIRT            (RK3288_SERVICE_PERI_VIRT + 0x0)
  80 /* service bus */
  81 #define RK3288_SERVICE_BUS_VIRT                 (RK3288_SERVICE_PERI_VIRT + RK3288_SERVICE_PERI_SIZE)
  82 /* service vio */
  83 #define RK3288_SERVICE_VIO_VIRT                 (RK3288_SERVICE_BUS_VIRT + RK3288_SERVICE_BUS_SIZE)
  84 #define RK3288_CPU_AXI_VIO0_IEP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x500)
  85 #define RK3288_CPU_AXI_VIO0_VIP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x480)
  86 #define RK3288_CPU_AXI_VIO0_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x400)
  87 #define RK3288_CPU_AXI_VIO1_ISP_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x900)
  88 #define RK3288_CPU_AXI_VIO1_ISP_W0_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x100)
  89 #define RK3288_CPU_AXI_VIO1_ISP_W1_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x180)
  90 #define RK3288_CPU_AXI_VIO1_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x0)
  91 #define RK3288_CPU_AXI_VIO2_RGA_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x800)
  92 #define RK3288_CPU_AXI_VIO2_RGA_W_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x880)
  93 /* service video */
  94 #define RK3288_SERVICE_VIDEO_VIRT               (RK3288_SERVICE_VIO_VIRT + RK3288_SERVICE_VIO_SIZE)
  95 #define RK3288_CPU_AXI_VIDEO_QOS_VIRT           (RK3288_SERVICE_VIDEO_VIRT + 0x0)
  96 /* service hevc */
  97 #define RK3288_SERVICE_HEVC_VIRT                (RK3288_SERVICE_VIDEO_VIRT + RK3288_SERVICE_VIDEO_SIZE)
  98 #define RK3288_CPU_AXI_HEVC_R_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x0)
  99 #define RK3288_CPU_AXI_HEVC_W_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x100)
 100
 101 #endif