arch/arm/mach-rockchip/ddr_freq.c

   1 #define pr_fmt(fmt) "ddrfreq: " fmt
   2 #include <linux/clk.h>
   3 #include <linux/fb.h>
   4 #include <linux/cpu.h>
   5 #include <linux/cpufreq.h>
   6 #include <linux/delay.h>
   7 #include <linux/freezer.h>
   8 #include <linux/fs.h>
   9 #include <linux/kthread.h>
  10 #include <linux/miscdevice.h>
  11 #include <linux/module.h>
  12 #include <linux/reboot.h>
  13 #include <linux/slab.h>
  14 #include <linux/uaccess.h>
  15 #include <linux/sched/rt.h>
  16 #include <linux/of.h>
  17 #include <linux/fb.h>
  18 #include <linux/input.h>
  19 #include <asm/cacheflush.h>
  20 #include <asm/tlbflush.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/rockchip/common.h>
  23 #include <linux/rockchip/dvfs.h>
  24 #include <dt-bindings/clock/ddr.h>
  25 #include <asm/io.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/rockchip/iomap.h>
  28 static struct dvfs_node *clk_cpu_dvfs_node = NULL;
  29 static int ddr_boost = 0;
  30
  31
  32 enum {
  33         DEBUG_DDR = 1U << 0,
  34         DEBUG_VIDEO_STATE = 1U << 1,
  35         DEBUG_SUSPEND = 1U << 2,
  36         DEBUG_VERBOSE = 1U << 3,
  37 };
  38 static int debug_mask = DEBUG_DDR;
  39
  40 module_param(debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  41 #define dprintk(mask, fmt, ...) do { if (mask & debug_mask) pr_info(fmt, ##__VA_ARGS__); } while (0)
  42
  43 #define MHZ     (1000*1000)
  44 #define KHZ     1000
  45
  46 struct ddr {
  47         struct dvfs_node *clk_dvfs_node;
  48         unsigned long normal_rate;
  49         unsigned long video_rate;
  50         unsigned long dualview_rate;
  51         unsigned long idle_rate;
  52         unsigned long suspend_rate;
  53         unsigned long reboot_rate;
  54         bool auto_freq;
  55         bool auto_self_refresh;
  56         char *mode;
  57         unsigned long sys_status;
  58         struct task_struct *task;
  59         wait_queue_head_t wait;
  60 };
  61 static struct ddr ddr;
  62
  63 module_param_named(sys_status, ddr.sys_status, ulong, S_IRUGO);
  64 module_param_named(auto_self_refresh, ddr.auto_self_refresh, bool, S_IRUGO);
  65 module_param_named(mode, ddr.mode, charp, S_IRUGO);
  66
  67 static noinline void ddrfreq_set_sys_status(int status)
  68 {
  69         ddr.sys_status |= status;
  70         wake_up(&ddr.wait);
  71 }
  72
  73 static noinline void ddrfreq_clear_sys_status(int status)
  74 {
  75         ddr.sys_status &= ~status;
  76         wake_up(&ddr.wait);
  77 }
  78
  79 static void ddrfreq_mode(bool auto_self_refresh, unsigned long *target_rate, char *name)
  80 {
  81         unsigned int min_rate, max_rate;
  82         int freq_limit_en;
  83
  84         ddr.mode = name;
  85         if (auto_self_refresh != ddr.auto_self_refresh) {
  86                 ddr_set_auto_self_refresh(auto_self_refresh);
  87                 ddr.auto_self_refresh = auto_self_refresh;
  88                 dprintk(DEBUG_DDR, "change auto self refresh to %d when %s\n", auto_self_refresh, name);
  89         }
  90         if (*target_rate != dvfs_clk_get_rate(ddr.clk_dvfs_node)) {
  91                 freq_limit_en = dvfs_clk_get_limit(clk_cpu_dvfs_node, &min_rate, &max_rate);
  92                 dvfs_clk_enable_limit(clk_cpu_dvfs_node, 600000000, -1);
  93                 if (dvfs_clk_set_rate(ddr.clk_dvfs_node, *target_rate) == 0) {
  94                         *target_rate = dvfs_clk_get_rate(ddr.clk_dvfs_node);
  95                         dprintk(DEBUG_DDR, "change freq to %lu MHz when %s\n", *target_rate / MHZ, name);
  96                 }
  97                 if (freq_limit_en) {
  98                         dvfs_clk_enable_limit(clk_cpu_dvfs_node, min_rate, max_rate);
  99                 } else {
 100                         dvfs_clk_disable_limit(clk_cpu_dvfs_node);
 101                 }
 102         }
 103 }
 104
 105 static void ddr_freq_input_event(struct input_handle *handle, unsigned int type,
 106                 unsigned int code, int value)
 107 {
 108         if (type == EV_ABS)
 109                 ddr_boost = 1;
 110 }
 111
 112 static int ddr_freq_input_connect(struct input_handler *handler,
 113                 struct input_dev *dev, const struct input_device_id *id)
 114 {
 115         struct input_handle *handle;
 116         int error;
 117
 118         handle = kzalloc(sizeof(struct input_handle), GFP_KERNEL);
 119         if (!handle)
 120                 return -ENOMEM;
 121
 122         handle->dev = dev;
 123         handle->handler = handler;
 124         handle->name = "ddr_freq";
 125
 126         error = input_register_handle(handle);
 127         if (error)
 128                 goto err2;
 129
 130         error = input_open_device(handle);
 131         if (error)
 132                 goto err1;
 133
 134         return 0;
 135 err1:
 136         input_unregister_handle(handle);
 137 err2:
 138         kfree(handle);
 139         return error;
 140 }
 141
 142 static void ddr_freq_input_disconnect(struct input_handle *handle)
 143 {
 144         input_close_device(handle);
 145         input_unregister_handle(handle);
 146         kfree(handle);
 147 }
 148
 149 static const struct input_device_id ddr_freq_ids[] = {
 150
 151         {
 152                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
 153                         INPUT_DEVICE_ID_MATCH_ABSBIT,
 154                 .evbit = { BIT_MASK(EV_ABS) },
 155                 .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
 156                         BIT_MASK(ABS_MT_POSITION_X) |
 157                         BIT_MASK(ABS_MT_POSITION_Y) },
 158         },
 159
 160         {
 161                 .flags = INPUT_DEVICE_ID_MATCH_KEYBIT |
 162                         INPUT_DEVICE_ID_MATCH_ABSBIT,
 163                 .keybit = { [BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH) },
 164                 .absbit = { [BIT_WORD(ABS_X)] =
 165                         BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
 166         },
 167
 168         {
 169                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
 170                 .evbit = { BIT_MASK(EV_KEY) },
 171         },
 172         { },
 173 };
 174
 175 static struct input_handler ddr_freq_input_handler = {
 176         .event          = ddr_freq_input_event,
 177         .connect        = ddr_freq_input_connect,
 178         .disconnect     = ddr_freq_input_disconnect,
 179         .name           = "ddr_freq",
 180         .id_table       = ddr_freq_ids,
 181 };
 182
 183 enum ddr_bandwidth_id{
 184     ddrbw_wr_num=0,
 185     ddrbw_rd_num,
 186     ddrbw_act_num,
 187     ddrbw_time_num,
 188     ddrbw_eff,
 189     ddrbw_id_end
 190 };
 191
 192
 193
 194 #define DDR_BOOST_HOLD_MS       300
 195 #define HIGH_LOAD_HOLD_MS       300
 196 #define HIGH_LOAD_DELAY_MS      0
 197 #define LOW_LOAD_DELAY_MS       200
 198 #define DDR_BOOST_HOLD          (DDR_BOOST_HOLD_MS/ddrbw_work_delay_ms)
 199 #define HIGH_LOAD_HOLD          (DDR_BOOST_HOLD_MS/ddrbw_work_delay_ms)
 200 #define HIGH_LOAD_DELAY         (HIGH_LOAD_DELAY_MS/ddrbw_work_delay_ms)
 201 #define LOW_LOAD_DELAY          (LOW_LOAD_DELAY_MS/ddrbw_work_delay_ms)
 202 #define DDR_RATE_NORMAL         240000000
 203 #define DDR_RATE_BOOST          324000000
 204 #define DDR_RATE_HIGH_LOAD      533000000
 205 #define DDR_RATE_1080P          240000000
 206 #define DDR_RATE_4K             300000000
 207 #define HIGH_LOAD_NORMAL        70
 208 #define HGIH_LOAD_VIDEO         50
 209
 210 static struct workqueue_struct *ddr_freq_wq;
 211 static u32 high_load = HIGH_LOAD_NORMAL;
 212 static u32 ddrbw_work_delay_ms = 20;
 213 static u32 ddr_rate_normal = DDR_RATE_NORMAL;
 214 static u32 ddr_rate_boost = DDR_RATE_BOOST;
 215 static u32 ddr_rate_high_load = DDR_RATE_HIGH_LOAD;
 216
 217
 218 //#define  ddr_monitor_start() grf_writel(0xc000c000,RK3288_GRF_SOC_CON4)
 219 #define  ddr_monitor_start() grf_writel((((readl_relaxed(RK_PMU_VIRT + 0x9c)>>13)&7)==3)?0xc000c000:0xe000e000,RK3288_GRF_SOC_CON4)
 220 #define  ddr_monitor_stop() grf_writel(0xc0000000,RK3288_GRF_SOC_CON4)
 221
 222 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
 223 #define grf_writel(v, offset)   do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
 224
 225
 226 void ddr_bandwidth_get(u32 *ch0_eff, u32 *ch1_eff)
 227 {
 228         u32 ddr_bw_val[2][ddrbw_id_end];
 229         u64 temp64;
 230         int i, j;
 231
 232         for(j = 0; j < 2; j++) {
 233                 for(i = 0; i < ddrbw_eff; i++ ){
 234                         ddr_bw_val[j][i] = grf_readl(RK3288_GRF_SOC_STATUS11+i*4+j*16);
 235                 }
 236         }
 237
 238         temp64 = ((u64)ddr_bw_val[0][0]+ddr_bw_val[0][1])*4*100;
 239         do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
 240         ddr_bw_val[0][ddrbw_eff] = temp64;
 241         *ch0_eff = temp64;
 242
 243         temp64 = ((u64)ddr_bw_val[1][0]+ddr_bw_val[1][1])*4*100;
 244         do_div(temp64, ddr_bw_val[1][ddrbw_time_num]);
 245         ddr_bw_val[1][ddrbw_eff] = temp64;
 246         *ch1_eff = temp64;
 247 }
 248
 249
 250 static void ddrbw_work_fn(struct work_struct *work)
 251 {
 252         unsigned long rate;
 253         u32 ch0_eff, ch1_eff;
 254         static u32 ddr_boost_hold=0, high_load_hold=0;
 255         static u32 high_load_delay = 0, low_load_delay = 0;
 256
 257         ddr_monitor_stop();
 258         ddr_bandwidth_get(&ch0_eff, &ch1_eff);
 259
 260         if (ddr_boost) {
 261                 ddr_boost = 0;
 262                 //dvfs_clk_set_rate(ddr.clk_dvfs_node, DDR_BOOST_RATE);
 263                 if (!high_load_hold && !low_load_delay) {
 264                         rate = ddr_rate_boost;
 265                         ddrfreq_mode(false, &rate, "boost");
 266                         ddr_boost_hold = DDR_BOOST_HOLD;
 267                 }
 268         } else if(!ddr_boost_hold && ((ch0_eff>high_load)||(ch1_eff>high_load))){
 269                 low_load_delay = LOW_LOAD_DELAY;
 270                 if (!high_load_delay) {
 271                         //dvfs_clk_set_rate(ddr.clk_dvfs_node, HIGH_LOAD_RATE);
 272                         rate = ddr_rate_high_load;
 273                         ddrfreq_mode(false, &rate, "high load");
 274                         high_load_hold = HIGH_LOAD_HOLD;
 275                 } else {
 276                         high_load_delay--;
 277                 }
 278         } else {
 279                 if (ddr_boost_hold) {
 280                         ddr_boost_hold--;
 281                 } else if (high_load_hold) {
 282                         high_load_hold--;
 283                 } else {
 284                         high_load_delay = HIGH_LOAD_DELAY;
 285                         //dvfs_clk_set_rate(ddr.clk_dvfs_node, DDR_NORMAL_RATE);
 286                         if (!low_load_delay) {
 287                                 rate = ddr_rate_normal;
 288                                 ddrfreq_mode(false, &rate, "normal");
 289                         } else {
 290                                 low_load_delay--;
 291                         }
 292                 }
 293           }
 294
 295         ddr_monitor_start();
 296
 297         queue_delayed_work_on(0, ddr_freq_wq, to_delayed_work(work), HZ*ddrbw_work_delay_ms/1000);
 298 }
 299
 300 static DECLARE_DELAYED_WORK(ddrbw_work, ddrbw_work_fn);
 301
 302 static noinline void ddrfreq_work(unsigned long sys_status)
 303 {
 304         static struct clk *cpu = NULL;
 305         static struct clk *gpu = NULL;
 306         unsigned long s = sys_status;
 307
 308         if (!cpu)
 309                 cpu = clk_get(NULL, "cpu");
 310         if (!gpu)
 311                 gpu = clk_get(NULL, "gpu");
 312
 313         dprintk(DEBUG_VERBOSE, "sys_status %02lx\n", sys_status);
 314
 315         if (ddr.auto_freq)
 316                 cancel_delayed_work_sync(&ddrbw_work);
 317
 318         if (ddr.reboot_rate && (s & SYS_STATUS_REBOOT)) {
 319                 ddrfreq_mode(false, &ddr.reboot_rate, "shutdown/reboot");
 320         } else if (ddr.suspend_rate && (s & SYS_STATUS_SUSPEND)) {
 321                 ddrfreq_mode(true, &ddr.suspend_rate, "suspend");
 322         } else if (ddr.dualview_rate &&
 323                 (s & SYS_STATUS_LCDC0) && (s & SYS_STATUS_LCDC1)) {
 324                 ddrfreq_mode(false, &ddr.dualview_rate, "dual-view");
 325         } else if (ddr.video_rate &&
 326                 ((s & SYS_STATUS_VIDEO_720P)||(s & SYS_STATUS_VIDEO_1080P))) {
 327                 ddrfreq_mode(false, &ddr.video_rate, "video");
 328         } else if (ddr.idle_rate
 329                 && !(s & SYS_STATUS_GPU)
 330                 && !(s & SYS_STATUS_RGA)
 331                 && !(s & SYS_STATUS_CIF0)
 332                 && !(s & SYS_STATUS_CIF1)
 333                 && (clk_get_rate(cpu) < 816 * MHZ)
 334                 && (clk_get_rate(gpu) <= 200 * MHZ)
 335                 ) {
 336                 ddrfreq_mode(false, &ddr.idle_rate, "idle");
 337         } else {
 338                 if (ddr.auto_freq)
 339                         queue_delayed_work_on(0, ddr_freq_wq, &ddrbw_work, 0);
 340                 else
 341                         ddrfreq_mode(false, &ddr.normal_rate, "normal");
 342         }
 343 }
 344
 345 static int ddrfreq_task(void *data)
 346 {
 347         set_freezable();
 348
 349         do {
 350                 unsigned long status = ddr.sys_status;
 351                 ddrfreq_work(status);
 352                 wait_event_freezable(ddr.wait, (status != ddr.sys_status) || kthread_should_stop());
 353         } while (!kthread_should_stop());
 354
 355         return 0;
 356 }
 357
 358 static int video_state_release(struct inode *inode, struct file *file)
 359 {
 360         dprintk(DEBUG_VIDEO_STATE, "video_state release\n");
 361         ddrfreq_clear_sys_status(SYS_STATUS_VIDEO);
 362         return 0;
 363 }
 364
 365 #define VIDEO_LOW_RESOLUTION       (1080*720)
 366 static ssize_t video_state_write(struct file *file, const char __user *buffer,
 367                                  size_t count, loff_t *ppos)
 368 {
 369         char state;
 370         char *cookie_pot;
 371         char *p;
 372         char *buf = vzalloc(count);
 373         uint32_t v_width=0,v_height=0,v_sync=0;
 374         cookie_pot = buf;
 375
 376         if(!buf)
 377                 return -ENOMEM;
 378
 379         if (count < 1){
 380                 vfree(buf);
 381                 return -EPERM;
 382         }
 383
 384         if (copy_from_user(cookie_pot, buffer, count)) {
 385                 vfree(buf);
 386                 return -EFAULT;
 387         }
 388
 389         dprintk(DEBUG_VIDEO_STATE, "video_state write %s,len %d\n", cookie_pot,count);
 390
 391         state=cookie_pot[0];
 392         if( (count>=3) && (cookie_pot[2]=='w') )
 393         {
 394                 strsep(&cookie_pot,",");
 395                 strsep(&cookie_pot,"=");
 396                 p=strsep(&cookie_pot,",");
 397                 v_width = simple_strtol(p,NULL,10);
 398                 strsep(&cookie_pot,"=");
 399                 p=strsep(&cookie_pot,",");
 400                 v_height= simple_strtol(p,NULL,10);
 401                 strsep(&cookie_pot,"=");
 402                 p=strsep(&cookie_pot,",");
 403                 v_sync= simple_strtol(p,NULL,10);
 404                 dprintk(DEBUG_VIDEO_STATE, "video_state %c,width=%d,height=%d,sync=%d\n", state,v_width,v_height,v_sync);
 405         }
 406
 407         switch (state) {
 408         case '0':
 409                 high_load = HIGH_LOAD_NORMAL;
 410                 ddr_rate_normal = DDR_RATE_NORMAL;
 411                 ddr_rate_high_load = DDR_RATE_HIGH_LOAD;
 412                 if (!ddr.auto_freq)
 413                         ddrfreq_clear_sys_status(SYS_STATUS_VIDEO);
 414                 break;
 415         case '1':
 416                 high_load = HGIH_LOAD_VIDEO;
 417                 ddr_rate_normal = DDR_RATE_1080P;
 418                 ddr_rate_high_load = DDR_RATE_4K;
 419                 if( (v_width == 0) && (v_height == 0)){
 420                         if (!ddr.auto_freq)
 421                                 ddrfreq_set_sys_status(SYS_STATUS_VIDEO_1080P);
 422                 }
 423                 else if(v_sync==1){
 424                         //if(ddr.video_low_rate && ((v_width*v_height) <= VIDEO_LOW_RESOLUTION) )
 425                         //      ddrfreq_set_sys_status(SYS_STATUS_VIDEO_720P);
 426                         //else
 427                         if (!ddr.auto_freq)
 428                                 ddrfreq_set_sys_status(SYS_STATUS_VIDEO_1080P);
 429                 }
 430                 else{
 431                         if (!ddr.auto_freq)
 432                                 ddrfreq_clear_sys_status(SYS_STATUS_VIDEO);
 433                 }
 434                 break;
 435         default:
 436                 vfree(buf);
 437                 return -EINVAL;
 438
 439         }
 440         vfree(buf);
 441         return count;
 442 }
 443
 444 static const struct file_operations video_state_fops = {
 445         .owner  = THIS_MODULE,
 446         .release= video_state_release,
 447         .write  = video_state_write,
 448 };
 449
 450 static struct miscdevice video_state_dev = {
 451         .fops   = &video_state_fops,
 452         .name   = "video_state",
 453         .minor  = MISC_DYNAMIC_MINOR,
 454 };
 455 /*
 456 static int ddrfreq_clk_event(int status, unsigned long event)
 457 {
 458         switch (event) {
 459         case PRE_RATE_CHANGE:
 460                 ddrfreq_set_sys_status(status);
 461                 break;
 462         case POST_RATE_CHANGE:
 463         case ABORT_RATE_CHANGE:
 464                 ddrfreq_clear_sys_status(status);
 465                 break;
 466         }
 467         return NOTIFY_OK;
 468 }
 469 */
 470 #define CLK_NOTIFIER(name, status) \
 471 static int ddrfreq_clk_##name##_event(struct notifier_block *this, unsigned long event, void *ptr) \
 472 { \
 473         return ddrfreq_clk_event(SYS_STATUS_##status, event); \
 474 } \
 475 static struct notifier_block ddrfreq_clk_##name##_notifier = { .notifier_call = ddrfreq_clk_##name##_event };
 476
 477 #define REGISTER_CLK_NOTIFIER(name) \
 478 do { \
 479         struct clk *clk = clk_get(NULL, #name); \
 480         clk_notifier_register(clk, &ddrfreq_clk_##name##_notifier); \
 481         clk_put(clk); \
 482 } while (0)
 483
 484 #define UNREGISTER_CLK_NOTIFIER(name) \
 485 do { \
 486         struct clk *clk = clk_get(NULL, #name); \
 487         clk_notifier_unregister(clk, &ddrfreq_clk_##name##_notifier); \
 488         clk_put(clk); \
 489 } while (0)
 490 /*
 491 CLK_NOTIFIER(pd_gpu, GPU);
 492 CLK_NOTIFIER(pd_rga, RGA);
 493 CLK_NOTIFIER(pd_cif0, CIF0);
 494 CLK_NOTIFIER(pd_cif1, CIF1);
 495 CLK_NOTIFIER(pd_lcdc0, LCDC0);
 496 CLK_NOTIFIER(pd_lcdc1, LCDC1);
 497 */
 498 static int ddrfreq_reboot_notifier_event(struct notifier_block *this, unsigned long event, void *ptr)
 499 {
 500         u32 timeout = 1000; // 10s
 501         ddrfreq_set_sys_status(SYS_STATUS_REBOOT);
 502         while (dvfs_clk_get_rate(ddr.clk_dvfs_node) != ddr.reboot_rate && --timeout) {
 503                 msleep(10);
 504         }
 505         if (!timeout) {
 506                 pr_err("failed to set ddr clk from %luMHz to %luMHz when shutdown/reboot\n", dvfs_clk_get_rate(ddr.clk_dvfs_node) / MHZ, ddr.reboot_rate / MHZ);
 507         }
 508         return NOTIFY_OK;
 509 }
 510
 511 static struct notifier_block ddrfreq_reboot_notifier = {
 512         .notifier_call = ddrfreq_reboot_notifier_event,
 513 };
 514
 515 int of_init_ddr_freq_table(void)
 516 {
 517         struct device_node *clk_ddr_dev_node;
 518         const struct property *prop;
 519         const __be32 *val;
 520         int nr;
 521
 522         clk_ddr_dev_node = of_find_node_by_name(NULL, "clk_ddr");
 523         if (IS_ERR_OR_NULL(clk_ddr_dev_node)) {
 524                 pr_err("%s: get clk ddr dev node err\n", __func__);
 525                 return PTR_ERR(clk_ddr_dev_node);
 526         }
 527
 528         prop = of_find_property(clk_ddr_dev_node, "auto_freq", NULL);
 529         if (prop && prop->value)
 530                 ddr.auto_freq = be32_to_cpup(prop->value);
 531
 532         prop = of_find_property(clk_ddr_dev_node, "freq_table", NULL);
 533         if (!prop)
 534                 return -ENODEV;
 535         if (!prop->value)
 536                 return -ENODATA;
 537
 538         nr = prop->length / sizeof(u32);
 539         if (nr % 2) {
 540                 pr_err("%s: Invalid freq list\n", __func__);
 541                 return -EINVAL;
 542         }
 543
 544         val = prop->value;
 545         while (nr) {
 546                 unsigned long status = be32_to_cpup(val++);
 547                 unsigned long rate = be32_to_cpup(val++) * 1000;
 548
 549                 if (status & SYS_STATUS_NORMAL)
 550                         ddr.normal_rate = rate;
 551                 if (status & SYS_STATUS_SUSPEND)
 552                         ddr.suspend_rate = rate;
 553                 if ((status & SYS_STATUS_VIDEO_720P)||(status & SYS_STATUS_VIDEO_720P))
 554                         ddr.video_rate = rate;
 555                 if ((status & SYS_STATUS_LCDC0)&&(status & SYS_STATUS_LCDC1))
 556                         ddr.dualview_rate = rate;
 557                 if (status & SYS_STATUS_IDLE)
 558                         ddr.idle_rate= rate;
 559                 if (status & SYS_STATUS_REBOOT)
 560                         ddr.reboot_rate= rate;
 561
 562                 nr -= 2;
 563         }
 564
 565         return 0;
 566 }
 567 #if 0//defined(CONFIG_RK_PM_TESTS)
 568 static void ddrfreq_tst_init(void);
 569 #endif
 570
 571 static int ddr_freq_suspend_notifier_call(struct notifier_block *self,
 572                                 unsigned long action, void *data)
 573 {
 574         struct fb_event *event = data;
 575         int blank_mode = *((int *)event->data);
 576
 577         if (action == FB_EARLY_EVENT_BLANK) {
 578                 switch (blank_mode) {
 579                 case FB_BLANK_UNBLANK:
 580                         ddrfreq_clear_sys_status(SYS_STATUS_SUSPEND);
 581                         break;
 582                 default:
 583                         break;
 584                 }
 585         }
 586         else if (action == FB_EVENT_BLANK) {
 587                 switch (blank_mode) {
 588                 case FB_BLANK_POWERDOWN:
 589                         ddrfreq_set_sys_status(SYS_STATUS_SUSPEND);
 590                         break;
 591                 default:
 592                         break;
 593                 }
 594         }
 595
 596         return NOTIFY_OK;
 597 }
 598
 599 static struct notifier_block ddr_freq_suspend_notifier = {
 600                 .notifier_call = ddr_freq_suspend_notifier_call,
 601 };
 602
 603
 604
 605
 606 static int ddrfreq_init(void)
 607 {
 608         struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
 609         int ret;
 610 #if 0//defined(CONFIG_RK_PM_TESTS)
 611         ddrfreq_tst_init();
 612 #endif
 613         clk_cpu_dvfs_node = clk_get_dvfs_node("clk_core");
 614         if (!clk_cpu_dvfs_node){
 615                 return -EINVAL;
 616         }
 617
 618         memset(&ddr, 0x00, sizeof(ddr));
 619         ddr.clk_dvfs_node = clk_get_dvfs_node("clk_ddr");
 620         if (!ddr.clk_dvfs_node){
 621                 return -EINVAL;
 622         }
 623
 624         clk_enable_dvfs(ddr.clk_dvfs_node);
 625
 626         ddr_freq_wq = alloc_workqueue("ddr_freq", WQ_NON_REENTRANT | WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_FREEZABLE, 1);
 627
 628         init_waitqueue_head(&ddr.wait);
 629         ddr.mode = "normal";
 630
 631         ddr.normal_rate = dvfs_clk_get_rate(ddr.clk_dvfs_node);
 632         ddr.suspend_rate = ddr.normal_rate;
 633         ddr.reboot_rate = ddr.normal_rate;
 634
 635         of_init_ddr_freq_table();
 636
 637         ret = input_register_handler(&ddr_freq_input_handler);
 638         if (ret)
 639                 ddr.auto_freq = false;
 640
 641         if (ddr.idle_rate) {
 642                 //REGISTER_CLK_NOTIFIER(pd_gpu);
 643                 //REGISTER_CLK_NOTIFIER(pd_rga);
 644                 //REGISTER_CLK_NOTIFIER(pd_cif0);
 645                 //REGISTER_CLK_NOTIFIER(pd_cif1);
 646         }
 647
 648         if (ddr.dualview_rate) {
 649              //REGISTER_CLK_NOTIFIER(pd_lcdc0);
 650              //REGISTER_CLK_NOTIFIER(pd_lcdc1);
 651         }
 652
 653         ret = misc_register(&video_state_dev);
 654         if (unlikely(ret)) {
 655                 pr_err("failed to register video_state misc device! error %d\n", ret);
 656                 goto err;
 657         }
 658
 659
 660         ddr.task = kthread_create(ddrfreq_task, NULL, "ddrfreqd");
 661         if (IS_ERR(ddr.task)) {
 662                 ret = PTR_ERR(ddr.task);
 663                 pr_err("failed to create kthread! error %d\n", ret);
 664                 goto err1;
 665         }
 666
 667         sched_setscheduler_nocheck(ddr.task, SCHED_FIFO, &param);
 668         get_task_struct(ddr.task);
 669         kthread_bind(ddr.task, 0);
 670         wake_up_process(ddr.task);
 671
 672         fb_register_client(&ddr_freq_suspend_notifier);
 673         register_reboot_notifier(&ddrfreq_reboot_notifier);
 674
 675         pr_info("verion 1.0 20140228\n");
 676         dprintk(DEBUG_DDR, "normal %luMHz video %luMHz dualview %luMHz idle %luMHz suspend %luMHz reboot %luMHz\n",
 677                 ddr.normal_rate / MHZ, ddr.video_rate / MHZ, ddr.dualview_rate / MHZ, ddr.idle_rate / MHZ, ddr.suspend_rate / MHZ, ddr.reboot_rate / MHZ);
 678
 679         return 0;
 680
 681 err1:
 682         misc_deregister(&video_state_dev);
 683 err:
 684         if (ddr.idle_rate) {
 685                 //UNREGISTER_CLK_NOTIFIER(pd_gpu);
 686                 //UNREGISTER_CLK_NOTIFIER(pd_rga);
 687                 //UNREGISTER_CLK_NOTIFIER(pd_cif0);
 688                 //UNREGISTER_CLK_NOTIFIER(pd_cif1);
 689         }
 690        if (ddr.dualview_rate) {
 691         //UNREGISTER_CLK_NOTIFIER(pd_lcdc0);
 692         //UNREGISTER_CLK_NOTIFIER(pd_lcdc1);
 693        }
 694
 695         return ret;
 696 }
 697 late_initcall(ddrfreq_init);
 698
 699 /****************************ddr bandwith tst************************************/
 700 #if 0//defined(CONFIG_RK_PM_TESTS)
 701
 702 #define USE_NORMAL_TIME
 703
 704 #ifdef USE_NORMAL_TIME
 705 static struct timer_list ddrbw_timer;
 706 #else
 707 static struct hrtimer ddrbw_hrtimer;
 708 #endif
 709 enum ddr_bandwidth_id{
 710     ddrbw_wr_num=0,
 711     ddrbw_rd_num,
 712     ddrbw_act_num,
 713     ddrbw_time_num,
 714     ddrbw_eff,
 715     ddrbw_id_end
 716 };
 717 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
 718 #define grf_writel(v, offset)   do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
 719
 720 static u32 ddr_bw_show_st=0;
 721
 722 #define  ddr_monitor_start() grf_writel(0xc000c000,RK3288_GRF_SOC_CON4)
 723 #define  ddr_monitor_end() grf_writel(0xc0000000,RK3288_GRF_SOC_CON4)
 724
 725 static ssize_t ddrbw_dyn_show(struct kobject *kobj, struct kobj_attribute *attr,
 726                 char *buf)
 727 {
 728         char *s = buf;
 729         return (s - buf);
 730 }
 731
 732 static ssize_t ddrbw_dyn_store(struct kobject *kobj, struct kobj_attribute *attr,
 733                 const char *buf, size_t n)
 734 {
 735         //const char *pbuf;
 736
 737         if((strncmp(buf, "start", strlen("start")) == 0)) {
 738             ddr_bw_show_st=1;
 739             ddr_monitor_start();
 740
 741             #ifdef USE_NORMAL_TIME
 742             mod_timer(&ddrbw_timer, jiffies + msecs_to_jiffies(500));
 743             #else
 744             hrtimer_start(&ddrbw_hrtimer, ktime_set(0, 5 * 1000 * 1000*1000), HRTIMER_MODE_REL);
 745             #endif
 746
 747         } else if((strncmp(buf, "stop", strlen("stop")) == 0)) {
 748             ddr_bw_show_st=0;
 749             ddr_monitor_end();
 750         }
 751
 752         return n;
 753 }
 754
 755 static void ddr_bandwidth_get(void)
 756 {
 757     u32 ddr_bw_val[2][ddrbw_id_end];
 758     int i,j;
 759     u64 temp64;
 760
 761
 762     for(j=0;j<2;j++)
 763     for(i=0;i<ddrbw_eff;i++)
 764     {
 765         ddr_bw_val[j][i]=grf_readl(RK3288_GRF_SOC_STATUS11+i*4+j*16);
 766     }
 767     ddr_monitor_end();//stop
 768     ddr_monitor_start();
 769
 770     temp64=((u64)ddr_bw_val[0][0]+ddr_bw_val[0][1])*8*100;
 771
 772    // printk("ch0 %llu\n",temp64);
 773
 774     do_div(temp64,ddr_bw_val[0][ddrbw_time_num]);
 775     ddr_bw_val[0][ddrbw_eff]= temp64;
 776     temp64=((u64)ddr_bw_val[1][0]+ddr_bw_val[1][1])*8*100;
 777
 778     //printk("ch1 %llu\n",temp64);
 779
 780     do_div(temp64,ddr_bw_val[1][ddrbw_time_num]);
 781     ddr_bw_val[1][ddrbw_eff]=  temp64;
 782
 783     printk("ddrch0,wr,rd,act,time,percent(%x,%x,%x,%x,%d)\n",
 784                                ddr_bw_val[0][0],ddr_bw_val[0][1],ddr_bw_val[0][2],ddr_bw_val[0][3],ddr_bw_val[0][4]);
 785     printk("ddrch1,wr,rd,act,time,percent(%x,%x,%x,%x,%d)\n",
 786                                ddr_bw_val[1][0],ddr_bw_val[1][1],ddr_bw_val[1][2],ddr_bw_val[1][3],ddr_bw_val[1][4]);
 787
 788 }
 789
 790 #ifdef USE_NORMAL_TIME
 791 static void ddrbw_timer_fn(unsigned long data)
 792 {
 793         //int i;
 794         ddr_bandwidth_get();
 795         if(ddr_bw_show_st)
 796         {
 797             mod_timer(&ddrbw_timer, jiffies + msecs_to_jiffies(500));
 798          }
 799 }
 800 #else
 801 struct hrtimer ddrbw_hrtimer;
 802 static enum hrtimer_restart ddrbw_hrtimer_timer_func(struct hrtimer *timer)
 803 {
 804         int i;
 805         ddr_bandwidth_get();
 806         if(ddr_bw_show_st)
 807         hrtimer_start(timer, ktime_set(0, 1 * 1000 * 1000), HRTIMER_MODE_REL);
 808
 809 }
 810 #endif
 811
 812 struct ddrfreq_attribute {
 813         struct attribute        attr;
 814         ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
 815                         char *buf);
 816         ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
 817                         const char *buf, size_t n);
 818 };
 819
 820 static struct ddrfreq_attribute ddrfreq_attrs[] = {
 821         /*     node_name        permision               show_func       store_func */
 822         __ATTR(ddrbw,   S_IRUSR | S_IRGRP | S_IWUSR,ddrbw_dyn_show,     ddrbw_dyn_store),
 823 };
 824 int rk_pm_tests_kobj_atrradd(const struct attribute *attr);
 825
 826 static void ddrfreq_tst_init(void)
 827 {
 828         int i,ret;
 829 #ifdef USE_NORMAL_TIME
 830             init_timer(&ddrbw_timer);
 831             //ddrbw_timer.expires = jiffies+msecs_to_jiffies(1);
 832             ddrbw_timer.function = ddrbw_timer_fn;
 833             //mod_timer(&ddrbw_timer,jiffies+msecs_to_jiffies(1));
 834 #else
 835             hrtimer_init(&ddrbw_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 836             ddrbw_hrtimer.function = ddrbw_hrtimer_timer_func;
 837             //hrtimer_start(&ddrbw_hrtimer,ktime_set(0, 5*1000*1000),HRTIMER_MODE_REL);
 838 #endif
 839             printk("*****%s*****\n",__FUNCTION__);
 840
 841             ret = rk_pm_tests_kobj_atrradd(&ddrfreq_attrs[0].attr);
 842             if (ret != 0) {
 843                 printk("create ddrfreq sysfs node error\n");
 844                 return;
 845             }
 846
 847 }
 848 #endif