2 * arch/arm/mach-rk2928/ddr.c-- for ddr3&ddr2
4 * Function Driver for DDR controller
6 * Copyright (C) 2012 Fuzhou Rockchip Electronics Co.,Ltd
15 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/clk.h>
20 #include <asm/cacheflush.h>
21 #include <asm/tlbflush.h>
22 #include <linux/cpu.h>
23 #include <dt-bindings/clock/ddr.h>
24 #include <linux/rockchip/cru.h>
25 #include <linux/rk_fb.h>
28 typedef uint32_t uint32;
30 #define DDR3_DDR2_DLL_DISABLE_FREQ (300) /* ¿ÅÁ£dll disableµÄƵÂÊ*/
31 #define DDR3_DDR2_ODT_DISABLE_FREQ (333) /*¿ÅÁ£odt disableµÄƵÂÊ*/
32 #define SR_IDLE (0x1) /*unit:32*DDR clk cycle, and 0 for disable auto self-refresh*/
33 #define PD_IDLE (0x40) /*unit:DDR clk cycle, and 0 for disable auto power-down*/
34 #define PHY_ODT_DISABLE_FREQ (333) /*¶¨ÒåÖ÷¿Ø¶Ëodt disableµÄƵÂÊ*/
35 #define PHY_DLL_DISABLE_FREQ (266) /*¶¨ÒåÖ÷¿Ø¶Ëdll bypassµÄƵÂÊ*/
37 #define ddr_print(x...) printk("DDR DEBUG: " x)
39 #define SRAM_CODE_OFFSET rockchip_sram_virt
40 #define SRAM_SIZE rockchip_sram_size
42 #ifdef CONFIG_FB_ROCKCHIP
43 #define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
46 /*#define PHY_RX_PHASE_CAL*/
47 #define PHY_DE_SKEW_STEP (20)
48 /***********************************
50 ***********************************/
53 #define DDR3_BC4_8 (1)
55 #define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
56 #define DDR3_WR(n) (((n)&0x7)<<9)
57 #define DDR3_DLL_RESET (1<<8)
58 #define DDR3_DLL_DeRESET (0<<8)
61 #define DDR3_DLL_ENABLE (0)
62 #define DDR3_DLL_DISABLE (1)
63 #define DDR3_MR1_AL(n) (((n)&0x7)<<3)
65 #define DDR3_DS_40 (0)
66 #define DDR3_DS_34 (1<<1)
67 #define DDR3_Rtt_Nom_DIS (0)
68 #define DDR3_Rtt_Nom_60 (1<<2)
69 #define DDR3_Rtt_Nom_120 (1<<6)
70 #define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
73 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
74 #define DDR3_Rtt_WR_DIS (0)
75 #define DDR3_Rtt_WR_60 (1<<9)
76 #define DDR3_Rtt_WR_120 (2<<9)
78 #define DDR_PLL_REFDIV (1)
79 #define FBDIV(n) ((0xFFF<<16) | (n&0xfff))
80 #define REFDIV(n) ((0x3F<<16) | (n&0x3f))
81 #define POSTDIV1(n) ((0x7<<(12+16)) | ((n&0x7)<<12))
82 #define POSTDIV2(n) ((0x7<<(6+16)) | ((n&0x7)<<6))
84 #define PLL_LOCK_STATUS (0x1<<10)
85 /*CRU Registers updated*/
86 typedef volatile struct tagCRU_STRUCT {
87 uint32 CRU_PLL_CON[4][4];
89 uint32 CRU_CLKSEL_CON[35];
90 uint32 CRU_CLKGATE_CON[11]; /*0xd0*/
91 uint32 reserved1; /*0xfc*/
92 uint32 CRU_GLB_SRST_FST_VALUE; /*0x100*/
93 uint32 CRU_GLB_SRST_SND_VALUE;
95 uint32 CRU_SOFTRST_CON[9]; /*0x110*/
96 uint32 CRU_MISC_CON; /*0x134*/
98 uint32 CRU_GLB_CNT_TH; /*0x140*/
100 uint32 CRU_GLB_RST_ST; /*0x150*/
101 uint32 reserved5[(0x1c0 - 0x154) / 4];
102 uint32 CRU_SDMMC_CON[2]; /*0x1c0*/
103 uint32 CRU_SDIO_CON[2];
105 uint32 CRU_EMMC_CON[2]; /*0x1d8*/
106 uint32 reserved7[(0x1f0 - 0x1e0) / 4];
107 uint32 CRU_PLL_PRG_EN;
108 } CRU_REG, *pCRU_REG;
110 typedef struct tagGPIO_LH {
115 typedef struct tagGPIO_IOMUX {
122 /********************************
123 *GRF ¼Ä´æÆ÷ÖÐGRF_OS_REG1 ´æddr rank£¬typeµÈÐÅÏ¢
124 *GRF_SOC_CON2¼Ä´æÆ÷ÖпØÖÆc_sysreqÐźÅÏòpctl·¢ËͽøÈëlow power ÇëÇó
125 *GRF_DDRC_STAT ¿É²éѯpctlÊÇ·ñ½ÓÊÜÇëÇó ½øÈëlow power
126 ********************************/
127 /*REG FILE registers*/
129 #define DDR_MONITOR_EN ((1<<(16+6))+(1<<6))
130 #define DDR_MONITOR_DISB ((1<<(16+6))+(0<<6))
133 #define sys_pwr_idle (1<<27)
134 #define gpu_pwr_idle (1<<26)
135 #define vpu_pwr_idle (1<<25)
136 #define vio_pwr_idle (1<<24)
137 #define peri_pwr_idle (1<<23)
138 #define core_pwr_idle (1<<22)
140 #define core_pwr_idlereq (13)
141 #define peri_pwr_idlereq (12)
142 #define vio_pwr_idlereq (11)
143 #define vpu_pwr_idlereq (10)
144 #define gpu_pwr_idlereq (9)
145 #define sys_pwr_idlereq (8)
146 #define GRF_DDR_LP_EN (0x1<<(2+16))
147 #define GRF_DDR_LP_DISB ((0x1<<(2+16))|(0x1<<2))
150 typedef volatile struct tagREG_FILE {
151 uint32 reserved0[(0xa8 - 0x0) / 4];
152 GPIO_IOMUX_T GRF_GPIO_IOMUX[4]; /*0x00a8*/
153 uint32 GRF_GPIO2C_IOMUX2; /*0xe8*/
154 uint32 GRF_CIF_IOMUX[2];
155 uint32 reserved1[(0x100 - 0xf4) / 4];
156 uint32 GRF_GPIO_DS; /*0x100*/
157 uint32 reserved2[(0x118 - 0x104) / 4];
158 GPIO_LH_T GRF_GPIO_PULL[4]; /*0x118*/
160 uint32 GRF_ACODEC_CON; /*0x13c*/
161 uint32 GRF_SOC_CON[3]; /*0x140*/
162 uint32 GRF_SOC_STATUS0;
163 uint32 GRF_LVDS_CON0; /*0x150*/
164 uint32 reserved4[(0x15c - 0x154) / 4];
165 uint32 GRF_DMAC_CON[3]; /*0x15c*/
166 uint32 GRF_MAC_CON[2];
167 uint32 GRF_TVE_CON; /*0x170*/
168 uint32 reserved5[(0x17c - 0x174) / 4];
169 uint32 GRF_UOC0_CON0; /*0x17c*/
171 uint32 GRF_UOC1_CON[5]; /*0x184*/
173 uint32 GRF_DDRC_STAT; /*0x19c*/
175 uint32 GRF_SOC_STATUS1; /*0x1a4*/
176 uint32 GRF_CPU_CON[4];
177 uint32 reserved9[(0x1c0 - 0x1b8) / 4];
178 uint32 GRF_CPU_STATUS[2]; /*0x1c0*/
179 uint32 GRF_OS_REG[8];
180 uint32 reserved10[(0x200 - 0x1e8) / 4];
181 uint32 GRF_PVTM_CON[4]; /*0x200*/
182 uint32 GRF_PVTM_STATUS[4];
183 /*uint32 reserved10[(0x220-0x214)/4];*/
184 uint32 GRF_DFI_WRNUM; /*0X220*/
185 uint32 GRF_DFI_RDNUM;
186 uint32 GRF_DFI_ACTNUM;
187 uint32 GRF_DFI_TIMERVAL;
188 uint32 GRF_NIF_FIFO[4];
189 uint32 reserved11[(0x280 - 0x240) / 4];
190 uint32 GRF_USBPHY0_CON[8]; /*0x280*/
191 uint32 GRF_USBPHY1_CON[8];
192 uint32 GRF_UOC_STATUS0; /*0x2c0*/
193 uint32 reserved12[(0x300 - 0x2c4) / 4];
195 uint32 GRF_SDMMC_DET_CNT;
196 uint32 reserved13[(0x37c - 0x308) / 4];
197 uint32 GRF_EFUSE_PRG_EN;
198 } REG_FILE, *pREG_FILE;
201 #define INIT_STATE (0)
202 #define CFG_STATE (1)
204 #define SLEEP_STATE (3)
205 #define WAKEUP_STATE (4)
210 #define Config_req (2)
212 #define Access_req (4)
213 #define Low_power (5)
214 #define Low_power_entry_req (6)
215 #define Low_power_exit_req (7)
218 #define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
219 #define pd_idle(n) ((n)<<8)
220 #define mddr_en (2<<22)
221 #define lpddr2_en (3<<22)
222 #define ddr2_en (0<<5)
223 #define ddr3_en (1<<5)
224 #define lpddr2_s2 (0<<6)
225 #define lpddr2_s4 (1<<6)
226 #define mddr_lpddr2_bl_2 (0<<20)
227 #define mddr_lpddr2_bl_4 (1<<20)
228 #define mddr_lpddr2_bl_8 (2<<20)
229 #define mddr_lpddr2_bl_16 (3<<20)
230 #define ddr2_ddr3_bl_4 (0)
231 #define ddr2_ddr3_bl_8 (1)
232 #define tfaw_cfg(n) (((n)-4)<<18)
233 #define pd_exit_slow (0<<17)
234 #define pd_exit_fast (1<<17)
235 #define pd_type(n) ((n)<<16)
236 #define two_t_en(n) ((n)<<3)
237 #define bl8int_en(n) ((n)<<2)
238 #define cke_or_en(n) ((n)<<1)
241 #define power_up_start (1<<0)
244 #define power_up_done (1<<0)
247 #define dfi_init_complete (1<<0)
250 #define cmd_tstat (1<<0)
253 #define cmd_tstat_en (1<<1)
256 #define Deselect_cmd (0)
266 #define lpddr2_op(n) ((n)<<12)
267 #define lpddr2_ma(n) ((n)<<4)
269 #define bank_addr(n) ((n)<<17)
270 #define cmd_addr(n) ((n)<<4)
272 #define start_cmd (1u<<31)
274 typedef union STAT_Tag {
278 unsigned reserved3:1;
280 unsigned reserved7_31:25;
284 typedef union SCFG_Tag {
287 unsigned hw_low_power_en:1;
288 unsigned reserved1_5:5;
289 unsigned nfifo_nif1_dis:1;
290 unsigned reserved7:1;
291 unsigned bbflags_timing:4;
292 unsigned reserved12_31:20;
296 /* DDR Controller register struct */
297 typedef volatile struct DDR_REG_Tag {
298 /*Operational State, Control, and Status Registers*/
299 SCFG_T SCFG; /*State Configuration Register*/
300 volatile uint32 SCTL; /*State Control Register*/
301 STAT_T STAT; /*State Status Register*/
302 volatile uint32 INTRSTAT; /*Interrupt Status Register*/
303 uint32 reserved0[(0x40 - 0x10) / 4];
304 /*Initailization Control and Status Registers*/
305 volatile uint32 MCMD; /*Memory Command Register*/
306 volatile uint32 POWCTL; /*Power Up Control Registers*/
307 volatile uint32 POWSTAT; /*Power Up Status Register*/
308 volatile uint32 CMDTSTAT; /*Command Timing Status Register*/
309 volatile uint32 CMDTSTATEN; /*Command Timing Status Enable Register*/
310 uint32 reserved1[(0x60 - 0x54) / 4];
311 volatile uint32 MRRCFG0; /*MRR Configuration 0 Register*/
312 volatile uint32 MRRSTAT0; /*MRR Status 0 Register*/
313 volatile uint32 MRRSTAT1; /*MRR Status 1 Register*/
314 uint32 reserved2[(0x7c - 0x6c) / 4];
315 /*Memory Control and Status Registers*/
316 volatile uint32 MCFG1; /*Memory Configuration 1 Register*/
317 volatile uint32 MCFG; /*Memory Configuration Register*/
318 volatile uint32 PPCFG; /*Partially Populated Memories Configuration Register*/
319 volatile uint32 MSTAT; /*Memory Status Register*/
320 volatile uint32 LPDDR2ZQCFG; /*LPDDR2 ZQ Configuration Register*/
322 /*DTU Control and Status Registers*/
323 volatile uint32 DTUPDES; /*DTU Status Register*/
324 volatile uint32 DTUNA; /*DTU Number of Random Addresses Created Register*/
325 volatile uint32 DTUNE; /*DTU Number of Errors Register*/
326 volatile uint32 DTUPRD0; /*DTU Parallel Read 0*/
327 volatile uint32 DTUPRD1; /*DTU Parallel Read 1*/
328 volatile uint32 DTUPRD2; /*DTU Parallel Read 2*/
329 volatile uint32 DTUPRD3; /*DTU Parallel Read 3*/
330 volatile uint32 DTUAWDT; /*DTU Address Width*/
331 uint32 reserved4[(0xc0 - 0xb4) / 4];
332 /*Memory Timing Registers*/
333 volatile uint32 TOGCNT1U; /*Toggle Counter 1U Register*/
334 volatile uint32 TINIT; /*t_init Timing Register*/
335 volatile uint32 TRSTH; /*Reset High Time Register*/
336 volatile uint32 TOGCNT100N; /*Toggle Counter 100N Register*/
337 volatile uint32 TREFI; /*t_refi Timing Register*/
338 volatile uint32 TMRD; /*t_mrd Timing Register*/
339 volatile uint32 TRFC; /*t_rfc Timing Register*/
340 volatile uint32 TRP; /*t_rp Timing Register*/
341 volatile uint32 TRTW; /*t_rtw Timing Register*/
342 volatile uint32 TAL; /*AL Latency Register*/
343 volatile uint32 TCL; /*CL Timing Register*/
344 volatile uint32 TCWL; /*CWL Register*/
345 volatile uint32 TRAS; /*t_ras Timing Register*/
346 volatile uint32 TRC; /*t_rc Timing Register*/
347 volatile uint32 TRCD; /*t_rcd Timing Register*/
348 volatile uint32 TRRD; /*t_rrd Timing Register*/
349 volatile uint32 TRTP; /*t_rtp Timing Register*/
350 volatile uint32 TWR; /*t_wr Timing Register*/
351 volatile uint32 TWTR; /*t_wtr Timing Register*/
352 volatile uint32 TEXSR; /*t_exsr Timing Register*/
353 volatile uint32 TXP; /*t_xp Timing Register*/
354 volatile uint32 TXPDLL; /*t_xpdll Timing Register*/
355 volatile uint32 TZQCS; /*t_zqcs Timing Register*/
356 volatile uint32 TZQCSI; /*t_zqcsi Timing Register*/
357 volatile uint32 TDQS; /*t_dqs Timing Register*/
358 volatile uint32 TCKSRE; /*t_cksre Timing Register*/
359 volatile uint32 TCKSRX; /*t_cksrx Timing Register*/
360 volatile uint32 TCKE; /*t_cke Timing Register*/
361 volatile uint32 TMOD; /*t_mod Timing Register*/
362 volatile uint32 TRSTL; /*Reset Low Timing Register*/
363 volatile uint32 TZQCL; /*t_zqcl Timing Register*/
364 volatile uint32 TMRR; /*t_mrr Timing Register*/
365 volatile uint32 TCKESR; /*t_ckesr Timing Register*/
366 volatile uint32 TDPD; /*t_dpd Timing Register*/
367 uint32 reserved5[(0x180 - 0x148) / 4];
368 /*ECC Configuration, Control, and Status Registers*/
369 volatile uint32 ECCCFG; /*ECC Configuration Register*/
370 volatile uint32 ECCTST; /*ECC Test Register*/
371 volatile uint32 ECCCLR; /*ECC Clear Register*/
372 volatile uint32 ECCLOG; /*ECC Log Register*/
373 uint32 reserved6[(0x200 - 0x190) / 4];
374 /*DTU Control and Status Registers*/
375 volatile uint32 DTUWACTL; /*DTU Write Address Control Register*/
376 volatile uint32 DTURACTL; /*DTU Read Address Control Register*/
377 volatile uint32 DTUCFG; /*DTU Configuration Control Register*/
378 volatile uint32 DTUECTL; /*DTU Execute Control Register*/
379 volatile uint32 DTUWD0; /*DTU Write Data 0*/
380 volatile uint32 DTUWD1; /*DTU Write Data 1*/
381 volatile uint32 DTUWD2; /*DTU Write Data 2*/
382 volatile uint32 DTUWD3; /*DTU Write Data 3*/
383 volatile uint32 DTUWDM; /*DTU Write Data Mask*/
384 volatile uint32 DTURD0; /*DTU Read Data 0*/
385 volatile uint32 DTURD1; /*DTU Read Data 1*/
386 volatile uint32 DTURD2; /*DTU Read Data 2*/
387 volatile uint32 DTURD3; /*DTU Read Data 3*/
388 volatile uint32 DTULFSRWD; /*DTU LFSR Seed for Write Data Generation*/
389 volatile uint32 DTULFSRRD; /*DTU LFSR Seed for Read Data Generation*/
390 volatile uint32 DTUEAF; /*DTU Error Address FIFO*/
391 /*DFI Control Registers*/
392 volatile uint32 DFITCTRLDELAY; /*DFI tctrl_delay Register*/
393 volatile uint32 DFIODTCFG; /*DFI ODT Configuration Register*/
394 volatile uint32 DFIODTCFG1; /*DFI ODT Configuration 1 Register*/
395 volatile uint32 DFIODTRANKMAP; /*DFI ODT Rank Mapping Register*/
396 /*DFI Write Data Registers*/
397 volatile uint32 DFITPHYWRDATA; /*DFI tphy_wrdata Register*/
398 volatile uint32 DFITPHYWRLAT; /*DFI tphy_wrlat Register*/
399 uint32 reserved7[(0x260 - 0x258) / 4];
400 volatile uint32 DFITRDDATAEN; /*DFI trddata_en Register*/
401 volatile uint32 DFITPHYRDLAT; /*DFI tphy_rddata Register*/
402 uint32 reserved8[(0x270 - 0x268) / 4];
403 /*DFI Update Registers*/
404 volatile uint32 DFITPHYUPDTYPE0; /*DFI tphyupd_type0 Register*/
405 volatile uint32 DFITPHYUPDTYPE1; /*DFI tphyupd_type1 Register*/
406 volatile uint32 DFITPHYUPDTYPE2; /*DFI tphyupd_type2 Register*/
407 volatile uint32 DFITPHYUPDTYPE3; /*DFI tphyupd_type3 Register*/
408 volatile uint32 DFITCTRLUPDMIN; /*DFI tctrlupd_min Register*/
409 volatile uint32 DFITCTRLUPDMAX; /*DFI tctrlupd_max Register*/
410 volatile uint32 DFITCTRLUPDDLY; /*DFI tctrlupd_dly Register*/
412 volatile uint32 DFIUPDCFG; /*DFI Update Configuration Register*/
413 volatile uint32 DFITREFMSKI; /*DFI Masked Refresh Interval Register*/
414 volatile uint32 DFITCTRLUPDI; /*DFI tctrlupd_interval Register*/
415 uint32 reserved10[(0x2ac - 0x29c) / 4];
416 volatile uint32 DFITRCFG0; /*DFI Training Configuration 0 Register*/
417 volatile uint32 DFITRSTAT0; /*DFI Training Status 0 Register*/
418 volatile uint32 DFITRWRLVLEN; /*DFI Training dfi_wrlvl_en Register*/
419 volatile uint32 DFITRRDLVLEN; /*DFI Training dfi_rdlvl_en Register*/
420 volatile uint32 DFITRRDLVLGATEEN; /*DFI Training dfi_rdlvl_gate_en Register*/
421 /*DFI Status Registers*/
422 volatile uint32 DFISTSTAT0; /*DFI Status Status 0 Register*/
423 volatile uint32 DFISTCFG0; /*DFI Status Configuration 0 Register*/
424 volatile uint32 DFISTCFG1; /*DFI Status configuration 1 Register*/
426 volatile uint32 DFITDRAMCLKEN; /*DFI tdram_clk_enalbe Register*/
427 volatile uint32 DFITDRAMCLKDIS; /*DFI tdram_clk_disalbe Register*/
428 volatile uint32 DFISTCFG2; /*DFI Status configuration 2 Register*/
429 volatile uint32 DFISTPARCLR; /*DFI Status Parity Clear Register*/
430 volatile uint32 DFISTPARLOG; /*DFI Status Parity Log Register*/
431 uint32 reserved12[(0x2f0 - 0x2e4) / 4];
432 /*DFI Low Power Registers*/
433 volatile uint32 DFILPCFG0; /*DFI Low Power Configuration 0 Register*/
434 uint32 reserved13[(0x300 - 0x2f4) / 4];
435 /*DFI Training 2 Registers*/
436 volatile uint32 DFITRWRLVLRESP0; /*DFI Training dif_wrlvl_resp Status 0 Register*/
437 volatile uint32 DFITRWRLVLRESP1; /*DFI Training dif_wrlvl_resp Status 1 Register*/
438 volatile uint32 DFITRWRLVLRESP2; /*DFI Training dif_wrlvl_resp Status 2 Register*/
439 volatile uint32 DFITRRDLVLRESP0; /*DFI Training dif_rdlvl_resp Status 0 Register*/
440 volatile uint32 DFITRRDLVLRESP1; /*DFI Training dif_rdlvl_resp Status 1 Register*/
441 volatile uint32 DFITRRDLVLRESP2; /*DFI Training dif_rdlvl_resp Status 2 Register*/
442 volatile uint32 DFITRWRLVLDELAY0; /*DFI Training dif_wrlvl_delay Configuration 0 Register*/
443 volatile uint32 DFITRWRLVLDELAY1; /*DFI Training dif_wrlvl_delay Configuration 1 Register*/
444 volatile uint32 DFITRWRLVLDELAY2; /*DFI Training dif_wrlvl_delay Configuration 2 Register*/
445 volatile uint32 DFITRRDLVLDELAY0; /*DFI Training dif_rdlvl_delay Configuration 0 Register*/
446 volatile uint32 DFITRRDLVLDELAY1; /*DFI Training dif_rdlvl_delay Configuration 1 Register*/
447 volatile uint32 DFITRRDLVLDELAY2; /*DFI Training dif_rdlvl_delay Configuration 2 Register*/
448 volatile uint32 DFITRRDLVLGATEDELAY0; /*DFI Training dif_rdlvl_gate_delay Configuration 0 Register*/
449 volatile uint32 DFITRRDLVLGATEDELAY1; /*DFI Training dif_rdlvl_gate_delay Configuration 1 Register*/
450 volatile uint32 DFITRRDLVLGATEDELAY2; /*DFI Training dif_rdlvl_gate_delay Configuration 2 Register*/
451 volatile uint32 DFITRCMD; /*DFI Training Command Register*/
452 uint32 reserved14[(0x3f8 - 0x340) / 4];
453 /*IP Status Registers*/
454 volatile uint32 IPVR; /*IP Version Register*/
455 volatile uint32 IPTR; /*IP Type Register*/
456 } DDR_REG_T, *pDDR_REG_T;
459 #define PHY_AUTO_CALIBRATION (1<<0)
460 #define PHY_SW_CALIBRATION (1<<1)
464 #define PHY_LPDDR2 (2)
465 #define PHY_Burst8 (1<<2)
468 #define PHY_CL(n) (((n)&0xF)<<4)
469 #define PHY_AL(n) ((n)&0xF)
471 #define PHY_RON_DISABLE (0)
472 #define PHY_RON_309ohm (1)
473 #define PHY_RON_155ohm (2)
474 #define PHY_RON_103ohm (3)
475 #define PHY_RON_77ohm (4)
476 #define PHY_RON_63ohm (5)
477 #define PHY_RON_52ohm (6)
478 #define PHY_RON_45ohm (7)
479 /*#define PHY_RON_77ohm (8)*/
480 #define PHY_RON_62ohm (9)
481 /*#define PHY_RON_52ohm (10)*/
482 #define PHY_RON_44ohm (11)
483 #define PHY_RON_39ohm (12)
484 #define PHY_RON_34ohm (13)
485 #define PHY_RON_31ohm (14)
486 #define PHY_RON_28ohm (15)
488 #define PHY_RTT_DISABLE (0)
489 #define PHY_RTT_816ohm (1)
490 #define PHY_RTT_431ohm (2)
491 #define PHY_RTT_287ohm (3)
492 #define PHY_RTT_216ohm (4)
493 #define PHY_RTT_172ohm (5)
494 #define PHY_RTT_145ohm (6)
495 #define PHY_RTT_124ohm (7)
496 #define PHY_RTT_215ohm (8)
497 /*#define PHY_RTT_172ohm (9)*/
498 #define PHY_RTT_144ohm (10)
499 #define PHY_RTT_123ohm (11)
500 #define PHY_RTT_108ohm (12)
501 #define PHY_RTT_96ohm (13)
502 #define PHY_RTT_86ohm (14)
503 #define PHY_RTT_78ohm (15)
505 #define PHY_DRV_ODT_SET(n) ((n<<4)|n)
507 /* DDR PHY register struct */
508 typedef volatile struct DDRPHY_REG_Tag
510 volatile uint32 PHY_REG1; //PHY soft reset Register
511 volatile uint32 PHY_REG3; //Burst type select Register
512 volatile uint32 PHY_REG2; //PHY DQS squelch calibration Register
513 uint32 reserved1[(0x38-0x0a)/4];
514 volatile uint32 PHY_REG4a; //CL,AL set register
515 volatile uint32 PHY_REG4b; //dqs gata delay select bypass mode register
516 uint32 reserved2[(0x54-0x40)/4];
517 volatile uint32 PHY_REG16; //
518 uint32 reserved3[(0x5c-0x58)/4];
519 volatile uint32 PHY_REG18; //0x5c
520 volatile uint32 PHY_REG19;
521 uint32 reserved4[(0x68-0x64)/4];
522 volatile uint32 PHY_REG21; //0x68
523 uint32 reserved5[(0x70-0x6c)/4];
524 volatile uint32 PHY_REG22; //0x70
525 uint32 reserved6[(0x80-0x74)/4];
526 volatile uint32 PHY_REG25; //0x80
527 volatile uint32 PHY_REG26;
528 volatile uint32 PHY_REG27;
529 volatile uint32 PHY_REG28;
530 uint32 reserved7[(0xd4-0x90)/4];
531 volatile uint32 PHY_REG6; //0xd4
532 volatile uint32 PHY_REG7;
533 uint32 reserved8[(0xe0-0xdc)/4];
534 volatile uint32 PHY_REG8; //0xe0
535 volatile uint32 PHY_REG0e4; //use for DQS ODT off
536 uint32 reserved9[(0x114-0xe8)/4];
537 volatile uint32 PHY_REG9; //0x114
538 volatile uint32 PHY_REG10;
539 uint32 reserved10[(0x120-0x11c)/4];
540 volatile uint32 PHY_REG11; //0x120
541 volatile uint32 PHY_REG124; //use for DQS ODT off
542 uint32 reserved11[(0x1c0-0x128)/4];
543 volatile uint32 PHY_REG29; //0x1c0
544 uint32 reserved12[(0x264-0x1c4)/4];
545 volatile uint32 PHY_REG264; //use for phy soft reset
546 uint32 reserved13[(0x2b0-0x268)/4];
547 volatile uint32 PHY_REG2a; //0x2b0
548 uint32 reserved14[(0x2c4-0x2b4)/4];
549 // volatile uint32 PHY_TX_DeSkew[24]; //0x2c4-0x320
550 volatile uint32 PHY_REG30;
551 volatile uint32 PHY_REG31;
552 volatile uint32 PHY_REG32;
553 volatile uint32 PHY_REG33;
554 volatile uint32 PHY_REG34;
555 volatile uint32 PHY_REG35;
556 volatile uint32 PHY_REG36;
557 volatile uint32 PHY_REG37;
558 volatile uint32 PHY_REG38;
559 volatile uint32 PHY_REG39;
560 volatile uint32 PHY_REG40;
561 volatile uint32 PHY_REG41;
562 volatile uint32 PHY_REG42;
563 volatile uint32 PHY_REG43;
564 volatile uint32 PHY_REG44;
565 volatile uint32 PHY_REG45;
566 volatile uint32 PHY_REG46;
567 volatile uint32 PHY_REG47;
568 volatile uint32 PHY_REG48;
569 volatile uint32 PHY_REG49;
570 volatile uint32 PHY_REG50;
571 volatile uint32 PHY_REG51;
572 volatile uint32 PHY_REG52;
573 volatile uint32 PHY_REG53;
574 uint32 reserved15[(0x328-0x324)/4];
575 // volatile uint32 PHY_RX_DeSkew[11]; //0x328-0x350
576 volatile uint32 PHY_REG54;
577 volatile uint32 PHY_REG55;
578 volatile uint32 PHY_REG56;
579 volatile uint32 PHY_REG57;
580 volatile uint32 PHY_REG58;
581 volatile uint32 PHY_REG59;
582 volatile uint32 PHY_REG5a;
583 volatile uint32 PHY_REG5b;
584 volatile uint32 PHY_REG5c;
585 volatile uint32 PHY_REG5d;
586 volatile uint32 PHY_REG5e;
587 uint32 reserved16[(0x3c4-0x354)/4];
588 volatile uint32 PHY_REG5f; //0x3c4
589 uint32 reserved17[(0x3e0-0x3c8)/4];
590 volatile uint32 PHY_REG60;
591 volatile uint32 PHY_REG61;
592 volatile uint32 PHY_REG62;
593 }DDRPHY_REG_T, *pDDRPHY_REG_T;
595 #define pCRU_Reg ((pCRU_REG)RK_CRU_VIRT)
596 #define pGRF_Reg ((pREG_FILE)RK_GRF_VIRT)
597 #define pDDR_Reg ((pDDR_REG_T)RK_DDR_VIRT)
598 #define pPHY_Reg ((pDDRPHY_REG_T)(RK_DDR_VIRT+RK3036_DDR_PCTL_SIZE))
599 #define SysSrv_DdrTiming (RK_CPU_AXI_BUS_VIRT+0xc)
600 #define PMU_PWEDN_ST (RK_PMU_VIRT + 0x8)
601 #define READ_CS_INFO() ((((pGRF_Reg->GRF_OS_REG[1])>>11)&0x1)+1)
602 #define READ_COL_INFO() (9+(((pGRF_Reg->GRF_OS_REG[1])>>9)&0x3))
603 #define READ_BK_INFO() (3-(((pGRF_Reg->GRF_OS_REG[1])>>8)&0x1))
604 #define READ_CS0_ROW_INFO() (13+(((pGRF_Reg->GRF_OS_REG[1])>>6)&0x3))
605 #define READ_CS1_ROW_INFO() (13+(((pGRF_Reg->GRF_OS_REG[1])>>4)&0x3))
606 #define READ_BW_INFO() (2>>(((pGRF_Reg->GRF_OS_REG[1])&0xc)>>2)) /*´úÂëÖÐ 0->8bit 1->16bit 2->32bit ÓëgrfÖж¨ÒåÏà·´*/
607 #define READ_DIE_BW_INFO() (2>>((pGRF_Reg->GRF_OS_REG[1])&0x3))
610 typedef enum PLL_ID_Tag {
618 typedef enum DRAM_TYPE_Tag {
630 unsigned long screen_ft_us;
631 unsigned long long t0;
632 unsigned long long t1;
636 typedef struct PCTRL_TIMING_Tag {
638 /*Memory Timing Registers*/
639 uint32 togcnt1u; /*Toggle Counter 1U Register*/
640 uint32 tinit; /*t_init Timing Register*/
641 uint32 trsth; /*Reset High Time Register*/
642 uint32 togcnt100n; /*Toggle Counter 100N Register*/
643 uint32 trefi; /*t_refi Timing Register*/
644 uint32 tmrd; /*t_mrd Timing Register*/
645 uint32 trfc; /*t_rfc Timing Register*/
646 uint32 trp; /*t_rp Timing Register*/
647 uint32 trtw; /*t_rtw Timing Register*/
648 uint32 tal; /*AL Latency Register*/
649 uint32 tcl; /*CL Timing Register*/
650 uint32 tcwl; /*CWL Register*/
651 uint32 tras; /*t_ras Timing Register*/
652 uint32 trc; /*t_rc Timing Register*/
653 uint32 trcd; /*t_rcd Timing Register*/
654 uint32 trrd; /*t_rrd Timing Register*/
655 uint32 trtp; /*t_rtp Timing Register*/
656 uint32 twr; /*t_wr Timing Register*/
657 uint32 twtr; /*t_wtr Timing Register*/
658 uint32 texsr; /*t_exsr Timing Register*/
659 uint32 txp; /*t_xp Timing Register*/
660 uint32 txpdll; /*t_xpdll Timing Register*/
661 uint32 tzqcs; /*t_zqcs Timing Register*/
662 uint32 tzqcsi; /*t_zqcsi Timing Register*/
663 uint32 tdqs; /*t_dqs Timing Register*/
664 uint32 tcksre; /*t_cksre Timing Register*/
665 uint32 tcksrx; /*t_cksrx Timing Register*/
666 uint32 tcke; /*t_cke Timing Register*/
667 uint32 tmod; /*t_mod Timing Register*/
668 uint32 trstl; /*Reset Low Timing Register*/
669 uint32 tzqcl; /*t_zqcl Timing Register*/
670 uint32 tmrr; /*t_mrr Timing Register*/
671 uint32 tckesr; /*t_ckesr Timing Register*/
672 uint32 tdpd; /*t_dpd Timing Register*/
675 struct ddr_change_freq_sram_param {
680 typedef union NOC_TIMING_Tag {
693 typedef struct BACKUP_REG_Tag {
694 PCTL_TIMING_T pctl_timing;
695 NOC_TIMING_T noc_timing;
698 uint32 ddr_speed_bin;
699 uint32 ddr_capability_per_die;
702 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
703 static BACKUP_REG_T *p_ddr_reg;
705 uint32 DEFINE_PIE_DATA(ddr_freq);
706 static uint32 *p_ddr_freq;
707 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
708 uint32 DEFINE_PIE_DATA(ddr_dll_status); /* ¼Ç¼ddr dllµÄ״̬£¬ÔÚselfrefresh exitʱѡÔñÊÇ·ñ½øÐÐdll reset*/
710 static const uint32_t ddr3_cl_cwl[22][4] = {
711 /* 0~330 330~400 400~533 speed
712 * tCK >3 2.5~3 1.875~2.5 1.875~1.5
713 * cl<<16, cwl cl<<16, cwl cl<<16, cwl */
714 {((5 << 16) | 5), ((5 << 16) | 5), 0, 0}, /*DDR3_800D*/
715 {((5 << 16) | 5), ((6 << 16) | 5), 0, 0}, /*DDR3_800E*/
717 {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), 0}, /*DDR3_1066E*/
718 {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), 0}, /*DDR3_1066F*/
719 {((5 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), 0}, /*DDR3_1066G*/
721 {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)}, /*DDR3_1333F*/
722 {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1333G*/
723 {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_1333H*/
724 {((5 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)}, /*DDR3_1333J*/
726 {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)}, /*DDR3_1600G*/
727 {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1600H*/
728 {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_1600J*/
729 {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((10 << 16) | 7)}, /*DDR3_1600K*/
731 {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1866J*/
732 {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1866K*/
733 {((6 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_1866L*/
734 {((6 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)}, /*DDR3_1866M*/
736 {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)}, /*DDR3_2133K*/
737 {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_2133L*/
738 {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_2133M*/
739 {((6 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_2133N*/
741 {((6 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)} /*DDR3_DEFAULT*/
744 static const uint32_t ddr3_tRC_tFAW[22] = {
746 ((50 << 16) | 50), /*DDR3_800D*/
747 ((53 << 16) | 50), /*DDR3_800E*/
749 ((49 << 16) | 50), /*DDR3_1066E*/
750 ((51 << 16) | 50), /*DDR3_1066F*/
751 ((53 << 16) | 50), /*DDR3_1066G*/
753 ((47 << 16) | 45), /*DDR3_1333F*/
754 ((48 << 16) | 45), /*DDR3_1333G*/
755 ((50 << 16) | 45), /*DDR3_1333H*/
756 ((51 << 16) | 45), /*DDR3_1333J*/
758 ((45 << 16) | 40), /*DDR3_1600G*/
759 ((47 << 16) | 40), /*DDR3_1600H*/
760 ((48 << 16) | 40), /*DDR3_1600J*/
761 ((49 << 16) | 40), /*DDR3_1600K*/
763 ((45 << 16) | 35), /*DDR3_1866J*/
764 ((46 << 16) | 35), /*DDR3_1866K*/
765 ((47 << 16) | 35), /*DDR3_1866L*/
766 ((48 << 16) | 35), /*DDR3_1866M*/
768 ((44 << 16) | 35), /*DDR3_2133K*/
769 ((45 << 16) | 35), /*DDR3_2133L*/
770 ((46 << 16) | 35), /*DDR3_2133M*/
771 ((47 << 16) | 35), /*DDR3_2133N*/
773 ((53 << 16) | 50) /*DDR3_DEFAULT*/
776 /****************************************************************************
777 *Internal sram us delay function
778 *Cpu highest frequency is 1.6 GHz
780 *1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
781 ******************************************************************************/
782 volatile uint32 DEFINE_PIE_DATA(loops_per_us);
783 #define LPJ_100MHZ 999456UL
785 /*----------------------------------------------------------------------
786 *Name : void __sramlocalfunc ddr_delayus(uint32_t us)
788 *Params : uint32_t us --ÑÓʱʱ¼ä
790 *Notes : loops_per_us Ϊȫ¾Ö±äÁ¿ ÐèÒª¸ù¾Ýarm freq¶ø¶¨
791 *----------------------------------------------------------------------*/
792 static void __sramfunc ddr_delayus(uint32 us)
795 volatile unsigned int i = (DATA(loops_per_us) * us);
799 asm volatile (".align 4; 1: subs %0, %0, #1; bne 1b;":"+r" (i));
803 /*----------------------------------------------------------------------
804 *Name : __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
805 *Desc : ddr ¿½±´¼Ä´æÆ÷º¯Êý
806 *Params : pDest ->Ä¿±ê¼Ä´æÆ÷Ê×µØÖ·
807 * pSrc ->Ô´±ê¼Ä´æÆ÷Ê×µØÖ·
811 *----------------------------------------------------------------------*/
813 static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
817 for (i = 0; i < words; i++) {
822 /*----------------------------------------------------------------------
823 *Name : __sramfunc void ddr_move_to_Lowpower_state(void)
824 *Desc : pctl ½øÈë lowpower state
828 *----------------------------------------------------------------------*/
829 static __sramfunc void ddr_move_to_Lowpower_state(void)
831 volatile uint32 value;
834 value = pDDR_Reg->STAT.b.ctl_stat;
835 if (value == Low_power) {
840 pDDR_Reg->SCTL = CFG_STATE;
842 while ((pDDR_Reg->STAT.b.ctl_stat) != Config)
845 pDDR_Reg->SCTL = GO_STATE;
847 while ((pDDR_Reg->STAT.b.ctl_stat) != Access)
850 pDDR_Reg->SCTL = SLEEP_STATE;
852 while ((pDDR_Reg->STAT.b.ctl_stat) != Low_power)
855 default: /*Transitional state*/
861 /*----------------------------------------------------------------------
862 *Name : __sramfunc void ddr_move_to_Access_state(void)
863 *Desc : pctl ½øÈë Access state
867 *----------------------------------------------------------------------*/
868 static __sramfunc void ddr_move_to_Access_state(void)
870 volatile uint32 value;
872 /*set auto self-refresh idle*/
874 (pDDR_Reg->MCFG1 & 0xffffff00) | DATA(ddr_sr_idle) | (1 << 31);
875 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & 0xffff00ff) | (PD_IDLE << 8);
877 value = pDDR_Reg->STAT.b.ctl_stat;
878 if ((value == Access)
879 || ((pDDR_Reg->STAT.b.lp_trig == 1)
880 && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))) {
885 pDDR_Reg->SCTL = WAKEUP_STATE;
887 while ((pDDR_Reg->STAT.b.ctl_stat) != Access)
891 pDDR_Reg->SCTL = CFG_STATE;
893 while ((pDDR_Reg->STAT.b.ctl_stat) != Config)
896 pDDR_Reg->SCTL = GO_STATE;
898 while (!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
899 || ((pDDR_Reg->STAT.b.lp_trig == 1)
900 && ((pDDR_Reg->STAT.b.ctl_stat) ==
904 default: /*Transitional state*/
908 pGRF_Reg->GRF_SOC_CON[2] = (1 << 16 | 0); /*de_hw_wakeup :enable auto sr if sr_idle != 0*/
911 /*----------------------------------------------------------------------
912 *Name : __sramfunc void ddr_move_to_Config_state(void)
913 *Desc : pctl ½øÈë config state
917 *----------------------------------------------------------------------*/
918 static __sramfunc void ddr_move_to_Config_state(void)
920 volatile uint32 value;
921 pGRF_Reg->GRF_SOC_CON[2] = (1 << 16 | 1); /*hw_wakeup :disable auto sr*/
923 value = pDDR_Reg->STAT.b.ctl_stat;
924 if (value == Config) {
929 pDDR_Reg->SCTL = WAKEUP_STATE;
933 pDDR_Reg->SCTL = CFG_STATE;
936 default: /*Transitional state*/
942 /*----------------------------------------------------------------------
943 *Name : void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
944 *Desc : ͨ¹ýд pctl MCMD¼Ä´æÆ÷Ïòddr·¢ËÍÃüÁî
945 *Params : rank ->ddr rank Êý
949 *Notes : arg°üÀ¨bank_addrºÍcmd_addr
950 *----------------------------------------------------------------------*/
951 static void __sramfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
953 while (pDDR_Reg->MCMD & start_cmd)
955 pDDR_Reg->MCMD = (start_cmd | (rank << 20) | arg | cmd);
959 __sramdata uint32 copy_data[8] = {
960 0xffffffff, 0x00000000, 0x55555555, 0xAAAAAAAA,
961 0xEEEEEEEE, 0x11111111, 0x22222222, 0xDDDDDDDD
964 EXPORT_PIE_SYMBOL(copy_data[8]);
965 static uint32 *p_copy_data;
967 /*----------------------------------------------------------------------
968 Name : uint32_t __sramlocalfunc ddr_data_training(void)
969 Desc : ¶Ôddr×ödata training
972 Notes : ûÓÐ×ödata trainingУÑé
973 ----------------------------------------------------------------------*/
974 static uint32_t __sramfunc ddr_data_training(void)
977 value = pDDR_Reg->TREFI;
979 pPHY_Reg->PHY_REG2 |= PHY_AUTO_CALIBRATION;
981 /*wait echo byte DTDONE*/
984 while((pPHY_Reg->PHY_REG62 & 0x3)!=0x3)
986 pPHY_Reg->PHY_REG2 = (pPHY_Reg->PHY_REG2 & (~0x1));
987 /*send some auto refresh to complement the lost while DTT*/
988 ddr_send_command(3, PREA_cmd, 0);
989 ddr_send_command(3, REF_cmd, 0);
990 ddr_send_command(3, REF_cmd, 0);
992 /*resume auto refresh*/
993 pDDR_Reg->TREFI = value;
997 /*----------------------------------------------------------------------
998 Name : void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
999 Desc : ÉèÖÃPHY dll ¹¤×÷ģʽ
1000 Params : freq -> ddr¹¤×÷ƵÂÊ
1003 ----------------------------------------------------------------------*/
1004 static void __sramfunc ddr_set_dll_bypass(uint32 freq)
1006 #if defined (PHY_RX_PHASE_CAL)
1007 uint32 phase_90, dll_set, de_skew;
1009 phase_90 = 1000000 / freq / 4;
1010 dll_set = (phase_90 - 300 + (0x7*PHY_DE_SKEW_STEP)) / (phase_90 / 4);
1011 de_skew = (phase_90 - 300 + (0x7*PHY_DE_SKEW_STEP) - ((phase_90 / 4) * dll_set));
1012 if (de_skew > PHY_DE_SKEW_STEP * 15) {
1020 de_skew = de_skew / PHY_DE_SKEW_STEP;
1023 pPHY_Reg->PHY_REG28 = dll_set;/*rx dll 45¡ãdelay*/
1024 pPHY_Reg->PHY_REG38 = dll_set;/*rx dll 45¡ãdelay*/
1025 pPHY_Reg->PHY_REG48 = dll_set;/*rx dll 45¡ãdelay*/
1026 pPHY_Reg->PHY_REG58 = dll_set;/*rx dll 45¡ãdelay*/
1027 pPHY_Reg->PHY_REG_skew[(0x324-0x2c0)/4] = 0x7 | (de_skew << 4);
1028 pPHY_Reg->PHY_REG_skew[(0x350-0x2c0)/4] = 0x7 | (de_skew << 4);
1029 pPHY_Reg->PHY_REG_skew[(0x37c-0x2c0)/4] = 0x7 | (de_skew << 4);
1030 pPHY_Reg->PHY_REG_skew[(0x3a8-0x2c0)/4] = 0x7 | (de_skew << 4);
1035 } else if (freq < 600) {
1039 pPHY_Reg->PHY_REG8 = phase;//rx dll 45¡ãdelay
1040 pPHY_Reg->PHY_REG11= phase;
1042 if (freq <= PHY_DLL_DISABLE_FREQ) {
1043 pPHY_Reg->PHY_REG2a = 0x1F; /*TX DLL bypass */
1045 pPHY_Reg->PHY_REG2a = 0x3; /* TX DLL bypass*/
1051 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id) /*APLL-1;CPLL-2;DPLL-3;GPLL-4*/
1055 if (((pCRU_Reg->CRU_MODE_CON >> (pll_id * 4)) & 1) == 1) /* DPLL Normal mode*/
1056 ret = 24 * ((pCRU_Reg->CRU_PLL_CON[pll_id][0] & 0xfff)) /* NF = 2*(CLKF+1)*/
1057 / ((pCRU_Reg->CRU_PLL_CON[pll_id][1] & 0x3f)
1058 * ((pCRU_Reg->CRU_PLL_CON[pll_id][0] >> 12) & 0x7) * ((pCRU_Reg->CRU_PLL_CON[pll_id][1] >> 6) & 0x7)); /* OD = 2^CLKOD*/
1065 static __sramdata uint32 clkFbDiv;
1066 static __sramdata uint32 clkPostDiv1;
1067 static __sramdata uint32 clkPostDiv2;
1069 /*****************************************
1070 *REFDIV FBDIV POSTDIV1/POSTDIV2 FOUTPOSTDIV freq Step FOUTPOSRDIV finally use
1071 *==================================================================================================================
1072 *1 17 - 66 4 100MHz - 400MHz 6MHz 200MHz <= 300MHz <= 150MHz
1073 *1 17 - 66 3 133MHz - 533MHz 8MHz
1074 *1 17 - 66 2 200MHz - 800MHz 12MHz 300MHz <= 600MHz 150MHz <= 300MHz
1075 *1 17 - 66 1 400MHz - 1600MHz 24MHz 600MHz <= 1200MHz 300MHz <= 600MHz
1076 *******************************************/
1077 /*for minimum jitter operation, the highest VCO and FREF frequencies should be used.*/
1078 /*----------------------------------------------------------------------
1079 *Name : uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
1081 *Params : nMHZ -> ddr¹¤×÷ƵÂÊ
1082 * set ->0»ñÈ¡ÉèÖõÄƵÂÊÐÅÏ¢
1084 *Return : ÉèÖõÄƵÂÊÖµ
1085 *Notes : ÔÚ±äƵʱÐèÒªÏÈset=0µ÷ÓÃÒ»´Îddr_set_pll£¬ÔÙset=1 µ÷ÓÃddr_set_pll
1086 -*---------------------------------------------------------------------*/
1087 static uint32 __sramfunc ddr_set_pll(uint32 nMHz, uint32 set)
1091 uint32 pll_id = 1; /*DPLL*/
1098 if (nMHz <= 150) { /*ʵ¼ÊÊä³öƵÂÊ<300*/
1100 } else if (nMHz <= 200) {
1102 } else if (nMHz <= 300) {
1104 } else if (nMHz <= 450) {
1110 clkFbDiv = (nMHz * 2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2) / 24; /*×îºóËÍÈëddrµÄÊÇÔÙ¾¹ý2·ÖƵ*/
1112 (24 * clkFbDiv) / (2 * DDR_PLL_REFDIV * clkPostDiv1 *
1115 pCRU_Reg->CRU_MODE_CON = (0x1 << ((pll_id * 4) + 16)) | (0x0 << (pll_id * 4)); /*PLL slow-mode*/
1117 pCRU_Reg->CRU_PLL_CON[pll_id][0] =
1118 FBDIV(clkFbDiv) | POSTDIV1(clkPostDiv1);
1119 pCRU_Reg->CRU_PLL_CON[pll_id][1] = REFDIV(DDR_PLL_REFDIV) | POSTDIV2(clkPostDiv2) | (0x10001 << 12); /*interger mode*/
1125 if (pCRU_Reg->CRU_PLL_CON[pll_id][1] & (PLL_LOCK_STATUS)) /*wait for pll locked*/
1130 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 << 16) | 0x0); /*clk_ddr_src:clk_ddrphy = 1:1*/
1131 pCRU_Reg->CRU_MODE_CON = (0x1 << ((pll_id * 4) + 16)) | (0x1 << (pll_id * 4)); /*PLL normal*/
1137 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1139 return ddr_set_pll(nMHz, set);
1142 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1143 static uint32(*p_ddr_set_pll) (uint32 nMHz, uint32 set);
1145 /*----------------------------------------------------------------------
1146 *Name : uint32_t ddr_get_parameter(uint32_t nMHz)
1147 *Desc : »ñÈ¡ÅäÖòÎÊý
1148 *Params : nMHZ -> ddr¹¤×÷ƵÂÊ
1151 * -4 ƵÂÊÖµ³¬¹ý¿ÅÁ£×î´óƵÂÊ
1153 *----------------------------------------------------------------------*/
1154 static uint32 ddr_get_parameter(uint32 nMHz)
1163 PCTL_TIMING_T *p_pctl_timing = &(p_ddr_reg->pctl_timing);
1164 NOC_TIMING_T *p_noc_timing = &(p_ddr_reg->noc_timing);
1166 p_pctl_timing->togcnt1u = nMHz;
1167 p_pctl_timing->togcnt100n = nMHz / 10;
1168 p_pctl_timing->tinit = 200;
1170 if (p_ddr_reg->ddr_speed_bin > DDR3_DEFAULT) {
1174 #define DDR3_tREFI_7_8_us (78)
1175 #define DDR3_tMRD (4)
1176 #define DDR3_tRFC_512Mb (90)
1177 #define DDR3_tRFC_1Gb (110)
1178 #define DDR3_tRFC_2Gb (160)
1179 #define DDR3_tRFC_4Gb (300)
1180 #define DDR3_tRFC_8Gb (350)
1181 #define DDR3_tRTW (2) /*register min valid value*/
1182 #define DDR3_tRAS (37)
1183 #define DDR3_tRRD (10)
1184 #define DDR3_tRTP (7)
1185 #define DDR3_tWR (15)
1186 #define DDR3_tWTR (7)
1187 #define DDR3_tXP (7)
1188 #define DDR3_tXPDLL (24)
1189 #define DDR3_tZQCS (80)
1190 #define DDR3_tZQCSI (10000)
1191 #define DDR3_tDQS (1)
1192 #define DDR3_tCKSRE (10)
1193 #define DDR3_tCKE_400MHz (7)
1194 #define DDR3_tCKE_533MHz (6)
1195 #define DDR3_tMOD (15)
1196 #define DDR3_tRSTL (100)
1197 #define DDR3_tZQCL (320)
1198 #define DDR3_tDLLK (512)
1199 p_pctl_timing->trsth = 500;
1204 } else if (nMHz <= 400) {
1206 } else if (nMHz <= 533) {
1211 if (nMHz <= DDR3_DDR2_DLL_DISABLE_FREQ) { /*when dll bypss cl = cwl = 6*/
1215 cl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] >> 16;
1217 ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] & 0x0ff;
1220 ret = -4; /*³¬¹ý¿ÅÁ£µÄ×î´óƵÂÊ*/
1222 if (nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ) {
1223 p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
1225 p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
1227 p_ddr_reg->ddrMR[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */ ;
1228 p_ddr_reg->ddrMR[3] = 0;
1229 /**************************************************
1231 **************************************************/
1233 * tREFI, average periodic refresh interval, 7.8us
1235 p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
1239 p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
1241 * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
1243 if (p_ddr_reg->ddr_capability_per_die <= 0x4000000) { /*512Mb 90ns*/
1244 tmp = DDR3_tRFC_512Mb;
1245 } else if (p_ddr_reg->ddr_capability_per_die <= 0x8000000) { /*1Gb 110ns*/
1246 tmp = DDR3_tRFC_1Gb;
1247 } else if (p_ddr_reg->ddr_capability_per_die <= 0x10000000) { /*2Gb 160ns*/
1248 tmp = DDR3_tRFC_2Gb;
1249 } else if (p_ddr_reg->ddr_capability_per_die <= 0x20000000) {/*4Gb 300ns*/
1250 tmp = DDR3_tRFC_4Gb;
1251 } else{ /*8Gb 350ns*/
1252 tmp = DDR3_tRFC_8Gb;
1254 p_pctl_timing->trfc = (tmp * nMHz + 999) / 1000;
1256 * tXSR, =tDLLK=512 tCK
1258 p_pctl_timing->texsr = DDR3_tDLLK;
1262 p_pctl_timing->trp = cl;
1264 * WrToMiss=WL*tCK + tWR + tRP + tRCD
1266 p_noc_timing->b.WrToMiss =
1267 ((cwl + ((DDR3_tWR * nMHz + 999) / 1000) + cl + cl) & 0x3F);
1271 p_pctl_timing->trc =
1272 ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin] >> 16) * nMHz +
1273 999) / 1000) & 0x3F);
1274 p_noc_timing->b.ActToAct =
1275 ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin] >> 16) * nMHz +
1276 999) / 1000) & 0x3F);
1278 p_pctl_timing->trtw = (cl + 2 - cwl); /*DDR3_tRTW*/
1279 p_noc_timing->b.RdToWr = ((cl + 2 - cwl) & 0x1F);
1280 p_pctl_timing->tal = al;
1281 p_pctl_timing->tcl = cl;
1282 p_pctl_timing->tcwl = cwl;
1284 * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
1286 p_pctl_timing->tras =
1287 (((DDR3_tRAS * nMHz + (nMHz >> 1) + 999) / 1000) & 0x3F);
1291 p_pctl_timing->trcd = cl;
1293 * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
1294 * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
1295 * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
1298 tmp = ((DDR3_tRRD * nMHz + 999) / 1000);
1302 p_pctl_timing->trrd = (tmp & 0xF);
1304 * tRTP, max(4 tCK,7.5ns)
1306 tmp = ((DDR3_tRTP * nMHz + (nMHz >> 1) + 999) / 1000);
1310 p_pctl_timing->trtp = tmp & 0xF;
1312 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
1314 p_noc_timing->b.RdToMiss = ((tmp + cl + cl - (bl >> 1)) & 0x3F);
1318 tmp = ((DDR3_tWR * nMHz + 999) / 1000);
1319 p_pctl_timing->twr = tmp & 0x1F;
1324 p_ddr_reg->ddrMR[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
1327 * tWTR, max(4 tCK,7.5ns)
1329 tmp = ((DDR3_tWTR * nMHz + (nMHz >> 1) + 999) / 1000);
1333 p_pctl_timing->twtr = tmp & 0xF;
1334 p_noc_timing->b.WrToRd = ((tmp + cwl) & 0x1F);
1336 * tXP, max(3 tCK, 7.5ns)(<933MHz)
1338 tmp = ((DDR3_tXP * nMHz + (nMHz >> 1) + 999) / 1000);
1342 p_pctl_timing->txp = tmp & 0x7;
1344 * tXPDLL, max(10 tCK,24ns)
1346 tmp = ((DDR3_tXPDLL * nMHz + 999) / 1000);
1350 p_pctl_timing->txpdll = tmp & 0x3F;
1352 * tZQCS, max(64 tCK, 80ns)
1354 tmp = ((DDR3_tZQCS * nMHz + 999) / 1000);
1358 p_pctl_timing->tzqcs = tmp & 0x7F;
1362 p_pctl_timing->tzqcsi = DDR3_tZQCSI;
1366 p_pctl_timing->tdqs = DDR3_tDQS;
1368 * tCKSRE, max(5 tCK, 10ns)
1370 tmp = ((DDR3_tCKSRE * nMHz + 999) / 1000);
1374 p_pctl_timing->tcksre = tmp & 0x1F;
1376 * tCKSRX, max(5 tCK, 10ns)
1378 p_pctl_timing->tcksrx = tmp & 0x1F;
1380 * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
1383 tmp = ((DDR3_tCKE_533MHz * nMHz + 999) / 1000);
1386 ((DDR3_tCKE_400MHz * nMHz + (nMHz >> 1) +
1392 p_pctl_timing->tcke = tmp & 0x7;
1394 * tCKESR, =tCKE + 1tCK
1396 p_pctl_timing->tckesr = (tmp + 1) & 0xF;
1398 * tMOD, max(12 tCK,15ns)
1400 tmp = ((DDR3_tMOD * nMHz + 999) / 1000);
1404 p_pctl_timing->tmod = tmp & 0x1F;
1408 p_pctl_timing->trstl =
1409 ((DDR3_tRSTL * nMHz + 999) / 1000) & 0x7F;
1411 * tZQCL, max(256 tCK, 320ns)
1413 tmp = ((DDR3_tZQCL * nMHz + 999) / 1000);
1417 p_pctl_timing->tzqcl = tmp & 0x3FF;
1421 p_pctl_timing->tmrr = 0;
1425 p_pctl_timing->tdpd = 0;
1427 /**************************************************
1429 **************************************************/
1430 p_noc_timing->b.BurstLen = ((bl >> 1) & 0x7);
1435 /*----------------------------------------------------------------------
1436 *Name : uint32_t __sramlocalfunc ddr_update_timing(void)
1437 *Desc : ¸üÐÂpctl phy Ïà¹Øtiming¼Ä´æÆ÷
1441 *----------------------------------------------------------------------*/
1442 static uint32 __sramfunc ddr_update_timing(void)
1446 PCTL_TIMING_T *p_pctl_timing = &(DATA(ddr_reg).pctl_timing);
1447 NOC_TIMING_T *p_noc_timing = &(DATA(ddr_reg).noc_timing);
1449 ddr_copy((uint32 *)&(pDDR_Reg->TOGCNT1U),
1450 (uint32 *)&(p_pctl_timing->togcnt1u), 34);
1451 /* pPHY_Reg->PHY_REG3 |= PHY_Burst8;*/ /*ddr3 burst length¹Ì¶¨Îª8*/
1452 pPHY_Reg->PHY_REG4a = ((p_pctl_timing->tcl << 4) | (p_pctl_timing->tal));
1453 *(volatile uint32 *)SysSrv_DdrTiming = p_noc_timing->d32;
1455 pDDR_Reg->MCFG =(pDDR_Reg->MCFG &
1456 (~(0x1 | (0x3 << 18) | (0x1 << 17) | (0x1 << 16))))
1457 | ddr2_ddr3_bl_8 | tfaw_cfg(5) | pd_exit_slow | pd_type(1);
1458 pDDR_Reg->DFITRDDATAEN = (pDDR_Reg->TAL + pDDR_Reg->TCL) - 3; /*trdata_en = rl-3*/
1459 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL - 1;
1463 /*----------------------------------------------------------------------
1464 *Name : uint32_t __sramlocalfunc ddr_update_mr(void)
1465 *Desc : ¸üпÅÁ£MR¼Ä´æÆ÷
1469 *----------------------------------------------------------------------*/
1470 static uint32 __sramfunc ddr_update_mr(void)
1473 cs = READ_CS_INFO();
1474 cs = (1 << cs) - 1; */
1475 if (DATA(ddr_freq) > DDR3_DDR2_DLL_DISABLE_FREQ) {
1476 if (DATA(ddr_dll_status) == DDR3_DLL_DISABLE) { /*off -> on*/
1477 ddr_send_command(3, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1]))); /*DLL enable*/
1478 ddr_send_command(3, MRS_cmd, bank_addr(0x0) | cmd_addr(((DATA(ddr_reg).ddrMR[0])) | DDR3_DLL_RESET)); /*DLL reset*/
1479 ddr_delayus(2); /*at least 200 DDR cycle*/
1480 ddr_send_command(3, MRS_cmd, bank_addr(0x0) |
1481 cmd_addr((DATA(ddr_reg).ddrMR[0])));
1482 DATA(ddr_dll_status) = DDR3_DLL_ENABLE;
1483 } else{ /*on -> on*/
1484 ddr_send_command(3, MRS_cmd, bank_addr(0x1) |
1485 cmd_addr((DATA(ddr_reg).ddrMR[1])));
1486 ddr_send_command(3, MRS_cmd, bank_addr(0x0) |
1487 cmd_addr((DATA(ddr_reg).ddrMR[0])));
1490 ddr_send_command(3, MRS_cmd, bank_addr(0x1) | cmd_addr(((DATA(ddr_reg).ddrMR[1])) | DDR3_DLL_DISABLE)); /*DLL disable*/
1491 ddr_send_command(3, MRS_cmd, bank_addr(0x0) |
1492 cmd_addr((DATA(ddr_reg).ddrMR[0])));
1493 DATA(ddr_dll_status) = DDR3_DLL_DISABLE;
1495 ddr_send_command(3, MRS_cmd, bank_addr(0x2) |
1496 cmd_addr((DATA(ddr_reg).ddrMR[2])));
1501 /*----------------------------------------------------------------------
1502 *Name : void __sramlocalfunc ddr_update_odt(void)
1503 *Desc : update PHY odt & PHY driver impedance
1506 *Notes :-------------------------------------------------*/
1507 static void __sramfunc ddr_update_odt(void)
1509 /*adjust DRV and ODT*/
1511 if (DATA(ddr_freq) <= PHY_ODT_DISABLE_FREQ) {
1512 phy_odt = PHY_RTT_DISABLE;
1514 phy_odt = PHY_RTT_216ohm;
1517 pPHY_Reg->PHY_REG27 = PHY_DRV_ODT_SET(phy_odt); /*DQS0 odt*/
1518 pPHY_Reg->PHY_REG28 = PHY_DRV_ODT_SET(phy_odt); /*DQS1 odt*/
1520 pPHY_Reg->PHY_REG16 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*cmd drv*/
1521 pPHY_Reg->PHY_REG22 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*clk drv*/
1523 pPHY_Reg->PHY_REG25 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*DQS0 drv*/
1524 pPHY_Reg->PHY_REG36 = PHY_DRV_ODT_SET(PHY_RON_44ohm); /*DQS1 drv*/
1529 void PIE_FUNC(ddr_adjust_config)(void)
1531 /*enter config state*/
1532 ddr_move_to_Config_state();
1534 /*set auto power down idle*/
1535 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & 0xffff00ff) | (PD_IDLE << 8);
1536 /*enable the hardware low-power interface*/
1537 pDDR_Reg->SCFG.b.hw_low_power_en = 1;
1539 /*enter access state*/
1540 ddr_move_to_Access_state();
1543 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
1545 /*----------------------------------------------------------------------
1546 Name : __sramfunc void ddr_adjust_config(uint32_t dram_type)
1548 Params : dram_type ->¿ÅÁ£ÀàÐÍ
1551 ----------------------------------------------------------------------*/
1553 static void ddr_adjust_config(uint32_t dram_type)
1555 unsigned long save_sp;
1558 volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
1560 /** 1. Make sure there is no host access */
1564 for (i = 0; i < 2; i++) {
1568 n = pDDR_Reg->SCFG.d32;
1569 n = pPHY_Reg->PHY_REG1;
1570 n = pCRU_Reg->CRU_PLL_CON[0][0];
1571 n = *(volatile uint32_t *)SysSrv_DdrTiming;
1574 call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
1575 (void *)0, rockchip_sram_stack);
1580 static void __sramfunc idle_port(void)
1583 uint32 clk_gate[11];
1585 uint32 idle_req, idle_stus;
1586 /*bit0:core bit1:gpu bit2:video bit3:vio 1:power off*/
1587 pd_status = *(volatile uint32 *)PMU_PWEDN_ST;
1588 /*save clock gate status*/
1589 for (i = 0; i < 11; i++) {
1590 clk_gate[i] = pCRU_Reg->CRU_CLKGATE_CON[i];
1592 /*enable all clock gate for request idle*/
1593 for (i = 0; i < 11; i++) {
1594 pCRU_Reg->CRU_CLKGATE_CON[i] = 0xffff0000;
1597 idle_req = (1 << peri_pwr_idlereq); /*peri*/
1598 idle_stus = peri_pwr_idle;
1599 if ((pd_status & (0x1<<3)) == 0) {/*pwr_vio*/
1600 idle_req |= (1 << vio_pwr_idlereq);
1601 idle_stus |= vio_pwr_idle;
1603 if ((pd_status & (0x1<<2)) == 0) {/*pwr_vpu*/
1604 idle_req |= (1 << vpu_pwr_idlereq);
1605 idle_stus |= vpu_pwr_idle;
1607 if ((pd_status & (0x1<<1)) == 0) {/*pwr_gpu*/
1608 idle_req |= (1 << gpu_pwr_idlereq);
1609 idle_stus |= gpu_pwr_idle;
1612 pGRF_Reg->GRF_SOC_CON[2] = (idle_req << 16) | idle_req;
1614 while ((pGRF_Reg->GRF_SOC_STATUS0 & idle_stus) != idle_stus)
1617 /*resume clock gate status*/
1618 for (i = 0; i < 11; i++)
1619 pCRU_Reg->CRU_CLKGATE_CON[i] = (clk_gate[i] | 0xffff0000);
1622 static void __sramfunc deidle_port(void)
1625 uint32 clk_gate[11];
1627 uint32 idle_req, idle_stus;
1628 /*bit0:core bit1:gpu bit2:video bit3:vio 1:power off*/
1629 pd_status = *(volatile uint32 *)PMU_PWEDN_ST;
1631 /*save clock gate status*/
1632 for (i = 0; i < 11; i++) {
1633 clk_gate[i] = pCRU_Reg->CRU_CLKGATE_CON[i];
1635 /*enable all clock gate for request idle*/
1636 for (i = 0; i < 11; i++) {
1637 pCRU_Reg->CRU_CLKGATE_CON[i] = 0xffff0000;
1640 idle_req = (1 << peri_pwr_idlereq); /*peri*/
1641 idle_stus = peri_pwr_idle;
1642 if ((pd_status & (0x1<<3)) == 0) {/*pwr_vio*/
1643 idle_req |= (1 << vio_pwr_idlereq);
1644 idle_stus |= vio_pwr_idle;
1646 if ((pd_status & (0x1<<2)) == 0) {/*pwr_vpu*/
1647 idle_req |= (1 << vpu_pwr_idlereq);
1648 idle_stus |= vpu_pwr_idle;
1650 if ((pd_status & (0x1<<1)) == 0) {/*pwr_gpu*/
1651 idle_req |= (1 << gpu_pwr_idlereq);
1652 idle_stus |= gpu_pwr_idle;
1655 pGRF_Reg->GRF_SOC_CON[2] = (idle_req << 16) | 0 ;
1657 while ((pGRF_Reg->GRF_SOC_STATUS0 & idle_stus) != 0)
1660 /*resume clock gate status*/
1661 for (i = 0; i < 11; i++)
1662 pCRU_Reg->CRU_CLKGATE_CON[i] = (clk_gate[i] | 0xffff0000);
1666 /*----------------------------------------------------------------------
1667 *Name : void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
1669 *Params : nMHz ->ddrƵÂÊ
1672 *----------------------------------------------------------------------*/
1674 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
1676 ddr_move_to_Config_state();
1677 ddr_move_to_Lowpower_state();
1678 /*pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_EN;*/
1679 pPHY_Reg->PHY_REG264 &= ~(1<<1);
1680 pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3 << 2))); /*phy soft reset*/
1682 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1 << 2) << 16) | (1 << 2); /*disable DDR PHY clock*/
1687 static uint32 dtt_buffer[8];
1689 /*----------------------------------------------------------------------
1690 *Name : void ddr_dtt_check(void)
1691 *Desc : data training check
1695 *----------------------------------------------------------------------*/
1696 static void ddr_dtt_check(void)
1699 for (i = 0; i < 8; i++) {
1700 dtt_buffer[i] = p_copy_data[i];
1705 for (i = 0; i < 8; i++) {
1706 if (dtt_buffer[i] != p_copy_data[i]) {
1707 /* sram_printascii("DTT failed!\n");*/
1714 /*----------------------------------------------------------------------
1715 Name : void __sramlocalfunc ddr_selfrefresh_exit(void)
1720 ----------------------------------------------------------------------*/
1722 static void __sramfunc ddr_selfrefresh_exit(void)
1724 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1 << 2) << 16) | (0 << 2); /*enable DDR PHY clock*/
1727 pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); /*phy soft de-reset*/
1728 /*pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_DISB;*/
1729 pPHY_Reg->PHY_REG264 |= (1<<1);
1731 ddr_move_to_Config_state();
1732 ddr_data_training();
1733 ddr_move_to_Access_state();
1734 /* ddr_dtt_check();*/
1738 /*----------------------------------------------------------------------
1739 *Name : void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
1740 *Desc : ÉèÖÃddr pllÇ°µÄtiming¼°mr²ÎÊýµ÷Õû
1741 *Params : freq_slew :±äƵбÂÊ 1Éýƽ 0½µÆµ
1744 *----------------------------------------------------------------------*/
1745 static void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
1747 uint32 value_100n, value_1u;
1749 if (freq_slew == 1) {
1750 value_100n = DATA(ddr_reg).pctl_timing.togcnt100n;
1751 value_1u = DATA(ddr_reg).pctl_timing.togcnt1u;
1752 DATA(ddr_reg).pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
1753 DATA(ddr_reg).pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
1754 ddr_update_timing();
1756 DATA(ddr_reg).pctl_timing.togcnt100n = value_100n;
1757 DATA(ddr_reg).pctl_timing.togcnt1u = value_1u;
1759 pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
1760 pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
1763 pDDR_Reg->TZQCSI = 0;
1767 /*----------------------------------------------------------------------
1768 *Name : void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
1769 *Desc : ÉèÖÃddr pllºóµÄtiming¼°mr²ÎÊýµ÷Õû
1770 *Params : freq_slew :±äƵбÂÊ 1Éýƽ 0½µÆµ
1773 *----------------------------------------------------------------------*/
1774 static void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
1776 if (freq_slew == 1) {
1777 pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
1778 pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
1779 pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl_timing.tzqcsi;
1781 ddr_update_timing();
1784 ddr_data_training();
1787 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew)
1791 ddr_move_to_Config_state();
1792 DATA(ddr_freq) = freq;
1793 ddr_change_freq_in(freq_slew);
1794 ddr_move_to_Lowpower_state();
1795 /*pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_EN;*/
1796 pPHY_Reg->PHY_REG264 &= ~(1<<1);
1797 pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2))); //phy soft reset
1799 /* 3. change frequence */
1800 FUNC(ddr_set_pll) (freq, 1);
1801 ddr_set_dll_bypass(freq); /*set phy dll mode;*/
1802 /*pPHY_Reg->PHY_REG0 = (pPHY_Reg->PHY_REG0 | (0x3 << 2)); */ /*phy soft de-reset */
1803 pPHY_Reg->PHY_REG1 |= (1 << 2); /*soft de-reset analogue(dll)*/
1805 pPHY_Reg->PHY_REG1 |= (1 << 3);/*soft de-reset digital*/
1806 /*pGRF_Reg->GRF_SOC_CON[2] = GRF_DDR_LP_DISB;*/
1807 pPHY_Reg->PHY_REG264 |= (1<<1);
1810 ddr_move_to_Config_state();
1811 ddr_change_freq_out(freq_slew);
1812 ddr_move_to_Access_state();
1817 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
1819 struct ddr_change_freq_sram_param *param = arg;
1820 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
1821 ddr_SRE_2_SRX(param->freq, param->freq_slew);
1824 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
1826 typedef struct freq_tag {
1828 struct ddr_freq_t *p_ddr_freq_t;
1831 /*----------------------------------------------------------------------
1832 *Name : uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
1834 *Params : nMHz -> ±äƵµÄƵÂÊÖµ
1837 *----------------------------------------------------------------------*/
1838 static uint32 ddr_change_freq_sram(void *arg)
1843 unsigned long flags;
1844 volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
1845 freq_t *p_freq_t = (freq_t *) arg;
1846 uint32 nMHz = p_freq_t->nMHz;
1847 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
1848 struct ddr_freq_t *p_ddr_freq_t = p_freq_t->p_ddr_freq_t;
1851 struct ddr_change_freq_sram_param param;
1855 arm_freq = ddr_get_pll_freq(APLL);
1856 *kern_to_pie(rockchip_pie_chunk, &DATA(loops_per_us)) =
1857 LPJ_100MHZ * arm_freq / 1000000;
1858 ret = p_ddr_set_pll(nMHz, 0);
1859 if (ret == *p_ddr_freq) {
1862 freq_slew = (ret > *p_ddr_freq) ? 1 : -1;
1864 ddr_get_parameter(ret);
1865 /*kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq))= ret;*/
1866 /** 1. Make sure there is no host access */
1867 local_irq_save(flags);
1868 local_fiq_disable();
1873 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
1874 if (p_ddr_freq_t->screen_ft_us > 0) {
1875 p_ddr_freq_t->t1 = cpu_clock(0);
1876 p_ddr_freq_t->t2 = (uint32)(p_ddr_freq_t->t1 - p_ddr_freq_t->t0); /*ns*/
1878 if ((p_ddr_freq_t->t2 > p_ddr_freq_t->screen_ft_us*1000) && (p_ddr_freq_t->screen_ft_us != 0xfefefefe)) {
1882 rk_fb_poll_wait_frame_complete();
1887 for (i = 0; i < 2; i++) {
1891 n = pDDR_Reg->SCFG.d32;
1892 n = pPHY_Reg->PHY_REG1;
1893 n = pCRU_Reg->CRU_PLL_CON[0][0];
1894 n = *(volatile uint32_t *)SysSrv_DdrTiming;
1895 n = pGRF_Reg->GRF_SOC_STATUS0;
1898 param.freq_slew = freq_slew;
1899 call_with_stack(fn_to_pie
1900 (rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
1902 rockchip_sram_stack - (NR_CPUS -
1903 1) * PAUSE_CPU_STACK_SIZE);
1904 /** 5. Issues a Mode Exit command */
1906 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
1910 local_irq_restore(flags);
1911 /* clk_set_rate(clk_get(NULL, "ddr_pll"), 0); */
1916 bool DEFINE_PIE_DATA(cpu_pause[NR_CPUS]);
1917 volatile bool *DATA(p_cpu_pause);
1918 static inline bool is_cpu0_paused(unsigned int cpu)
1921 return DATA(cpu_pause)[0];
1924 static inline void set_cpuX_paused(unsigned int cpu, bool pause)
1926 DATA(cpu_pause)[cpu] = pause;
1930 static inline bool is_cpuX_paused(unsigned int cpu)
1933 return DATA(p_cpu_pause)[cpu];
1936 static inline void set_cpu0_paused(bool pause)
1938 DATA(p_cpu_pause)[0] = pause;
1942 #define MAX_TIMEOUT (16000000UL << 6) /*>0.64s*/
1944 /* Do not use stack, safe on SMP */
1945 void PIE_FUNC(_pause_cpu)(void *arg)
1947 unsigned int cpu = (unsigned int)arg;
1949 set_cpuX_paused(cpu, true);
1950 while (is_cpu0_paused(cpu))
1952 set_cpuX_paused(cpu, false);
1955 static void pause_cpu(void *info)
1957 unsigned int cpu = raw_smp_processor_id();
1959 call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(_pause_cpu)),
1961 rockchip_sram_stack - (cpu - 1) * PAUSE_CPU_STACK_SIZE);
1964 static void wait_cpu(void *info)
1968 static int call_with_single_cpu(u32(*fn) (void *arg), void *arg)
1970 u32 timeout = MAX_TIMEOUT;
1972 unsigned int this_cpu = smp_processor_id(); /*»ñÈ¡µ±Ç°cpu*/
1974 cpu_maps_update_begin();
1975 local_bh_disable(); /*disable swi*/
1976 set_cpu0_paused(true);
1977 smp_call_function((smp_call_func_t) pause_cpu, NULL, 0);
1979 for_each_online_cpu(cpu) {
1980 if (cpu == this_cpu)
1982 while (!is_cpuX_paused(cpu) && --timeout)
1985 pr_err("pause cpu %d timeout\n", cpu);
1993 set_cpu0_paused(false);
1995 smp_call_function(wait_cpu, NULL, true);
1996 cpu_maps_update_done();
2001 static int __ddr_change_freq(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
2007 freq.p_ddr_freq_t = &ddr_freq_t;
2008 ret = call_with_single_cpu(&ddr_change_freq_sram, (void *)&freq);
2009 /*ret = ddr_change_freq_sram((void*)&freq);*/
2013 static int _ddr_change_freq(uint32 nMHz)
2015 struct ddr_freq_t ddr_freq_t;
2016 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
2017 unsigned long remain_t, vblank_t, pass_t;
2018 static unsigned long reserve_t = 800; /*us*/
2019 unsigned long long tmp;
2023 /*ddr_print("ddr change freq to:%d\n",nMHz);*/
2024 memset(&ddr_freq_t, 0x00, sizeof(ddr_freq_t));
2026 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
2028 ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
2029 ddr_freq_t.t0 = rk_fb_get_prmry_screen_framedone_t();
2030 if (!ddr_freq_t.screen_ft_us)
2031 return __ddr_change_freq(nMHz, ddr_freq_t);
2033 tmp = cpu_clock(0) - ddr_freq_t.t0;
2036 /*lost frame interrupt*/
2037 while (pass_t > ddr_freq_t.screen_ft_us) {
2038 int n = pass_t / ddr_freq_t.screen_ft_us;
2040 /*printk("lost frame int, pass_t:%lu\n", pass_t);*/
2041 pass_t -= n * ddr_freq_t.screen_ft_us;
2042 ddr_freq_t.t0 += n * ddr_freq_t.screen_ft_us * 1000;
2045 remain_t = ddr_freq_t.screen_ft_us - pass_t;
2046 if (remain_t < reserve_t) {
2047 /*printk("remain_t(%lu) < reserve_t(%lu)\n", remain_t, reserve_t);*/
2048 vblank_t = rk_fb_get_prmry_screen_vbt();
2049 usleep_range(remain_t + vblank_t, remain_t + vblank_t);
2054 if (test_count > 10) {
2055 ddr_freq_t.screen_ft_us = 0xfefefefe;
2057 /*printk("ft:%lu, pass_t:%lu, remaint_t:%lu, reservet_t:%lu\n",
2058 * ddr_freq_t.screen_ft_us, (unsigned long)pass_t, remain_t, reserve_t);*/
2059 usleep_range(remain_t - reserve_t, remain_t - reserve_t);
2062 ret = __ddr_change_freq(nMHz, ddr_freq_t);
2067 if (reserve_t < 3000)
2072 ret = __ddr_change_freq(nMHz, ddr_freq_t);
2078 /*----------------------------------------------------------------------
2079 *Name : void ddr_set_auto_self_refresh(bool en)
2080 *Desc : ÉèÖýøÈë selfrefesh µÄÖÜÆÚÊý
2081 *Params : en -> ʹÄÜauto selfrefresh
2083 *Notes : ÖÜÆÚÊýΪ1*32 cycle
2084 *----------------------------------------------------------------------*/
2085 static void _ddr_set_auto_self_refresh(bool en)
2087 /*set auto self-refresh idle */
2088 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
2091 /*----------------------------------------------------------------------
2092 *Name : void __sramfunc ddr_suspend(void)
2093 *Desc : ½øÈëddr suspend
2097 *----------------------------------------------------------------------*/
2098 void PIE_FUNC(ddr_suspend)(void)
2100 ddr_selfrefresh_enter(0);
2101 pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x0 << (1 * 4)); /*PLL slow-mode*/
2104 pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x1 << 13); /*PLL power-down*/
2110 EXPORT_PIE_SYMBOL(FUNC(ddr_suspend));
2113 static void ddr_suspend(void)
2117 volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
2118 /** 1. Make sure there is no host access */
2121 /*flush_tlb_all();*/
2124 for (i = 0; i < 2; i++) {
2128 n = pDDR_Reg->SCFG.d32;
2129 n = pPHY_Reg->PHY_REG1;
2130 n = pCRU_Reg->CRU_PLL_CON[0][0];
2131 n = *(volatile uint32_t *)SysSrv_DdrTiming;
2132 n = pGRF_Reg->GRF_SOC_STATUS0;
2135 fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_suspend)) ();
2139 /*----------------------------------------------------------------------
2140 *Name : void __sramfunc ddr_resume(void)
2145 *----------------------------------------------------------------------*/
2146 void PIE_FUNC(ddr_resume)(void)
2148 uint32 delay = 1000;
2150 pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x0 << 13); /*PLL no power-down*/
2154 if (pCRU_Reg->CRU_PLL_CON[1][1] & (0x1 << 10))
2159 pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x1 << (1 * 4)); /*PLL normal*/
2162 ddr_selfrefresh_exit();
2165 EXPORT_PIE_SYMBOL(FUNC(ddr_resume));
2168 static void ddr_resume(void)
2170 fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)) ();
2174 /*----------------------------------------------------------------------
2175 *Name : uint32 ddr_get_cap(void)
2176 *Desc : »ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
2180 *----------------------------------------------------------------------*/
2181 static uint32 ddr_get_cap(void)
2183 uint32 cs, bank, row, col, row1, bw;
2185 bank = READ_BK_INFO();
2186 row = READ_CS0_ROW_INFO();
2187 col = READ_COL_INFO();
2188 cs = READ_CS_INFO();
2189 bw = READ_BW_INFO();
2191 row1 = READ_CS1_ROW_INFO();
2192 return ((1 << (row + col + bank + bw)) +
2193 (1 << (row1 + col + bank + bw)));
2195 return (1 << (row + col + bank + bw));
2199 static long _ddr_round_rate(uint32 nMHz)
2201 return p_ddr_set_pll(nMHz, 0);
2204 enum ddr_bandwidth_id{
2212 static void ddr_dfi_monitor_strat(void)
2214 pGRF_Reg->GRF_SOC_CON[0] = DDR_MONITOR_EN;
2216 static void ddr_dfi_monitor_stop(void)
2218 pGRF_Reg->GRF_SOC_CON[0] = DDR_MONITOR_DISB;
2221 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0, struct ddr_bw_info *ddr_bw_ch1)
2223 uint32 ddr_bw_val[ddrbw_id_end], ddr_freq;
2228 ddr_bw = READ_BW_INFO();
2229 ddr_dfi_monitor_stop();
2230 for (i = 0; i < ddrbw_id_end; i++) {
2231 ddr_bw_val[i] = *(uint32 *)(&(pGRF_Reg->GRF_DFI_WRNUM) + i);
2233 if (!ddr_bw_val[ddrbw_time_num])
2236 ddr_freq = pDDR_Reg->TOGCNT1U;
2237 temp64 = ((u64)ddr_bw_val[ddrbw_wr_num] + (u64)ddr_bw_val[ddrbw_rd_num])*4*100;
2238 do_div(temp64, ddr_bw_val[ddrbw_time_num]);
2240 ddr_bw_ch0->ddr_percent = (uint32)temp64;
2241 ddr_bw_ch0->ddr_time = ddr_bw_val[ddrbw_time_num]/(ddr_freq*1000); /*ms*/
2242 ddr_bw_ch0->ddr_wr = (ddr_bw_val[ddrbw_wr_num]*8*ddr_bw*2)*ddr_freq/ddr_bw_val[ddrbw_time_num];/*Byte/us,MB/s*/
2243 ddr_bw_ch0->ddr_rd = (ddr_bw_val[ddrbw_rd_num]*8*ddr_bw*2)*ddr_freq/ddr_bw_val[ddrbw_time_num];
2244 ddr_bw_ch0->ddr_act = ddr_bw_val[ddrbw_act_num];
2245 ddr_bw_ch0->ddr_total = ddr_freq*2*ddr_bw*2;
2247 ddr_dfi_monitor_strat();
2250 /*----------------------------------------------------------------------
2251 *Name : int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
2252 *Desc : ddr ³õʼ»¯º¯Êý
2253 *Params : dram_speed_bin ->ddr¿ÅÁ£ÀàÐÍ
2257 *----------------------------------------------------------------------*/
2258 static int ddr_init(uint32_t dram_speed_bin, uint32 freq)
2261 uint32_t cs, die = 1;
2262 /*uint32_t calStatusLeft, calStatusRight*/
2265 ddr_print("version 1.02 20140828\n");
2266 cs = READ_CS_INFO(); /*case 1:1rank ; case 2:2rank*/
2268 p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
2269 p_ddr_freq = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
2270 p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
2272 kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
2273 p_ddr_reg->mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) & 0x7);
2274 p_ddr_reg->ddr_speed_bin = dram_speed_bin;
2276 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
2277 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_dll_status)) =
2279 p_copy_data = kern_to_pie(rockchip_pie_chunk, ©_data[0]);
2281 switch (p_ddr_reg->mem_type) {
2283 ddr_print("DRAM Type:DDR3\n");
2286 ddr_print("DRAM Type:LPDDR2\n");
2289 ddr_print("ddr type error type=%d\n", (p_ddr_reg->mem_type));
2291 die = 1 << (READ_BW_INFO() - READ_DIE_BW_INFO());
2292 p_ddr_reg->ddr_capability_per_die = ddr_get_cap() / (cs * die);
2293 ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n",
2294 cs, READ_CS0_ROW_INFO(),
2295 (0x1 << (READ_BK_INFO())),
2297 (ddr_get_cap() >> 20));
2299 clk = clk_get(NULL, "clk_ddr");
2301 ddr_print("failed to get ddr clk\n");
2305 value = clk_set_rate(clk, 1000 * 1000 * freq);
2307 value = clk_set_rate(clk, clk_get_rate(clk));
2308 ddr_print("init success!!! freq=%luMHz\n",
2309 clk ? clk_get_rate(clk) / 1000000 : freq);