arch/arm/mach-rockchip/ddr_rk32.c

   1 /*
   2  * Function Driver for DDR controller
   3  *
   4  * Copyright (C) 2011-2014 Fuzhou Rockchip Electronics Co.,Ltd
   5  * Author:
   6  * hcy@rock-chips.com
   7  * yk@rock-chips.com
   8  *
   9  * v1.00
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/tlbflush.h>
  19 #include <linux/cpu.h>
  20 #include <dt-bindings/clock/ddr.h>
  21 #include <linux/rockchip/cpu_axi.h>
  22 #include <linux/rockchip/cru.h>
  23 #include <linux/rk_fb.h>
  24
  25 typedef uint32_t uint32;
  26
  27 #ifdef CONFIG_FB_ROCKCHIP
  28 #define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
  29 #endif
  30 /***********************************
  31  * Global Control Macro
  32  ***********************************/
  33 //#define ENABLE_DDR_CLCOK_GPLL_PATH  //for RK3188
  34
  35 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)
  36 #define DDR3_DDR2_DLL_DISABLE_FREQ    (333)
  37 #define SR_IDLE                       (0x3)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
  38 #define PD_IDLE                       (0X40)  //unit:DDR clk cycle, and 0 for disable auto power-down
  39
  40 //#if (DDR3_DDR2_ODT_DISABLE_FREQ > DDR3_DDR2_DLL_DISABLE_FREQ)
  41 //#error
  42 //#endif
  43
  44 #define ddr_print(x...) printk( "DDR DEBUG: " x )
  45
  46 /***********************************
  47  * ARCH Relative Macro and Struction
  48  ***********************************/
  49 #define SRAM_CODE_OFFSET        rockchip_sram_virt
  50 #define SRAM_SIZE               rockchip_sram_size
  51
  52 /*
  53  * PMU
  54  */
  55 //PMU_PWRDN_ST
  56 #define pd_scu_pwr_st       (1<<11)
  57 #define pd_hevc_pwr_st      (1<<10)
  58 #define pd_gpu_pwr_st       (1<<9)
  59 #define pd_video_pwr_st     (1<<8)
  60 #define pd_vio_pwr_st       (1<<7)
  61 #define pd_peri_pwr_st      (1<<6)
  62 #define pd_bus_pwr_st      (1<<5)
  63 //PMU_IDLE_REQ
  64 #define idle_req_hevc_cfg   (1<<9)
  65 #define idle_req_cpup_cfg   (1<<8)
  66 #define idle_req_dma_cfg    (1<<7)
  67 #define idle_req_alive_cfg  (1<<6)
  68 #define idle_req_core_cfg   (1<<5)
  69 #define idle_req_vio_cfg    (1<<4)
  70 #define idle_req_video_cfg  (1<<3)
  71 #define idle_req_gpu_cfg    (1<<2)
  72 #define idle_req_peri_cfg   (1<<1)
  73 #define idle_req_bus_cfg    (1<<0)
  74
  75 //PMU_IDLE_ST
  76 #define idle_ack_hevc     (1<<25)
  77 #define idle_ack_cpup     (1<<24)
  78 #define idle_ack_dma      (1<<23)
  79 #define idle_ack_alive    (1<<22)
  80 #define idle_ack_core     (1<<21)
  81 #define idle_ack_vio      (1<<20)
  82 #define idle_ack_video    (1<<19)
  83 #define idle_ack_gpu      (1<<18)
  84 #define idle_ack_peir     (1<<17)
  85 #define idle_ack_bus      (1<<16)
  86
  87 #define idle_hevc   (1<<9)
  88 #define idle_cpup   (1<<8)
  89 #define idle_dma    (1<<7)
  90 #define idle_alive  (1<<6)
  91 #define idle_core   (1<<5)
  92 #define idle_vio    (1<<4)
  93 #define idle_video  (1<<3)
  94 #define idle_gpu    (1<<2)
  95 #define idle_peri   (1<<1)
  96 #define idle_bus    (1<<0)
  97
  98 //PMU_PWRMODE_CON
  99 /* ch=0, channel a
 100    ch=1, channel b
 101  */
 102 #define ddrio_ret_de_req(ch)  (1<<(21+(ch)))
 103 #define ddrc_gating_en(ch)    (1<<(19+(ch)))
 104 #define ddrio_ret_en(ch)      (1<<(17+(ch)))
 105 #define sref_enter_en(ch)     (1<<(15+(ch)))
 106
 107 //PMU_PWR_STATE
 108 #define SREF_EXIT             (1<<26)
 109 #define DDR_IO_PWRUP          (1<<25)
 110
 111 //PMU registers
 112 typedef volatile struct tagPMU_FILE
 113 {
 114     uint32 PMU_WAKEUP_CFG[2];
 115     uint32 PMU_PWRDN_CON;
 116     uint32 PMU_PWRDN_ST;
 117     uint32 PMU_IDLE_REQ;
 118     uint32 PMU_IDLE_ST;
 119     uint32 PMU_PWRMODE_CON;
 120     uint32 PMU_PWR_STATE;
 121     uint32 PMU_OSC_CNT;
 122     uint32 PMU_PLL_CNT;
 123     uint32 PMU_STABL_CNT;
 124     uint32 PMU_DDR0IO_PWRON_CNT;
 125     uint32 PMU_DDR1IO_PWRON_CNT;
 126     uint32 PMU_CORE_PWRDN_CNT;
 127     uint32 PMU_CORE_PWRUP_CNT;
 128     uint32 PMU_GPU_PWRDWN_CNT;
 129     uint32 PMU_GPU_PWRUP_CNT;
 130     uint32 PMU_WAKEUP_RST_CLR_CNT;
 131     uint32 PMU_SFT_CON;
 132     uint32 PMU_DDR_SREF_ST;
 133     uint32 PMU_INT_CON;
 134     uint32 PMU_INT_ST;
 135     uint32 PMU_BOOT_ADDR_SEL;
 136     uint32 PMU_GRF_CON;
 137     uint32 PMU_GPIO_SR;
 138     uint32 PMU_GPIO0_A_PULL;
 139     uint32 PMU_GPIO0_B_PULL;
 140     uint32 PMU_GPIO0_C_PULL;
 141     uint32 PMU_GPIO0_A_DRV;
 142     uint32 PMU_GPIO0_B_DRV;
 143     uint32 PMU_GPIO0_C_DRV;
 144     uint32 PMU_GPIO_OP;
 145     uint32 PMU_GPIO0_SEL18;
 146     uint32 PMU_GPIO0_A_IOMUX;
 147     uint32 PMU_GPIO0_B_IOMUX;
 148     uint32 PMU_GPIO0_C_IOMUX;
 149     uint32 PMU_GPIO0_D_IOMUX;
 150     uint32 PMU_PMU_SYS_REG[4];
 151 }PMU_FILE, *pPMU_FILE;
 152
 153 /*
 154  * CRU
 155  */
 156 typedef enum PLL_ID_Tag
 157 {
 158     APLL=0,
 159     DPLL,
 160     CPLL,
 161     GPLL,
 162     PLL_MAX
 163 }PLL_ID;
 164
 165 #define PLL_RESET  (((0x1<<5)<<16) | (0x1<<5))
 166 #define PLL_DE_RESET  (((0x1<<5)<<16) | (0x0<<5))
 167 #define NR(n)      ((0x3F<<(8+16)) | (((n)-1)<<8))
 168 #define NO(n)      ((0xF<<16) | ((n)-1))
 169 #define NF(n)      ((0x1FFF<<16) | ((n)-1))
 170 #define NB(n)      ((0xFFF<<16) | ((n)-1))
 171
 172  //CRU Registers
 173 typedef volatile struct tagCRU_STRUCT
 174 {
 175     uint32 CRU_PLL_CON[5][4];
 176     uint32 CRU_MODE_CON;
 177     uint32 reserved1[(0x60-0x54)/4];
 178     uint32 CRU_CLKSEL_CON[43];
 179     uint32 reserved2[(0x160-0x10c)/4];
 180     uint32 CRU_CLKGATE_CON[19];
 181     uint32 reserved3[(0x1b0-0x1ac)/4];
 182     uint32 CRU_GLB_SRST_FST_VALUE;
 183     uint32 CRU_GLB_SRST_SND_VALUE;
 184     uint32 CRU_SOFTRST_CON[12];
 185     uint32 CRU_MISC_CON;
 186     uint32 CRU_GLB_CNT_TH;
 187     uint32 CRU_TSADC_RST_CON;
 188     uint32 reserved4[(0x200-0x1f4)/4];
 189     uint32 CRU_SDMMC_CON[2];
 190     uint32 CRU_SDIO0_CON[2];
 191     uint32 CRU_SDIO1_CON[2];
 192     uint32 CRU_EMMC_CON[2];
 193     // other regigster unused in boot
 194 } CRU_REG, *pCRU_REG;
 195
 196 /*
 197  * GRF
 198  */
 199 //REG FILE registers
 200 typedef volatile struct tagREG_FILE
 201 {
 202     uint32 GRF_GPIO1A_IOMUX;
 203     uint32 GRF_GPIO1B_IOMUX;
 204     uint32 GRF_GPIO1C_IOMUX;
 205     uint32 GRF_GPIO1D_IOMUX;
 206     uint32 GRF_GPIO2A_IOMUX;
 207     uint32 GRF_GPIO2B_IOMUX;
 208     uint32 GRF_GPIO2C_IOMUX;
 209     uint32 GRF_GPIO2D_IOMUX;
 210     uint32 GRF_GPIO3A_IOMUX;
 211     uint32 GRF_GPIO3B_IOMUX;
 212     uint32 GRF_GPIO3C_IOMUX;
 213     uint32 GRF_GPIO3DL_IOMUX;
 214     uint32 GRF_GPIO3DH_IOMUX;
 215     uint32 GRF_GPIO4AL_IOMUX;
 216     uint32 GRF_GPIO4AH_IOMUX;
 217     uint32 GRF_GPIO4BL_IOMUX;
 218     uint32 GRF_GPIO4BH_IOMUX;
 219     uint32 GRF_GPIO4C_IOMUX;
 220     uint32 GRF_GPIO4D_IOMUX;
 221     uint32 GRF_GPIO5A_IOMUX;
 222     uint32 GRF_GPIO5B_IOMUX;
 223     uint32 GRF_GPIO5C_IOMUX;
 224     uint32 GRF_GPIO5D_IOMUX;
 225     uint32 GRF_GPIO6A_IOMUX;
 226     uint32 GRF_GPIO6B_IOMUX;
 227     uint32 GRF_GPIO6C_IOMUX;
 228     uint32 GRF_GPIO6D_IOMUX;
 229     uint32 GRF_GPIO7A_IOMUX;
 230     uint32 GRF_GPIO7B_IOMUX;
 231     uint32 GRF_GPIO7CL_IOMUX;
 232     uint32 GRF_GPIO7CH_IOMUX;
 233     uint32 GRF_GPIO7D_IOMUX;
 234     uint32 GRF_GPIO8A_IOMUX;
 235     uint32 GRF_GPIO8B_IOMUX;
 236     uint32 GRF_GPIO8C_IOMUX;
 237     uint32 GRF_GPIO8D_IOMUX;
 238     uint32 reserved1[(0x100-0x90)/4];
 239     uint32 GRF_GPIO1L_SR;
 240     uint32 GRF_GPIO1H_SR;
 241     uint32 GRF_GPIO2L_SR;
 242     uint32 GRF_GPIO2H_SR;
 243     uint32 GRF_GPIO3L_SR;
 244     uint32 GRF_GPIO3H_SR;
 245     uint32 GRF_GPIO4L_SR;
 246     uint32 GRF_GPIO4H_SR;
 247     uint32 GRF_GPIO5L_SR;
 248     uint32 GRF_GPIO5H_SR;
 249     uint32 GRF_GPIO6L_SR;
 250     uint32 GRF_GPIO6H_SR;
 251     uint32 GRF_GPIO7L_SR;
 252     uint32 GRF_GPIO7H_SR;
 253     uint32 GRF_GPIO8L_SR;
 254     uint32 GRF_GPIO8H_SR;
 255     uint32 GRF_GPIO1A_P;
 256     uint32 GRF_GPIO1B_P;
 257     uint32 GRF_GPIO1C_P;
 258     uint32 GRF_GPIO1D_P;
 259     uint32 GRF_GPIO2A_P;
 260     uint32 GRF_GPIO2B_P;
 261     uint32 GRF_GPIO2C_P;
 262     uint32 GRF_GPIO2D_P;
 263     uint32 GRF_GPIO3A_P;
 264     uint32 GRF_GPIO3B_P;
 265     uint32 GRF_GPIO3C_P;
 266     uint32 GRF_GPIO3D_P;
 267     uint32 GRF_GPIO4A_P;
 268     uint32 GRF_GPIO4B_P;
 269     uint32 GRF_GPIO4C_P;
 270     uint32 GRF_GPIO4D_P;
 271     uint32 GRF_GPIO5A_P;
 272     uint32 GRF_GPIO5B_P;
 273     uint32 GRF_GPIO5C_P;
 274     uint32 GRF_GPIO5D_P;
 275     uint32 GRF_GPIO6A_P;
 276     uint32 GRF_GPIO6B_P;
 277     uint32 GRF_GPIO6C_P;
 278     uint32 GRF_GPIO6D_P;
 279     uint32 GRF_GPIO7A_P;
 280     uint32 GRF_GPIO7B_P;
 281     uint32 GRF_GPIO7C_P;
 282     uint32 GRF_GPIO7D_P;
 283     uint32 GRF_GPIO8A_P;
 284     uint32 GRF_GPIO8B_P;
 285     uint32 GRF_GPIO8C_P;
 286     uint32 GRF_GPIO8D_P;
 287     uint32 GRF_GPIO1A_E;
 288     uint32 GRF_GPIO1B_E;
 289     uint32 GRF_GPIO1C_E;
 290     uint32 GRF_GPIO1D_E;
 291     uint32 GRF_GPIO2A_E;
 292     uint32 GRF_GPIO2B_E;
 293     uint32 GRF_GPIO2C_E;
 294     uint32 GRF_GPIO2D_E;
 295     uint32 GRF_GPIO3A_E;
 296     uint32 GRF_GPIO3B_E;
 297     uint32 GRF_GPIO3C_E;
 298     uint32 GRF_GPIO3D_E;
 299     uint32 GRF_GPIO4A_E;
 300     uint32 GRF_GPIO4B_E;
 301     uint32 GRF_GPIO4C_E;
 302     uint32 GRF_GPIO4D_E;
 303     uint32 GRF_GPIO5A_E;
 304     uint32 GRF_GPIO5B_E;
 305     uint32 GRF_GPIO5C_E;
 306     uint32 GRF_GPIO5D_E;
 307     uint32 GRF_GPIO6A_E;
 308     uint32 GRF_GPIO6B_E;
 309     uint32 GRF_GPIO6C_E;
 310     uint32 GRF_GPIO6D_E;
 311     uint32 GRF_GPIO7A_E;
 312     uint32 GRF_GPIO7B_E;
 313     uint32 GRF_GPIO7C_E;
 314     uint32 GRF_GPIO7D_E;
 315     uint32 GRF_GPIO8A_E;
 316     uint32 GRF_GPIO8B_E;
 317     uint32 GRF_GPIO8C_E;
 318     uint32 GRF_GPIO8D_E;
 319     uint32 GRF_GPIO_SMT;
 320     uint32 GRF_SOC_CON[15];
 321     uint32 GRF_SOC_STATUS[23];
 322     uint32 reserved2[(0x2e0-0x2dc)/4];
 323     uint32 GRF_DMAC2_CON[4];
 324     uint32 GRF_DDRC0_CON0;
 325     uint32 GRF_DDRC1_CON0;
 326     uint32 GRF_CPU_CON[5];
 327     uint32 reserved3[(0x318-0x30c)/4];
 328     uint32 GRF_CPU_STATUS0;
 329     uint32 reserved4[(0x320-0x31c)/4];
 330     uint32 GRF_UOC0_CON[5];
 331     uint32 GRF_UOC1_CON[5];
 332     uint32 GRF_UOC2_CON[4];
 333     uint32 GRF_UOC3_CON[2];
 334     uint32 GRF_UOC4_CON[2];
 335     uint32 GRF_DLL_CON[3];
 336     uint32 GRF_DLL_STATUS[3];
 337     uint32 GRF_IO_VSEL;
 338     uint32 GRF_SARADC_TESTBIT;
 339     uint32 GRF_TSADC_TESTBIT_L;
 340     uint32 GRF_TSADC_TESTBIT_H;
 341     uint32 GRF_OS_REG[4];
 342     uint32 GRF_FAST_BOOT_ADDR;
 343     uint32 GRF_SOC_CON15;
 344     uint32 GRF_SOC_CON16;
 345 } REG_FILE, *pREG_FILE;
 346
 347 /*
 348  * PCTL
 349  */
 350 //SCTL
 351 #define INIT_STATE                     (0)
 352 #define CFG_STATE                      (1)
 353 #define GO_STATE                       (2)
 354 #define SLEEP_STATE                    (3)
 355 #define WAKEUP_STATE                   (4)
 356
 357 //STAT
 358 #define Init_mem                       (0)
 359 #define Config                         (1)
 360 #define Config_req                     (2)
 361 #define Access                         (3)
 362 #define Access_req                     (4)
 363 #define Low_power                      (5)
 364 #define Low_power_entry_req            (6)
 365 #define Low_power_exit_req             (7)
 366
 367 //MCFG
 368 #define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
 369 #define pd_idle(n)                     ((n)<<8)
 370 #define mddr_en                        (2<<22)
 371 #define lpddr2_en                      (3<<22)
 372 #define ddr2_en                        (0<<5)
 373 #define ddr3_en                        (1<<5)
 374 #define lpddr2_s2                      (0<<6)
 375 #define lpddr2_s4                      (1<<6)
 376 #define mddr_lpddr2_bl_2               (0<<20)
 377 #define mddr_lpddr2_bl_4               (1<<20)
 378 #define mddr_lpddr2_bl_8               (2<<20)
 379 #define mddr_lpddr2_bl_16              (3<<20)
 380 #define ddr2_ddr3_bl_4                 (0)
 381 #define ddr2_ddr3_bl_8                 (1)
 382 #define tfaw_cfg(n)                    (((n)-4)<<18)
 383 #define pd_exit_slow                   (0<<17)
 384 #define pd_exit_fast                   (1<<17)
 385 #define pd_type(n)                     ((n)<<16)
 386 #define two_t_en(n)                    ((n)<<3)
 387 #define bl8int_en(n)                   ((n)<<2)
 388 #define cke_or_en(n)                   ((n)<<1)
 389
 390 //POWCTL
 391 #define power_up_start                 (1<<0)
 392
 393 //POWSTAT
 394 #define power_up_done                  (1<<0)
 395
 396 //DFISTSTAT0
 397 #define dfi_init_complete              (1<<0)
 398
 399 //CMDTSTAT
 400 #define cmd_tstat                      (1<<0)
 401
 402 //CMDTSTATEN
 403 #define cmd_tstat_en                   (1<<1)
 404
 405 //MCMD
 406 #define Deselect_cmd                   (0)
 407 #define PREA_cmd                       (1)
 408 #define REF_cmd                        (2)
 409 #define MRS_cmd                        (3)
 410 #define ZQCS_cmd                       (4)
 411 #define ZQCL_cmd                       (5)
 412 #define RSTL_cmd                       (6)
 413 #define MRR_cmd                        (8)
 414 #define DPDE_cmd                       (9)
 415
 416 #define lpddr2_op(n)                   ((n)<<12)
 417 #define lpddr2_ma(n)                   ((n)<<4)
 418
 419 #define bank_addr(n)                   ((n)<<17)
 420 #define cmd_addr(n)                    ((n)<<4)
 421
 422 #define start_cmd                      (1u<<31)
 423
 424 typedef union STAT_Tag
 425 {
 426     uint32 d32;
 427     struct
 428     {
 429         unsigned ctl_stat : 3;
 430         unsigned reserved3 : 1;
 431         unsigned lp_trig : 3;
 432         unsigned reserved7_31 : 25;
 433     }b;
 434 }STAT_T;
 435
 436 typedef union SCFG_Tag
 437 {
 438     uint32 d32;
 439     struct
 440     {
 441         unsigned hw_low_power_en : 1;
 442         unsigned reserved1_5 : 5;
 443         unsigned nfifo_nif1_dis : 1;
 444         unsigned reserved7 : 1;
 445         unsigned bbflags_timing : 4;
 446         unsigned reserved12_31 : 20;
 447     } b;
 448 }SCFG_T;
 449
 450 /* DDR Controller register struct */
 451 typedef volatile struct DDR_REG_Tag
 452 {
 453     //Operational State, Control, and Status Registers
 454     SCFG_T SCFG;                   //State Configuration Register
 455     volatile uint32 SCTL;                   //State Control Register
 456     STAT_T STAT;                   //State Status Register
 457     volatile uint32 INTRSTAT;               //Interrupt Status Register
 458     uint32 reserved0[(0x40-0x10)/4];
 459     //Initailization Control and Status Registers
 460     volatile uint32 MCMD;                   //Memory Command Register
 461     volatile uint32 POWCTL;                 //Power Up Control Registers
 462     volatile uint32 POWSTAT;                //Power Up Status Register
 463     volatile uint32 CMDTSTAT;               //Command Timing Status Register
 464     volatile uint32 CMDTSTATEN;             //Command Timing Status Enable Register
 465     uint32 reserved1[(0x60-0x54)/4];
 466     volatile uint32 MRRCFG0;                //MRR Configuration 0 Register
 467     volatile uint32 MRRSTAT0;               //MRR Status 0 Register
 468     volatile uint32 MRRSTAT1;               //MRR Status 1 Register
 469     uint32 reserved2[(0x7c-0x6c)/4];
 470     //Memory Control and Status Registers
 471     volatile uint32 MCFG1;                  //Memory Configuration 1 Register
 472     volatile uint32 MCFG;                   //Memory Configuration Register
 473     volatile uint32 PPCFG;                  //Partially Populated Memories Configuration Register
 474     volatile uint32 MSTAT;                  //Memory Status Register
 475     volatile uint32 LPDDR2ZQCFG;            //LPDDR2 ZQ Configuration Register
 476     uint32 reserved3;
 477     //DTU Control and Status Registers
 478     volatile uint32 DTUPDES;                //DTU Status Register
 479     volatile uint32 DTUNA;                  //DTU Number of Random Addresses Created Register
 480     volatile uint32 DTUNE;                  //DTU Number of Errors Register
 481     volatile uint32 DTUPRD0;                //DTU Parallel Read 0
 482     volatile uint32 DTUPRD1;                //DTU Parallel Read 1
 483     volatile uint32 DTUPRD2;                //DTU Parallel Read 2
 484     volatile uint32 DTUPRD3;                //DTU Parallel Read 3
 485     volatile uint32 DTUAWDT;                //DTU Address Width
 486     uint32 reserved4[(0xc0-0xb4)/4];
 487     //Memory Timing Registers
 488     volatile uint32 TOGCNT1U;               //Toggle Counter 1U Register
 489     volatile uint32 TINIT;                  //t_init Timing Register
 490     volatile uint32 TRSTH;                  //Reset High Time Register
 491     volatile uint32 TOGCNT100N;             //Toggle Counter 100N Register
 492     volatile uint32 TREFI;                  //t_refi Timing Register
 493     volatile uint32 TMRD;                   //t_mrd Timing Register
 494     volatile uint32 TRFC;                   //t_rfc Timing Register
 495     volatile uint32 TRP;                    //t_rp Timing Register
 496     volatile uint32 TRTW;                   //t_rtw Timing Register
 497     volatile uint32 TAL;                    //AL Latency Register
 498     volatile uint32 TCL;                    //CL Timing Register
 499     volatile uint32 TCWL;                   //CWL Register
 500     volatile uint32 TRAS;                   //t_ras Timing Register
 501     volatile uint32 TRC;                    //t_rc Timing Register
 502     volatile uint32 TRCD;                   //t_rcd Timing Register
 503     volatile uint32 TRRD;                   //t_rrd Timing Register
 504     volatile uint32 TRTP;                   //t_rtp Timing Register
 505     volatile uint32 TWR;                    //t_wr Timing Register
 506     volatile uint32 TWTR;                   //t_wtr Timing Register
 507     volatile uint32 TEXSR;                  //t_exsr Timing Register
 508     volatile uint32 TXP;                    //t_xp Timing Register
 509     volatile uint32 TXPDLL;                 //t_xpdll Timing Register
 510     volatile uint32 TZQCS;                  //t_zqcs Timing Register
 511     volatile uint32 TZQCSI;                 //t_zqcsi Timing Register
 512     volatile uint32 TDQS;                   //t_dqs Timing Register
 513     volatile uint32 TCKSRE;                 //t_cksre Timing Register
 514     volatile uint32 TCKSRX;                 //t_cksrx Timing Register
 515     volatile uint32 TCKE;                   //t_cke Timing Register
 516     volatile uint32 TMOD;                   //t_mod Timing Register
 517     volatile uint32 TRSTL;                  //Reset Low Timing Register
 518     volatile uint32 TZQCL;                  //t_zqcl Timing Register
 519     volatile uint32 TMRR;                   //t_mrr Timing Register
 520     volatile uint32 TCKESR;                 //t_ckesr Timing Register
 521     volatile uint32 TDPD;                   //t_dpd Timing Register
 522     uint32 reserved5[(0x180-0x148)/4];
 523     //ECC Configuration, Control, and Status Registers
 524     volatile uint32 ECCCFG;                   //ECC Configuration Register
 525     volatile uint32 ECCTST;                   //ECC Test Register
 526     volatile uint32 ECCCLR;                   //ECC Clear Register
 527     volatile uint32 ECCLOG;                   //ECC Log Register
 528     uint32 reserved6[(0x200-0x190)/4];
 529     //DTU Control and Status Registers
 530     volatile uint32 DTUWACTL;                 //DTU Write Address Control Register
 531     volatile uint32 DTURACTL;                 //DTU Read Address Control Register
 532     volatile uint32 DTUCFG;                   //DTU Configuration Control Register
 533     volatile uint32 DTUECTL;                  //DTU Execute Control Register
 534     volatile uint32 DTUWD0;                   //DTU Write Data 0
 535     volatile uint32 DTUWD1;                   //DTU Write Data 1
 536     volatile uint32 DTUWD2;                   //DTU Write Data 2
 537     volatile uint32 DTUWD3;                   //DTU Write Data 3
 538     volatile uint32 DTUWDM;                   //DTU Write Data Mask
 539     volatile uint32 DTURD0;                   //DTU Read Data 0
 540     volatile uint32 DTURD1;                   //DTU Read Data 1
 541     volatile uint32 DTURD2;                   //DTU Read Data 2
 542     volatile uint32 DTURD3;                   //DTU Read Data 3
 543     volatile uint32 DTULFSRWD;                //DTU LFSR Seed for Write Data Generation
 544     volatile uint32 DTULFSRRD;                //DTU LFSR Seed for Read Data Generation
 545     volatile uint32 DTUEAF;                   //DTU Error Address FIFO
 546     //DFI Control Registers
 547     volatile uint32 DFITCTRLDELAY;            //DFI tctrl_delay Register
 548     volatile uint32 DFIODTCFG;                //DFI ODT Configuration Register
 549     volatile uint32 DFIODTCFG1;               //DFI ODT Configuration 1 Register
 550     volatile uint32 DFIODTRANKMAP;            //DFI ODT Rank Mapping Register
 551     //DFI Write Data Registers
 552     volatile uint32 DFITPHYWRDATA;            //DFI tphy_wrdata Register
 553     volatile uint32 DFITPHYWRLAT;             //DFI tphy_wrlat Register
 554     uint32 reserved7[(0x260-0x258)/4];
 555     volatile uint32 DFITRDDATAEN;             //DFI trddata_en Register
 556     volatile uint32 DFITPHYRDLAT;             //DFI tphy_rddata Register
 557     uint32 reserved8[(0x270-0x268)/4];
 558     //DFI Update Registers
 559     volatile uint32 DFITPHYUPDTYPE0;          //DFI tphyupd_type0 Register
 560     volatile uint32 DFITPHYUPDTYPE1;          //DFI tphyupd_type1 Register
 561     volatile uint32 DFITPHYUPDTYPE2;          //DFI tphyupd_type2 Register
 562     volatile uint32 DFITPHYUPDTYPE3;          //DFI tphyupd_type3 Register
 563     volatile uint32 DFITCTRLUPDMIN;           //DFI tctrlupd_min Register
 564     volatile uint32 DFITCTRLUPDMAX;           //DFI tctrlupd_max Register
 565     volatile uint32 DFITCTRLUPDDLY;           //DFI tctrlupd_dly Register
 566     uint32 reserved9;
 567     volatile uint32 DFIUPDCFG;                //DFI Update Configuration Register
 568     volatile uint32 DFITREFMSKI;              //DFI Masked Refresh Interval Register
 569     volatile uint32 DFITCTRLUPDI;             //DFI tctrlupd_interval Register
 570     uint32 reserved10[(0x2ac-0x29c)/4];
 571     volatile uint32 DFITRCFG0;                //DFI Training Configuration 0 Register
 572     volatile uint32 DFITRSTAT0;               //DFI Training Status 0 Register
 573     volatile uint32 DFITRWRLVLEN;             //DFI Training dfi_wrlvl_en Register
 574     volatile uint32 DFITRRDLVLEN;             //DFI Training dfi_rdlvl_en Register
 575     volatile uint32 DFITRRDLVLGATEEN;         //DFI Training dfi_rdlvl_gate_en Register
 576     //DFI Status Registers
 577     volatile uint32 DFISTSTAT0;               //DFI Status Status 0 Register
 578     volatile uint32 DFISTCFG0;                //DFI Status Configuration 0 Register
 579     volatile uint32 DFISTCFG1;                //DFI Status configuration 1 Register
 580     uint32 reserved11;
 581     volatile uint32 DFITDRAMCLKEN;            //DFI tdram_clk_enalbe Register
 582     volatile uint32 DFITDRAMCLKDIS;           //DFI tdram_clk_disalbe Register
 583     volatile uint32 DFISTCFG2;                //DFI Status configuration 2 Register
 584     volatile uint32 DFISTPARCLR;              //DFI Status Parity Clear Register
 585     volatile uint32 DFISTPARLOG;              //DFI Status Parity Log Register
 586     uint32 reserved12[(0x2f0-0x2e4)/4];
 587     //DFI Low Power Registers
 588     volatile uint32 DFILPCFG0;                //DFI Low Power Configuration 0 Register
 589     uint32 reserved13[(0x300-0x2f4)/4];
 590     //DFI Training 2 Registers
 591     volatile uint32 DFITRWRLVLRESP0;          //DFI Training dif_wrlvl_resp Status 0 Register
 592     volatile uint32 DFITRWRLVLRESP1;          //DFI Training dif_wrlvl_resp Status 1 Register
 593     volatile uint32 DFITRWRLVLRESP2;          //DFI Training dif_wrlvl_resp Status 2 Register
 594     volatile uint32 DFITRRDLVLRESP0;          //DFI Training dif_rdlvl_resp Status 0 Register
 595     volatile uint32 DFITRRDLVLRESP1;          //DFI Training dif_rdlvl_resp Status 1 Register
 596     volatile uint32 DFITRRDLVLRESP2;          //DFI Training dif_rdlvl_resp Status 2 Register
 597     volatile uint32 DFITRWRLVLDELAY0;         //DFI Training dif_wrlvl_delay Configuration 0 Register
 598     volatile uint32 DFITRWRLVLDELAY1;         //DFI Training dif_wrlvl_delay Configuration 1 Register
 599     volatile uint32 DFITRWRLVLDELAY2;         //DFI Training dif_wrlvl_delay Configuration 2 Register
 600     volatile uint32 DFITRRDLVLDELAY0;         //DFI Training dif_rdlvl_delay Configuration 0 Register
 601     volatile uint32 DFITRRDLVLDELAY1;         //DFI Training dif_rdlvl_delay Configuration 1 Register
 602     volatile uint32 DFITRRDLVLDELAY2;         //DFI Training dif_rdlvl_delay Configuration 2 Register
 603     volatile uint32 DFITRRDLVLGATEDELAY0;     //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
 604     volatile uint32 DFITRRDLVLGATEDELAY1;     //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
 605     volatile uint32 DFITRRDLVLGATEDELAY2;     //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
 606     volatile uint32 DFITRCMD;                 //DFI Training Command Register
 607     uint32 reserved14[(0x3f8-0x340)/4];
 608     //IP Status Registers
 609     volatile uint32 IPVR;                     //IP Version Register
 610     volatile uint32 IPTR;                     //IP Type Register
 611 }DDR_REG_T, *pDDR_REG_T;
 612
 613 /*
 614  * PUBL
 615  */
 616 //PIR
 617 #define INIT                 (1<<0)
 618 #define DLLSRST              (1<<1)
 619 #define DLLLOCK              (1<<2)
 620 #define ZCAL                 (1<<3)
 621 #define ITMSRST              (1<<4)
 622 #define DRAMRST              (1<<5)
 623 #define DRAMINIT             (1<<6)
 624 #define QSTRN                (1<<7)
 625 #define EYETRN               (1<<8)
 626 #define ICPC                 (1<<16)
 627 #define DLLBYP               (1<<17)
 628 #define CTLDINIT             (1<<18)
 629 #define CLRSR                (1<<28)
 630 #define LOCKBYP              (1<<29)
 631 #define ZCALBYP              (1<<30)
 632 #define INITBYP              (1u<<31)
 633
 634 //PGCR
 635 #define DFTLMT(n)            ((n)<<3)
 636 #define DFTCMP(n)            ((n)<<2)
 637 #define DQSCFG(n)            ((n)<<1)
 638 #define ITMDMD(n)            ((n)<<0)
 639 #define RANKEN(n)            ((n)<<18)
 640
 641 //PGSR
 642 #define IDONE                (1<<0)
 643 #define DLDONE               (1<<1)
 644 #define ZCDONE               (1<<2)
 645 #define DIDONE               (1<<3)
 646 #define DTDONE               (1<<4)
 647 #define DTERR                (1<<5)
 648 #define DTIERR               (1<<6)
 649 #define DFTERR               (1<<7)
 650 #define TQ                   (1u<<31)
 651
 652 //PTR0
 653 #define tITMSRST(n)          ((n)<<18)
 654 #define tDLLLOCK(n)          ((n)<<6)
 655 #define tDLLSRST(n)          ((n)<<0)
 656
 657 //PTR1
 658 #define tDINIT1(n)           ((n)<<19)
 659 #define tDINIT0(n)           ((n)<<0)
 660
 661 //PTR2
 662 #define tDINIT3(n)           ((n)<<17)
 663 #define tDINIT2(n)           ((n)<<0)
 664
 665 //DSGCR
 666 #define DQSGE(n)             ((n)<<8)
 667 #define DQSGX(n)             ((n)<<5)
 668
 669 typedef union DCR_Tag
 670 {
 671     uint32 d32;
 672     struct
 673     {
 674         unsigned DDRMD : 3;
 675         unsigned DDR8BNK : 1;
 676         unsigned PDQ : 3;
 677         unsigned MPRDQ : 1;
 678         unsigned DDRTYPE : 2;
 679         unsigned reserved10_26 : 17;
 680         unsigned NOSRA : 1;
 681         unsigned DDR2T : 1;
 682         unsigned UDIMM : 1;
 683         unsigned RDIMM : 1;
 684         unsigned TPD : 1;
 685     } b;
 686 }DCR_T;
 687
 688 typedef volatile struct DATX8_REG_Tag
 689 {
 690     volatile uint32 DXGCR;                 //DATX8 General Configuration Register
 691     volatile uint32 DXGSR[2];              //DATX8 General Status Register
 692     volatile uint32 DXDLLCR;               //DATX8 DLL Control Register
 693     volatile uint32 DXDQTR;                //DATX8 DQ Timing Register
 694     volatile uint32 DXDQSTR;               //DATX8 DQS Timing Register
 695     uint32 reserved[0x80-0x76];
 696 }DATX8_REG_T;
 697
 698 /* DDR PHY register struct */
 699 typedef volatile struct DDRPHY_REG_Tag
 700 {
 701     volatile uint32 RIDR;                   //Revision Identification Register
 702     volatile uint32 PIR;                    //PHY Initialization Register
 703     volatile uint32 PGCR;                   //PHY General Configuration Register
 704     volatile uint32 PGSR;                   //PHY General Status Register
 705     volatile uint32 DLLGCR;                 //DLL General Control Register
 706     volatile uint32 ACDLLCR;                //AC DLL Control Register
 707     volatile uint32 PTR[3];                 //PHY Timing Registers 0-2
 708     volatile uint32 ACIOCR;                 //AC I/O Configuration Register
 709     volatile uint32 DXCCR;                  //DATX8 Common Configuration Register
 710     volatile uint32 DSGCR;                  //DDR System General Configuration Register
 711     DCR_T DCR;                    //DRAM Configuration Register
 712     volatile uint32 DTPR[3];                //DRAM Timing Parameters Register 0-2
 713     volatile uint32 MR[4];                    //Mode Register 0-3
 714     volatile uint32 ODTCR;                  //ODT Configuration Register
 715     volatile uint32 DTAR;                   //Data Training Address Register
 716     volatile uint32 DTDR[2];                //Data Training Data Register 0-1
 717
 718     uint32 reserved1[0x30-0x18];
 719     uint32 DCU[0x38-0x30];
 720     uint32 reserved2[0x40-0x38];
 721     uint32 BIST[0x51-0x40];
 722     uint32 reserved3[0x60-0x51];
 723
 724     volatile uint32 ZQ0CR[2];               //ZQ 0 Impedance Control Register 0-1
 725     volatile uint32 ZQ0SR[2];               //ZQ 0 Impedance Status Register 0-1
 726     volatile uint32 ZQ1CR[2];               //ZQ 1 Impedance Control Register 0-1
 727     volatile uint32 ZQ1SR[2];               //ZQ 1 Impedance Status Register 0-1
 728     volatile uint32 ZQ2CR[2];               //ZQ 2 Impedance Control Register 0-1
 729     volatile uint32 ZQ2SR[2];               //ZQ 2 Impedance Status Register 0-1
 730     volatile uint32 ZQ3CR[2];               //ZQ 3 Impedance Control Register 0-1
 731     volatile uint32 ZQ3SR[2];               //ZQ 3 Impedance Status Register 0-1
 732
 733     DATX8_REG_T     DATX8[9];               //DATX8 Register
 734 }DDRPHY_REG_T, *pDDRPHY_REG_T;
 735
 736 typedef union NOC_TIMING_Tag
 737 {
 738     uint32 d32;
 739     struct
 740     {
 741         unsigned ActToAct : 6;
 742         unsigned RdToMiss : 6;
 743         unsigned WrToMiss : 6;
 744         unsigned BurstLen : 3;
 745         unsigned RdToWr : 5;
 746         unsigned WrToRd : 5;
 747         unsigned BwRatio : 1;
 748     } b;
 749 }NOC_TIMING_T;
 750
 751 typedef union NOC_ACTIVATE_Tag
 752 {
 753     uint32 d32;
 754     struct
 755     {
 756         unsigned Rrd : 4;  //bit[0:3]
 757         unsigned Faw : 6;  //bit[4:9]
 758         unsigned Fawbank : 1; //bit 10
 759         unsigned reserved : 21;
 760     } b;
 761 }NOC_ACTIVATE_T;
 762
 763 typedef volatile struct MSCH_REG_Tag
 764 {
 765     volatile uint32 coreid;
 766     volatile uint32 revisionid;
 767     volatile uint32 ddrconf;
 768     volatile NOC_TIMING_T ddrtiming;
 769     volatile uint32 ddrmode;
 770     volatile uint32 readlatency;
 771     uint32 reserved1[(0x38-0x18)/4];
 772     volatile NOC_ACTIVATE_T activate;
 773     volatile uint32 devtodev;
 774 }MSCH_REG, *pMSCH_REG;
 775
 776 #define CH_MAX                 (2)
 777 #define DRAM_PHYS              (0)   //DRAM Channel a physical address start
 778 #define pPMU_Reg               ((pPMU_FILE)RK_PMU_VIRT)
 779 #define pCRU_Reg               ((pCRU_REG)RK_CRU_VIRT)
 780 #define pGRF_Reg               ((pREG_FILE)RK_GRF_VIRT)
 781 #define pDDR_REG(ch)           ((ch) ? ((pDDR_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)):((pDDR_REG_T)RK_DDR_VIRT))
 782 #define pPHY_REG(ch)           ((ch) ? ((pDDRPHY_REG_T)(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)) : ((pDDRPHY_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE)))
 783 #define pMSCH_REG(ch)          ((ch)? ((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT+0x80)):((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT)))
 784 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 785 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 786 #define GET_LPDDR3_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 787 #define DDR_GET_RANK_2_ROW15() (0)
 788 #define DDR_GET_BANK_2_RANK()  (0)
 789 #define DDR_HW_WAKEUP(ch,en)   do{pGRF_Reg->GRF_SOC_CON[0] = (1<<(16+5+ch)) | (en<<(5+ch));}while(0)
 790 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[0])
 791 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS[1] & (1<<5))
 792 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<2))<<16)|(src<<2)| div;}while(0)
 793 #define GET_DDR_PLL_SRC()           ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<2)) ? GPLL : DPLL)
 794 #define DDR_GPLL_CLK_GATE(en)       do{pCRU_Reg->CRU_CLKGATE_CON[0] = 0x02000000 | (en<<9);}while(0)
 795 #define SET_DDRPHY_CLKGATE(ch,dis)  do{pCRU_Reg->CRU_CLKGATE_CON[4] = ((0x1<<(12+ch))<<16) | (dis<<(12+ch));}while(0)
 796 #define READ_DDR_STRIDE()           (readl_relaxed(RK_SGRF_VIRT+0x8) &0x1F)
 797
 798 #define READ_CH_CNT()         (1+((pPMU_Reg->PMU_PMU_SYS_REG[2]>>12)&0x1))
 799 #define READ_CH_INFO()        ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>28)&0x3)
 800 #define READ_CH_ROW_INFO(ch)  ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>(30+(ch)))&0x1)    //row_3_4:0=normal, 1=6Gb or 12Gb
 801
 802 #define SET_PLL_MODE(pll, mode) do{pCRU_Reg->CRU_MODE_CON = ((mode<<((pll)*4))|(0x3<<(16+(pll)*4)));}while(0)
 803 #define SET_PLL_PD(pll, pd)     do{pCRU_Reg->CRU_PLL_CON[pll][3] = ((0x1<<1)<<16) | (pd<<1);}while(0)
 804
 805 #define READ_DRAMTYPE_INFO()    ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>13)&0x7)
 806 #define READ_CS_INFO(ch)        ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(11+(ch)*16))&0x1)+1)
 807 #define READ_BW_INFO(ch)        (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(2+(ch)*16))&0x3))
 808 #define READ_COL_INFO(ch)       (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(9+(ch)*16))&0x3))
 809 #define READ_BK_INFO(ch)        (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(8+(ch)*16))&0x1))
 810 #define READ_ROW_INFO(ch,cs)    (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(6-(2*cs)+(ch)*16))&0x3))
 811 #define READ_DIE_BW_INFO(ch)    (2>>((pPMU_Reg->PMU_PMU_SYS_REG[2]>>((ch)*16))&0x3))
 812
 813 static const uint16_t  ddr_cfg_2_rbc[] =
 814 {
 815     /****************************/
 816     // [8:7]  bank(n:n bit bank)
 817     // [6:4]  row(12+n)
 818     // [3:2]  bank(n:n bit bank)
 819     // [1:0]  col(9+n)
 820     /****************************/
 821     //all config have (13col,3bank,16row,1cs)
 822     //bank,  row,   bank, col          col bank row(32bit)
 823     ((3<<7)|(3<<4)|(0<<2)|2),  // 0     11   8   15
 824     ((0<<7)|(1<<4)|(3<<2)|1),  // 1     10   8   13
 825     ((0<<7)|(2<<4)|(3<<2)|1),  // 2     10   8   14
 826     ((0<<7)|(3<<4)|(3<<2)|1),  // 3     10   8   15
 827     ((0<<7)|(4<<4)|(3<<2)|1),  // 4     10   8   16
 828     ((0<<7)|(1<<4)|(3<<2)|2),  // 5     11   8   13  // 32bit not use
 829     ((0<<7)|(2<<4)|(3<<2)|2),  // 6     11   8   14
 830     ((0<<7)|(3<<4)|(3<<2)|2),  // 7     11   8   15
 831     ((0<<7)|(1<<4)|(3<<2)|0),  // 8     9    8   13
 832     ((0<<7)|(2<<4)|(3<<2)|0),  // 9     9    8   14
 833     ((0<<7)|(3<<4)|(3<<2)|0),  // 10    9    8   15
 834     ((0<<7)|(2<<4)|(2<<2)|0),  // 11    9    4   14
 835     ((0<<7)|(1<<4)|(2<<2)|1),  // 12    10   4   13
 836     ((0<<7)|(0<<4)|(2<<2)|2),  // 13    11   4   12
 837     ((3<<7)|(4<<4)|(0<<2)|1),  // 14    10   8   16 / 10, 4,15 / 10, 8, 15
 838     ((0<<7)|(4<<4)|(3<<2)|2),  // 15    11   8   16
 839 };
 840
 841 /***********************************
 842  * LPDDR2 define
 843  ***********************************/
 844 //MR0 (Device Information)
 845 #define  LPDDR2_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 846 #define  LPDDR2_DI     (0x1<<1)     // 0:S2 or S4 SDRAM, 1:NVM
 847 #define  LPDDR2_DNVI   (0x1<<2)     // 0:DNV not supported, 1:DNV supported
 848 #define  LPDDR2_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 849                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 850
 851 //MR1 (Device Feature)
 852 #define LPDDR2_BL4     (0x2)
 853 #define LPDDR2_BL8     (0x3)
 854 #define LPDDR2_BL16    (0x4)
 855 #define LPDDR2_nWR(n)  (((n)-2)<<5)
 856
 857 //MR2 (Device Feature 2)
 858 #define LPDDR2_RL3_WL1  (0x1)
 859 #define LPDDR2_RL4_WL2  (0x2)
 860 #define LPDDR2_RL5_WL2  (0x3)
 861 #define LPDDR2_RL6_WL3  (0x4)
 862 #define LPDDR2_RL7_WL4  (0x5)
 863 #define LPDDR2_RL8_WL4  (0x6)
 864
 865 //MR3 (IO Configuration 1)
 866 #define LPDDR2_DS_34    (0x1)
 867 #define LPDDR2_DS_40    (0x2)
 868 #define LPDDR2_DS_48    (0x3)
 869 #define LPDDR2_DS_60    (0x4)
 870 #define LPDDR2_DS_80    (0x6)
 871 #define LPDDR2_DS_120   (0x7)   //optional
 872
 873 //MR4 (Device Temperature)
 874 #define LPDDR2_tREF_MASK (0x7)
 875 #define LPDDR2_4_tREF    (0x1)
 876 #define LPDDR2_2_tREF    (0x2)
 877 #define LPDDR2_1_tREF    (0x3)
 878 #define LPDDR2_025_tREF  (0x5)
 879 #define LPDDR2_025_tREF_DERATE    (0x6)
 880
 881 #define LPDDR2_TUF       (0x1<<7)
 882
 883 //MR8 (Basic configuration 4)
 884 #define LPDDR2_S4        (0x0)
 885 #define LPDDR2_S2        (0x1)
 886 #define LPDDR2_N         (0x2)
 887 #define LPDDR2_Density(mr8)  (8<<(((mr8)>>2)&0xf))   // Unit:MB
 888 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
 889
 890 //MR10 (Calibration)
 891 #define LPDDR2_ZQINIT   (0xFF)
 892 #define LPDDR2_ZQCL     (0xAB)
 893 #define LPDDR2_ZQCS     (0x56)
 894 #define LPDDR2_ZQRESET  (0xC3)
 895
 896 //MR16 (PASR Bank Mask)
 897 // S2 SDRAM Only
 898 #define LPDDR2_PASR_Full (0x0)
 899 #define LPDDR2_PASR_1_2  (0x1)
 900 #define LPDDR2_PASR_1_4  (0x2)
 901 #define LPDDR2_PASR_1_8  (0x3)
 902
 903 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 904
 905 //MR32 (DQ Calibration Pattern A)
 906
 907 //MR40 (DQ Calibration Pattern B)
 908
 909 /***********************************
 910  * LPDDR3 define
 911  ***********************************/
 912 //MR0 (Device Information)
 913 #define  LPDDR3_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 914 #define  LPDDR3_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 915                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 916 #define  LPDDR3_WL_SUPOT (1<<6)     // 0:DRAM does not support WL(Set B), 1:DRAM support WL(Set B)
 917 #define  LPDDR3_RL3_SUPOT (1<<7)    // 0:DRAM does not support RL=3,nWR=3,WL=1; 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
 918
 919 //MR1 (Device Feature)
 920 #define LPDDR3_BL8     (0x3)
 921 #define LPDDR3_nWR(n)  ((n)<<5)
 922
 923 //MR2 (Device Feature 2)
 924 //WL Set A,default
 925 #define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 926 #define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 927 #define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 928 #define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 929 #define LPDDR3_RL10_WL6  (0x8)       // <=667MHz,default
 930 #define LPDDR3_RL11_WL6  (0x9)       // <=733MHz
 931 #define LPDDR3_RL12_WL6  (0xa)       // <=800MHz
 932 #define LPDDR3_RL14_WL8  (0xc)       // <=933MHz
 933 #define LPDDR3_RL16_WL8  (0xe)       // <=1066MHz
 934 //WL Set B, optional
 935 //#define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 936 //#define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 937 //#define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 938 //#define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 939 #define LPDDR3_RL10_WL8  (0x8)       // <=667MHz,default
 940 #define LPDDR3_RL11_WL9  (0x9)       // <=733MHz
 941 #define LPDDR3_RL12_WL9  (0xa)       // <=800MHz
 942 #define LPDDR3_RL14_WL11 (0xc)       // <=933MHz
 943 #define LPDDR3_RL16_WL13 (0xe)       // <=1066MHz
 944
 945 #define LPDDR3_nWRE      (1<<4)      // 1:enable nWR programming > 9(defualt)
 946 #define LPDDR3_WL_S      (1<<6)      // 1:Select WL Set B
 947 #define LPDDR3_WR_LEVEL  (1<<7)      // 1:enable
 948
 949 //MR3 (IO Configuration 1)
 950 #define LPDDR3_DS_34    (0x1)
 951 #define LPDDR3_DS_40    (0x2)
 952 #define LPDDR3_DS_48    (0x3)
 953 #define LPDDR3_DS_60    (0x4)        //reserved
 954 #define LPDDR3_DS_80    (0x6)        //reserved
 955 #define LPDDR3_DS_34D_40U   (0x9)
 956 #define LPDDR3_DS_40D_48U   (0xa)
 957 #define LPDDR3_DS_34D_48U   (0xb)
 958
 959 //MR4 (Device Temperature)
 960 #define LPDDR3_tREF_MASK (0x7)
 961 #define LPDDR3_LT_EXED   (0x0)       // SDRAM Low temperature operating limit exceeded
 962 #define LPDDR3_4_tREF    (0x1)
 963 #define LPDDR3_2_tREF    (0x2)
 964 #define LPDDR3_1_tREF    (0x3)
 965 #define LPDDR3_05_tREF   (0x4)
 966 #define LPDDR3_025_tREF  (0x5)
 967 #define LPDDR3_025_tREF_DERATE    (0x6)
 968 #define LPDDR3_HT_EXED   (0x7)       // SDRAM High temperature operating limit exceeded
 969
 970 #define LPDDR3_TUF       (0x1<<7)    // 1:value has changed since last read of MR4
 971
 972 //MR8 (Basic configuration 4)
 973 #define LPDDR3_S8        (0x3)
 974 #define LPDDR3_Density(mr8)  (8<<((mr8>>2)&0xf))   // Unit:MB
 975 #define LPDDR3_IO_Width(mr8) (32>>((mr8>>6)&0x3))
 976
 977 //MR10 (Calibration)
 978 #define LPDDR3_ZQINIT   (0xFF)
 979 #define LPDDR3_ZQCL     (0xAB)
 980 #define LPDDR3_ZQCS     (0x56)
 981 #define LPDDR3_ZQRESET  (0xC3)
 982
 983 //MR11 (ODT Control)
 984 #define LPDDR3_ODT_60   (1)           //optional for 1333 and 1600
 985 #define LPDDR3_ODT_120  (2)
 986 #define LPDDR3_ODT_240  (3)
 987 #define LPDDR3_ODT_DIS  (0)
 988
 989 //MR16 (PASR Bank Mask)
 990
 991 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 992
 993 //MR32 (DQ Calibration Pattern A)
 994
 995 //MR40 (DQ Calibration Pattern B)
 996
 997 /***********************************
 998  * DDR3 define
 999  ***********************************/
1000 //mr0 for ddr3
1001 #define DDR3_BL8          (0)
1002 #define DDR3_BC4_8        (1)
1003 #define DDR3_BC4          (2)
1004 #define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
1005 #define DDR3_WR(n)        (((n)&0x7)<<9)
1006 #define DDR3_DLL_RESET    (1<<8)
1007 #define DDR3_DLL_DeRESET  (0<<8)
1008
1009 //mr1 for ddr3
1010 #define DDR3_DLL_ENABLE    (0)
1011 #define DDR3_DLL_DISABLE   (1)
1012 #define DDR3_MR1_AL(n)  (((n)&0x3)<<3)
1013
1014 #define DDR3_DS_40            (0)
1015 #define DDR3_DS_34            (1<<1)
1016 #define DDR3_Rtt_Nom_DIS      (0)
1017 #define DDR3_Rtt_Nom_60       (1<<2)
1018 #define DDR3_Rtt_Nom_120      (1<<6)
1019 #define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
1020
1021     //mr2 for ddr3
1022 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
1023 #define DDR3_Rtt_WR_DIS       (0)
1024 #define DDR3_Rtt_WR_60        (1<<9)
1025 #define DDR3_Rtt_WR_120       (2<<9)
1026
1027 /***********************************
1028  * DDR2 define
1029  ***********************************/
1030 //MR;                     //Mode Register
1031 #define DDR2_BL4           (2)
1032 #define DDR2_BL8           (3)
1033 #define DDR2_CL(n)         (((n)&0x7)<<4)
1034 #define DDR2_WR(n)        ((((n)-1)&0x7)<<9)
1035 #define DDR2_DLL_RESET    (1<<8)
1036 #define DDR2_DLL_DeRESET  (0<<8)
1037
1038 //EMR;                    //Extended Mode Register
1039 #define DDR2_DLL_ENABLE    (0)
1040 #define DDR2_DLL_DISABLE   (1)
1041
1042 #define DDR2_STR_FULL     (0)
1043 #define DDR2_STR_REDUCE   (1<<1)
1044 #define DDR2_AL(n)        (((n)&0x7)<<3)
1045 #define DDR2_Rtt_Nom_DIS      (0)
1046 #define DDR2_Rtt_Nom_150      (0x40)
1047 #define DDR2_Rtt_Nom_75       (0x4)
1048 #define DDR2_Rtt_Nom_50       (0x44)
1049
1050 /***********************************
1051  * LPDDR define
1052  ***********************************/
1053 #define mDDR_BL2           (1)
1054 #define mDDR_BL4           (2)
1055 #define mDDR_BL8           (3)
1056 #define mDDR_CL(n)         (((n)&0x7)<<4)
1057
1058 #define mDDR_DS_Full       (0)
1059 #define mDDR_DS_1_2        (1<<5)
1060 #define mDDR_DS_1_4        (2<<5)
1061 #define mDDR_DS_1_8        (3<<5)
1062 #define mDDR_DS_3_4        (4<<5)
1063
1064 static const uint8_t ddr3_cl_cwl[22][7]={
1065 /*speed   0~330         331~400       401~533        534~666       667~800        801~933      934~1066
1066  * tCK    >3            2.5~3         1.875~2.5      1.5~1.875     1.25~1.5       1.07~1.25    0.938~1.07
1067  *        cl<<4, cwl    cl<<4, cwl    cl<<4, cwl              */
1068          {((5<<4)|5),   ((5<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800D (5-5-5)
1069          {((5<<4)|5),   ((6<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800E (6-6-6)
1070
1071          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    0,            0,             0,            0}, //DDR3_1066E (6-6-6)
1072          {((5<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    0,            0,             0,            0}, //DDR3_1066F (7-7-7)
1073          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    0,            0,             0,            0}, //DDR3_1066G (8-8-8)
1074
1075          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   0,             0,            0}, //DDR3_1333F (7-7-7)
1076          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   0,             0,            0}, //DDR3_1333G (8-8-8)
1077          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((9<<4)|7),   0,             0,            0}, //DDR3_1333H (9-9-9)
1078          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  0,             0,            0}, //DDR3_1333J (10-10-10)
1079
1080          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((8<<4)|8),    0,            0}, //DDR3_1600G (8-8-8)
1081          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    0,            0}, //DDR3_1600H (9-9-9)
1082          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   0,            0}, //DDR3_1600J (10-10-10)
1083          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   0,            0}, //DDR3_1600K (11-11-11)
1084
1085          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  0}, //DDR3_1866J (10-10-10)
1086          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   ((10<<4)|8),   ((11<<4)|9),  0}, //DDR3_1866K (11-11-11)
1087          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((12<<4)|9),  0}, //DDR3_1866L (12-12-12)
1088          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  0}, //DDR3_1866M (13-13-13)
1089
1090          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((9<<4)|8),    ((10<<4)|9),  ((11<<4)|10)}, //DDR3_2133K (11-11-11)
1091          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  ((12<<4)|10)}, //DDR3_2133L (12-12-12)
1092          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   ((12<<4)|9),  ((13<<4)|10)}, //DDR3_2133M (13-13-13)
1093          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)},  //DDR3_2133N (14-14-14)
1094
1095          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)} //DDR3_DEFAULT
1096 };
1097
1098 static const uint16_t ddr3_tRC_tFAW[22]={
1099 /**    tRC    tFAW   */
1100     ((50<<8)|50), //DDR3_800D (5-5-5)
1101     ((53<<8)|50), //DDR3_800E (6-6-6)
1102
1103     ((49<<8)|50), //DDR3_1066E (6-6-6)
1104     ((51<<8)|50), //DDR3_1066F (7-7-7)
1105     ((53<<8)|50), //DDR3_1066G (8-8-8)
1106
1107     ((47<<8)|45), //DDR3_1333F (7-7-7)
1108     ((48<<8)|45), //DDR3_1333G (8-8-8)
1109     ((50<<8)|45), //DDR3_1333H (9-9-9)
1110     ((51<<8)|45), //DDR3_1333J (10-10-10)
1111
1112     ((45<<8)|40), //DDR3_1600G (8-8-8)
1113     ((47<<8)|40), //DDR3_1600H (9-9-9)
1114     ((48<<8)|40), //DDR3_1600J (10-10-10)
1115     ((49<<8)|40), //DDR3_1600K (11-11-11)
1116
1117     ((45<<8)|35), //DDR3_1866J (10-10-10)
1118     ((46<<8)|35), //DDR3_1866K (11-11-11)
1119     ((47<<8)|35), //DDR3_1866L (12-12-12)
1120     ((48<<8)|35), //DDR3_1866M (13-13-13)
1121
1122     ((44<<8)|35), //DDR3_2133K (11-11-11)
1123     ((45<<8)|35), //DDR3_2133L (12-12-12)
1124     ((46<<8)|35), //DDR3_2133M (13-13-13)
1125     ((47<<8)|35), //DDR3_2133N (14-14-14)
1126
1127     ((53<<8)|50)  //DDR3_DEFAULT
1128 };
1129
1130 typedef enum DRAM_TYPE_Tag
1131 {
1132     LPDDR = 0,
1133     DDR,
1134     DDR2,
1135     DDR3,
1136     LPDDR2,
1137     LPDDR3,
1138
1139     DRAM_MAX
1140 }DRAM_TYPE;
1141
1142 typedef struct PCTRL_TIMING_Tag
1143 {
1144     uint32 ddrFreq;
1145     //Memory Timing Registers
1146     uint32 togcnt1u;               //Toggle Counter 1U Register
1147     uint32 tinit;                  //t_init Timing Register
1148     uint32 trsth;                  //Reset High Time Register
1149     uint32 togcnt100n;             //Toggle Counter 100N Register
1150     uint32 trefi;                  //t_refi Timing Register
1151     uint32 tmrd;                   //t_mrd Timing Register
1152     uint32 trfc;                   //t_rfc Timing Register
1153     uint32 trp;                    //t_rp Timing Register
1154     uint32 trtw;                   //t_rtw Timing Register
1155     uint32 tal;                    //AL Latency Register
1156     uint32 tcl;                    //CL Timing Register
1157     uint32 tcwl;                   //CWL Register
1158     uint32 tras;                   //t_ras Timing Register
1159     uint32 trc;                    //t_rc Timing Register
1160     uint32 trcd;                   //t_rcd Timing Register
1161     uint32 trrd;                   //t_rrd Timing Register
1162     uint32 trtp;                   //t_rtp Timing Register
1163     uint32 twr;                    //t_wr Timing Register
1164     uint32 twtr;                   //t_wtr Timing Register
1165     uint32 texsr;                  //t_exsr Timing Register
1166     uint32 txp;                    //t_xp Timing Register
1167     uint32 txpdll;                 //t_xpdll Timing Register
1168     uint32 tzqcs;                  //t_zqcs Timing Register
1169     uint32 tzqcsi;                 //t_zqcsi Timing Register
1170     uint32 tdqs;                   //t_dqs Timing Register
1171     uint32 tcksre;                 //t_cksre Timing Register
1172     uint32 tcksrx;                 //t_cksrx Timing Register
1173     uint32 tcke;                   //t_cke Timing Register
1174     uint32 tmod;                   //t_mod Timing Register
1175     uint32 trstl;                  //Reset Low Timing Register
1176     uint32 tzqcl;                  //t_zqcl Timing Register
1177     uint32 tmrr;                   //t_mrr Timing Register
1178     uint32 tckesr;                 //t_ckesr Timing Register
1179     uint32 tdpd;                   //t_dpd Timing Register
1180 }PCTL_TIMING_T;
1181
1182 typedef union DTPR_0_Tag
1183 {
1184     uint32 d32;
1185     struct
1186     {
1187         unsigned tMRD : 2;
1188         unsigned tRTP : 3;
1189         unsigned tWTR : 3;
1190         unsigned tRP : 4;
1191         unsigned tRCD : 4;
1192         unsigned tRAS : 5;
1193         unsigned tRRD : 4;
1194         unsigned tRC : 6;
1195         unsigned tCCD : 1;
1196     } b;
1197 }DTPR_0_T;
1198
1199 typedef union DTPR_1_Tag
1200 {
1201     uint32 d32;
1202     struct
1203     {
1204         unsigned tAOND : 2;
1205         unsigned tRTW : 1;
1206         unsigned tFAW : 6;
1207         unsigned tMOD : 2;
1208         unsigned tRTODT : 1;
1209         unsigned reserved12_15 : 4;
1210         unsigned tRFC : 8;
1211         unsigned tDQSCK : 3;
1212         unsigned tDQSCKmax : 3;
1213         unsigned reserved30_31 : 2;
1214     } b;
1215 }DTPR_1_T;
1216
1217 typedef union DTPR_2_Tag
1218 {
1219     uint32 d32;
1220     struct
1221     {
1222         unsigned tXS : 10;
1223         unsigned tXP : 5;
1224         unsigned tCKE : 4;
1225         unsigned tDLLK : 10;
1226         unsigned reserved29_31 : 3;
1227     } b;
1228 }DTPR_2_T;
1229
1230 typedef struct PHY_TIMING_Tag
1231 {
1232     DTPR_0_T  dtpr0;
1233     DTPR_1_T  dtpr1;
1234     DTPR_2_T  dtpr2;
1235     uint32    mr[4];   //LPDDR2 no MR0, mr[2] is mDDR MR1
1236     uint32    mr11;    //for LPDDR3 only
1237 }PHY_TIMING_T;
1238
1239 typedef struct PCTL_REG_Tag
1240 {
1241     uint32 SCFG;
1242     uint32 CMDTSTATEN;
1243     uint32 MCFG1;
1244     uint32 MCFG;
1245     PCTL_TIMING_T pctl_timing;
1246     //DFI Control Registers
1247     uint32 DFITCTRLDELAY;
1248     uint32 DFIODTCFG;
1249     uint32 DFIODTCFG1;
1250     uint32 DFIODTRANKMAP;
1251     //DFI Write Data Registers
1252     uint32 DFITPHYWRDATA;
1253     uint32 DFITPHYWRLAT;
1254     //DFI Read Data Registers
1255     uint32 DFITRDDATAEN;
1256     uint32 DFITPHYRDLAT;
1257     //DFI Update Registers
1258     uint32 DFITPHYUPDTYPE0;
1259     uint32 DFITPHYUPDTYPE1;
1260     uint32 DFITPHYUPDTYPE2;
1261     uint32 DFITPHYUPDTYPE3;
1262     uint32 DFITCTRLUPDMIN;
1263     uint32 DFITCTRLUPDMAX;
1264     uint32 DFITCTRLUPDDLY;
1265     uint32 DFIUPDCFG;
1266     uint32 DFITREFMSKI;
1267     uint32 DFITCTRLUPDI;
1268     //DFI Status Registers
1269     uint32 DFISTCFG0;
1270     uint32 DFISTCFG1;
1271     uint32 DFITDRAMCLKEN;
1272     uint32 DFITDRAMCLKDIS;
1273     uint32 DFISTCFG2;
1274     //DFI Low Power Register
1275     uint32 DFILPCFG0;
1276 }PCTL_REG_T;
1277
1278 typedef struct PUBL_DQS_REG_Tag
1279 {
1280     uint32 DX0GCR;
1281     uint32 DX0DLLCR;
1282     uint32 DX0DQTR;
1283     uint32 DX0DQSTR;
1284
1285     uint32 DX1GCR;
1286     uint32 DX1DLLCR;
1287     uint32 DX1DQTR;
1288     uint32 DX1DQSTR;
1289
1290     uint32 DX2GCR;
1291     uint32 DX2DLLCR;
1292     uint32 DX2DQTR;
1293     uint32 DX2DQSTR;
1294
1295     uint32 DX3GCR;
1296     uint32 DX3DLLCR;
1297     uint32 DX3DQTR;
1298     uint32 DX3DQSTR;
1299 }PUBL_DQS_REG;
1300
1301 typedef struct PUBL_REG_Tag
1302 {
1303     uint32 PIR;
1304     uint32 PGCR;
1305     uint32 DLLGCR;
1306     uint32 ACDLLCR;
1307     uint32 PTR[3];
1308     uint32 ACIOCR;
1309     uint32 DXCCR;
1310     uint32 DSGCR;
1311     uint32 DCR;
1312     PHY_TIMING_T phy_timing;
1313     uint32 ODTCR;
1314     uint32 DTAR;
1315     uint32 ZQ0CR0;
1316     uint32 ZQ1CR0;
1317 }PUBL_REG_T;
1318
1319 typedef struct SET_REG_Tag
1320 {
1321     uint32 addr;
1322     uint32 val;
1323 }SET_REG_T;
1324
1325 typedef struct BACKUP_REG_Tag
1326 {
1327     uint32 tag;
1328     /* any addr = 0xFFFFFFFF, indicate invalid */
1329     uint32 pctlAddr[CH_MAX];
1330     PCTL_REG_T pctl;
1331     uint32 publAddr[CH_MAX];
1332     PUBL_REG_T publ;
1333     PUBL_DQS_REG dqs[CH_MAX];
1334     uint32 nocAddr[CH_MAX];
1335     MSCH_REG   noc[CH_MAX];
1336
1337     uint32 pllpdAddr;
1338     uint32 pllpdMask;
1339     uint32 pllpdVal;
1340
1341     uint32 dpllmodeAddr;
1342     uint32 dpllSlowMode;
1343     uint32 dpllNormalMode;
1344     uint32 dpllResetAddr;
1345     uint32 dpllReset;
1346     uint32 dpllDeReset;
1347     uint32 dpllConAddr;
1348     uint32 dpllCon[4];
1349     uint32 dpllLockAddr;
1350     uint32 dpllLockMask;
1351     uint32 dpllLockVal;
1352
1353     uint32 ddrPllSrcDivAddr;
1354     uint32 ddrPllSrcDiv;
1355
1356     uint32 retenDisAddr;
1357     uint32 retenDisVal;
1358     uint32 retenStAddr;
1359     uint32 retenStMask;
1360     uint32 retenStVal;
1361
1362     /* ddr relative grf register */
1363     uint32 grfRegCnt;     //if no grf, set 0
1364     SET_REG_T grf[3];        //SET_REG_T grf[grfRegCnt];
1365
1366     /* other ddr relative register */
1367     //uint32 otherRegCnt; // if = 0xFFFFFFFF, indicate invalid
1368     //SET_REG_T other[grfRegCnt];
1369     uint32 endTag;         //must = 0xFFFFFFFF
1370 }BACKUP_REG_T;
1371
1372 typedef struct CHANNEL_INFO_Tag
1373 {
1374     //inited data
1375     uint32        chNum;  //channel number,0:channel a; 1:channel b;
1376     pDDR_REG_T    pDDR_Reg;
1377     pDDRPHY_REG_T pPHY_Reg;
1378     pMSCH_REG     pMSCH_Reg;
1379     //need init data
1380     DRAM_TYPE     mem_type; // =DRAM_MAX, channel invalid
1381     uint32        ddr_speed_bin;    // used for ddr3 only
1382     uint32        ddr_capability_per_die;  // one chip cs capability
1383     uint32        dtt_cs;  //data training cs
1384 }CH_INFO,*pCH_INFO;
1385
1386 struct ddr_freq_t {
1387     unsigned long screen_ft_us;
1388     unsigned long long t0;
1389     unsigned long long t1;
1390     unsigned long t2;
1391 };
1392
1393 typedef struct STRIDE_INFO_Tag
1394 {
1395     uint32  size;
1396     uint32  halfCap;
1397 }STRIDE_INFO;
1398
1399 static const STRIDE_INFO   gStrideInfo[]={
1400     {0x10000000,0x10000000},  // 256
1401     {0x20000000,0x20000000},  // 512
1402     {0x40000000,0x40000000},  // 1G
1403     {0x80000000,0x80000000},  // 2G
1404
1405     {128,0x20000000},
1406     {256,0x20000000},
1407     {512,0x20000000},
1408     {4096,0x20000000},
1409
1410     {128,0x40000000},
1411     {256,0x40000000},
1412     {512,0x40000000},
1413     {4096,0x40000000},
1414
1415     {128,0x80000000},
1416     {256,0x80000000},
1417     {512,0x80000000},
1418     {4096,0x80000000},
1419
1420     {128,0x60000000},
1421     {256,0x60000000},
1422     {512,0x60000000},
1423     {4096,0x60000000},
1424
1425     {0,0x20000000},
1426     {0,0x40000000},
1427     {0,0x80000000},
1428     {0,0x80000000},  // 4GB
1429
1430     {0,0},  //reserved
1431     {0,0},  //reserved
1432
1433     {0,0},
1434     {128,0},
1435 };
1436
1437 CH_INFO DEFINE_PIE_DATA(ddr_ch[2]);
1438 static pCH_INFO p_ddr_ch[2];    //only used in kern, not pie
1439 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
1440 static BACKUP_REG_T *p_ddr_reg;
1441 static __attribute__((aligned(4096))) uint32 ddr_data_training_buf[32+8192/4];  //data in two channel even use max stride
1442 uint32 DEFINE_PIE_DATA(ddr_freq);
1443 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
1444
1445 /***********************************
1446  * ARCH Relative Data and Function
1447  ***********************************/
1448 static __sramdata uint32 clkr;
1449 static __sramdata uint32 clkf;
1450 static __sramdata uint32 clkod;
1451 uint32 DEFINE_PIE_DATA(ddr_select_gpll_div); // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1452 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
1453 static uint32 *p_ddr_select_gpll_div;
1454 #endif
1455
1456 static void __sramfunc ddr_delayus(uint32 us);
1457
1458 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
1459 {
1460     uint32 ret = 0;
1461
1462      // freq = (Fin/NR)*NF/OD
1463     if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1)             // DPLL Normal mode
1464         ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x1fff)+1)    // NF = 2*(CLKF+1)
1465                 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1)           // NR = CLKR+1
1466                 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xF)+1));             // OD = 2^CLKOD
1467     else
1468         ret = 24;
1469
1470     return ret;
1471 }
1472
1473 /*****************************************
1474 NR   NO     NF               Fout                       freq Step     finally use
1475 1    8      12.5 - 62.5      37.5MHz  - 187.5MHz        3MHz          50MHz   <= 150MHz
1476 1    6      12.5 - 62.5      50MHz    - 250MHz          4MHz          150MHz  <= 200MHz
1477 1    4      12.5 - 62.5      75MHz    - 375MHz          6MHz          200MHz  <= 300MHz
1478 1    2      12.5 - 62.5      150MHz   - 750MHz          12MHz         300MHz  <= 600MHz
1479 1    1      12.5 - 62.5      300MHz   - 1500MHz         24MHz         600MHz  <= 1200MHz
1480 ******************************************/
1481 static uint32 __sramfunc ddr_set_pll_rk3188_plus(uint32 nMHz, uint32 set)
1482 {
1483     uint32 ret = 0;
1484     int delay;
1485
1486     if(nMHz == 24)
1487     {
1488         ret = 24;
1489         goto out;
1490     }
1491
1492     if(set==0)
1493     {
1494         if(nMHz <= 150)
1495         {
1496             clkod = 8;
1497         }
1498         else if(nMHz <= 200)
1499         {
1500             clkod = 6;
1501         }
1502         else if(nMHz <= 300)
1503         {
1504             clkod = 4;
1505         }
1506         else if(nMHz <= 600)
1507         {
1508             clkod = 2;
1509         }
1510         else
1511         {
1512             clkod = 1;
1513         }
1514         clkr = 1;
1515         clkf=(nMHz*clkr*clkod)/24;
1516         ret = (24*clkf)/(clkr*clkod);
1517     }
1518     else if(set == 1)
1519     {
1520         SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)-1));  //clk_ddr_src = GPLL
1521
1522         SET_PLL_MODE(DPLL,0);            //PLL slow-mode
1523         dsb();
1524
1525         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
1526         ddr_delayus(1);
1527         pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
1528         pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
1529         pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
1530         ddr_delayus(1);
1531         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
1532         dsb();
1533     }
1534     else
1535     {
1536         delay = 1000;
1537         while (delay > 0)
1538         {
1539             if (GET_DPLL_LOCK_STATUS())
1540                 break;
1541             ddr_delayus(1);
1542             delay--;
1543         }
1544
1545         SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1546         SET_PLL_MODE(DPLL,1);            //PLL normal
1547         dsb();
1548     }
1549
1550 out:
1551     return ret;
1552 }
1553
1554 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1555 {
1556     return ddr_set_pll_rk3188_plus(nMHz,set);
1557 }
1558 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1559 static uint32 (*p_ddr_set_pll)(uint32 nMHz, uint32 set);
1560
1561 static void __sramfunc idle_port(void)
1562 {
1563     register int i,j;
1564     uint32 clk_gate[19];
1565
1566     pPMU_Reg->PMU_IDLE_REQ |= idle_req_core_cfg;
1567     dsb();
1568     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) == 0 );
1569
1570     //save clock gate status
1571     for(i=0;i<19;i++)
1572         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1573
1574     //enable all clock gate for request idle
1575     for(i=0;i<19;i++)
1576         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1577
1578     i = pPMU_Reg->PMU_PWRDN_ST;
1579     j = idle_req_dma_cfg;
1580
1581     if ( (i & pd_peri_pwr_st) == 0 )
1582     {
1583         j |= idle_req_peri_cfg;
1584     }
1585
1586     if ( (i & pd_video_pwr_st) == 0 )
1587     {
1588         j |= idle_req_video_cfg;
1589     }
1590
1591     if ( (i & pd_gpu_pwr_st) == 0 )
1592     {
1593         j |= idle_req_gpu_cfg;
1594     }
1595
1596     if ( (i & pd_hevc_pwr_st) == 0 )
1597     {
1598         j |= idle_req_hevc_cfg;
1599     }
1600
1601     if ( (i & pd_vio_pwr_st) == 0 )
1602     {
1603         j |= idle_req_vio_cfg;
1604     }
1605
1606     pPMU_Reg->PMU_IDLE_REQ |= j;
1607     dsb();
1608     while( (pPMU_Reg->PMU_IDLE_ST & j) != j );
1609
1610     //resume clock gate status
1611     for(i=0;i<19;i++)
1612         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1613 }
1614
1615 static void inline deidle_port(void)
1616 {
1617     register int i,j;
1618     uint32 clk_gate[19];
1619
1620     //save clock gate status
1621     for(i=0;i<19;i++)
1622         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1623
1624     //enable all clock gate for request idle
1625     for(i=0;i<19;i++)
1626         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1627
1628     i = pPMU_Reg->PMU_PWRDN_ST;
1629     j = idle_req_dma_cfg;
1630
1631     if ( (i & pd_peri_pwr_st) == 0 )
1632     {
1633         j |= idle_req_peri_cfg;
1634     }
1635
1636     if ( (i & pd_video_pwr_st) == 0 )
1637     {
1638         j |= idle_req_video_cfg;
1639     }
1640
1641     if ( (i & pd_gpu_pwr_st) == 0 )
1642     {
1643         j |= idle_req_gpu_cfg;
1644     }
1645
1646     if ( (i & pd_hevc_pwr_st) == 0 )
1647     {
1648         j |= idle_req_hevc_cfg;
1649     }
1650
1651     if ( (i & pd_vio_pwr_st) == 0 )
1652     {
1653         j |= idle_req_vio_cfg;
1654     }
1655
1656     pPMU_Reg->PMU_IDLE_REQ &= ~j;
1657     dsb();
1658     while( (pPMU_Reg->PMU_IDLE_ST & j) != 0 );
1659
1660     pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_core_cfg;
1661     dsb();
1662     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) != 0 );
1663
1664     //resume clock gate status
1665     for(i=0;i<19;i++)
1666         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1667
1668 }
1669
1670 /***********************************
1671  * Only DDR Relative Function
1672  ***********************************/
1673
1674 /****************************************************************************
1675 Internal sram us delay function
1676 Cpu highest frequency is 1.6 GHz
1677 1 cycle = 1/1.6 ns
1678 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1679 *****************************************************************************/
1680 __sramdata volatile uint32 loops_per_us;
1681
1682 #define LPJ_100MHZ  999456UL
1683
1684 static void __sramfunc ddr_delayus(uint32 us)
1685 {
1686     do
1687     {
1688         volatile unsigned int i = (loops_per_us*us);
1689         if (i < 7) i = 7;
1690         barrier();
1691         asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1692     } while (0);
1693 }
1694
1695 void PIE_FUNC(ddr_copy)(uint64_t *pDest, uint64_t *pSrc, uint32 wword)
1696 {
1697     uint32 i;
1698
1699     for(i=0; i<wword; i++)
1700     {
1701         pDest[i] = pSrc[i];
1702     }
1703 }
1704 EXPORT_PIE_SYMBOL(FUNC(ddr_copy));
1705
1706 static void ddr_get_datatraing_addr(uint32 *pdtar)
1707 {
1708     uint32          addr;
1709     uint32          stride;
1710     uint32          strideSize;
1711     uint32          halfCap;
1712     uint32          ch,chCnt;
1713     uint32          socAddr[2];
1714     uint32          chAddr[2];
1715     uint32          col;
1716     uint32          row;
1717     uint32          bank;
1718     uint32          bw;
1719     uint32          conf;
1720     uint32          cap1;
1721
1722     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1723     {
1724         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1725         {
1726             chCnt++;
1727         }
1728         p_ddr_ch[ch]->dtt_cs = 0;
1729     }
1730
1731     // caculate aglined physical address
1732     addr =  __pa((unsigned long)ddr_data_training_buf);
1733     ddr_print("addr=0x%x\n",addr);
1734     if(addr&0x3F)
1735     {
1736         addr += (64-(addr&0x3F));  // 64byte align
1737     }
1738     addr -= DRAM_PHYS;
1739     if(chCnt > 1)
1740     {
1741         //find stride info
1742         stride = READ_DDR_STRIDE();
1743         strideSize = gStrideInfo[stride].size;
1744         halfCap = gStrideInfo[stride].halfCap;
1745         ddr_print("stride=%d, size=%d, halfcap=%x\n", stride,strideSize,halfCap);
1746         //get soc addr
1747         if(addr & strideSize)  // odd stride size
1748         {
1749             socAddr[0] = addr + strideSize;
1750             socAddr[1] = addr;
1751         }
1752         else
1753         {
1754             socAddr[0] = addr;
1755             socAddr[1] = addr + strideSize;
1756         }
1757         ddr_print("socAddr[0]=0x%x, socAddr[1]=0x%x\n", socAddr[0], socAddr[1]);
1758          if(stride < 4)
1759          {
1760                  cap1 = (1 << (READ_ROW_INFO(1,0)+READ_COL_INFO(1)+READ_BK_INFO(1)+READ_BW_INFO(1)));
1761                 if(READ_CS_INFO(1) > 1)
1762                 {
1763                     cap1 += cap1 >> (READ_ROW_INFO(1,0)-READ_ROW_INFO(1,1));
1764                 }
1765                 if(READ_CH_ROW_INFO(1))
1766                 {
1767                     cap1 = cap1*3/4;
1768                 }
1769                  chAddr[0] = addr;
1770                  chAddr[1] = cap1 - PAGE_SIZE;
1771                  if(READ_CS_INFO(1) > 1)
1772                          p_ddr_ch[1]->dtt_cs = 1;
1773          }
1774         else if((stride >= 0x10) && (stride <= 0x13))  // 3GB stride
1775         {
1776             //conver to ch addr
1777             if(addr < 0x40000000)
1778             {
1779                 chAddr[0] = socAddr[0];
1780                 chAddr[1] = socAddr[1] - strideSize;
1781             }
1782             else if(addr < 0x80000000)
1783             {
1784                 chAddr[0] = socAddr[0] - 0x40000000 + strideSize;
1785                 chAddr[1] = socAddr[1] - 0x40000000;
1786             }
1787             else if(addr < 0xA0000000)
1788             {
1789                 chAddr[0] = socAddr[0] - 0x40000000;
1790                 chAddr[1] = socAddr[1] - 0x40000000 - strideSize;
1791             }
1792             else
1793             {
1794                 chAddr[0] = socAddr[0] - 0x60000000 + strideSize;
1795                 chAddr[1] = socAddr[1] - 0x60000000;
1796             }
1797         }
1798         else
1799         {
1800             //conver to ch addr
1801             if(addr <  halfCap)
1802             {
1803                 chAddr[0] = socAddr[0];
1804                 chAddr[1] = socAddr[1] - strideSize;
1805             }
1806             else
1807             {
1808                 chAddr[0] = socAddr[0] - halfCap + strideSize;
1809                 chAddr[1] = socAddr[1] - halfCap;
1810             }
1811         }
1812     }
1813     else
1814     {
1815         chAddr[0] = addr;
1816         chAddr[1] = addr;
1817     }
1818     ddr_print("chAddr[0]=0x%x, chAddr[1]=0x%x\n", chAddr[0], chAddr[1]);
1819
1820     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1821     {
1822         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1823         {
1824             // find out col£¬row£¬bank,config
1825             row = READ_ROW_INFO(ch,0);
1826             bank = READ_BK_INFO(ch);
1827             col = READ_COL_INFO(ch);
1828             bw = READ_BW_INFO(ch);
1829             conf = p_ddr_ch[ch]->pMSCH_Reg->ddrconf;
1830             // according different address mapping, caculate DTAR register value
1831             pdtar[ch] = 0;
1832             pdtar[ch] |= ((chAddr[ch])>>bw) & ((0x1<<col)-1);  // col
1833             pdtar[ch] |= (((chAddr[ch])>>(bw+col+((ddr_cfg_2_rbc[conf]>>2)&0x3))) & ((0x1<<row)-1)) << 12;  // row
1834             if(((ddr_cfg_2_rbc[conf]>>7)&0x3)==3)
1835             {
1836                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col+row)) & ((0x1<<bank)-1))  << 28);  // bank
1837             }
1838             else
1839             {
1840                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col)) & 0x7) << 28);  // bank
1841             }
1842         }
1843     }
1844     ddr_print("dtar[0]=0x%x, dtar[1]=0x%x\n", pdtar[0], pdtar[1]);
1845 }
1846
1847 static __sramfunc void ddr_reset_dll(uint32 ch)
1848 {
1849     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1850     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1851
1852     pPHY_Reg->ACDLLCR &= ~0x40000000;
1853     pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1854     pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1855     if(!(pDDR_Reg->PPCFG & 1))
1856     {
1857         pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1858         pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1859     }
1860     ddr_delayus(1);
1861     pPHY_Reg->ACDLLCR |= 0x40000000;
1862     pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1863     pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1864     if(!(pDDR_Reg->PPCFG & 1))
1865     {
1866         pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1867         pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1868     }
1869     ddr_delayus(1);
1870 }
1871
1872 static __sramfunc void ddr_move_to_Lowpower_state(uint32 ch)
1873 {
1874     register uint32 value;
1875     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1876
1877     while(1)
1878     {
1879         value = pDDR_Reg->STAT.b.ctl_stat;
1880         if(value == Low_power)
1881         {
1882             break;
1883         }
1884         switch(value)
1885         {
1886             case Init_mem:
1887                 pDDR_Reg->SCTL = CFG_STATE;
1888                 dsb();
1889                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1890             case Config:
1891                 pDDR_Reg->SCTL = GO_STATE;
1892                 dsb();
1893                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1894             case Access:
1895                 pDDR_Reg->SCTL = SLEEP_STATE;
1896                 dsb();
1897                 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1898                 break;
1899             default:  //Transitional state
1900                 break;
1901         }
1902     }
1903 }
1904
1905 static __sramfunc void ddr_move_to_Access_state(uint32 ch)
1906 {
1907     register uint32 value;
1908     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1909     register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1910
1911     //set auto self-refresh idle
1912     pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00) | DATA(ddr_sr_idle) | (1<<31);
1913     dsb();
1914
1915     while(1)
1916     {
1917         value = pDDR_Reg->STAT.b.ctl_stat;
1918         if((value == Access)
1919            || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1920         {
1921             break;
1922         }
1923         switch(value)
1924         {
1925             case Low_power:
1926                 pDDR_Reg->SCTL = WAKEUP_STATE;
1927                 dsb();
1928                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1929                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1930                 break;
1931             case Init_mem:
1932                 pDDR_Reg->SCTL = CFG_STATE;
1933                 dsb();
1934                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1935             case Config:
1936                 pDDR_Reg->SCTL = GO_STATE;
1937                 dsb();
1938                 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1939                       || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1940                 break;
1941             default:  //Transitional state
1942                 break;
1943         }
1944     }
1945     /* de_hw_wakeup :enable auto sr if sr_idle != 0 */
1946     DDR_HW_WAKEUP(ch,0);
1947 }
1948
1949 static __sramfunc void ddr_move_to_Config_state(uint32 ch)
1950 {
1951     register uint32 value;
1952     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1953     register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1954
1955     /* hw_wakeup :disable auto sr */
1956     DDR_HW_WAKEUP(ch,1);
1957         dsb();
1958
1959     while(1)
1960     {
1961         value = pDDR_Reg->STAT.b.ctl_stat;
1962         if(value == Config)
1963         {
1964             break;
1965         }
1966         switch(value)
1967         {
1968             case Low_power:
1969                 pDDR_Reg->SCTL = WAKEUP_STATE;
1970                 dsb();
1971                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1972                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1973             case Access:
1974             case Init_mem:
1975                 pDDR_Reg->SCTL = CFG_STATE;
1976                 dsb();
1977                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1978                 break;
1979             default:  //Transitional state
1980                 break;
1981         }
1982     }
1983 }
1984
1985 //arg°üÀ¨bank_addrºÍcmd_addr
1986 static void __sramfunc ddr_send_command(uint32 ch, uint32 rank, uint32 cmd, uint32 arg)
1987 {
1988     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1989
1990     pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1991     dsb();
1992     while(pDDR_Reg->MCMD & start_cmd);
1993 }
1994
1995 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
1996 //0  DTT³É¹¦
1997 //!0 DTTÊ§°Ü
1998 static uint32 __sramfunc ddr_data_training_trigger(uint32 ch)
1999 {
2000     uint32        cs;
2001     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2002     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2003
2004     // disable auto refresh
2005     pDDR_Reg->TREFI = 0;
2006     dsb();
2007     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
2008        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
2009     {
2010         // passive window
2011         pPHY_Reg->PGCR |= (1<<1);
2012     }
2013     // clear DTDONE status
2014     pPHY_Reg->PIR |= CLRSR;
2015     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2016     if(DATA(ddr_ch[ch]).dtt_cs == 0)
2017             pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18);  //use cs0 dtt
2018     else
2019             pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (2<<18);  //use cs1 dtt
2020     // trigger DTT
2021     pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
2022     return cs;
2023 }
2024 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
2025 //0  DTT³É¹¦
2026 //!0 DTTÊ§°Ü
2027 static uint32 __sramfunc ddr_data_training(uint32 ch, uint32 cs)
2028 {
2029     uint32        i,byte=2,cs_msk;
2030     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2031     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2032
2033     if(DATA(ddr_ch[ch]).dtt_cs == 0){
2034         cs_msk = 1;
2035     }else{
2036         cs_msk = 2;
2037     }
2038     // wait echo byte DTDONE
2039     while((pPHY_Reg->DATX8[0].DXGSR[0] & cs_msk) != cs_msk);
2040     while((pPHY_Reg->DATX8[1].DXGSR[0] & cs_msk) != cs_msk);
2041     if(!(pDDR_Reg->PPCFG & 1))
2042     {
2043         while((pPHY_Reg->DATX8[2].DXGSR[0] & cs_msk) != cs_msk);
2044         while((pPHY_Reg->DATX8[3].DXGSR[0] & cs_msk) != cs_msk);
2045         byte=4;
2046     }
2047     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18);  //restore cs
2048     if(DATA(ddr_ch[ch]).dtt_cs == 0){
2049         for(i=0;i<byte;i++)
2050         {
2051             pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))\
2052                                           | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)\
2053                                           | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
2054         }
2055     }else{
2056         for(i=0;i<byte;i++)
2057         {
2058             pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<0)|(0x3<<12))))\
2059                                           | ((pPHY_Reg->DATX8[i].DXDQSTR>>3) & 0x7)\
2060                                           | (((pPHY_Reg->DATX8[i].DXDQSTR>>14) & 0x3)<<12);
2061         }
2062     }
2063     // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×î³¤Ê±¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
2064     if(cs > 1)
2065     {
2066         ddr_send_command(ch,cs, REF_cmd, 0);
2067         ddr_send_command(ch,cs, REF_cmd, 0);
2068         ddr_send_command(ch,cs, REF_cmd, 0);
2069         ddr_send_command(ch,cs, REF_cmd, 0);
2070     }
2071     else
2072     {
2073         ddr_send_command(ch,cs, REF_cmd, 0);
2074         ddr_send_command(ch,cs, REF_cmd, 0);
2075     }
2076     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
2077        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
2078     {
2079         // active window
2080         pPHY_Reg->PGCR &= ~(1<<1);
2081     }
2082     // resume auto refresh
2083     pDDR_Reg->TREFI = DATA(ddr_reg).pctl.pctl_timing.trefi;
2084
2085     if(pPHY_Reg->PGSR & DTERR)
2086     {
2087         return (-1);
2088     }
2089     else
2090     {
2091         return 0;
2092     }
2093 }
2094
2095
2096 static void __sramfunc ddr_set_dll_bypass(uint32 ch, uint32 freq)
2097 {
2098     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2099     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2100
2101     if(freq<=150)
2102     {
2103         pPHY_Reg->DLLGCR &= ~(1<<23);
2104         pPHY_Reg->ACDLLCR |= 0x80000000;
2105         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2106         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2107         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2108         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2109         pPHY_Reg->PIR |= DLLBYP;
2110     }
2111     else if(freq<=250)
2112     {
2113         pPHY_Reg->DLLGCR |= (1<<23);
2114         pPHY_Reg->ACDLLCR |= 0x80000000;
2115         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2116         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2117         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2118         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2119         pPHY_Reg->PIR |= DLLBYP;
2120     }
2121     else
2122     {
2123         pPHY_Reg->DLLGCR &= ~(1<<23);
2124         pPHY_Reg->ACDLLCR &= ~0x80000000;
2125         pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
2126         pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
2127         if(!(pDDR_Reg->PPCFG & 1))
2128         {
2129             pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
2130             pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
2131         }
2132         pPHY_Reg->PIR &= ~DLLBYP;
2133     }
2134 }
2135
2136 static noinline uint32 ddr_get_parameter(uint32 nMHz)
2137 {
2138     uint32 tmp;
2139     uint32 ret = 0;
2140     uint32 al;
2141     uint32 bl,bl_tmp;
2142     uint32 cl;
2143     uint32 cwl;
2144     PCTL_TIMING_T *p_pctl_timing=&(p_ddr_reg->pctl.pctl_timing);
2145     PHY_TIMING_T  *p_publ_timing=&(p_ddr_reg->publ.phy_timing);
2146     volatile NOC_TIMING_T  *p_noc_timing=&(p_ddr_reg->noc[0].ddrtiming);
2147     volatile NOC_ACTIVATE_T  *p_noc_activate=&(p_ddr_reg->noc[0].activate);
2148     uint32 ch;
2149     uint32 mem_type;
2150     uint32 ddr_speed_bin=DDR3_DEFAULT;
2151     uint32 ddr_capability_per_die=0;
2152
2153     for(ch=0;ch<CH_MAX;ch++)
2154     {
2155         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
2156         {
2157             mem_type = p_ddr_ch[ch]->mem_type;
2158             if(ddr_speed_bin == DDR3_DEFAULT)
2159             {
2160                 ddr_speed_bin = p_ddr_ch[ch]->ddr_speed_bin;
2161             }
2162             else
2163             {
2164                 ddr_speed_bin = (ddr_speed_bin > p_ddr_ch[ch]->ddr_speed_bin) ? ddr_speed_bin : p_ddr_ch[ch]->ddr_speed_bin;
2165             }
2166             if(ddr_capability_per_die == 0)
2167             {
2168                 ddr_capability_per_die = p_ddr_ch[ch]->ddr_capability_per_die;
2169             }
2170             else
2171             {
2172                 ddr_capability_per_die = (ddr_capability_per_die > p_ddr_ch[ch]->ddr_capability_per_die) ? ddr_capability_per_die : p_ddr_ch[ch]->ddr_capability_per_die;
2173             }
2174             break;
2175         }
2176     }
2177
2178     p_pctl_timing->togcnt1u = nMHz;
2179     p_pctl_timing->togcnt100n = nMHz/10;
2180     p_pctl_timing->tinit = 200;
2181     p_pctl_timing->trsth = 500;
2182
2183     if(mem_type == DDR3)
2184     {
2185         if(ddr_speed_bin > DDR3_DEFAULT){
2186             ret = -1;
2187             goto out;
2188         }
2189
2190         #define DDR3_tREFI_7_8_us    (78)  //unit 100ns
2191         #define DDR3_tMRD            (4)   //tCK
2192         #define DDR3_tRFC_512Mb      (90)  //ns
2193         #define DDR3_tRFC_1Gb        (110) //ns
2194         #define DDR3_tRFC_2Gb        (160) //ns
2195         #define DDR3_tRFC_4Gb        (300) //ns
2196         #define DDR3_tRFC_8Gb        (350) //ns
2197         #define DDR3_tRTW            (2)   //register min valid value
2198         #define DDR3_tRAS            (37)  //ns
2199         #define DDR3_tRRD            (10)  //ns
2200         #define DDR3_tRTP            (7)   //ns
2201         #define DDR3_tWR             (15)  //ns
2202         #define DDR3_tWTR            (7)   //ns
2203         #define DDR3_tXP             (7)   //ns
2204         #define DDR3_tXPDLL          (24)  //ns
2205         #define DDR3_tZQCS           (80)  //ns
2206         #define DDR3_tZQCSI          (0)   //ns
2207         #define DDR3_tDQS            (1)   //tCK
2208         #define DDR3_tCKSRE          (10)  //ns
2209         #define DDR3_tCKE_400MHz     (7)   //ns
2210         #define DDR3_tCKE_533MHz     (6)   //ns
2211         #define DDR3_tMOD            (15)  //ns
2212         #define DDR3_tRSTL           (100) //ns
2213         #define DDR3_tZQCL           (320) //ns
2214         #define DDR3_tDLLK           (512) //tCK
2215
2216         al = 0;
2217         bl = 8;
2218         if(nMHz <= 330)
2219         {
2220             tmp = 0;
2221         }
2222         else if(nMHz<=400)
2223         {
2224             tmp = 1;
2225         }
2226         else if(nMHz<=533)
2227         {
2228             tmp = 2;
2229         }
2230         else if(nMHz<=666)
2231         {
2232             tmp = 3;
2233         }
2234         else if(nMHz<=800)
2235         {
2236             tmp = 4;
2237         }
2238         else if(nMHz<=933)
2239         {
2240             tmp = 5;
2241         }
2242         else
2243         {
2244             tmp = 6;
2245         }
2246
2247         if(nMHz < 300)       //when dll bypss cl = cwl = 6;
2248         {
2249             cl = 6;
2250             cwl = 6;
2251         }
2252         else
2253         {
2254             cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
2255             cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
2256         }
2257         if(cl == 0)
2258             ret = -4;
2259         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2260         {
2261             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
2262         }
2263         else
2264         {
2265             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
2266         }
2267         p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
2268         p_publ_timing->mr[3] = 0;
2269         /**************************************************
2270          * PCTL Timing
2271          **************************************************/
2272         /*
2273          * tREFI, average periodic refresh interval, 7.8us
2274          */
2275         p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
2276         /*
2277          * tMRD, 4 tCK
2278          */
2279         p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
2280         p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
2281         /*
2282          * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
2283          */
2284         if(ddr_capability_per_die <= 0x4000000)         // 512Mb 90ns
2285         {
2286             tmp = DDR3_tRFC_512Mb;
2287         }
2288         else if(ddr_capability_per_die <= 0x8000000)    // 1Gb 110ns
2289         {
2290             tmp = DDR3_tRFC_1Gb;
2291         }
2292         else if(ddr_capability_per_die <= 0x10000000)   // 2Gb 160ns
2293         {
2294             tmp = DDR3_tRFC_2Gb;
2295         }
2296         else if(ddr_capability_per_die <= 0x20000000)   // 4Gb 300ns
2297         {
2298             tmp = DDR3_tRFC_4Gb;
2299         }
2300         else    // 8Gb  350ns
2301         {
2302             tmp = DDR3_tRFC_8Gb;
2303         }
2304         p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2305         p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000);
2306         /*
2307          * tXSR, =tDLLK=512 tCK
2308          */
2309         p_pctl_timing->texsr = DDR3_tDLLK;
2310         p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
2311         /*
2312          * tRP=CL
2313          */
2314         p_pctl_timing->trp = cl;
2315         p_publ_timing->dtpr0.b.tRP = cl;
2316         /*
2317          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2318          */
2319         p_noc_timing->b.WrToMiss = (cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl);
2320         /*
2321          * tRC=tRAS+tRP
2322          */
2323         p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2324         p_noc_timing->b.ActToAct = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2325         p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2326
2327         p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
2328         p_publ_timing->dtpr1.b.tRTW = 0;
2329         p_noc_timing->b.RdToWr = (cl+2-cwl);
2330         p_pctl_timing->tal = al;
2331         p_pctl_timing->tcl = cl;
2332         p_pctl_timing->tcwl = cwl;
2333         /*
2334          * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
2335          */
2336         p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
2337         p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000);
2338         /*
2339          * tRCD=CL
2340          */
2341         p_pctl_timing->trcd = cl;
2342         p_publ_timing->dtpr0.b.tRCD = cl;
2343         /*
2344          * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2345          *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2346          *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2347          *
2348          */
2349         tmp = ((DDR3_tRRD*nMHz+999)/1000);
2350         if(tmp < 4)
2351         {
2352             tmp = 4;
2353         }
2354         p_pctl_timing->trrd = (tmp&0xF);
2355         p_publ_timing->dtpr0.b.tRRD = tmp;
2356         p_noc_activate->b.Rrd = tmp;
2357         /*
2358          * tRTP, max(4 tCK,7.5ns)
2359          */
2360         tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2361         if(tmp < 4)
2362         {
2363             tmp = 4;
2364         }
2365         p_pctl_timing->trtp = tmp&0xF;
2366         p_publ_timing->dtpr0.b.tRTP = tmp;
2367         /*
2368          * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2369          */
2370         p_noc_timing->b.RdToMiss = (tmp+cl+cl-(bl>>1));
2371         /*
2372          * tWR, 15ns
2373          */
2374         tmp = ((DDR3_tWR*nMHz+999)/1000);
2375         p_pctl_timing->twr = tmp&0x1F;
2376         if(tmp<9)
2377         {
2378             tmp = tmp - 4;
2379         }
2380         else
2381         {
2382             tmp += (tmp&0x1) ? 1:0;
2383             tmp = tmp>>1;
2384         }
2385         bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2386         p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2387
2388         /*
2389          * tWTR, max(4 tCK,7.5ns)
2390          */
2391         tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2392         if(tmp < 4)
2393         {
2394             tmp = 4;
2395         }
2396         p_pctl_timing->twtr = tmp&0xF;
2397         p_publ_timing->dtpr0.b.tWTR = tmp;
2398         /*
2399          * WrToRd=WL+tWTR
2400          */
2401         p_noc_timing->b.WrToRd = (tmp+cwl);
2402         /*
2403          * tXP, max(3 tCK, 7.5ns)(<933MHz)
2404          */
2405         tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2406         if(tmp < 3)
2407         {
2408             tmp = 3;
2409         }
2410         p_pctl_timing->txp = tmp&0x7;
2411         /*
2412          * tXPDLL, max(10 tCK,24ns)
2413          */
2414         tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2415         if(tmp < 10)
2416         {
2417             tmp = 10;
2418         }
2419         p_pctl_timing->txpdll = tmp & 0x3F;
2420         p_publ_timing->dtpr2.b.tXP = tmp;
2421         /*
2422          * tZQCS, max(64 tCK, 80ns)
2423          */
2424         tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2425         if(tmp < 64)
2426         {
2427             tmp = 64;
2428         }
2429         p_pctl_timing->tzqcs = tmp&0x7F;
2430         /*
2431          * tZQCSI,
2432          */
2433         p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2434         /*
2435          * tDQS,
2436          */
2437         p_pctl_timing->tdqs = DDR3_tDQS;
2438         /*
2439          * tCKSRE, max(5 tCK, 10ns)
2440          */
2441         tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2442         if(tmp < 5)
2443         {
2444             tmp = 5;
2445         }
2446         p_pctl_timing->tcksre = tmp & 0x1F;
2447         /*
2448          * tCKSRX, max(5 tCK, 10ns)
2449          */
2450         p_pctl_timing->tcksrx = tmp & 0x1F;
2451         /*
2452          * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2453          */
2454         if(nMHz>=533)
2455         {
2456             tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2457         }
2458         else
2459         {
2460             tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2461         }
2462         if(tmp < 3)
2463         {
2464             tmp = 3;
2465         }
2466         p_pctl_timing->tcke = tmp & 0x7;
2467         /*
2468          * tCKESR, =tCKE + 1tCK
2469          */
2470         p_pctl_timing->tckesr = (tmp+1)&0xF;
2471         p_publ_timing->dtpr2.b.tCKE = tmp+1;
2472         /*
2473          * tMOD, max(12 tCK,15ns)
2474          */
2475         tmp = ((DDR3_tMOD*nMHz+999)/1000);
2476         if(tmp < 12)
2477         {
2478             tmp = 12;
2479         }
2480         p_pctl_timing->tmod = tmp&0x1F;
2481         p_publ_timing->dtpr1.b.tMOD = (tmp-12);
2482         /*
2483          * tRSTL, 100ns
2484          */
2485         p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2486         /*
2487          * tZQCL, max(256 tCK, 320ns)
2488          */
2489         tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2490         if(tmp < 256)
2491         {
2492             tmp = 256;
2493         }
2494         p_pctl_timing->tzqcl = tmp&0x3FF;
2495         /*
2496          * tMRR, 0 tCK
2497          */
2498         p_pctl_timing->tmrr = 0;
2499         /*
2500          * tDPD, 0
2501          */
2502         p_pctl_timing->tdpd = 0;
2503
2504         /**************************************************
2505          * PHY Timing
2506          **************************************************/
2507         /*
2508          * tCCD, BL/2 for DDR2 and 4 for DDR3
2509          */
2510         p_publ_timing->dtpr0.b.tCCD = 0;
2511         /*
2512          * tDQSCKmax,5.5ns
2513          */
2514         p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2515         /*
2516          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2517          *         1:ODT may not be turned on until one clock after the read post-amble
2518          */
2519         p_publ_timing->dtpr1.b.tRTODT = 1;
2520         /*
2521          * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page)   50ns(533MHz 2KB page)
2522          */
2523         tmp = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000);
2524         p_publ_timing->dtpr1.b.tFAW = tmp;
2525         p_noc_activate->b.Fawbank = 1;
2526         p_noc_activate->b.Faw = tmp;
2527         /*
2528          * tAOND_tAOFD
2529          */
2530         p_publ_timing->dtpr1.b.tAOND = 0;
2531         /*
2532          * tDLLK,512 tCK
2533          */
2534         p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2535         /**************************************************
2536          * NOC Timing
2537          **************************************************/
2538         p_noc_timing->b.BurstLen = (bl>>1);
2539     }
2540     else if(mem_type == LPDDR2)
2541     {
2542         #define LPDDR2_tREFI_3_9_us    (39)  //unit 100ns
2543         #define LPDDR2_tREFI_7_8_us    (78)  //unit 100ns
2544         #define LPDDR2_tMRD            (5)   //tCK
2545         #define LPDDR2_tRFC_8Gb        (210)  //ns
2546         #define LPDDR2_tRFC_4Gb        (130)  //ns
2547         #define LPDDR2_tRPpb_4_BANK             (24)  //ns
2548         #define LPDDR2_tRPab_SUB_tRPpb_4_BANK   (0)   //ns
2549         #define LPDDR2_tRPpb_8_BANK             (24)  //ns
2550         #define LPDDR2_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2551         #define LPDDR2_tRTW          (1)   //tCK register min valid value
2552         #define LPDDR2_tRAS          (42)  //ns
2553         #define LPDDR2_tRCD          (24)  //ns
2554         #define LPDDR2_tRRD          (10)  //ns
2555         #define LPDDR2_tRTP          (7)   //ns
2556         #define LPDDR2_tWR           (15)  //ns
2557         #define LPDDR2_tWTR_GREAT_200MHz         (7)  //ns
2558         #define LPDDR2_tWTR_LITTLE_200MHz        (10) //ns
2559         #define LPDDR2_tXP           (7)  //ns
2560         #define LPDDR2_tXPDLL        (0)
2561         #define LPDDR2_tZQCS         (90) //ns
2562         #define LPDDR2_tZQCSI        (0)
2563         #define LPDDR2_tDQS          (1)
2564         #define LPDDR2_tCKSRE        (1)  //tCK
2565         #define LPDDR2_tCKSRX        (2)  //tCK
2566         #define LPDDR2_tCKE          (3)  //tCK
2567         #define LPDDR2_tMOD          (0)
2568         #define LPDDR2_tRSTL         (0)
2569         #define LPDDR2_tZQCL         (360)  //ns
2570         #define LPDDR2_tMRR          (2)    //tCK
2571         #define LPDDR2_tCKESR        (15)   //ns
2572         #define LPDDR2_tDPD_US       (500)  //us
2573         #define LPDDR2_tFAW_GREAT_200MHz    (50)  //ns
2574         #define LPDDR2_tFAW_LITTLE_200MHz   (60)  //ns
2575         #define LPDDR2_tDLLK         (2)  //tCK
2576         #define LPDDR2_tDQSCK_MAX    (3)  //tCK
2577         #define LPDDR2_tDQSCK_MIN    (0)  //tCK
2578         #define LPDDR2_tDQSS         (1)  //tCK
2579
2580         uint32 trp_tmp;
2581         uint32 trcd_tmp;
2582         uint32 tras_tmp;
2583         uint32 trtp_tmp;
2584         uint32 twr_tmp;
2585
2586         al = 0;
2587         bl = 8;
2588         /*     1066 933 800 667 533 400 333
2589          * RL,   8   7   6   5   4   3   3
2590          * WL,   4   4   3   2   2   1   1
2591          */
2592         if(nMHz<=200)
2593         {
2594             cl = 3;
2595             cwl = 1;
2596             p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2597         }
2598         else if(nMHz<=266)
2599         {
2600             cl = 4;
2601             cwl = 2;
2602             p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2603         }
2604         else if(nMHz<=333)
2605         {
2606             cl = 5;
2607             cwl = 2;
2608             p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2609         }
2610         else if(nMHz<=400)
2611         {
2612             cl = 6;
2613             cwl = 3;
2614             p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2615         }
2616         else if(nMHz<=466)
2617         {
2618             cl = 7;
2619             cwl = 4;
2620             p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2621         }
2622         else //(nMHz<=1066)
2623         {
2624             cl = 8;
2625             cwl = 4;
2626             p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2627         }
2628         p_publ_timing->mr[3] = LPDDR2_DS_34;
2629         p_publ_timing->mr[0] = 0;
2630         /**************************************************
2631          * PCTL Timing
2632          **************************************************/
2633         /*
2634          * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2635          */
2636         if(ddr_capability_per_die >= 0x10000000)   // 2Gb
2637         {
2638             p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2639         }
2640         else
2641         {
2642             p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2643         }
2644
2645         /*
2646          * tMRD, (=tMRW), 5 tCK
2647          */
2648         p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2649         p_publ_timing->dtpr0.b.tMRD = 3;
2650         /*
2651          * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2652          */
2653         if(ddr_capability_per_die >= 0x40000000)   // 8Gb
2654         {
2655             p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2656             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000);
2657             /*
2658              * tXSR, max(2tCK,tRFC+10ns)
2659              */
2660             tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
2661         }
2662         else
2663         {
2664             p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2665             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000);
2666             tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
2667         }
2668         if(tmp<2)
2669         {
2670             tmp=2;
2671         }
2672         p_pctl_timing->texsr = tmp&0x3FF;
2673         p_publ_timing->dtpr2.b.tXS = tmp;
2674
2675         /*
2676          * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
2677          */
2678         //if(pPHY_Reg->DCR.b.DDR8BNK)
2679         if(1)
2680         {
2681             trp_tmp = ((LPDDR2_tRPpb_8_BANK*nMHz+999)/1000);
2682             if(trp_tmp<3)
2683             {
2684                 trp_tmp=3;
2685             }
2686             p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
2687         }
2688         else
2689         {
2690             trp_tmp = ((LPDDR2_tRPpb_4_BANK*nMHz+999)/1000);
2691             if(trp_tmp<3)
2692             {
2693                 trp_tmp=3;
2694             }
2695             p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
2696         }
2697         p_publ_timing->dtpr0.b.tRP = trp_tmp;
2698         /*
2699          * tRAS, max(3tCK,42ns)
2700          */
2701         tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
2702         if(tras_tmp<3)
2703         {
2704             tras_tmp=3;
2705         }
2706         p_pctl_timing->tras = (tras_tmp&0x3F);
2707         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
2708
2709         /*
2710          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
2711          */
2712         trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
2713         if(trcd_tmp<3)
2714         {
2715             trcd_tmp=3;
2716         }
2717         p_pctl_timing->trcd = (trcd_tmp&0xF);
2718         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
2719
2720         /*
2721          * tRTP, max(2tCK, 7.5ns)
2722          */
2723         trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2724         if(trtp_tmp<2)
2725         {
2726             trtp_tmp = 2;
2727         }
2728         p_pctl_timing->trtp = trtp_tmp&0xF;
2729         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
2730
2731         /*
2732          * tWR, max(3tCK,15ns)
2733          */
2734         twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
2735         if(twr_tmp<3)
2736         {
2737             twr_tmp=3;
2738         }
2739         p_pctl_timing->twr = twr_tmp&0x1F;
2740         bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2741         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
2742
2743         /*
2744          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2745          */
2746         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
2747         /*
2748          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2749          */
2750         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
2751         /*
2752          * tRC=tRAS+tRP
2753          */
2754         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
2755         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
2756         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
2757
2758         /*
2759          * RdToWr=(cl+2-cwl)
2760          */
2761         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
2762         p_publ_timing->dtpr1.b.tRTW = 0;
2763         p_noc_timing->b.RdToWr = (cl+2-cwl);
2764         p_pctl_timing->tal = al;
2765         p_pctl_timing->tcl = cl;
2766         p_pctl_timing->tcwl = cwl;
2767         /*
2768          * tRRD, max(2tCK,10ns)
2769          */
2770         tmp=((LPDDR2_tRRD*nMHz+999)/1000);
2771         if(tmp<2)
2772         {
2773             tmp=2;
2774         }
2775         p_pctl_timing->trrd = (tmp&0xF);
2776         p_publ_timing->dtpr0.b.tRRD = tmp;
2777         p_noc_activate->b.Rrd = tmp;
2778         /*
2779          * tWTR, max(2tCK, 7.5ns(533-266MHz)  10ns(200-166MHz))
2780          */
2781         if(nMHz > 200)
2782         {
2783             tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2784         }
2785         else
2786         {
2787             tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2788         }
2789         if(tmp<2)
2790         {
2791             tmp=2;
2792         }
2793         p_pctl_timing->twtr = tmp&0xF;
2794         p_publ_timing->dtpr0.b.tWTR = tmp;
2795         /*
2796          * WrToRd=WL+tWTR
2797          */
2798         p_noc_timing->b.WrToRd = (cwl+tmp);
2799         /*
2800          * tXP, max(2tCK,7.5ns)
2801          */
2802         tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
2803         if(tmp<2)
2804         {
2805             tmp=2;
2806         }
2807         p_pctl_timing->txp = tmp&0x7;
2808         p_publ_timing->dtpr2.b.tXP = tmp;
2809         /*
2810          * tXPDLL, 0ns
2811          */
2812         p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2813         /*
2814          * tZQCS, 90ns
2815          */
2816         p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2817         /*
2818          * tZQCSI,
2819          */
2820         //if(pDDR_Reg->MCFG &= lpddr2_s4)
2821         if(1)
2822         {
2823             p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2824         }
2825         else
2826         {
2827             p_pctl_timing->tzqcsi = 0;
2828         }
2829         /*
2830          * tDQS,
2831          */
2832         p_pctl_timing->tdqs = LPDDR2_tDQS;
2833         /*
2834          * tCKSRE, 1 tCK
2835          */
2836         p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2837         /*
2838          * tCKSRX, 2 tCK
2839          */
2840         p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2841         /*
2842          * tCKE, 3 tCK
2843          */
2844         p_pctl_timing->tcke = LPDDR2_tCKE;
2845         p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2846         /*
2847          * tMOD, 0 tCK
2848          */
2849         p_pctl_timing->tmod = LPDDR2_tMOD;
2850         p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2851         /*
2852          * tRSTL, 0 tCK
2853          */
2854         p_pctl_timing->trstl = LPDDR2_tRSTL;
2855         /*
2856          * tZQCL, 360ns
2857          */
2858         p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2859         /*
2860          * tMRR, 2 tCK
2861          */
2862         p_pctl_timing->tmrr = LPDDR2_tMRR;
2863         /*
2864          * tCKESR, max(3tCK,15ns)
2865          */
2866         tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
2867         if(tmp < 3)
2868         {
2869             tmp = 3;
2870         }
2871         p_pctl_timing->tckesr = tmp&0xF;
2872         /*
2873          * tDPD, 500us
2874          */
2875         p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2876
2877         /**************************************************
2878          * PHY Timing
2879          **************************************************/
2880         /*
2881          * tCCD, BL/2 for DDR2 and 4 for DDR3
2882          */
2883         p_publ_timing->dtpr0.b.tCCD = 0;
2884         /*
2885          * tDQSCKmax,5.5ns
2886          */
2887         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2888         /*
2889          * tDQSCKmin,2.5ns
2890          */
2891         p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2892         /*
2893          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2894          *         1:ODT may not be turned on until one clock after the read post-amble
2895          */
2896         p_publ_timing->dtpr1.b.tRTODT = 1;
2897         /*
2898          * tFAW,max(8tCK, 50ns(200-533MHz)  60ns(166MHz))
2899          */
2900         if(nMHz>=200)
2901         {
2902             tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
2903         }
2904         else
2905         {
2906             tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
2907         }
2908         if(tmp<8)
2909         {
2910             tmp=8;
2911         }
2912         p_publ_timing->dtpr1.b.tFAW = tmp;
2913         p_noc_activate->b.Fawbank = 1;
2914         p_noc_activate->b.Faw = tmp;
2915         /*
2916          * tAOND_tAOFD
2917          */
2918         p_publ_timing->dtpr1.b.tAOND = 0;
2919         /*
2920          * tDLLK,0
2921          */
2922         p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2923         /**************************************************
2924          * NOC Timing
2925          **************************************************/
2926         p_noc_timing->b.BurstLen = (bl>>1);
2927     }
2928     else if(mem_type == LPDDR3)
2929     {
2930         #define LPDDR3_tREFI_3_9_us    (39)  //unit 100ns
2931         #define LPDDR3_tMRD            (10)   //tCK
2932         #define LPDDR3_tRFC_8Gb        (210)  //ns
2933         #define LPDDR3_tRFC_4Gb        (130)  //ns
2934         #define LPDDR3_tRPpb_8_BANK             (24)  //ns
2935         #define LPDDR3_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2936         #define LPDDR3_tRTW          (1)   //tCK register min valid value
2937         #define LPDDR3_tRAS          (42)  //ns
2938         #define LPDDR3_tRCD          (24)  //ns
2939         #define LPDDR3_tRRD          (10)  //ns
2940         #define LPDDR3_tRTP          (7)   //ns
2941         #define LPDDR3_tWR           (15)  //ns
2942         #define LPDDR3_tWTR          (7)  //ns
2943         #define LPDDR3_tXP           (7)  //ns
2944         #define LPDDR3_tXPDLL        (0)
2945         #define LPDDR3_tZQCS         (90) //ns
2946         #define LPDDR3_tZQCSI        (0)
2947         #define LPDDR3_tDQS          (1)
2948         #define LPDDR3_tCKSRE        (2)  //tCK
2949         #define LPDDR3_tCKSRX        (2)  //tCK
2950         #define LPDDR3_tCKE          (3)  //tCK
2951         #define LPDDR3_tMOD          (0)
2952         #define LPDDR3_tRSTL         (0)
2953         #define LPDDR3_tZQCL         (360)  //ns
2954         #define LPDDR3_tMRR          (4)    //tCK
2955         #define LPDDR3_tCKESR        (15)   //ns
2956         #define LPDDR3_tDPD_US       (500)   //us
2957         #define LPDDR3_tFAW          (50)  //ns
2958         #define LPDDR3_tDLLK         (2)  //tCK
2959         #define LPDDR3_tDQSCK_MAX    (3)  //tCK
2960         #define LPDDR3_tDQSCK_MIN    (0)  //tCK
2961         #define LPDDR3_tDQSS         (1)  //tCK
2962
2963         uint32 trp_tmp;
2964         uint32 trcd_tmp;
2965         uint32 tras_tmp;
2966         uint32 trtp_tmp;
2967         uint32 twr_tmp;
2968
2969         al = 0;
2970         bl = 8;
2971         /* Only support Write Latency Set A here
2972          *     1066 933 800 733 667 600 533 400 166
2973          * RL,   16  14  12  11  10  9   8   6   3
2974          * WL,   8   8   6   6   6   5   4   3   1
2975          */
2976         if(nMHz<=166)
2977         {
2978             cl = 3;
2979             cwl = 1;
2980             p_publ_timing->mr[2] = LPDDR3_RL3_WL1;
2981         }
2982         else if(nMHz<=400)
2983         {
2984             cl = 6;
2985             cwl = 3;
2986             p_publ_timing->mr[2] = LPDDR3_RL6_WL3;
2987         }
2988         else if(nMHz<=533)
2989         {
2990             cl = 8;
2991             cwl = 4;
2992             p_publ_timing->mr[2] = LPDDR3_RL8_WL4;
2993         }
2994         else if(nMHz<=600)
2995         {
2996             cl = 9;
2997             cwl = 5;
2998             p_publ_timing->mr[2] = LPDDR3_RL9_WL5;
2999         }
3000         else if(nMHz<=667)
3001         {
3002             cl = 10;
3003             cwl = 6;
3004             p_publ_timing->mr[2] = LPDDR3_RL10_WL6;
3005         }
3006         else if(nMHz<=733)
3007         {
3008             cl = 11;
3009             cwl = 6;
3010             p_publ_timing->mr[2] = LPDDR3_RL11_WL6;
3011         }
3012         else if(nMHz<=800)
3013         {
3014             cl = 12;
3015             cwl = 6;
3016             p_publ_timing->mr[2] = LPDDR3_RL12_WL6;
3017         }
3018         else if(nMHz<=933)
3019         {
3020             cl = 14;
3021             cwl = 8;
3022             p_publ_timing->mr[2] = LPDDR3_RL14_WL8;
3023         }
3024         else //(nMHz<=1066)
3025         {
3026             cl = 16;
3027             cwl = 8;
3028             p_publ_timing->mr[2] = LPDDR3_RL16_WL8;
3029         }
3030         p_publ_timing->mr[3] = LPDDR3_DS_34;
3031         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
3032         {
3033             p_publ_timing->mr11 = LPDDR3_ODT_DIS;
3034         }
3035         else
3036         {
3037             p_publ_timing->mr11 = LPDDR3_ODT_240;
3038         }
3039         p_publ_timing->mr[0] = 0;
3040         /**************************************************
3041          * PCTL Timing
3042          **************************************************/
3043         /*
3044          * tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb)
3045          */
3046         p_pctl_timing->trefi = LPDDR3_tREFI_3_9_us;
3047
3048         /*
3049          * tMRD, (=tMRW), 10 tCK
3050          */
3051         p_pctl_timing->tmrd = LPDDR3_tMRD & 0x7;
3052         p_publ_timing->dtpr0.b.tMRD = 3;  //max value
3053         /*
3054          * tRFC, 130ns(4Gb) 210ns(>4Gb)
3055          */
3056         if(ddr_capability_per_die > 0x20000000)   // >4Gb
3057         {
3058             p_pctl_timing->trfc = (LPDDR3_tRFC_8Gb*nMHz+999)/1000;
3059             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_8Gb*nMHz+999)/1000);
3060             /*
3061              * tXSR, max(2tCK,tRFC+10ns)
3062              */
3063             tmp=(((LPDDR3_tRFC_8Gb+10)*nMHz+999)/1000);
3064         }
3065         else
3066         {
3067             p_pctl_timing->trfc = (LPDDR3_tRFC_4Gb*nMHz+999)/1000;
3068             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_4Gb*nMHz+999)/1000);
3069             tmp=(((LPDDR3_tRFC_4Gb+10)*nMHz+999)/1000);
3070         }
3071         if(tmp<2)
3072         {
3073             tmp=2;
3074         }
3075         p_pctl_timing->texsr = tmp&0x3FF;
3076         p_publ_timing->dtpr2.b.tXS = tmp;
3077
3078         /*
3079          * tRP, max(3tCK, 18ns(Fast) 21ns(Typ) 27ns(Slow))
3080          */
3081         //if(pPHY_Reg->DCR.b.DDR8BNK)
3082         if(1)
3083         {
3084             trp_tmp = ((LPDDR3_tRPpb_8_BANK*nMHz+999)/1000);
3085             if(trp_tmp<3)
3086             {
3087                 trp_tmp=3;
3088             }
3089             p_pctl_timing->trp = ((((LPDDR3_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
3090         }
3091         p_publ_timing->dtpr0.b.tRP = trp_tmp;
3092         /*
3093          * tRAS, max(3tCK,42ns)
3094          */
3095         tras_tmp=((LPDDR3_tRAS*nMHz+999)/1000);
3096         if(tras_tmp<3)
3097         {
3098             tras_tmp=3;
3099         }
3100         p_pctl_timing->tras = (tras_tmp&0x3F);
3101         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
3102
3103         /*
3104          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
3105          */
3106         trcd_tmp = ((LPDDR3_tRCD*nMHz+999)/1000);
3107         if(trcd_tmp<3)
3108         {
3109             trcd_tmp=3;
3110         }
3111         p_pctl_timing->trcd = (trcd_tmp&0xF);
3112         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
3113
3114         /*
3115          * tRTP, max(4tCK, 7.5ns)
3116          */
3117         trtp_tmp = ((LPDDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
3118         if(trtp_tmp<4)
3119         {
3120             trtp_tmp = 4;
3121         }
3122         p_pctl_timing->trtp = trtp_tmp&0xF;
3123         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
3124
3125         /*
3126          * tWR, max(4tCK,15ns)
3127          */
3128         twr_tmp=((LPDDR3_tWR*nMHz+999)/1000);
3129         if(twr_tmp<4)
3130         {
3131             twr_tmp=4;
3132         }
3133         p_pctl_timing->twr = twr_tmp&0x1F;
3134         bl_tmp = LPDDR3_BL8;
3135         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
3136
3137         /*
3138          * WrToMiss=WL*tCK + tWR + tRP + tRCD
3139          */
3140         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
3141         /*
3142          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
3143          */
3144         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
3145         /*
3146          * tRC=tRAS+tRP
3147          */
3148         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
3149         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
3150         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
3151
3152         /*
3153          * RdToWr=(cl+2-cwl)
3154          */
3155         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
3156         p_publ_timing->dtpr1.b.tRTW = 0;
3157         p_noc_timing->b.RdToWr = (cl+2-cwl);
3158         p_pctl_timing->tal = al;
3159         p_pctl_timing->tcl = cl;
3160         p_pctl_timing->tcwl = cwl;
3161         /*
3162          * tRRD, max(2tCK,10ns)
3163          */
3164         tmp=((LPDDR3_tRRD*nMHz+999)/1000);
3165         if(tmp<2)
3166         {
3167             tmp=2;
3168         }
3169         p_pctl_timing->trrd = (tmp&0xF);
3170         p_publ_timing->dtpr0.b.tRRD = tmp;
3171         p_noc_activate->b.Rrd = tmp;
3172         /*
3173          * tWTR, max(4tCK, 7.5ns)
3174          */
3175         tmp=((LPDDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
3176         if(tmp<4)
3177         {
3178             tmp=4;
3179         }
3180         p_pctl_timing->twtr = tmp&0xF;
3181         p_publ_timing->dtpr0.b.tWTR = tmp;
3182         /*
3183          * WrToRd=WL+tWTR
3184          */
3185         p_noc_timing->b.WrToRd = (cwl+tmp);
3186         /*
3187          * tXP, max(3tCK,7.5ns)
3188          */
3189         tmp=((LPDDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
3190         if(tmp<3)
3191         {
3192             tmp=3;
3193         }
3194         p_pctl_timing->txp = tmp&0x7;
3195         p_publ_timing->dtpr2.b.tXP = tmp;
3196         /*
3197          * tXPDLL, 0ns
3198          */
3199         p_pctl_timing->txpdll = LPDDR3_tXPDLL;
3200         /*
3201          * tZQCS, 90ns
3202          */
3203         p_pctl_timing->tzqcs = ((LPDDR3_tZQCS*nMHz+999)/1000)&0x7F;
3204         /*
3205          * tZQCSI,
3206          */
3207         p_pctl_timing->tzqcsi = LPDDR3_tZQCSI;
3208         /*
3209          * tDQS,
3210          */
3211         p_pctl_timing->tdqs = LPDDR3_tDQS;
3212         /*
3213          * tCKSRE=tCPDED, 2 tCK
3214          */
3215         p_pctl_timing->tcksre = LPDDR3_tCKSRE;
3216         /*
3217          * tCKSRX, 2 tCK
3218          */
3219         p_pctl_timing->tcksrx = LPDDR3_tCKSRX;
3220         /*
3221          * tCKE, (max 7.5ns,3 tCK)
3222          */
3223         tmp=((7*nMHz+(nMHz>>1)+999)/1000);
3224         if(tmp<LPDDR3_tCKE)
3225         {
3226             tmp=LPDDR3_tCKE;
3227         }
3228         p_pctl_timing->tcke = tmp;
3229         p_publ_timing->dtpr2.b.tCKE = tmp;
3230         /*
3231          * tMOD, 0 tCK
3232          */
3233         p_pctl_timing->tmod = LPDDR3_tMOD;
3234         p_publ_timing->dtpr1.b.tMOD = LPDDR3_tMOD;
3235         /*
3236          * tRSTL, 0 tCK
3237          */
3238         p_pctl_timing->trstl = LPDDR3_tRSTL;
3239         /*
3240          * tZQCL, 360ns
3241          */
3242         p_pctl_timing->tzqcl = ((LPDDR3_tZQCL*nMHz+999)/1000)&0x3FF;
3243         /*
3244          * tMRR, 4 tCK
3245          */
3246         p_pctl_timing->tmrr = LPDDR3_tMRR;
3247         /*
3248          * tCKESR, max(3tCK,15ns)
3249          */
3250         tmp = ((LPDDR3_tCKESR*nMHz+999)/1000);
3251         if(tmp < 3)
3252         {
3253             tmp = 3;
3254         }
3255         p_pctl_timing->tckesr = tmp&0xF;
3256         /*
3257          * tDPD, 500us
3258          */
3259         p_pctl_timing->tdpd = LPDDR3_tDPD_US;
3260
3261         /**************************************************
3262          * PHY Timing
3263          **************************************************/
3264         /*
3265          * tCCD, BL/2 for DDR2 and 4 for DDR3
3266          */
3267         p_publ_timing->dtpr0.b.tCCD = 0;
3268         /*
3269          * tDQSCKmax,5.5ns
3270          */
3271         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR3_tDQSCK_MAX;
3272         /*
3273          * tDQSCKmin,2.5ns
3274          */
3275         p_publ_timing->dtpr1.b.tDQSCK = LPDDR3_tDQSCK_MIN;
3276         /*
3277          * tRTODT, 0:ODT may be turned on immediately after read post-amble
3278          *         1:ODT may not be turned on until one clock after the read post-amble
3279          */
3280         p_publ_timing->dtpr1.b.tRTODT = 1;
3281         /*
3282          * tFAW,max(8tCK, 50ns)
3283          */
3284         tmp=((LPDDR3_tFAW*nMHz+999)/1000);
3285         if(tmp<8)
3286         {
3287             tmp=8;
3288         }
3289         p_publ_timing->dtpr1.b.tFAW = tmp;
3290         p_noc_activate->b.Fawbank = 1;
3291         p_noc_activate->b.Faw = tmp;
3292         /*
3293          * tAOND_tAOFD
3294          */
3295         p_publ_timing->dtpr1.b.tAOND = 0;
3296         /*
3297          * tDLLK,0
3298          */
3299         p_publ_timing->dtpr2.b.tDLLK = LPDDR3_tDLLK;
3300         /**************************************************
3301          * NOC Timing
3302          **************************************************/
3303         p_noc_timing->b.BurstLen = (bl>>1);
3304     }
3305
3306 out:
3307     return ret;
3308 }
3309
3310 static uint32 __sramfunc ddr_update_timing(uint32 ch)
3311 {
3312     uint32 i,bl_tmp=0;
3313     PCTL_TIMING_T *p_pctl_timing=&(DATA(ddr_reg).pctl.pctl_timing);
3314     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3315     volatile NOC_TIMING_T  *p_noc_timing=&(DATA(ddr_reg).noc[0].ddrtiming);
3316     volatile NOC_ACTIVATE_T  *p_noc_activate=&(DATA(ddr_reg).noc[0].activate);
3317     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3318     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3319     pMSCH_REG     pMSCH_Reg= DATA(ddr_ch[ch]).pMSCH_Reg;
3320
3321     FUNC(ddr_copy)((uint64_t *)&(pDDR_Reg->TOGCNT1U), (uint64_t*)&(p_pctl_timing->togcnt1u), 17);
3322     pPHY_Reg->DTPR[0] = p_publ_timing->dtpr0.d32;
3323     pPHY_Reg->DTPR[1] = p_publ_timing->dtpr1.d32;
3324     pPHY_Reg->DTPR[2] = p_publ_timing->dtpr2.d32;
3325     pMSCH_Reg->ddrtiming.d32 = (pMSCH_Reg->ddrtiming.b.BwRatio) | p_noc_timing->d32;
3326     pMSCH_Reg->activate.d32 = p_noc_activate->d32;
3327     // Update PCTL BL
3328     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3329     {
3330         bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3331         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
3332         if(DATA(ddr_freq) <= DDR3_DDR2_DLL_DISABLE_FREQ)
3333         {
3334             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-3;
3335         }
3336         else
3337         {
3338             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-2;
3339         }
3340         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL-1;
3341     }
3342     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3343     {
3344         if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
3345         {
3346             bl_tmp = mddr_lpddr2_bl_8;
3347         }
3348         else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3349         {
3350             bl_tmp = mddr_lpddr2_bl_4;
3351         }
3352         else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
3353         {
3354             bl_tmp = mddr_lpddr2_bl_16;
3355         }
3356         if((DATA(ddr_freq)>=200)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3357         {
3358             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3359         }
3360         else
3361         {
3362             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
3363         }
3364         i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
3365         pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8);  //tDQSCKmax-tDQSCK
3366         pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-1;
3367         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL;
3368     }
3369
3370     return 0;
3371 }
3372
3373 static uint32 __sramfunc ddr_update_mr(uint32 ch)
3374 {
3375     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3376     uint32         cs,dll_off;
3377     pDDRPHY_REG_T  pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3378
3379     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3380     dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
3381     FUNC(ddr_copy)((uint64_t *)&(pPHY_Reg->MR[0]), (uint64_t*)&(p_publ_timing->mr[0]), 2);
3382     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3383     {
3384         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
3385         if(DATA(ddr_freq)>DDR3_DDR2_DLL_DISABLE_FREQ)
3386         {
3387             if(dll_off)  // off -> on
3388             {
3389                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));  //DLL enable
3390                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET));  //DLL reset
3391                 ddr_delayus(1);  //at least 200 DDR cycle
3392                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3393             }
3394             else // on -> on
3395             {
3396                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
3397                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3398             }
3399         }
3400         else
3401         {
3402             pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3403             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));  //DLL disable
3404             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3405         }
3406     }
3407     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3408     {
3409         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
3410         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
3411         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
3412         if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3413         {
3414             ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(11) | lpddr2_op((p_publ_timing->mr11)));
3415         }
3416     }
3417     else //mDDR
3418     {
3419         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3420         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
3421     }
3422     return 0;
3423 }
3424
3425 static void __sramfunc ddr_update_odt(uint32 ch)
3426 {
3427     uint32        cs,tmp;
3428     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3429     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3430
3431     //adjust DRV and ODT
3432     if((DATA(ddr_ch[ch]).mem_type == DDR3) || (DATA(ddr_ch[ch]).mem_type == LPDDR3))
3433     {
3434         if(DATA(ddr_freq) <= DDR3_DDR2_ODT_DISABLE_FREQ)
3435         {
3436             pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3437             pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3438             if(!(pDDR_Reg->PPCFG & 1))
3439             {
3440                 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3441                 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3442             }
3443         }
3444         else
3445         {
3446             pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9);  //dynamic RTT enable
3447             pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
3448             if(!(pDDR_Reg->PPCFG & 1))
3449             {
3450                 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
3451                 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
3452             }
3453         }
3454     }
3455     else
3456     {
3457         pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3458         pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3459         if(!(pDDR_Reg->PPCFG & 1))
3460         {
3461             pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3462             pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3463         }
3464     }
3465     if(DATA(ddr_ch[ch]).mem_type == LPDDR2)
3466     {
3467         tmp = GET_LPDDR2_DS_ODT();  //DS=34ohm,ODT=171ohm
3468     }
3469     else if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3470     {
3471         tmp = GET_LPDDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3472     }
3473     else
3474     {
3475         tmp = GET_DDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3476     }
3477     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3478     if(cs > 1)
3479     {
3480         pPHY_Reg->ZQ1CR[0] = tmp;
3481         dsb();
3482     }
3483     pPHY_Reg->ZQ0CR[0] = tmp;
3484     dsb();
3485 }
3486
3487 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
3488 {
3489     uint32 ch;
3490     pDDR_REG_T    pDDR_Reg;
3491     pDDRPHY_REG_T pPHY_Reg;
3492
3493     for(ch=0;ch<CH_MAX;ch++)
3494     {
3495         pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3496         pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3497
3498         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3499         {
3500             ddr_move_to_Lowpower_state(ch);
3501             pDDR_Reg->TZQCSI = 0;
3502         }
3503     }
3504 }
3505
3506 #if defined(CONFIG_ARCH_RK3066B)
3507 static __sramdata uint32 data8_dqstr[25][4];
3508 static __sramdata uint32 min_ddr_freq,dqstr_flag=false;
3509
3510 int ddr_get_datatraing_value_3168(bool end_flag,uint32 dqstr_value,uint32 min_freq)
3511 {
3512     if(end_flag == true)
3513     {
3514         dqstr_flag = true;    //complete learn data training value flag
3515         min_ddr_freq = min_freq;
3516         return 0;
3517     }
3518
3519     data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3520     data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3521     data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3522     data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3523
3524     ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3525         clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3526         data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3527     return 0;
3528 }
3529
3530 static void __sramfunc ddr_set_pll_enter_3168(uint32 freq_slew)
3531 {
3532     uint32 value_1u,value_100n;
3533     ddr_move_to_Config_state();
3534
3535     if(freq_slew == 1)
3536     {
3537         value_100n = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3538         value_1u = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3539         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3540         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3541         ddr_update_timing();
3542         ddr_update_mr();
3543         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = value_100n;
3544         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = value_1u;
3545     }
3546     else
3547     {
3548         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3549         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3550     }
3551
3552     pDDR_Reg->TZQCSI = 0;
3553     ddr_move_to_Lowpower_state();
3554
3555     ddr_set_dll_bypass(0);  //dll bypass
3556     SET_DDRPHY_CLKGATE(ch,1);  //disable DDR PHY clock
3557     dsb();
3558 }
3559
3560 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32 dqstr_value)
3561 {
3562     SET_DDRPHY_CLKGATE(ch,0);  //enable DDR PHY clock
3563     dsb();
3564     ddr_set_dll_bypass(DATA(ddr_freq));
3565     ddr_reset_dll();
3566
3567     if(dqstr_flag==true)
3568     {
3569         pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3570         pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3571         pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3572         pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3573     }
3574
3575     ddr_update_odt();
3576     ddr_move_to_Config_state();
3577     if(freq_slew == 1)
3578     {
3579         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3580         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3581         pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl.pctl_timing.tzqcsi;
3582     }
3583     else
3584     {
3585         ddr_update_timing();
3586         ddr_update_mr();
3587     }
3588     ddr_data_training();
3589     ddr_move_to_Access_state();
3590 }
3591 #endif
3592
3593 static void __sramfunc ddr_chb_update_timing_odt(void)
3594 {
3595     ddr_set_dll_bypass(1,0); //always use dll bypass
3596     ddr_update_timing(1);
3597     ddr_update_odt(1);
3598 }
3599
3600 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3601 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew,uint32 dqstr_value)
3602 {
3603     uint32 n,ch;
3604     uint32 cs[CH_MAX];
3605
3606     /** 2. ddr enter self-refresh mode or precharge power-down mode */
3607     idle_port();
3608 #if defined(CONFIG_ARCH_RK3066B)
3609     ddr_set_pll_enter_3168(freq_slew);
3610 #else
3611     ddr_selfrefresh_enter(freq);
3612 #endif
3613
3614     /** 3. change frequence  */
3615     FUNC(ddr_set_pll)(freq,1);
3616     DATA(ddr_freq) = freq;
3617
3618     /** 5. Issues a Mode Exit command   */
3619 #if defined(CONFIG_ARCH_RK3066B)
3620     ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3621 #else
3622     //ddr_selfrefresh_exit();
3623     if(DATA(ddr_ch[1]).mem_type != DRAM_MAX)
3624     {
3625         ddr_chb_update_timing_odt();
3626     }
3627     ddr_set_dll_bypass(0,0); //always use dll bypass
3628     ddr_update_timing(0);
3629     ddr_update_odt(0);
3630     FUNC(ddr_set_pll)(freq,2);
3631     for(ch=0;ch<CH_MAX;ch++)
3632     {
3633         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3634         {
3635             ddr_set_dll_bypass(ch,DATA(ddr_freq));
3636             ddr_reset_dll(ch);
3637             //ddr_delayus(10);   //wait DLL lock
3638
3639             ddr_move_to_Config_state(ch);
3640             ddr_update_mr(ch);
3641             cs[ch] = ddr_data_training_trigger(ch);
3642         }
3643     }
3644     for(ch=0;ch<CH_MAX;ch++)
3645     {
3646         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3647         {
3648             n = ddr_data_training(ch,cs[ch]);
3649             ddr_move_to_Access_state(ch);
3650             if(n!=0)
3651             {
3652                 sram_printascii("DTT failed!\n");
3653             }
3654         }
3655     }
3656 #endif
3657     deidle_port();
3658     dsb();
3659 }
3660
3661 struct ddr_change_freq_sram_param {
3662     uint32 arm_freq;
3663     uint32 freq;
3664     uint32 freq_slew;
3665     uint32 dqstr_value;
3666 };
3667
3668 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
3669 {
3670     struct ddr_change_freq_sram_param *param = arg;
3671     loops_per_us = LPJ_100MHZ * param->arm_freq / 1000000;
3672     /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3673     ddr_SRE_2_SRX(param->freq, param->freq_slew, param->dqstr_value);
3674 }
3675 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
3676
3677 typedef struct freq_tag{
3678     uint32_t nMHz;
3679     struct ddr_freq_t *p_ddr_freq_t;
3680 }freq_t;
3681
3682 static noinline uint32 ddr_change_freq_sram(void *arg)
3683 {
3684     uint32 freq;
3685     uint32 freq_slew=0;
3686     uint32 dqstr_value=0;
3687     unsigned long flags;
3688     struct ddr_change_freq_sram_param param;
3689     volatile uint32 n;
3690     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3691     uint32 i;
3692     uint32 gpllvaluel;
3693     freq_t *p_freq_t=(freq_t *)arg;
3694     uint32 nMHz=p_freq_t->nMHz;
3695         static struct rk_screen screen;
3696         static int dclk_div, down_dclk_div;
3697
3698 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3699     struct ddr_freq_t *p_ddr_freq_t=p_freq_t->p_ddr_freq_t;
3700 #endif
3701
3702 #if defined(CONFIG_ARCH_RK3066B)
3703     if(dqstr_flag==true)
3704     {
3705         dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
3706         freq_slew = (nMHz>ddr_freq)? 1 : 0;
3707     }
3708 #endif
3709         if (!screen.mode.pixclock) {
3710                 rk_fb_get_prmry_screen(&screen);
3711                 if (screen.lcdc_id == 0)
3712                         dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(27)) >> 8) & 0xff;
3713                 else if (screen.lcdc_id == 1)
3714                         dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(29)) >> 8) & 0xff;
3715                 down_dclk_div = 64*(dclk_div+1)-1;
3716         }
3717     param.arm_freq = ddr_get_pll_freq(APLL);
3718     gpllvaluel = ddr_get_pll_freq(GPLL);
3719     if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3720     {
3721         if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3722         {
3723             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 4;
3724         }
3725         else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3726         {
3727             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 2;
3728         }
3729         else        //200-400MHz  /1:200MHz-400MHz
3730         {
3731             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 1;
3732         }
3733     }
3734     else
3735     {
3736         ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3737     }
3738     freq=p_ddr_set_pll(nMHz,0);
3739
3740     ddr_get_parameter(freq);
3741
3742     /** 1. Make sure there is no host access */
3743     local_irq_save(flags);
3744     local_fiq_disable();
3745     flush_tlb_all();
3746     isb();
3747
3748 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3749     if(p_ddr_freq_t->screen_ft_us > 0)
3750     {
3751         p_ddr_freq_t->t1 = cpu_clock(0);
3752         p_ddr_freq_t->t2 = (uint32)(p_ddr_freq_t->t1 - p_ddr_freq_t->t0);   //ns
3753
3754         //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
3755         if( (p_ddr_freq_t->t2 > p_ddr_freq_t->screen_ft_us*1000) && (p_ddr_freq_t->screen_ft_us != 0xfefefefe))
3756         {
3757             freq = 0;
3758             goto end;
3759         }
3760         else
3761         {
3762              rk_fb_poll_wait_frame_complete();
3763         }
3764     }
3765 #endif
3766     for(i=0;i<SRAM_SIZE/4096;i++)
3767     {
3768         n=temp[1024*i];
3769         barrier();
3770     }
3771
3772     for(i=0;i<CH_MAX;i++)
3773     {
3774         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3775         {
3776             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3777             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3778             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3779         }
3780     }
3781     n= pCRU_Reg->CRU_PLL_CON[0][0];
3782     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3783     n= READ_GRF_REG();
3784     dsb();
3785
3786     param.freq = freq;
3787     param.freq_slew = freq_slew;
3788     param.dqstr_value = dqstr_value;
3789         rk_fb_set_prmry_screen_status(SCREEN_PREPARE_DDR_CHANGE);
3790         if (screen.lcdc_id == 0)
3791                 cru_writel(0 | CRU_W_MSK_SETBITS(down_dclk_div, 8, 0xff),
3792                            RK3288_CRU_CLKSELS_CON(27));
3793         else if (screen.lcdc_id == 1)
3794                 cru_writel(0 | CRU_W_MSK_SETBITS(down_dclk_div, 8, 0xff),
3795                            RK3288_CRU_CLKSELS_CON(29));
3796
3797     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
3798                     &param,
3799                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
3800
3801         if (screen.lcdc_id == 0)
3802                 cru_writel(0 | CRU_W_MSK_SETBITS(dclk_div, 8, 0xff),
3803                 RK3288_CRU_CLKSELS_CON(27));
3804         else if (screen.lcdc_id == 1)
3805                 cru_writel(0 | CRU_W_MSK_SETBITS(dclk_div, 8, 0xff),
3806                 RK3288_CRU_CLKSELS_CON(29));
3807         rk_fb_set_prmry_screen_status(SCREEN_UNPREPARE_DDR_CHANGE);
3808
3809 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3810 end:
3811 #endif
3812     local_fiq_enable();
3813     local_irq_restore(flags);
3814     return freq;
3815 }
3816
3817 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
3818 static uint32 ddr_change_freq_gpll_dpll(uint32 nMHz)
3819 {
3820     uint32 gpll_freq,gpll_div;
3821     struct ddr_freq_t ddr_freq_t;
3822     ddr_freq_t.screen_ft_us = 0;
3823
3824     if(true == ddr_rk3188_dpll_is_good)
3825     {
3826         gpllvaluel = ddr_get_pll_freq(GPLL);
3827
3828         if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3829         {
3830             gpll_div = (gpllvaluel+nMHz-1)/nMHz;
3831             if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3832             {
3833                 gpll_freq = gpllvaluel/4;
3834                 gpll_div = 4;
3835             }
3836             else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3837             {
3838                 gpll_freq = gpllvaluel/2;
3839                 gpll_div = 2;
3840             }
3841             else        //200-400MHz  /1:200MHz-400MHz
3842             {
3843                 gpll_freq = gpllvaluel;
3844                 gpll_div = 1;
3845             }
3846
3847             *p_ddr_select_gpll_div=gpll_div;    //select GPLL
3848             ddr_change_freq_sram(gpll_freq,ddr_freq_t);
3849             *p_ddr_select_gpll_div=0;
3850
3851             p_ddr_set_pll(nMHz,0); //count DPLL
3852             p_ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3853         }
3854         else
3855         {
3856             ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3857         }
3858     }
3859
3860     return ddr_change_freq_sram(nMHz,ddr_freq_t);
3861
3862 }
3863 #endif
3864
3865 bool DEFINE_PIE_DATA(cpu_pause[NR_CPUS]);
3866 volatile bool *DATA(p_cpu_pause);
3867 static inline bool is_cpu0_paused(unsigned int cpu) { smp_rmb(); return DATA(cpu_pause)[0]; }
3868 static inline void set_cpuX_paused(unsigned int cpu, bool pause) { DATA(cpu_pause)[cpu] = pause; smp_wmb(); }
3869 static inline bool is_cpuX_paused(unsigned int cpu) { smp_rmb(); return DATA(p_cpu_pause)[cpu]; }
3870 static inline void set_cpu0_paused(bool pause) { DATA(p_cpu_pause)[0] = pause; smp_wmb();}
3871
3872 /* Do not use stack, safe on SMP */
3873 void PIE_FUNC(_pause_cpu)(void *arg)
3874 {
3875     unsigned int cpu = (unsigned int)arg;
3876
3877     set_cpuX_paused(cpu, true);
3878     while (is_cpu0_paused(cpu));
3879     set_cpuX_paused(cpu, false);
3880 }
3881
3882 static void pause_cpu(void *info)
3883 {
3884     unsigned int cpu = raw_smp_processor_id();
3885
3886     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(_pause_cpu)),
3887             (void *)cpu,
3888             rockchip_sram_stack-(cpu-1)*PAUSE_CPU_STACK_SIZE);
3889 }
3890
3891 static void wait_cpu(void *info)
3892 {
3893 }
3894
3895 static int call_with_single_cpu(u32 (*fn)(void *arg), void *arg)
3896 {
3897         s64 now_ns, timeout_ns;
3898         unsigned int cpu;
3899         unsigned int this_cpu = smp_processor_id();
3900         int ret = 0;
3901
3902         cpu_maps_update_begin();
3903         local_bh_disable();
3904
3905         /* It should take much less than 1s to pause the cpus. It typically
3906         * takes around 20us. */
3907         timeout_ns = ktime_to_ns(ktime_add_ns(ktime_get(), NSEC_PER_SEC));
3908         now_ns = ktime_to_ns(ktime_get());
3909         set_cpu0_paused(true);
3910         smp_call_function((smp_call_func_t)pause_cpu, NULL, 0);
3911         for_each_online_cpu(cpu) {
3912                 if (cpu == this_cpu)
3913                         continue;
3914                 while (!is_cpuX_paused(cpu) && (now_ns < timeout_ns))
3915                         now_ns = ktime_to_ns(ktime_get());
3916                 if (now_ns >= timeout_ns) {
3917                         pr_err("pause cpu %d timeout\n", cpu);
3918                         ret = -EPERM;
3919                         goto out;
3920                 }
3921         }
3922         ret = fn(arg);
3923 out:
3924         set_cpu0_paused(false);
3925         local_bh_enable();
3926         smp_call_function(wait_cpu, NULL, true);
3927         cpu_maps_update_done();
3928
3929         return ret;
3930 }
3931
3932 void PIE_FUNC(ddr_adjust_config)(void *arg)
3933 {
3934     uint32 value[CH_MAX];
3935     uint32 ch;
3936     pDDR_REG_T    pDDR_Reg;
3937     pDDRPHY_REG_T pPHY_Reg;
3938
3939     for(ch=0;ch<CH_MAX;ch++)
3940     {
3941         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3942         {
3943             value[ch] = ((uint32 *)arg)[ch];
3944             pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3945             pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3946
3947             //enter config state
3948             ddr_move_to_Config_state(ch);
3949
3950             //set data training address
3951             pPHY_Reg->DTAR = value[ch];
3952
3953             //set auto power down idle
3954             pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
3955
3956             //CKDV=00
3957             pPHY_Reg->PGCR &= ~(0x3<<12);
3958
3959             //enable the hardware low-power interface
3960             pDDR_Reg->SCFG.b.hw_low_power_en = 1;
3961
3962             if(pDDR_Reg->PPCFG & 1)
3963             {
3964                 pPHY_Reg->DATX8[2].DXGCR &= ~(1);          //disable byte
3965                 pPHY_Reg->DATX8[3].DXGCR &= ~(1);
3966                 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;  //disable DLL
3967                 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
3968             }
3969
3970             ddr_update_odt(ch);
3971
3972             //enter access state
3973             ddr_move_to_Access_state(ch);
3974         }
3975     }
3976 }
3977 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
3978
3979 static uint32 _ddr_adjust_config(void *dtar)
3980 {
3981     uint32 i;
3982     unsigned long flags;
3983     volatile uint32 n;
3984     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3985
3986      /** 1. Make sure there is no host access */
3987     local_irq_save(flags);
3988     local_fiq_disable();
3989     flush_tlb_all();
3990     isb();
3991
3992     for(i=0;i<SRAM_SIZE/4096;i++)
3993     {
3994         n=temp[1024*i];
3995         barrier();
3996     }
3997     for(i=0;i<CH_MAX;i++)
3998     {
3999         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
4000         {
4001             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
4002             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
4003             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
4004         }
4005     }
4006     n= pCRU_Reg->CRU_PLL_CON[0][0];
4007     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
4008     n= READ_GRF_REG();
4009     dsb();
4010
4011     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
4012                     (void *)dtar,
4013                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
4014     local_fiq_enable();
4015     local_irq_restore(flags);
4016     return 0;
4017 }
4018
4019 static void ddr_adjust_config(void)
4020 {
4021     uint32 dtar[CH_MAX];
4022     uint32 i;
4023
4024     //get data training address before idle port
4025     ddr_get_datatraing_addr(dtar);
4026
4027     call_with_single_cpu(&_ddr_adjust_config, (void*)dtar);
4028     //_ddr_adjust_config(dtar);
4029     //disable unused channel
4030     for(i=0;i<CH_MAX;i++)
4031     {
4032         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
4033         {
4034             //FIXME
4035         }
4036     }
4037 }
4038
4039 static int __ddr_change_freq(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
4040 {
4041     freq_t freq;
4042     int ret = 0;
4043
4044     freq.nMHz = nMHz;
4045     freq.p_ddr_freq_t = &ddr_freq_t;
4046     ret = call_with_single_cpu(&ddr_change_freq_sram,
4047                                (void*)&freq);
4048
4049     return ret;
4050 }
4051
4052 static int _ddr_change_freq(uint32 nMHz)
4053 {
4054         struct ddr_freq_t ddr_freq_t;
4055         #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
4056         unsigned long remain_t, vblank_t, pass_t;
4057         static unsigned long reserve_t = 800;//us
4058         unsigned long long tmp;
4059         int test_count=0;
4060         #endif
4061         int ret;
4062
4063         memset(&ddr_freq_t, 0x00, sizeof(ddr_freq_t));
4064
4065 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
4066         do
4067         {
4068                 ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
4069                 ddr_freq_t.t0 = rk_fb_get_prmry_screen_framedone_t();
4070                 if (!ddr_freq_t.screen_ft_us)
4071                         return __ddr_change_freq(nMHz, ddr_freq_t);
4072
4073                 tmp = cpu_clock(0) - ddr_freq_t.t0;
4074                 do_div(tmp, 1000);
4075                 pass_t = tmp;
4076                 //lost frame interrupt
4077                 while (pass_t > ddr_freq_t.screen_ft_us){
4078                         int n = pass_t/ddr_freq_t.screen_ft_us;
4079
4080                         //printk("lost frame int, pass_t:%lu\n", pass_t);
4081                         pass_t -= n*ddr_freq_t.screen_ft_us;
4082                         ddr_freq_t.t0 += n*ddr_freq_t.screen_ft_us*1000;
4083                 }
4084
4085                 remain_t = ddr_freq_t.screen_ft_us - pass_t;
4086                 if (remain_t < reserve_t) {
4087                         //printk("remain_t(%lu) < reserve_t(%lu)\n", remain_t, reserve_t);
4088                         vblank_t = rk_fb_get_prmry_screen_vbt();
4089                         usleep_range(remain_t+vblank_t, remain_t+vblank_t);
4090                         continue;
4091                 }
4092
4093                 //test 10 times
4094                 test_count++;
4095                 if(test_count > 10)
4096                 {
4097                         ddr_freq_t.screen_ft_us = 0xfefefefe;
4098                 }
4099                 //printk("ft:%lu, pass_t:%lu, remaint_t:%lu, reservet_t:%lu\n",
4100                 //      ddr_freq_t.screen_ft_us, (unsigned long)pass_t, remain_t, reserve_t);
4101                 usleep_range(remain_t-reserve_t, remain_t-reserve_t);
4102                 flush_tlb_all();
4103
4104                 ret = __ddr_change_freq(nMHz, ddr_freq_t);
4105                 if (ret) {
4106                         reserve_t = 800;
4107                         return ret;
4108                 } else {
4109                         if (reserve_t < 3000)
4110                                 reserve_t += 200;
4111                 }
4112         }while(1);
4113 #else
4114         ret = __ddr_change_freq(nMHz, ddr_freq_t);
4115 #endif
4116
4117         return ret;
4118 }
4119
4120 static long _ddr_round_rate(uint32 nMHz)
4121 {
4122         return p_ddr_set_pll(nMHz, 0);
4123 }
4124
4125 static void _ddr_set_auto_self_refresh(bool en)
4126 {
4127     //set auto self-refresh idle
4128     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
4129 }
4130
4131 #define PERI_ACLK_DIV_MASK 0x1f
4132 #define PERI_ACLK_DIV_OFF 0
4133
4134 #define PERI_HCLK_DIV_MASK 0x3
4135 #define PERI_HCLK_DIV_OFF 8
4136
4137 #define PERI_PCLK_DIV_MASK 0x3
4138 #define PERI_PCLK_DIV_OFF 12
4139 #if 0
4140 static __sramdata u32 cru_sel32_sram;
4141 static void __sramfunc ddr_suspend(void)
4142 {
4143     u32 i;
4144     volatile u32 n;
4145     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
4146     int pll_id;
4147
4148         pll_id=GET_DDR_PLL_SRC();
4149     /** 1. Make sure there is no host access */
4150     flush_cache_all();
4151     outer_flush_all();
4152     //flush_tlb_all();
4153
4154     for(i=0;i<SRAM_SIZE/4096;i++)
4155     {
4156         n=temp[1024*i];
4157         barrier();
4158     }
4159
4160     n= pDDR_Reg->SCFG.d32;
4161     n= pPHY_Reg->RIDR;
4162     n= pCRU_Reg->CRU_PLL_CON[0][0];
4163     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
4164     n= *(volatile uint32_t *)SysSrv_DdrConf;
4165     n= READ_GRF_REG();
4166     dsb();
4167
4168     ddr_selfrefresh_enter(0);
4169
4170     SET_PLL_MODE(pll_id, 0);   //PLL slow-mode
4171     dsb();
4172     ddr_delayus(1);
4173     SET_PLL_PD(pll_id, 1);         //PLL power-down
4174     dsb();
4175     ddr_delayus(1);
4176     if(pll_id==GPLL)
4177     {
4178         cru_sel32_sram=   pCRU_Reg->CRU_CLKSEL_CON[10];
4179
4180         pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
4181                                    | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
4182                                    |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
4183     }
4184     pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29)));  //CKOE
4185 }
4186
4187 static void __sramfunc ddr_resume(void)
4188 {
4189     int delay=1000;
4190     int pll_id;
4191
4192     pll_id=GET_DDR_PLL_SRC();
4193         pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29));  //CKOE
4194         dsb();
4195
4196         if(pll_id==GPLL)
4197         pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
4198
4199     SET_PLL_PD(pll_id, 0);         //PLL no power-down
4200     dsb();
4201     while (delay > 0)
4202     {
4203         if (GET_DPLL_LOCK_STATUS())
4204             break;
4205         ddr_delayus(1);
4206         delay--;
4207     }
4208
4209     SET_PLL_MODE(pll_id, 1);   //PLL normal
4210     dsb();
4211
4212     ddr_selfrefresh_exit();
4213 }
4214 #endif
4215
4216 //pArg:Ö¸ÕëÄÚÈÝ±íÊ¾pll pd or not¡£
4217 void ddr_reg_save(uint32 *pArg)
4218 {
4219     uint32        ch;
4220     pDDR_REG_T    pDDR_Reg=NULL;
4221     pDDRPHY_REG_T pPHY_Reg=NULL;
4222     pMSCH_REG     pMSCH_Reg;
4223
4224     p_ddr_reg->tag = 0x56313031;
4225     if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4226     {
4227         p_ddr_reg->pctlAddr[0] = RK3288_DDR_PCTL0_PHYS;
4228         p_ddr_reg->publAddr[0] = RK3288_DDR_PUBL0_PHYS;
4229         p_ddr_reg->nocAddr[0] = RK3288_SERVICE_BUS_PHYS;
4230         pDDR_Reg = p_ddr_ch[0]->pDDR_Reg;
4231         pPHY_Reg = p_ddr_ch[0]->pPHY_Reg;
4232     }
4233     else
4234     {
4235         p_ddr_reg->pctlAddr[0] = 0xFFFFFFFF;
4236         p_ddr_reg->publAddr[0] = 0xFFFFFFFF;
4237         p_ddr_reg->nocAddr[0] = 0xFFFFFFFF;
4238     }
4239     if(p_ddr_ch[1]->mem_type != DRAM_MAX)
4240     {
4241         p_ddr_reg->pctlAddr[1] = RK3288_DDR_PCTL1_PHYS;
4242         p_ddr_reg->publAddr[1] = RK3288_DDR_PUBL1_PHYS;
4243         p_ddr_reg->nocAddr[1] = RK3288_SERVICE_BUS_PHYS+0x80;
4244         if((pDDR_Reg == NULL) || (pPHY_Reg == NULL))
4245         {
4246             pDDR_Reg = p_ddr_ch[1]->pDDR_Reg;
4247             pPHY_Reg = p_ddr_ch[1]->pPHY_Reg;
4248         }
4249     }
4250     else
4251     {
4252         p_ddr_reg->pctlAddr[1] = 0xFFFFFFFF;
4253         p_ddr_reg->publAddr[1] = 0xFFFFFFFF;
4254         p_ddr_reg->nocAddr[1] = 0xFFFFFFFF;
4255     }
4256
4257     //PCTLR
4258     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->pctl.pctl_timing.togcnt1u), (uint64_t *)&(pDDR_Reg->TOGCNT1U), 17);
4259     p_ddr_reg->pctl.SCFG = pDDR_Reg->SCFG.d32;
4260     p_ddr_reg->pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
4261     p_ddr_reg->pctl.MCFG1 = pDDR_Reg->MCFG1;
4262     p_ddr_reg->pctl.MCFG = pDDR_Reg->MCFG;
4263     p_ddr_reg->pctl.pctl_timing.ddrFreq = *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
4264     p_ddr_reg->pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
4265     p_ddr_reg->pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
4266     p_ddr_reg->pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
4267     p_ddr_reg->pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
4268     p_ddr_reg->pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
4269     p_ddr_reg->pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
4270     p_ddr_reg->pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
4271     p_ddr_reg->pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
4272     p_ddr_reg->pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
4273     p_ddr_reg->pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
4274     p_ddr_reg->pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
4275     p_ddr_reg->pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
4276     p_ddr_reg->pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
4277     p_ddr_reg->pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
4278     p_ddr_reg->pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
4279
4280     p_ddr_reg->pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
4281     p_ddr_reg->pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
4282     p_ddr_reg->pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
4283     p_ddr_reg->pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
4284     p_ddr_reg->pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
4285     p_ddr_reg->pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
4286     p_ddr_reg->pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
4287     p_ddr_reg->pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
4288     p_ddr_reg->pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
4289
4290     //PUBL
4291     p_ddr_reg->publ.phy_timing.dtpr0.d32 = pPHY_Reg->DTPR[0];
4292     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->publ.phy_timing.dtpr1), (uint64_t *)&(pPHY_Reg->DTPR[1]), 3);
4293     p_ddr_reg->publ.PIR = pPHY_Reg->PIR;
4294     p_ddr_reg->publ.PGCR = pPHY_Reg->PGCR;
4295     p_ddr_reg->publ.DLLGCR = pPHY_Reg->DLLGCR;
4296     p_ddr_reg->publ.ACDLLCR = pPHY_Reg->ACDLLCR;
4297     p_ddr_reg->publ.PTR[0] = pPHY_Reg->PTR[0];
4298     p_ddr_reg->publ.PTR[1] = pPHY_Reg->PTR[1];
4299     p_ddr_reg->publ.PTR[2] = pPHY_Reg->PTR[2];
4300     p_ddr_reg->publ.ACIOCR = pPHY_Reg->ACIOCR;
4301     p_ddr_reg->publ.DXCCR = pPHY_Reg->DXCCR;
4302     p_ddr_reg->publ.DSGCR = pPHY_Reg->DSGCR;
4303     p_ddr_reg->publ.DCR = pPHY_Reg->DCR.d32;
4304     p_ddr_reg->publ.ODTCR = pPHY_Reg->ODTCR;
4305     p_ddr_reg->publ.DTAR = pPHY_Reg->DTAR;
4306     p_ddr_reg->publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
4307     p_ddr_reg->publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
4308
4309     for(ch=0;ch<CH_MAX;ch++)
4310     {
4311         if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4312         {
4313             pPHY_Reg = p_ddr_ch[ch]->pPHY_Reg;
4314             p_ddr_reg->dqs[ch].DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
4315             p_ddr_reg->dqs[ch].DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
4316             p_ddr_reg->dqs[ch].DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
4317             p_ddr_reg->dqs[ch].DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
4318
4319             p_ddr_reg->dqs[ch].DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
4320             p_ddr_reg->dqs[ch].DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
4321             p_ddr_reg->dqs[ch].DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
4322             p_ddr_reg->dqs[ch].DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
4323
4324             p_ddr_reg->dqs[ch].DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
4325             p_ddr_reg->dqs[ch].DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
4326             p_ddr_reg->dqs[ch].DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
4327             p_ddr_reg->dqs[ch].DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
4328
4329             p_ddr_reg->dqs[ch].DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
4330             p_ddr_reg->dqs[ch].DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
4331             p_ddr_reg->dqs[ch].DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
4332             p_ddr_reg->dqs[ch].DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
4333
4334             //NOC
4335             pMSCH_Reg= p_ddr_ch[ch]->pMSCH_Reg;
4336             p_ddr_reg->noc[ch].ddrconf = pMSCH_Reg->ddrconf;
4337             p_ddr_reg->noc[ch].ddrtiming.d32 = pMSCH_Reg->ddrtiming.d32;
4338             p_ddr_reg->noc[ch].ddrmode = pMSCH_Reg->ddrmode;
4339             p_ddr_reg->noc[ch].readlatency = pMSCH_Reg->readlatency;
4340             p_ddr_reg->noc[ch].activate.d32 = pMSCH_Reg->activate.d32;
4341             p_ddr_reg->noc[ch].devtodev = pMSCH_Reg->devtodev;
4342         }
4343     }
4344
4345     //PLLPD
4346     p_ddr_reg->pllpdAddr = (uint32_t)pArg;  //pll power-down tag addr
4347     p_ddr_reg->pllpdMask = 1;
4348     p_ddr_reg->pllpdVal = 1;
4349
4350     //DPLL
4351     p_ddr_reg->dpllmodeAddr = RK3288_CRU_PHYS + 0x50;  //APCRU_MODE_CON
4352     p_ddr_reg->dpllSlowMode = ((3<<4)<<16) | (0<<4);
4353     p_ddr_reg->dpllNormalMode = ((3<<4)<<16) | (1<<4);
4354     p_ddr_reg->dpllResetAddr = RK3288_CRU_PHYS + 0x1c; //APCRU_DPLL_CON3
4355     p_ddr_reg->dpllReset = (((0x1<<5)<<16) | (0x1<<5));
4356     p_ddr_reg->dpllDeReset = (((0x1<<5)<<16) | (0x0<<5));
4357     p_ddr_reg->dpllConAddr = RK3288_CRU_PHYS + 0x10;   //APCRU_DPLL_CON0
4358     p_ddr_reg->dpllCon[0] = pCRU_Reg->CRU_PLL_CON[DPLL][0] | (0xFFFF<<16);
4359     p_ddr_reg->dpllCon[1] = pCRU_Reg->CRU_PLL_CON[DPLL][1] | (0xFFFF<<16);
4360     p_ddr_reg->dpllCon[2] = pCRU_Reg->CRU_PLL_CON[DPLL][2] | (0xFFFF<<16);
4361     p_ddr_reg->dpllCon[3] = pCRU_Reg->CRU_PLL_CON[DPLL][3] | (0xFFFF<<16);
4362     p_ddr_reg->dpllLockAddr = RK3288_GRF_PHYS + 0x284;  //GRF_SOC_STATUS1
4363     p_ddr_reg->dpllLockMask = (1<<5);
4364     p_ddr_reg->dpllLockVal = (1<<5);
4365
4366     //SET_DDR_PLL_SRC
4367     p_ddr_reg->ddrPllSrcDivAddr = RK3288_CRU_PHYS + 0xc8;
4368     p_ddr_reg->ddrPllSrcDiv = (pCRU_Reg->CRU_CLKSEL_CON[26] & 0x7) | (0x7<<16);
4369
4370     p_ddr_reg->retenDisAddr = RK3288_PMU_PHYS+0x18;  //pmu_pwrmode_con
4371     p_ddr_reg->retenDisVal = (3<<21);  //OR operation
4372     p_ddr_reg->retenStAddr = RK3288_PMU_PHYS+0x1c;  //pmu_pwrmode_con
4373     p_ddr_reg->retenStMask = (1<<6);
4374     p_ddr_reg->retenStVal = (0<<6);
4375
4376     p_ddr_reg->grfRegCnt = 3;
4377     //DDR_16BIT,DDR_HW_WAKEUP,DDR_TYPE
4378     p_ddr_reg->grf[0].addr = RK3288_GRF_PHYS + 0x244;
4379     p_ddr_reg->grf[0].val = (pGRF_Reg->GRF_SOC_CON[0] & ((0x3<<8)|(0x3<<5)|(0x3<<3))) | (((0x3<<8)|(0x3<<5)|(0x3<<3))<<16);
4380
4381     //LPDDR_TYPE
4382     p_ddr_reg->grf[1].addr = RK3288_GRF_PHYS + 0x24c;
4383     p_ddr_reg->grf[1].val = (pGRF_Reg->GRF_SOC_CON[2] & (0x3f<<8)) | ((0x3f<<8)<<16);
4384
4385     //STRIDE
4386     p_ddr_reg->grf[2].addr = RK3288_SGRF_PHYS + 0x8;
4387     p_ddr_reg->grf[2].val = READ_DDR_STRIDE() | (0x1F<<16);
4388
4389     p_ddr_reg->endTag = 0xFFFFFFFF;
4390 }
4391
4392 __attribute__((aligned(4)))   uint32 ddr_reg_resume[]=
4393 {
4394 #include "ddr_reg_resume.inc"
4395 };
4396
4397 char * ddr_get_resume_code_info(u32 *size)
4398 {
4399     *size=sizeof(ddr_reg_resume);
4400
4401     return (char *)ddr_reg_resume;
4402
4403 }
4404 EXPORT_SYMBOL(ddr_get_resume_code_info);
4405
4406 char * ddr_get_resume_data_info(u32 *size)
4407 {
4408     *size=sizeof(DATA(ddr_reg));
4409     return (char *) kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4410 }
4411 EXPORT_SYMBOL(ddr_get_resume_data_info);
4412
4413 /**********************ddr bandwidth calc*********************/
4414 enum ddr_bandwidth_id {
4415         ddrbw_wr_num = 0,
4416         ddrbw_rd_num,
4417         ddrbw_act_num,
4418         ddrbw_time_num,
4419         ddrbw_eff,
4420         ddrbw_id_end
4421 };
4422
4423 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
4424 #define grf_writel(v, offset) \
4425         do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
4426
4427 #define noc_readl(offset)       readl_relaxed(RK3288_SERVICE_BUS_VIRT + offset)
4428 #define noc_writel(v, offset) \
4429         do { writel_relaxed(v, RK3288_SERVICE_BUS_VIRT + offset); \
4430                 dsb(); } while (0)
4431
4432 static void ddr_monitor_start(void)
4433 {
4434         int i;
4435
4436         for (i = 1; i < 8; i++) {
4437                 noc_writel(0x8, (0x400*i+0x8));
4438                 noc_writel(0x1, (0x400*i+0xc));
4439                 noc_writel(0x6, (0x400*i+0x138));
4440                 noc_writel(0x10, (0x400*i+0x14c));
4441                 noc_writel(0x8, (0x400*i+0x160));
4442                 noc_writel(0x10, (0x400*i+0x174));
4443         }
4444
4445         grf_writel((((readl_relaxed(RK_PMU_VIRT+0x9c)>>13)&7) == 3) ?
4446                         0xc000c000 : 0xe000e000, RK3288_GRF_SOC_CON4);
4447
4448         for (i = 1; i < 8; i++)
4449                 noc_writel(0x1, (0x400*i+0x28));
4450 }
4451
4452 static void ddr_monitor_stop(void)
4453 {
4454         grf_writel(0xc0000000, RK3288_GRF_SOC_CON4);
4455 }
4456
4457 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
4458                         struct ddr_bw_info *ddr_bw_ch1)
4459 {
4460         u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq;
4461         u64 temp64;
4462         int i, j;
4463
4464         ddr_monitor_stop();
4465         for (j = 0; j < 2; j++) {
4466                 for (i = 0; i < ddrbw_eff; i++)
4467                         ddr_bw_val[j][i] =
4468                                 grf_readl(RK3288_GRF_SOC_STATUS11+i*4+j*16);
4469         }
4470         if (!ddr_bw_val[0][ddrbw_time_num])
4471                 goto end;
4472
4473         if (ddr_bw_ch0) {
4474                 ddr_freq = readl_relaxed(RK_DDR_VIRT + 0xc0);
4475
4476                 temp64 = ((u64)ddr_bw_val[0][0]+ddr_bw_val[0][1])*4*100;
4477                 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
4478                 ddr_bw_val[0][ddrbw_eff] = temp64;
4479
4480                 ddr_bw_ch0->ddr_percent = temp64;
4481                 ddr_bw_ch0->ddr_time =
4482                         ddr_bw_val[0][ddrbw_time_num]/(ddr_freq*1000);
4483                 ddr_bw_ch0->ddr_wr =
4484                         (ddr_bw_val[0][ddrbw_wr_num]*8*4)*
4485                                 ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4486                 ddr_bw_ch0->ddr_rd =
4487                         (ddr_bw_val[0][ddrbw_rd_num]*8*4)*
4488                                 ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4489                 ddr_bw_ch0->ddr_act =
4490                         ddr_bw_val[0][ddrbw_act_num];
4491                 ddr_bw_ch0->ddr_total =
4492                         ddr_freq*2*4;
4493
4494                 ddr_bw_ch0->cpum = (noc_readl(0x400+0x178)<<16)
4495                         + (noc_readl(0x400+0x164));
4496                 ddr_bw_ch0->gpu = (noc_readl(0x800+0x178)<<16)
4497                         + (noc_readl(0x800+0x164));
4498                 ddr_bw_ch0->peri = (noc_readl(0xc00+0x178)<<16)
4499                         + (noc_readl(0xc00+0x164));
4500                 ddr_bw_ch0->video = (noc_readl(0x1000+0x178)<<16)
4501                         + (noc_readl(0x1000+0x164));
4502                 ddr_bw_ch0->vio0 = (noc_readl(0x1400+0x178)<<16)
4503                         + (noc_readl(0x1400+0x164));
4504                 ddr_bw_ch0->vio1 = (noc_readl(0x1800+0x178)<<16)
4505                         + (noc_readl(0x1800+0x164));
4506                 ddr_bw_ch0->vio2 = (noc_readl(0x1c00+0x178)<<16)
4507                         + (noc_readl(0x1c00+0x164));
4508
4509                 ddr_bw_ch0->cpum =
4510                         ddr_bw_ch0->cpum*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4511                 ddr_bw_ch0->gpu =
4512                         ddr_bw_ch0->gpu*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4513                 ddr_bw_ch0->peri =
4514                         ddr_bw_ch0->peri*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4515                 ddr_bw_ch0->video =
4516                         ddr_bw_ch0->video*
4517                                 ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4518                 ddr_bw_ch0->vio0 =
4519                         ddr_bw_ch0->vio0*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4520                 ddr_bw_ch0->vio1 =
4521                         ddr_bw_ch0->vio1*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4522                 ddr_bw_ch0->vio2 =
4523                         ddr_bw_ch0->vio2*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4524         }
4525 end:
4526         ddr_monitor_start();
4527 }
4528
4529 /******************************************************************/
4530
4531 static int ddr_init(uint32 dram_speed_bin, uint32 freq)
4532 {
4533     uint32 tmp;
4534     uint32 die=1;
4535     uint32 gsr,dqstr;
4536     struct clk *clk;
4537     uint32 ch,cap=0,cs_cap;
4538
4539     ddr_print("version 1.00 20150126 \n");
4540
4541     p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4542     p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
4543     DATA(p_cpu_pause) = kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
4544
4545     tmp = clk_get_rate(clk_get(NULL, "clk_ddr"))/1000000;
4546     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)) = tmp;
4547     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
4548
4549     for(ch=0;ch<CH_MAX;ch++)
4550     {
4551         p_ddr_ch[ch] = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_ch[ch]));
4552
4553         p_ddr_ch[ch]->chNum = ch;
4554         p_ddr_ch[ch]->pDDR_Reg = pDDR_REG(ch);
4555         p_ddr_ch[ch]->pPHY_Reg = pPHY_REG(ch);
4556         p_ddr_ch[ch]->pMSCH_Reg = pMSCH_REG(ch);
4557
4558         if(!(READ_CH_INFO()&(1<<ch)))
4559         {
4560             p_ddr_ch[ch]->mem_type = DRAM_MAX;
4561             continue;
4562         }
4563         else
4564         {
4565             if(ch)
4566             {
4567                 ddr_print("Channel b: \n");
4568             }
4569             else
4570             {
4571                 ddr_print("Channel a: \n");
4572             }
4573             tmp = p_ddr_ch[ch]->pPHY_Reg->DCR.b.DDRMD;
4574             if((tmp ==  LPDDR2) && (READ_DRAMTYPE_INFO() == 6))
4575             {
4576                 tmp = LPDDR3;
4577             }
4578             switch(tmp)
4579             {
4580                 case DDR3:
4581                     ddr_print("DDR3 Device\n");
4582                     break;
4583                 case LPDDR3:
4584                     ddr_print("LPDDR3 Device\n");
4585                     break;
4586                 case LPDDR2:
4587                     ddr_print("LPDDR2 Device\n");
4588                     break;
4589                 default:
4590                     ddr_print("Unkown Device\n");
4591                     tmp = DRAM_MAX;
4592                     break;
4593             }
4594             p_ddr_ch[ch]->mem_type = tmp;
4595             if(tmp == DRAM_MAX)
4596             {
4597                 p_ddr_ch[ch]->mem_type = DRAM_MAX;
4598                 continue;
4599             }
4600         }
4601
4602         p_ddr_ch[ch]->ddr_speed_bin = dram_speed_bin;
4603         //get capability per chip, not total size, used for calculate tRFC
4604         die = (8<<READ_BW_INFO(ch))/(8<<READ_DIE_BW_INFO(ch));
4605         cap = (1 << (READ_ROW_INFO(ch,0)+READ_COL_INFO(ch)+READ_BK_INFO(ch)+READ_BW_INFO(ch)));
4606         cs_cap = cap;
4607         if(READ_CS_INFO(ch) > 1)
4608         {
4609             cap += cap >> (READ_ROW_INFO(ch,0)-READ_ROW_INFO(ch,1));
4610         }
4611         if(READ_CH_ROW_INFO(ch))
4612         {
4613             cap = cap*3/4;
4614         }
4615         p_ddr_ch[ch]->ddr_capability_per_die = cs_cap/die;
4616         ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
4617                                                                         READ_BW_INFO(ch)*16,\
4618                                                                         READ_COL_INFO(ch), \
4619                                                                         (0x1<<(READ_BK_INFO(ch))), \
4620                                                                         READ_ROW_INFO(ch,0), \
4621                                                                         READ_CS_INFO(ch), \
4622                                                                         (cap>>20));
4623     }
4624
4625     ddr_adjust_config();
4626
4627     clk = clk_get(NULL, "clk_ddr");
4628     if (IS_ERR(clk)) {
4629         ddr_print("failed to get ddr clk\n");
4630         clk = NULL;
4631     }
4632     if(freq != 0)
4633         tmp = clk_set_rate(clk, 1000*1000*freq);
4634     else
4635         tmp = clk_set_rate(clk, clk_get_rate(clk));
4636     ddr_print("init success!!! freq=%luMHz\n", clk ? clk_get_rate(clk)/1000000 : freq);
4637
4638     for(ch=0;ch<CH_MAX;ch++)
4639     {
4640         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
4641         {
4642             if(ch)
4643             {
4644                 ddr_print("Channel b: \n");
4645             }
4646             else
4647             {
4648                 ddr_print("Channel a: \n");
4649             }
4650             for(tmp=0;tmp<4;tmp++)
4651             {
4652                 gsr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXGSR[0];
4653                 dqstr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXDQSTR;
4654                 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=%d,%d, DGSL=%d,%d extra clock, DGPS=%d,%d\n", \
4655                                                                     (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), \
4656                                                                     ((gsr>>13)&0x7), ((gsr>>16)&0x7),\
4657                                                                     (dqstr&0x7), ((dqstr>>3)&0x7),\
4658                                                                     ((((dqstr>>12)&0x3)+1)*90), ((((dqstr>>14)&0x3)+1)*90));
4659             }
4660             ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
4661                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
4662                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
4663                                                         p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]&0x3,\
4664                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
4665                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
4666                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>6)&0x3);
4667             ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
4668             ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
4669         }
4670     }
4671
4672     return 0;
4673 }
4674