arch/arm/mach-rockchip/ddr_rk32.c

   1 /*
   2  * Function Driver for DDR controller
   3  *
   4  * Copyright (C) 2011-2014 Fuzhou Rockchip Electronics Co.,Ltd
   5  * Author:
   6  * hcy@rock-chips.com
   7  * yk@rock-chips.com
   8  *
   9  * v1.00
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/tlbflush.h>
  19 #include <linux/cpu.h>
  20 #include <dt-bindings/clock/ddr.h>
  21 #include <linux/rockchip/cru.h>
  22 #include "cpu_axi.h"
  23
  24 typedef uint32_t uint32;
  25
  26 /***********************************
  27  * Global Control Macro
  28  ***********************************/
  29 //#define ENABLE_DDR_CLCOK_GPLL_PATH  //for RK3188
  30
  31 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)
  32 #define DDR3_DDR2_DLL_DISABLE_FREQ    (333)
  33 #define SR_IDLE                       (0x1)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
  34 #define PD_IDLE                       (0X40)  //unit:DDR clk cycle, and 0 for disable auto power-down
  35
  36 //#if (DDR3_DDR2_ODT_DISABLE_FREQ > DDR3_DDR2_DLL_DISABLE_FREQ)
  37 //#error
  38 //#endif
  39
  40 #define ddr_print(x...) printk( "DDR DEBUG: " x )
  41
  42 /***********************************
  43  * ARCH Relative Macro and Struction
  44  ***********************************/
  45 #define SRAM_CODE_OFFSET        rockchip_sram_virt
  46 #define SRAM_SIZE               rockchip_sram_size
  47
  48 /*
  49  * PMU
  50  */
  51 //PMU_PWRDN_ST
  52 #define pd_scu_pwr_st       (1<<11)
  53 #define pd_hevc_pwr_st      (1<<10)
  54 #define pd_gpu_pwr_st       (1<<9)
  55 #define pd_video_pwr_st     (1<<8)
  56 #define pd_vio_pwr_st       (1<<7)
  57 #define pd_peri_pwr_st      (1<<6)
  58 #define pd_bus_pwr_st      (1<<5)
  59 //PMU_IDLE_REQ
  60 #define idle_req_hevc_cfg   (1<<9)
  61 #define idle_req_cpup_cfg   (1<<8)
  62 #define idle_req_dma_cfg    (1<<7)
  63 #define idle_req_alive_cfg  (1<<6)
  64 #define idle_req_core_cfg   (1<<5)
  65 #define idle_req_vio_cfg    (1<<4)
  66 #define idle_req_video_cfg  (1<<3)
  67 #define idle_req_gpu_cfg    (1<<2)
  68 #define idle_req_peri_cfg   (1<<1)
  69 #define idle_req_bus_cfg    (1<<0)
  70
  71 //PMU_IDLE_ST
  72 #define idle_ack_hevc     (1<<25)
  73 #define idle_ack_cpup     (1<<24)
  74 #define idle_ack_dma      (1<<23)
  75 #define idle_ack_alive    (1<<22)
  76 #define idle_ack_core     (1<<21)
  77 #define idle_ack_vio      (1<<20)
  78 #define idle_ack_video    (1<<19)
  79 #define idle_ack_gpu      (1<<18)
  80 #define idle_ack_peir     (1<<17)
  81 #define idle_ack_bus      (1<<16)
  82
  83 #define idle_hevc   (1<<9)
  84 #define idle_cpup   (1<<8)
  85 #define idle_dma    (1<<7)
  86 #define idle_alive  (1<<6)
  87 #define idle_core   (1<<5)
  88 #define idle_vio    (1<<4)
  89 #define idle_video  (1<<3)
  90 #define idle_gpu    (1<<2)
  91 #define idle_peri   (1<<1)
  92 #define idle_bus    (1<<0)
  93
  94 //PMU_PWRMODE_CON
  95 /* ch=0, channel a
  96    ch=1, channel b
  97  */
  98 #define ddrio_ret_de_req(ch)  (1<<(21+(ch)))
  99 #define ddrc_gating_en(ch)    (1<<(19+(ch)))
 100 #define ddrio_ret_en(ch)      (1<<(17+(ch)))
 101 #define sref_enter_en(ch)     (1<<(15+(ch)))
 102
 103 //PMU_PWR_STATE
 104 #define SREF_EXIT             (1<<26)
 105 #define DDR_IO_PWRUP          (1<<25)
 106
 107 //PMU registers
 108 typedef volatile struct tagPMU_FILE
 109 {
 110     uint32 PMU_WAKEUP_CFG[2];
 111     uint32 PMU_PWRDN_CON;
 112     uint32 PMU_PWRDN_ST;
 113     uint32 PMU_IDLE_REQ;
 114     uint32 PMU_IDLE_ST;
 115     uint32 PMU_PWRMODE_CON;
 116     uint32 PMU_PWR_STATE;
 117     uint32 PMU_OSC_CNT;
 118     uint32 PMU_PLL_CNT;
 119     uint32 PMU_STABL_CNT;
 120     uint32 PMU_DDR0IO_PWRON_CNT;
 121     uint32 PMU_DDR1IO_PWRON_CNT;
 122     uint32 PMU_CORE_PWRDN_CNT;
 123     uint32 PMU_CORE_PWRUP_CNT;
 124     uint32 PMU_GPU_PWRDWN_CNT;
 125     uint32 PMU_GPU_PWRUP_CNT;
 126     uint32 PMU_WAKEUP_RST_CLR_CNT;
 127     uint32 PMU_SFT_CON;
 128     uint32 PMU_DDR_SREF_ST;
 129     uint32 PMU_INT_CON;
 130     uint32 PMU_INT_ST;
 131     uint32 PMU_BOOT_ADDR_SEL;
 132     uint32 PMU_GRF_CON;
 133     uint32 PMU_GPIO_SR;
 134     uint32 PMU_GPIO0_A_PULL;
 135     uint32 PMU_GPIO0_B_PULL;
 136     uint32 PMU_GPIO0_C_PULL;
 137     uint32 PMU_GPIO0_A_DRV;
 138     uint32 PMU_GPIO0_B_DRV;
 139     uint32 PMU_GPIO0_C_DRV;
 140     uint32 PMU_GPIO_OP;
 141     uint32 PMU_GPIO0_SEL18;
 142     uint32 PMU_GPIO0_A_IOMUX;
 143     uint32 PMU_GPIO0_B_IOMUX;
 144     uint32 PMU_GPIO0_C_IOMUX;
 145     uint32 PMU_GPIO0_D_IOMUX;
 146     uint32 PMU_PMU_SYS_REG[4];
 147 }PMU_FILE, *pPMU_FILE;
 148
 149 /*
 150  * CRU
 151  */
 152 typedef enum PLL_ID_Tag
 153 {
 154     APLL=0,
 155     DPLL,
 156     CPLL,
 157     GPLL,
 158     PLL_MAX
 159 }PLL_ID;
 160
 161 #define PLL_RESET  (((0x1<<5)<<16) | (0x1<<5))
 162 #define PLL_DE_RESET  (((0x1<<5)<<16) | (0x0<<5))
 163 #define NR(n)      ((0x3F<<(8+16)) | (((n)-1)<<8))
 164 #define NO(n)      ((0xF<<16) | ((n)-1))
 165 #define NF(n)      ((0x1FFF<<16) | ((n)-1))
 166 #define NB(n)      ((0xFFF<<16) | ((n)-1))
 167
 168  //CRU Registers
 169 typedef volatile struct tagCRU_STRUCT
 170 {
 171     uint32 CRU_PLL_CON[5][4];
 172     uint32 CRU_MODE_CON;
 173     uint32 reserved1[(0x60-0x54)/4];
 174     uint32 CRU_CLKSEL_CON[43];
 175     uint32 reserved2[(0x160-0x10c)/4];
 176     uint32 CRU_CLKGATE_CON[19];
 177     uint32 reserved3[(0x1b0-0x1ac)/4];
 178     uint32 CRU_GLB_SRST_FST_VALUE;
 179     uint32 CRU_GLB_SRST_SND_VALUE;
 180     uint32 CRU_SOFTRST_CON[12];
 181     uint32 CRU_MISC_CON;
 182     uint32 CRU_GLB_CNT_TH;
 183     uint32 CRU_TSADC_RST_CON;
 184     uint32 reserved4[(0x200-0x1f4)/4];
 185     uint32 CRU_SDMMC_CON[2];
 186     uint32 CRU_SDIO0_CON[2];
 187     uint32 CRU_SDIO1_CON[2];
 188     uint32 CRU_EMMC_CON[2];
 189     // other regigster unused in boot
 190 } CRU_REG, *pCRU_REG;
 191
 192 /*
 193  * GRF
 194  */
 195 //REG FILE registers
 196 typedef volatile struct tagREG_FILE
 197 {
 198     uint32 GRF_GPIO1A_IOMUX;
 199     uint32 GRF_GPIO1B_IOMUX;
 200     uint32 GRF_GPIO1C_IOMUX;
 201     uint32 GRF_GPIO1D_IOMUX;
 202     uint32 GRF_GPIO2A_IOMUX;
 203     uint32 GRF_GPIO2B_IOMUX;
 204     uint32 GRF_GPIO2C_IOMUX;
 205     uint32 GRF_GPIO2D_IOMUX;
 206     uint32 GRF_GPIO3A_IOMUX;
 207     uint32 GRF_GPIO3B_IOMUX;
 208     uint32 GRF_GPIO3C_IOMUX;
 209     uint32 GRF_GPIO3DL_IOMUX;
 210     uint32 GRF_GPIO3DH_IOMUX;
 211     uint32 GRF_GPIO4AL_IOMUX;
 212     uint32 GRF_GPIO4AH_IOMUX;
 213     uint32 GRF_GPIO4BL_IOMUX;
 214     uint32 GRF_GPIO4BH_IOMUX;
 215     uint32 GRF_GPIO4C_IOMUX;
 216     uint32 GRF_GPIO4D_IOMUX;
 217     uint32 GRF_GPIO5A_IOMUX;
 218     uint32 GRF_GPIO5B_IOMUX;
 219     uint32 GRF_GPIO5C_IOMUX;
 220     uint32 GRF_GPIO5D_IOMUX;
 221     uint32 GRF_GPIO6A_IOMUX;
 222     uint32 GRF_GPIO6B_IOMUX;
 223     uint32 GRF_GPIO6C_IOMUX;
 224     uint32 GRF_GPIO6D_IOMUX;
 225     uint32 GRF_GPIO7A_IOMUX;
 226     uint32 GRF_GPIO7B_IOMUX;
 227     uint32 GRF_GPIO7CL_IOMUX;
 228     uint32 GRF_GPIO7CH_IOMUX;
 229     uint32 GRF_GPIO7D_IOMUX;
 230     uint32 GRF_GPIO8A_IOMUX;
 231     uint32 GRF_GPIO8B_IOMUX;
 232     uint32 GRF_GPIO8C_IOMUX;
 233     uint32 GRF_GPIO8D_IOMUX;
 234     uint32 reserved1[(0x100-0x90)/4];
 235     uint32 GRF_GPIO1L_SR;
 236     uint32 GRF_GPIO1H_SR;
 237     uint32 GRF_GPIO2L_SR;
 238     uint32 GRF_GPIO2H_SR;
 239     uint32 GRF_GPIO3L_SR;
 240     uint32 GRF_GPIO3H_SR;
 241     uint32 GRF_GPIO4L_SR;
 242     uint32 GRF_GPIO4H_SR;
 243     uint32 GRF_GPIO5L_SR;
 244     uint32 GRF_GPIO5H_SR;
 245     uint32 GRF_GPIO6L_SR;
 246     uint32 GRF_GPIO6H_SR;
 247     uint32 GRF_GPIO7L_SR;
 248     uint32 GRF_GPIO7H_SR;
 249     uint32 GRF_GPIO8L_SR;
 250     uint32 GRF_GPIO8H_SR;
 251     uint32 GRF_GPIO1A_P;
 252     uint32 GRF_GPIO1B_P;
 253     uint32 GRF_GPIO1C_P;
 254     uint32 GRF_GPIO1D_P;
 255     uint32 GRF_GPIO2A_P;
 256     uint32 GRF_GPIO2B_P;
 257     uint32 GRF_GPIO2C_P;
 258     uint32 GRF_GPIO2D_P;
 259     uint32 GRF_GPIO3A_P;
 260     uint32 GRF_GPIO3B_P;
 261     uint32 GRF_GPIO3C_P;
 262     uint32 GRF_GPIO3D_P;
 263     uint32 GRF_GPIO4A_P;
 264     uint32 GRF_GPIO4B_P;
 265     uint32 GRF_GPIO4C_P;
 266     uint32 GRF_GPIO4D_P;
 267     uint32 GRF_GPIO5A_P;
 268     uint32 GRF_GPIO5B_P;
 269     uint32 GRF_GPIO5C_P;
 270     uint32 GRF_GPIO5D_P;
 271     uint32 GRF_GPIO6A_P;
 272     uint32 GRF_GPIO6B_P;
 273     uint32 GRF_GPIO6C_P;
 274     uint32 GRF_GPIO6D_P;
 275     uint32 GRF_GPIO7A_P;
 276     uint32 GRF_GPIO7B_P;
 277     uint32 GRF_GPIO7C_P;
 278     uint32 GRF_GPIO7D_P;
 279     uint32 GRF_GPIO8A_P;
 280     uint32 GRF_GPIO8B_P;
 281     uint32 GRF_GPIO8C_P;
 282     uint32 GRF_GPIO8D_P;
 283     uint32 GRF_GPIO1A_E;
 284     uint32 GRF_GPIO1B_E;
 285     uint32 GRF_GPIO1C_E;
 286     uint32 GRF_GPIO1D_E;
 287     uint32 GRF_GPIO2A_E;
 288     uint32 GRF_GPIO2B_E;
 289     uint32 GRF_GPIO2C_E;
 290     uint32 GRF_GPIO2D_E;
 291     uint32 GRF_GPIO3A_E;
 292     uint32 GRF_GPIO3B_E;
 293     uint32 GRF_GPIO3C_E;
 294     uint32 GRF_GPIO3D_E;
 295     uint32 GRF_GPIO4A_E;
 296     uint32 GRF_GPIO4B_E;
 297     uint32 GRF_GPIO4C_E;
 298     uint32 GRF_GPIO4D_E;
 299     uint32 GRF_GPIO5A_E;
 300     uint32 GRF_GPIO5B_E;
 301     uint32 GRF_GPIO5C_E;
 302     uint32 GRF_GPIO5D_E;
 303     uint32 GRF_GPIO6A_E;
 304     uint32 GRF_GPIO6B_E;
 305     uint32 GRF_GPIO6C_E;
 306     uint32 GRF_GPIO6D_E;
 307     uint32 GRF_GPIO7A_E;
 308     uint32 GRF_GPIO7B_E;
 309     uint32 GRF_GPIO7C_E;
 310     uint32 GRF_GPIO7D_E;
 311     uint32 GRF_GPIO8A_E;
 312     uint32 GRF_GPIO8B_E;
 313     uint32 GRF_GPIO8C_E;
 314     uint32 GRF_GPIO8D_E;
 315     uint32 GRF_GPIO_SMT;
 316     uint32 GRF_SOC_CON[15];
 317     uint32 GRF_SOC_STATUS[23];
 318     uint32 reserved2[(0x2e0-0x2dc)/4];
 319     uint32 GRF_DMAC2_CON[4];
 320     uint32 GRF_DDRC0_CON0;
 321     uint32 GRF_DDRC1_CON0;
 322     uint32 GRF_CPU_CON[5];
 323     uint32 reserved3[(0x318-0x30c)/4];
 324     uint32 GRF_CPU_STATUS0;
 325     uint32 reserved4[(0x320-0x31c)/4];
 326     uint32 GRF_UOC0_CON[5];
 327     uint32 GRF_UOC1_CON[5];
 328     uint32 GRF_UOC2_CON[4];
 329     uint32 GRF_UOC3_CON[2];
 330     uint32 GRF_UOC4_CON[2];
 331     uint32 GRF_DLL_CON[3];
 332     uint32 GRF_DLL_STATUS[3];
 333     uint32 GRF_IO_VSEL;
 334     uint32 GRF_SARADC_TESTBIT;
 335     uint32 GRF_TSADC_TESTBIT_L;
 336     uint32 GRF_TSADC_TESTBIT_H;
 337     uint32 GRF_OS_REG[4];
 338     uint32 GRF_FAST_BOOT_ADDR;
 339     uint32 GRF_SOC_CON15;
 340     uint32 GRF_SOC_CON16;
 341 } REG_FILE, *pREG_FILE;
 342
 343 /*
 344  * PCTL
 345  */
 346 //SCTL
 347 #define INIT_STATE                     (0)
 348 #define CFG_STATE                      (1)
 349 #define GO_STATE                       (2)
 350 #define SLEEP_STATE                    (3)
 351 #define WAKEUP_STATE                   (4)
 352
 353 //STAT
 354 #define Init_mem                       (0)
 355 #define Config                         (1)
 356 #define Config_req                     (2)
 357 #define Access                         (3)
 358 #define Access_req                     (4)
 359 #define Low_power                      (5)
 360 #define Low_power_entry_req            (6)
 361 #define Low_power_exit_req             (7)
 362
 363 //MCFG
 364 #define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
 365 #define pd_idle(n)                     ((n)<<8)
 366 #define mddr_en                        (2<<22)
 367 #define lpddr2_en                      (3<<22)
 368 #define ddr2_en                        (0<<5)
 369 #define ddr3_en                        (1<<5)
 370 #define lpddr2_s2                      (0<<6)
 371 #define lpddr2_s4                      (1<<6)
 372 #define mddr_lpddr2_bl_2               (0<<20)
 373 #define mddr_lpddr2_bl_4               (1<<20)
 374 #define mddr_lpddr2_bl_8               (2<<20)
 375 #define mddr_lpddr2_bl_16              (3<<20)
 376 #define ddr2_ddr3_bl_4                 (0)
 377 #define ddr2_ddr3_bl_8                 (1)
 378 #define tfaw_cfg(n)                    (((n)-4)<<18)
 379 #define pd_exit_slow                   (0<<17)
 380 #define pd_exit_fast                   (1<<17)
 381 #define pd_type(n)                     ((n)<<16)
 382 #define two_t_en(n)                    ((n)<<3)
 383 #define bl8int_en(n)                   ((n)<<2)
 384 #define cke_or_en(n)                   ((n)<<1)
 385
 386 //POWCTL
 387 #define power_up_start                 (1<<0)
 388
 389 //POWSTAT
 390 #define power_up_done                  (1<<0)
 391
 392 //DFISTSTAT0
 393 #define dfi_init_complete              (1<<0)
 394
 395 //CMDTSTAT
 396 #define cmd_tstat                      (1<<0)
 397
 398 //CMDTSTATEN
 399 #define cmd_tstat_en                   (1<<1)
 400
 401 //MCMD
 402 #define Deselect_cmd                   (0)
 403 #define PREA_cmd                       (1)
 404 #define REF_cmd                        (2)
 405 #define MRS_cmd                        (3)
 406 #define ZQCS_cmd                       (4)
 407 #define ZQCL_cmd                       (5)
 408 #define RSTL_cmd                       (6)
 409 #define MRR_cmd                        (8)
 410 #define DPDE_cmd                       (9)
 411
 412 #define lpddr2_op(n)                   ((n)<<12)
 413 #define lpddr2_ma(n)                   ((n)<<4)
 414
 415 #define bank_addr(n)                   ((n)<<17)
 416 #define cmd_addr(n)                    ((n)<<4)
 417
 418 #define start_cmd                      (1u<<31)
 419
 420 typedef union STAT_Tag
 421 {
 422     uint32 d32;
 423     struct
 424     {
 425         unsigned ctl_stat : 3;
 426         unsigned reserved3 : 1;
 427         unsigned lp_trig : 3;
 428         unsigned reserved7_31 : 25;
 429     }b;
 430 }STAT_T;
 431
 432 typedef union SCFG_Tag
 433 {
 434     uint32 d32;
 435     struct
 436     {
 437         unsigned hw_low_power_en : 1;
 438         unsigned reserved1_5 : 5;
 439         unsigned nfifo_nif1_dis : 1;
 440         unsigned reserved7 : 1;
 441         unsigned bbflags_timing : 4;
 442         unsigned reserved12_31 : 20;
 443     } b;
 444 }SCFG_T;
 445
 446 /* DDR Controller register struct */
 447 typedef volatile struct DDR_REG_Tag
 448 {
 449     //Operational State, Control, and Status Registers
 450     SCFG_T SCFG;                   //State Configuration Register
 451     volatile uint32 SCTL;                   //State Control Register
 452     STAT_T STAT;                   //State Status Register
 453     volatile uint32 INTRSTAT;               //Interrupt Status Register
 454     uint32 reserved0[(0x40-0x10)/4];
 455     //Initailization Control and Status Registers
 456     volatile uint32 MCMD;                   //Memory Command Register
 457     volatile uint32 POWCTL;                 //Power Up Control Registers
 458     volatile uint32 POWSTAT;                //Power Up Status Register
 459     volatile uint32 CMDTSTAT;               //Command Timing Status Register
 460     volatile uint32 CMDTSTATEN;             //Command Timing Status Enable Register
 461     uint32 reserved1[(0x60-0x54)/4];
 462     volatile uint32 MRRCFG0;                //MRR Configuration 0 Register
 463     volatile uint32 MRRSTAT0;               //MRR Status 0 Register
 464     volatile uint32 MRRSTAT1;               //MRR Status 1 Register
 465     uint32 reserved2[(0x7c-0x6c)/4];
 466     //Memory Control and Status Registers
 467     volatile uint32 MCFG1;                  //Memory Configuration 1 Register
 468     volatile uint32 MCFG;                   //Memory Configuration Register
 469     volatile uint32 PPCFG;                  //Partially Populated Memories Configuration Register
 470     volatile uint32 MSTAT;                  //Memory Status Register
 471     volatile uint32 LPDDR2ZQCFG;            //LPDDR2 ZQ Configuration Register
 472     uint32 reserved3;
 473     //DTU Control and Status Registers
 474     volatile uint32 DTUPDES;                //DTU Status Register
 475     volatile uint32 DTUNA;                  //DTU Number of Random Addresses Created Register
 476     volatile uint32 DTUNE;                  //DTU Number of Errors Register
 477     volatile uint32 DTUPRD0;                //DTU Parallel Read 0
 478     volatile uint32 DTUPRD1;                //DTU Parallel Read 1
 479     volatile uint32 DTUPRD2;                //DTU Parallel Read 2
 480     volatile uint32 DTUPRD3;                //DTU Parallel Read 3
 481     volatile uint32 DTUAWDT;                //DTU Address Width
 482     uint32 reserved4[(0xc0-0xb4)/4];
 483     //Memory Timing Registers
 484     volatile uint32 TOGCNT1U;               //Toggle Counter 1U Register
 485     volatile uint32 TINIT;                  //t_init Timing Register
 486     volatile uint32 TRSTH;                  //Reset High Time Register
 487     volatile uint32 TOGCNT100N;             //Toggle Counter 100N Register
 488     volatile uint32 TREFI;                  //t_refi Timing Register
 489     volatile uint32 TMRD;                   //t_mrd Timing Register
 490     volatile uint32 TRFC;                   //t_rfc Timing Register
 491     volatile uint32 TRP;                    //t_rp Timing Register
 492     volatile uint32 TRTW;                   //t_rtw Timing Register
 493     volatile uint32 TAL;                    //AL Latency Register
 494     volatile uint32 TCL;                    //CL Timing Register
 495     volatile uint32 TCWL;                   //CWL Register
 496     volatile uint32 TRAS;                   //t_ras Timing Register
 497     volatile uint32 TRC;                    //t_rc Timing Register
 498     volatile uint32 TRCD;                   //t_rcd Timing Register
 499     volatile uint32 TRRD;                   //t_rrd Timing Register
 500     volatile uint32 TRTP;                   //t_rtp Timing Register
 501     volatile uint32 TWR;                    //t_wr Timing Register
 502     volatile uint32 TWTR;                   //t_wtr Timing Register
 503     volatile uint32 TEXSR;                  //t_exsr Timing Register
 504     volatile uint32 TXP;                    //t_xp Timing Register
 505     volatile uint32 TXPDLL;                 //t_xpdll Timing Register
 506     volatile uint32 TZQCS;                  //t_zqcs Timing Register
 507     volatile uint32 TZQCSI;                 //t_zqcsi Timing Register
 508     volatile uint32 TDQS;                   //t_dqs Timing Register
 509     volatile uint32 TCKSRE;                 //t_cksre Timing Register
 510     volatile uint32 TCKSRX;                 //t_cksrx Timing Register
 511     volatile uint32 TCKE;                   //t_cke Timing Register
 512     volatile uint32 TMOD;                   //t_mod Timing Register
 513     volatile uint32 TRSTL;                  //Reset Low Timing Register
 514     volatile uint32 TZQCL;                  //t_zqcl Timing Register
 515     volatile uint32 TMRR;                   //t_mrr Timing Register
 516     volatile uint32 TCKESR;                 //t_ckesr Timing Register
 517     volatile uint32 TDPD;                   //t_dpd Timing Register
 518     uint32 reserved5[(0x180-0x148)/4];
 519     //ECC Configuration, Control, and Status Registers
 520     volatile uint32 ECCCFG;                   //ECC Configuration Register
 521     volatile uint32 ECCTST;                   //ECC Test Register
 522     volatile uint32 ECCCLR;                   //ECC Clear Register
 523     volatile uint32 ECCLOG;                   //ECC Log Register
 524     uint32 reserved6[(0x200-0x190)/4];
 525     //DTU Control and Status Registers
 526     volatile uint32 DTUWACTL;                 //DTU Write Address Control Register
 527     volatile uint32 DTURACTL;                 //DTU Read Address Control Register
 528     volatile uint32 DTUCFG;                   //DTU Configuration Control Register
 529     volatile uint32 DTUECTL;                  //DTU Execute Control Register
 530     volatile uint32 DTUWD0;                   //DTU Write Data 0
 531     volatile uint32 DTUWD1;                   //DTU Write Data 1
 532     volatile uint32 DTUWD2;                   //DTU Write Data 2
 533     volatile uint32 DTUWD3;                   //DTU Write Data 3
 534     volatile uint32 DTUWDM;                   //DTU Write Data Mask
 535     volatile uint32 DTURD0;                   //DTU Read Data 0
 536     volatile uint32 DTURD1;                   //DTU Read Data 1
 537     volatile uint32 DTURD2;                   //DTU Read Data 2
 538     volatile uint32 DTURD3;                   //DTU Read Data 3
 539     volatile uint32 DTULFSRWD;                //DTU LFSR Seed for Write Data Generation
 540     volatile uint32 DTULFSRRD;                //DTU LFSR Seed for Read Data Generation
 541     volatile uint32 DTUEAF;                   //DTU Error Address FIFO
 542     //DFI Control Registers
 543     volatile uint32 DFITCTRLDELAY;            //DFI tctrl_delay Register
 544     volatile uint32 DFIODTCFG;                //DFI ODT Configuration Register
 545     volatile uint32 DFIODTCFG1;               //DFI ODT Configuration 1 Register
 546     volatile uint32 DFIODTRANKMAP;            //DFI ODT Rank Mapping Register
 547     //DFI Write Data Registers
 548     volatile uint32 DFITPHYWRDATA;            //DFI tphy_wrdata Register
 549     volatile uint32 DFITPHYWRLAT;             //DFI tphy_wrlat Register
 550     uint32 reserved7[(0x260-0x258)/4];
 551     volatile uint32 DFITRDDATAEN;             //DFI trddata_en Register
 552     volatile uint32 DFITPHYRDLAT;             //DFI tphy_rddata Register
 553     uint32 reserved8[(0x270-0x268)/4];
 554     //DFI Update Registers
 555     volatile uint32 DFITPHYUPDTYPE0;          //DFI tphyupd_type0 Register
 556     volatile uint32 DFITPHYUPDTYPE1;          //DFI tphyupd_type1 Register
 557     volatile uint32 DFITPHYUPDTYPE2;          //DFI tphyupd_type2 Register
 558     volatile uint32 DFITPHYUPDTYPE3;          //DFI tphyupd_type3 Register
 559     volatile uint32 DFITCTRLUPDMIN;           //DFI tctrlupd_min Register
 560     volatile uint32 DFITCTRLUPDMAX;           //DFI tctrlupd_max Register
 561     volatile uint32 DFITCTRLUPDDLY;           //DFI tctrlupd_dly Register
 562     uint32 reserved9;
 563     volatile uint32 DFIUPDCFG;                //DFI Update Configuration Register
 564     volatile uint32 DFITREFMSKI;              //DFI Masked Refresh Interval Register
 565     volatile uint32 DFITCTRLUPDI;             //DFI tctrlupd_interval Register
 566     uint32 reserved10[(0x2ac-0x29c)/4];
 567     volatile uint32 DFITRCFG0;                //DFI Training Configuration 0 Register
 568     volatile uint32 DFITRSTAT0;               //DFI Training Status 0 Register
 569     volatile uint32 DFITRWRLVLEN;             //DFI Training dfi_wrlvl_en Register
 570     volatile uint32 DFITRRDLVLEN;             //DFI Training dfi_rdlvl_en Register
 571     volatile uint32 DFITRRDLVLGATEEN;         //DFI Training dfi_rdlvl_gate_en Register
 572     //DFI Status Registers
 573     volatile uint32 DFISTSTAT0;               //DFI Status Status 0 Register
 574     volatile uint32 DFISTCFG0;                //DFI Status Configuration 0 Register
 575     volatile uint32 DFISTCFG1;                //DFI Status configuration 1 Register
 576     uint32 reserved11;
 577     volatile uint32 DFITDRAMCLKEN;            //DFI tdram_clk_enalbe Register
 578     volatile uint32 DFITDRAMCLKDIS;           //DFI tdram_clk_disalbe Register
 579     volatile uint32 DFISTCFG2;                //DFI Status configuration 2 Register
 580     volatile uint32 DFISTPARCLR;              //DFI Status Parity Clear Register
 581     volatile uint32 DFISTPARLOG;              //DFI Status Parity Log Register
 582     uint32 reserved12[(0x2f0-0x2e4)/4];
 583     //DFI Low Power Registers
 584     volatile uint32 DFILPCFG0;                //DFI Low Power Configuration 0 Register
 585     uint32 reserved13[(0x300-0x2f4)/4];
 586     //DFI Training 2 Registers
 587     volatile uint32 DFITRWRLVLRESP0;          //DFI Training dif_wrlvl_resp Status 0 Register
 588     volatile uint32 DFITRWRLVLRESP1;          //DFI Training dif_wrlvl_resp Status 1 Register
 589     volatile uint32 DFITRWRLVLRESP2;          //DFI Training dif_wrlvl_resp Status 2 Register
 590     volatile uint32 DFITRRDLVLRESP0;          //DFI Training dif_rdlvl_resp Status 0 Register
 591     volatile uint32 DFITRRDLVLRESP1;          //DFI Training dif_rdlvl_resp Status 1 Register
 592     volatile uint32 DFITRRDLVLRESP2;          //DFI Training dif_rdlvl_resp Status 2 Register
 593     volatile uint32 DFITRWRLVLDELAY0;         //DFI Training dif_wrlvl_delay Configuration 0 Register
 594     volatile uint32 DFITRWRLVLDELAY1;         //DFI Training dif_wrlvl_delay Configuration 1 Register
 595     volatile uint32 DFITRWRLVLDELAY2;         //DFI Training dif_wrlvl_delay Configuration 2 Register
 596     volatile uint32 DFITRRDLVLDELAY0;         //DFI Training dif_rdlvl_delay Configuration 0 Register
 597     volatile uint32 DFITRRDLVLDELAY1;         //DFI Training dif_rdlvl_delay Configuration 1 Register
 598     volatile uint32 DFITRRDLVLDELAY2;         //DFI Training dif_rdlvl_delay Configuration 2 Register
 599     volatile uint32 DFITRRDLVLGATEDELAY0;     //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
 600     volatile uint32 DFITRRDLVLGATEDELAY1;     //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
 601     volatile uint32 DFITRRDLVLGATEDELAY2;     //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
 602     volatile uint32 DFITRCMD;                 //DFI Training Command Register
 603     uint32 reserved14[(0x3f8-0x340)/4];
 604     //IP Status Registers
 605     volatile uint32 IPVR;                     //IP Version Register
 606     volatile uint32 IPTR;                     //IP Type Register
 607 }DDR_REG_T, *pDDR_REG_T;
 608
 609 /*
 610  * PUBL
 611  */
 612 //PIR
 613 #define INIT                 (1<<0)
 614 #define DLLSRST              (1<<1)
 615 #define DLLLOCK              (1<<2)
 616 #define ZCAL                 (1<<3)
 617 #define ITMSRST              (1<<4)
 618 #define DRAMRST              (1<<5)
 619 #define DRAMINIT             (1<<6)
 620 #define QSTRN                (1<<7)
 621 #define EYETRN               (1<<8)
 622 #define ICPC                 (1<<16)
 623 #define DLLBYP               (1<<17)
 624 #define CTLDINIT             (1<<18)
 625 #define CLRSR                (1<<28)
 626 #define LOCKBYP              (1<<29)
 627 #define ZCALBYP              (1<<30)
 628 #define INITBYP              (1u<<31)
 629
 630 //PGCR
 631 #define DFTLMT(n)            ((n)<<3)
 632 #define DFTCMP(n)            ((n)<<2)
 633 #define DQSCFG(n)            ((n)<<1)
 634 #define ITMDMD(n)            ((n)<<0)
 635 #define RANKEN(n)            ((n)<<18)
 636
 637 //PGSR
 638 #define IDONE                (1<<0)
 639 #define DLDONE               (1<<1)
 640 #define ZCDONE               (1<<2)
 641 #define DIDONE               (1<<3)
 642 #define DTDONE               (1<<4)
 643 #define DTERR                (1<<5)
 644 #define DTIERR               (1<<6)
 645 #define DFTERR               (1<<7)
 646 #define TQ                   (1u<<31)
 647
 648 //PTR0
 649 #define tITMSRST(n)          ((n)<<18)
 650 #define tDLLLOCK(n)          ((n)<<6)
 651 #define tDLLSRST(n)          ((n)<<0)
 652
 653 //PTR1
 654 #define tDINIT1(n)           ((n)<<19)
 655 #define tDINIT0(n)           ((n)<<0)
 656
 657 //PTR2
 658 #define tDINIT3(n)           ((n)<<17)
 659 #define tDINIT2(n)           ((n)<<0)
 660
 661 //DSGCR
 662 #define DQSGE(n)             ((n)<<8)
 663 #define DQSGX(n)             ((n)<<5)
 664
 665 typedef union DCR_Tag
 666 {
 667     uint32 d32;
 668     struct
 669     {
 670         unsigned DDRMD : 3;
 671         unsigned DDR8BNK : 1;
 672         unsigned PDQ : 3;
 673         unsigned MPRDQ : 1;
 674         unsigned DDRTYPE : 2;
 675         unsigned reserved10_26 : 17;
 676         unsigned NOSRA : 1;
 677         unsigned DDR2T : 1;
 678         unsigned UDIMM : 1;
 679         unsigned RDIMM : 1;
 680         unsigned TPD : 1;
 681     } b;
 682 }DCR_T;
 683
 684 typedef volatile struct DATX8_REG_Tag
 685 {
 686     volatile uint32 DXGCR;                 //DATX8 General Configuration Register
 687     volatile uint32 DXGSR[2];              //DATX8 General Status Register
 688     volatile uint32 DXDLLCR;               //DATX8 DLL Control Register
 689     volatile uint32 DXDQTR;                //DATX8 DQ Timing Register
 690     volatile uint32 DXDQSTR;               //DATX8 DQS Timing Register
 691     uint32 reserved[0x80-0x76];
 692 }DATX8_REG_T;
 693
 694 /* DDR PHY register struct */
 695 typedef volatile struct DDRPHY_REG_Tag
 696 {
 697     volatile uint32 RIDR;                   //Revision Identification Register
 698     volatile uint32 PIR;                    //PHY Initialization Register
 699     volatile uint32 PGCR;                   //PHY General Configuration Register
 700     volatile uint32 PGSR;                   //PHY General Status Register
 701     volatile uint32 DLLGCR;                 //DLL General Control Register
 702     volatile uint32 ACDLLCR;                //AC DLL Control Register
 703     volatile uint32 PTR[3];                 //PHY Timing Registers 0-2
 704     volatile uint32 ACIOCR;                 //AC I/O Configuration Register
 705     volatile uint32 DXCCR;                  //DATX8 Common Configuration Register
 706     volatile uint32 DSGCR;                  //DDR System General Configuration Register
 707     DCR_T DCR;                    //DRAM Configuration Register
 708     volatile uint32 DTPR[3];                //DRAM Timing Parameters Register 0-2
 709     volatile uint32 MR[4];                    //Mode Register 0-3
 710     volatile uint32 ODTCR;                  //ODT Configuration Register
 711     volatile uint32 DTAR;                   //Data Training Address Register
 712     volatile uint32 DTDR[2];                //Data Training Data Register 0-1
 713
 714     uint32 reserved1[0x30-0x18];
 715     uint32 DCU[0x38-0x30];
 716     uint32 reserved2[0x40-0x38];
 717     uint32 BIST[0x51-0x40];
 718     uint32 reserved3[0x60-0x51];
 719
 720     volatile uint32 ZQ0CR[2];               //ZQ 0 Impedance Control Register 0-1
 721     volatile uint32 ZQ0SR[2];               //ZQ 0 Impedance Status Register 0-1
 722     volatile uint32 ZQ1CR[2];               //ZQ 1 Impedance Control Register 0-1
 723     volatile uint32 ZQ1SR[2];               //ZQ 1 Impedance Status Register 0-1
 724     volatile uint32 ZQ2CR[2];               //ZQ 2 Impedance Control Register 0-1
 725     volatile uint32 ZQ2SR[2];               //ZQ 2 Impedance Status Register 0-1
 726     volatile uint32 ZQ3CR[2];               //ZQ 3 Impedance Control Register 0-1
 727     volatile uint32 ZQ3SR[2];               //ZQ 3 Impedance Status Register 0-1
 728
 729     DATX8_REG_T     DATX8[9];               //DATX8 Register
 730 }DDRPHY_REG_T, *pDDRPHY_REG_T;
 731
 732 typedef union NOC_TIMING_Tag
 733 {
 734     uint32 d32;
 735     struct
 736     {
 737         unsigned ActToAct : 6;
 738         unsigned RdToMiss : 6;
 739         unsigned WrToMiss : 6;
 740         unsigned BurstLen : 3;
 741         unsigned RdToWr : 5;
 742         unsigned WrToRd : 5;
 743         unsigned BwRatio : 1;
 744     } b;
 745 }NOC_TIMING_T;
 746
 747 typedef union NOC_ACTIVATE_Tag
 748 {
 749     uint32 d32;
 750     struct
 751     {
 752         unsigned Rrd : 4;  //bit[0:3]
 753         unsigned Faw : 6;  //bit[4:9]
 754         unsigned Fawbank : 1; //bit 10
 755         unsigned reserved : 21;
 756     } b;
 757 }NOC_ACTIVATE_T;
 758
 759 typedef volatile struct MSCH_REG_Tag
 760 {
 761     volatile uint32 coreid;
 762     volatile uint32 revisionid;
 763     volatile uint32 ddrconf;
 764     volatile NOC_TIMING_T ddrtiming;
 765     volatile uint32 ddrmode;
 766     volatile uint32 readlatency;
 767     uint32 reserved1[(0x38-0x18)/4];
 768     volatile NOC_ACTIVATE_T activate;
 769     volatile uint32 devtodev;
 770 }MSCH_REG, *pMSCH_REG;
 771
 772 #define CH_MAX                 (2)
 773 #define DRAM_PHYS              (0)   //DRAM Channel a physical address start
 774 #define pPMU_Reg               ((pPMU_FILE)RK_PMU_VIRT)
 775 #define pCRU_Reg               ((pCRU_REG)RK_CRU_VIRT)
 776 #define pGRF_Reg               ((pREG_FILE)RK_GRF_VIRT)
 777 #define pDDR_REG(ch)           ((ch) ? ((pDDR_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)):((pDDR_REG_T)RK_DDR_VIRT))
 778 #define pPHY_REG(ch)           ((ch) ? ((pDDRPHY_REG_T)(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)) : ((pDDRPHY_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE)))
 779 #define pMSCH_REG(ch)          ((ch)? ((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT+0x80)):((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT)))
 780 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 781 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 782 #define GET_LPDDR3_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 783 #define DDR_GET_RANK_2_ROW15() (0)
 784 #define DDR_GET_BANK_2_RANK()  (0)
 785 #define DDR_HW_WAKEUP(ch,en)   do{pGRF_Reg->GRF_SOC_CON[0] = (1<<(16+5+ch)) | (en<<(5+ch));}while(0)
 786 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[0])
 787 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS[1] & (1<<5))
 788 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<2))<<16)|(src<<2)| div;}while(0)
 789 #define GET_DDR_PLL_SRC()           ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<2)) ? GPLL : DPLL)
 790 #define DDR_GPLL_CLK_GATE(en)       do{pCRU_Reg->CRU_CLKGATE_CON[0] = 0x02000000 | (en<<9);}while(0)
 791 #define SET_DDRPHY_CLKGATE(ch,dis)  do{pCRU_Reg->CRU_CLKGATE_CON[4] = ((0x1<<(12+ch))<<16) | (dis<<(12+ch));}while(0)
 792 #define READ_DDR_STRIDE()           (readl_relaxed(RK_SGRF_VIRT+0x8) &0x1F)
 793
 794 #define READ_CH_CNT()         (1+((pPMU_Reg->PMU_PMU_SYS_REG[2]>>12)&0x1))
 795 #define READ_CH_INFO()        ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>28)&0x3)
 796 #define READ_CH_ROW_INFO(ch)  ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>(30+(ch)))&0x1)    //row_3_4:0=normal, 1=6Gb or 12Gb
 797
 798 #define SET_PLL_MODE(pll, mode) do{pCRU_Reg->CRU_MODE_CON = ((mode<<((pll)*4))|(0x3<<(16+(pll)*4)));}while(0)
 799 #define SET_PLL_PD(pll, pd)     do{pCRU_Reg->CRU_PLL_CON[pll][3] = ((0x1<<1)<<16) | (pd<<1);}while(0)
 800
 801 #define READ_DRAMTYPE_INFO()    ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>13)&0x7)
 802 #define READ_CS_INFO(ch)        ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(11+(ch)*16))&0x1)+1)
 803 #define READ_BW_INFO(ch)        (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(2+(ch)*16))&0x3))
 804 #define READ_COL_INFO(ch)       (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(9+(ch)*16))&0x3))
 805 #define READ_BK_INFO(ch)        (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(8+(ch)*16))&0x1))
 806 #define READ_ROW_INFO(ch,cs)    (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(6-(2*cs)+(ch)*16))&0x3))
 807 #define READ_DIE_BW_INFO(ch)    (2>>((pPMU_Reg->PMU_PMU_SYS_REG[2]>>((ch)*16))&0x3))
 808
 809 static const uint16_t  ddr_cfg_2_rbc[] =
 810 {
 811     /****************************/
 812     // [8:7]  bank(n:n bit bank)
 813     // [6:4]  row(12+n)
 814     // [3:2]  bank(n:n bit bank)
 815     // [1:0]  col(9+n)
 816     /****************************/
 817     //all config have (13col,3bank,16row,1cs)
 818     //bank,  row,   bank, col          col bank row(32bit)
 819     ((3<<7)|(3<<4)|(0<<2)|2),  // 0     11   8   15
 820     ((0<<7)|(1<<4)|(3<<2)|1),  // 1     10   8   13
 821     ((0<<7)|(2<<4)|(3<<2)|1),  // 2     10   8   14
 822     ((0<<7)|(3<<4)|(3<<2)|1),  // 3     10   8   15
 823     ((0<<7)|(4<<4)|(3<<2)|1),  // 4     10   8   16
 824     ((0<<7)|(1<<4)|(3<<2)|2),  // 5     11   8   13  // 32bit not use
 825     ((0<<7)|(2<<4)|(3<<2)|2),  // 6     11   8   14
 826     ((0<<7)|(3<<4)|(3<<2)|2),  // 7     11   8   15
 827     ((0<<7)|(1<<4)|(3<<2)|0),  // 8     9    8   13
 828     ((0<<7)|(2<<4)|(3<<2)|0),  // 9     9    8   14
 829     ((0<<7)|(3<<4)|(3<<2)|0),  // 10    9    8   15
 830     ((0<<7)|(2<<4)|(2<<2)|0),  // 11    9    4   14
 831     ((0<<7)|(1<<4)|(2<<2)|1),  // 12    10   4   13
 832     ((0<<7)|(0<<4)|(2<<2)|2),  // 13    11   4   12
 833     ((3<<7)|(4<<4)|(0<<2)|1),  // 14    10   8   16 / 10, 4,15 / 10, 8, 15
 834     ((0<<7)|(4<<4)|(3<<2)|2),  // 15    11   8   16
 835 };
 836
 837 /***********************************
 838  * LPDDR2 define
 839  ***********************************/
 840 //MR0 (Device Information)
 841 #define  LPDDR2_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 842 #define  LPDDR2_DI     (0x1<<1)     // 0:S2 or S4 SDRAM, 1:NVM
 843 #define  LPDDR2_DNVI   (0x1<<2)     // 0:DNV not supported, 1:DNV supported
 844 #define  LPDDR2_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 845                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 846
 847 //MR1 (Device Feature)
 848 #define LPDDR2_BL4     (0x2)
 849 #define LPDDR2_BL8     (0x3)
 850 #define LPDDR2_BL16    (0x4)
 851 #define LPDDR2_nWR(n)  (((n)-2)<<5)
 852
 853 //MR2 (Device Feature 2)
 854 #define LPDDR2_RL3_WL1  (0x1)
 855 #define LPDDR2_RL4_WL2  (0x2)
 856 #define LPDDR2_RL5_WL2  (0x3)
 857 #define LPDDR2_RL6_WL3  (0x4)
 858 #define LPDDR2_RL7_WL4  (0x5)
 859 #define LPDDR2_RL8_WL4  (0x6)
 860
 861 //MR3 (IO Configuration 1)
 862 #define LPDDR2_DS_34    (0x1)
 863 #define LPDDR2_DS_40    (0x2)
 864 #define LPDDR2_DS_48    (0x3)
 865 #define LPDDR2_DS_60    (0x4)
 866 #define LPDDR2_DS_80    (0x6)
 867 #define LPDDR2_DS_120   (0x7)   //optional
 868
 869 //MR4 (Device Temperature)
 870 #define LPDDR2_tREF_MASK (0x7)
 871 #define LPDDR2_4_tREF    (0x1)
 872 #define LPDDR2_2_tREF    (0x2)
 873 #define LPDDR2_1_tREF    (0x3)
 874 #define LPDDR2_025_tREF  (0x5)
 875 #define LPDDR2_025_tREF_DERATE    (0x6)
 876
 877 #define LPDDR2_TUF       (0x1<<7)
 878
 879 //MR8 (Basic configuration 4)
 880 #define LPDDR2_S4        (0x0)
 881 #define LPDDR2_S2        (0x1)
 882 #define LPDDR2_N         (0x2)
 883 #define LPDDR2_Density(mr8)  (8<<(((mr8)>>2)&0xf))   // Unit:MB
 884 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
 885
 886 //MR10 (Calibration)
 887 #define LPDDR2_ZQINIT   (0xFF)
 888 #define LPDDR2_ZQCL     (0xAB)
 889 #define LPDDR2_ZQCS     (0x56)
 890 #define LPDDR2_ZQRESET  (0xC3)
 891
 892 //MR16 (PASR Bank Mask)
 893 // S2 SDRAM Only
 894 #define LPDDR2_PASR_Full (0x0)
 895 #define LPDDR2_PASR_1_2  (0x1)
 896 #define LPDDR2_PASR_1_4  (0x2)
 897 #define LPDDR2_PASR_1_8  (0x3)
 898
 899 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 900
 901 //MR32 (DQ Calibration Pattern A)
 902
 903 //MR40 (DQ Calibration Pattern B)
 904
 905 /***********************************
 906  * LPDDR3 define
 907  ***********************************/
 908 //MR0 (Device Information)
 909 #define  LPDDR3_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 910 #define  LPDDR3_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 911                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 912 #define  LPDDR3_WL_SUPOT (1<<6)     // 0:DRAM does not support WL(Set B), 1:DRAM support WL(Set B)
 913 #define  LPDDR3_RL3_SUPOT (1<<7)    // 0:DRAM does not support RL=3,nWR=3,WL=1; 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
 914
 915 //MR1 (Device Feature)
 916 #define LPDDR3_BL8     (0x3)
 917 #define LPDDR3_nWR(n)  ((n)<<5)
 918
 919 //MR2 (Device Feature 2)
 920 //WL Set A,default
 921 #define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 922 #define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 923 #define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 924 #define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 925 #define LPDDR3_RL10_WL6  (0x8)       // <=667MHz,default
 926 #define LPDDR3_RL11_WL6  (0x9)       // <=733MHz
 927 #define LPDDR3_RL12_WL6  (0xa)       // <=800MHz
 928 #define LPDDR3_RL14_WL8  (0xc)       // <=933MHz
 929 #define LPDDR3_RL16_WL8  (0xe)       // <=1066MHz
 930 //WL Set B, optional
 931 //#define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 932 //#define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 933 //#define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 934 //#define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 935 #define LPDDR3_RL10_WL8  (0x8)       // <=667MHz,default
 936 #define LPDDR3_RL11_WL9  (0x9)       // <=733MHz
 937 #define LPDDR3_RL12_WL9  (0xa)       // <=800MHz
 938 #define LPDDR3_RL14_WL11 (0xc)       // <=933MHz
 939 #define LPDDR3_RL16_WL13 (0xe)       // <=1066MHz
 940
 941 #define LPDDR3_nWRE      (1<<4)      // 1:enable nWR programming > 9(defualt)
 942 #define LPDDR3_WL_S      (1<<6)      // 1:Select WL Set B
 943 #define LPDDR3_WR_LEVEL  (1<<7)      // 1:enable
 944
 945 //MR3 (IO Configuration 1)
 946 #define LPDDR3_DS_34    (0x1)
 947 #define LPDDR3_DS_40    (0x2)
 948 #define LPDDR3_DS_48    (0x3)
 949 #define LPDDR3_DS_60    (0x4)        //reserved
 950 #define LPDDR3_DS_80    (0x6)        //reserved
 951 #define LPDDR3_DS_34D_40U   (0x9)
 952 #define LPDDR3_DS_40D_48U   (0xa)
 953 #define LPDDR3_DS_34D_48U   (0xb)
 954
 955 //MR4 (Device Temperature)
 956 #define LPDDR3_tREF_MASK (0x7)
 957 #define LPDDR3_LT_EXED   (0x0)       // SDRAM Low temperature operating limit exceeded
 958 #define LPDDR3_4_tREF    (0x1)
 959 #define LPDDR3_2_tREF    (0x2)
 960 #define LPDDR3_1_tREF    (0x3)
 961 #define LPDDR3_05_tREF   (0x4)
 962 #define LPDDR3_025_tREF  (0x5)
 963 #define LPDDR3_025_tREF_DERATE    (0x6)
 964 #define LPDDR3_HT_EXED   (0x7)       // SDRAM High temperature operating limit exceeded
 965
 966 #define LPDDR3_TUF       (0x1<<7)    // 1:value has changed since last read of MR4
 967
 968 //MR8 (Basic configuration 4)
 969 #define LPDDR3_S8        (0x3)
 970 #define LPDDR3_Density(mr8)  (8<<((mr8>>2)&0xf))   // Unit:MB
 971 #define LPDDR3_IO_Width(mr8) (32>>((mr8>>6)&0x3))
 972
 973 //MR10 (Calibration)
 974 #define LPDDR3_ZQINIT   (0xFF)
 975 #define LPDDR3_ZQCL     (0xAB)
 976 #define LPDDR3_ZQCS     (0x56)
 977 #define LPDDR3_ZQRESET  (0xC3)
 978
 979 //MR11 (ODT Control)
 980 #define LPDDR3_ODT_60   (1)           //optional for 1333 and 1600
 981 #define LPDDR3_ODT_120  (2)
 982 #define LPDDR3_ODT_240  (3)
 983 #define LPDDR3_ODT_DIS  (0)
 984
 985 //MR16 (PASR Bank Mask)
 986
 987 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 988
 989 //MR32 (DQ Calibration Pattern A)
 990
 991 //MR40 (DQ Calibration Pattern B)
 992
 993 /***********************************
 994  * DDR3 define
 995  ***********************************/
 996 //mr0 for ddr3
 997 #define DDR3_BL8          (0)
 998 #define DDR3_BC4_8        (1)
 999 #define DDR3_BC4          (2)
1000 #define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
1001 #define DDR3_WR(n)        (((n)&0x7)<<9)
1002 #define DDR3_DLL_RESET    (1<<8)
1003 #define DDR3_DLL_DeRESET  (0<<8)
1004
1005 //mr1 for ddr3
1006 #define DDR3_DLL_ENABLE    (0)
1007 #define DDR3_DLL_DISABLE   (1)
1008 #define DDR3_MR1_AL(n)  (((n)&0x3)<<3)
1009
1010 #define DDR3_DS_40            (0)
1011 #define DDR3_DS_34            (1<<1)
1012 #define DDR3_Rtt_Nom_DIS      (0)
1013 #define DDR3_Rtt_Nom_60       (1<<2)
1014 #define DDR3_Rtt_Nom_120      (1<<6)
1015 #define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
1016
1017     //mr2 for ddr3
1018 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
1019 #define DDR3_Rtt_WR_DIS       (0)
1020 #define DDR3_Rtt_WR_60        (1<<9)
1021 #define DDR3_Rtt_WR_120       (2<<9)
1022
1023 /***********************************
1024  * DDR2 define
1025  ***********************************/
1026 //MR;                     //Mode Register
1027 #define DDR2_BL4           (2)
1028 #define DDR2_BL8           (3)
1029 #define DDR2_CL(n)         (((n)&0x7)<<4)
1030 #define DDR2_WR(n)        ((((n)-1)&0x7)<<9)
1031 #define DDR2_DLL_RESET    (1<<8)
1032 #define DDR2_DLL_DeRESET  (0<<8)
1033
1034 //EMR;                    //Extended Mode Register
1035 #define DDR2_DLL_ENABLE    (0)
1036 #define DDR2_DLL_DISABLE   (1)
1037
1038 #define DDR2_STR_FULL     (0)
1039 #define DDR2_STR_REDUCE   (1<<1)
1040 #define DDR2_AL(n)        (((n)&0x7)<<3)
1041 #define DDR2_Rtt_Nom_DIS      (0)
1042 #define DDR2_Rtt_Nom_150      (0x40)
1043 #define DDR2_Rtt_Nom_75       (0x4)
1044 #define DDR2_Rtt_Nom_50       (0x44)
1045
1046 /***********************************
1047  * LPDDR define
1048  ***********************************/
1049 #define mDDR_BL2           (1)
1050 #define mDDR_BL4           (2)
1051 #define mDDR_BL8           (3)
1052 #define mDDR_CL(n)         (((n)&0x7)<<4)
1053
1054 #define mDDR_DS_Full       (0)
1055 #define mDDR_DS_1_2        (1<<5)
1056 #define mDDR_DS_1_4        (2<<5)
1057 #define mDDR_DS_1_8        (3<<5)
1058 #define mDDR_DS_3_4        (4<<5)
1059
1060 static const uint8_t ddr3_cl_cwl[22][7]={
1061 /*speed   0~330         331~400       401~533        534~666       667~800        801~933      934~1066
1062  * tCK    >3            2.5~3         1.875~2.5      1.5~1.875     1.25~1.5       1.07~1.25    0.938~1.07
1063  *        cl<<4, cwl    cl<<4, cwl    cl<<4, cwl              */
1064          {((5<<4)|5),   ((5<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800D (5-5-5)
1065          {((5<<4)|5),   ((6<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800E (6-6-6)
1066
1067          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    0,            0,             0,            0}, //DDR3_1066E (6-6-6)
1068          {((5<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    0,            0,             0,            0}, //DDR3_1066F (7-7-7)
1069          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    0,            0,             0,            0}, //DDR3_1066G (8-8-8)
1070
1071          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   0,             0,            0}, //DDR3_1333F (7-7-7)
1072          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   0,             0,            0}, //DDR3_1333G (8-8-8)
1073          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((9<<4)|7),   0,             0,            0}, //DDR3_1333H (9-9-9)
1074          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  0,             0,            0}, //DDR3_1333J (10-10-10)
1075
1076          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((8<<4)|8),    0,            0}, //DDR3_1600G (8-8-8)
1077          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    0,            0}, //DDR3_1600H (9-9-9)
1078          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   0,            0}, //DDR3_1600J (10-10-10)
1079          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   0,            0}, //DDR3_1600K (11-11-11)
1080
1081          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  0}, //DDR3_1866J (10-10-10)
1082          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   ((10<<4)|8),   ((11<<4)|9),  0}, //DDR3_1866K (11-11-11)
1083          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((12<<4)|9),  0}, //DDR3_1866L (12-12-12)
1084          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  0}, //DDR3_1866M (13-13-13)
1085
1086          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((9<<4)|8),    ((10<<4)|9),  ((11<<4)|10)}, //DDR3_2133K (11-11-11)
1087          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  ((12<<4)|10)}, //DDR3_2133L (12-12-12)
1088          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   ((12<<4)|9),  ((13<<4)|10)}, //DDR3_2133M (13-13-13)
1089          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)},  //DDR3_2133N (14-14-14)
1090
1091          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)} //DDR3_DEFAULT
1092 };
1093
1094 static const uint16_t ddr3_tRC_tFAW[22]={
1095 /**    tRC    tFAW   */
1096     ((50<<8)|50), //DDR3_800D (5-5-5)
1097     ((53<<8)|50), //DDR3_800E (6-6-6)
1098
1099     ((49<<8)|50), //DDR3_1066E (6-6-6)
1100     ((51<<8)|50), //DDR3_1066F (7-7-7)
1101     ((53<<8)|50), //DDR3_1066G (8-8-8)
1102
1103     ((47<<8)|45), //DDR3_1333F (7-7-7)
1104     ((48<<8)|45), //DDR3_1333G (8-8-8)
1105     ((50<<8)|45), //DDR3_1333H (9-9-9)
1106     ((51<<8)|45), //DDR3_1333J (10-10-10)
1107
1108     ((45<<8)|40), //DDR3_1600G (8-8-8)
1109     ((47<<8)|40), //DDR3_1600H (9-9-9)
1110     ((48<<8)|40), //DDR3_1600J (10-10-10)
1111     ((49<<8)|40), //DDR3_1600K (11-11-11)
1112
1113     ((45<<8)|35), //DDR3_1866J (10-10-10)
1114     ((46<<8)|35), //DDR3_1866K (11-11-11)
1115     ((47<<8)|35), //DDR3_1866L (12-12-12)
1116     ((48<<8)|35), //DDR3_1866M (13-13-13)
1117
1118     ((44<<8)|35), //DDR3_2133K (11-11-11)
1119     ((45<<8)|35), //DDR3_2133L (12-12-12)
1120     ((46<<8)|35), //DDR3_2133M (13-13-13)
1121     ((47<<8)|35), //DDR3_2133N (14-14-14)
1122
1123     ((53<<8)|50)  //DDR3_DEFAULT
1124 };
1125
1126 typedef enum DRAM_TYPE_Tag
1127 {
1128     LPDDR = 0,
1129     DDR,
1130     DDR2,
1131     DDR3,
1132     LPDDR2,
1133     LPDDR3,
1134
1135     DRAM_MAX
1136 }DRAM_TYPE;
1137
1138 typedef struct PCTRL_TIMING_Tag
1139 {
1140     uint32 ddrFreq;
1141     //Memory Timing Registers
1142     uint32 togcnt1u;               //Toggle Counter 1U Register
1143     uint32 tinit;                  //t_init Timing Register
1144     uint32 trsth;                  //Reset High Time Register
1145     uint32 togcnt100n;             //Toggle Counter 100N Register
1146     uint32 trefi;                  //t_refi Timing Register
1147     uint32 tmrd;                   //t_mrd Timing Register
1148     uint32 trfc;                   //t_rfc Timing Register
1149     uint32 trp;                    //t_rp Timing Register
1150     uint32 trtw;                   //t_rtw Timing Register
1151     uint32 tal;                    //AL Latency Register
1152     uint32 tcl;                    //CL Timing Register
1153     uint32 tcwl;                   //CWL Register
1154     uint32 tras;                   //t_ras Timing Register
1155     uint32 trc;                    //t_rc Timing Register
1156     uint32 trcd;                   //t_rcd Timing Register
1157     uint32 trrd;                   //t_rrd Timing Register
1158     uint32 trtp;                   //t_rtp Timing Register
1159     uint32 twr;                    //t_wr Timing Register
1160     uint32 twtr;                   //t_wtr Timing Register
1161     uint32 texsr;                  //t_exsr Timing Register
1162     uint32 txp;                    //t_xp Timing Register
1163     uint32 txpdll;                 //t_xpdll Timing Register
1164     uint32 tzqcs;                  //t_zqcs Timing Register
1165     uint32 tzqcsi;                 //t_zqcsi Timing Register
1166     uint32 tdqs;                   //t_dqs Timing Register
1167     uint32 tcksre;                 //t_cksre Timing Register
1168     uint32 tcksrx;                 //t_cksrx Timing Register
1169     uint32 tcke;                   //t_cke Timing Register
1170     uint32 tmod;                   //t_mod Timing Register
1171     uint32 trstl;                  //Reset Low Timing Register
1172     uint32 tzqcl;                  //t_zqcl Timing Register
1173     uint32 tmrr;                   //t_mrr Timing Register
1174     uint32 tckesr;                 //t_ckesr Timing Register
1175     uint32 tdpd;                   //t_dpd Timing Register
1176 }PCTL_TIMING_T;
1177
1178 typedef union DTPR_0_Tag
1179 {
1180     uint32 d32;
1181     struct
1182     {
1183         unsigned tMRD : 2;
1184         unsigned tRTP : 3;
1185         unsigned tWTR : 3;
1186         unsigned tRP : 4;
1187         unsigned tRCD : 4;
1188         unsigned tRAS : 5;
1189         unsigned tRRD : 4;
1190         unsigned tRC : 6;
1191         unsigned tCCD : 1;
1192     } b;
1193 }DTPR_0_T;
1194
1195 typedef union DTPR_1_Tag
1196 {
1197     uint32 d32;
1198     struct
1199     {
1200         unsigned tAOND : 2;
1201         unsigned tRTW : 1;
1202         unsigned tFAW : 6;
1203         unsigned tMOD : 2;
1204         unsigned tRTODT : 1;
1205         unsigned reserved12_15 : 4;
1206         unsigned tRFC : 8;
1207         unsigned tDQSCK : 3;
1208         unsigned tDQSCKmax : 3;
1209         unsigned reserved30_31 : 2;
1210     } b;
1211 }DTPR_1_T;
1212
1213 typedef union DTPR_2_Tag
1214 {
1215     uint32 d32;
1216     struct
1217     {
1218         unsigned tXS : 10;
1219         unsigned tXP : 5;
1220         unsigned tCKE : 4;
1221         unsigned tDLLK : 10;
1222         unsigned reserved29_31 : 3;
1223     } b;
1224 }DTPR_2_T;
1225
1226 typedef struct PHY_TIMING_Tag
1227 {
1228     DTPR_0_T  dtpr0;
1229     DTPR_1_T  dtpr1;
1230     DTPR_2_T  dtpr2;
1231     uint32    mr[4];   //LPDDR2 no MR0, mr[2] is mDDR MR1
1232     uint32    mr11;    //for LPDDR3 only
1233 }PHY_TIMING_T;
1234
1235 typedef struct PCTL_REG_Tag
1236 {
1237     uint32 SCFG;
1238     uint32 CMDTSTATEN;
1239     uint32 MCFG1;
1240     uint32 MCFG;
1241     PCTL_TIMING_T pctl_timing;
1242     //DFI Control Registers
1243     uint32 DFITCTRLDELAY;
1244     uint32 DFIODTCFG;
1245     uint32 DFIODTCFG1;
1246     uint32 DFIODTRANKMAP;
1247     //DFI Write Data Registers
1248     uint32 DFITPHYWRDATA;
1249     uint32 DFITPHYWRLAT;
1250     //DFI Read Data Registers
1251     uint32 DFITRDDATAEN;
1252     uint32 DFITPHYRDLAT;
1253     //DFI Update Registers
1254     uint32 DFITPHYUPDTYPE0;
1255     uint32 DFITPHYUPDTYPE1;
1256     uint32 DFITPHYUPDTYPE2;
1257     uint32 DFITPHYUPDTYPE3;
1258     uint32 DFITCTRLUPDMIN;
1259     uint32 DFITCTRLUPDMAX;
1260     uint32 DFITCTRLUPDDLY;
1261     uint32 DFIUPDCFG;
1262     uint32 DFITREFMSKI;
1263     uint32 DFITCTRLUPDI;
1264     //DFI Status Registers
1265     uint32 DFISTCFG0;
1266     uint32 DFISTCFG1;
1267     uint32 DFITDRAMCLKEN;
1268     uint32 DFITDRAMCLKDIS;
1269     uint32 DFISTCFG2;
1270     //DFI Low Power Register
1271     uint32 DFILPCFG0;
1272 }PCTL_REG_T;
1273
1274 typedef struct PUBL_DQS_REG_Tag
1275 {
1276     uint32 DX0GCR;
1277     uint32 DX0DLLCR;
1278     uint32 DX0DQTR;
1279     uint32 DX0DQSTR;
1280
1281     uint32 DX1GCR;
1282     uint32 DX1DLLCR;
1283     uint32 DX1DQTR;
1284     uint32 DX1DQSTR;
1285
1286     uint32 DX2GCR;
1287     uint32 DX2DLLCR;
1288     uint32 DX2DQTR;
1289     uint32 DX2DQSTR;
1290
1291     uint32 DX3GCR;
1292     uint32 DX3DLLCR;
1293     uint32 DX3DQTR;
1294     uint32 DX3DQSTR;
1295 }PUBL_DQS_REG;
1296
1297 typedef struct PUBL_REG_Tag
1298 {
1299     uint32 PIR;
1300     uint32 PGCR;
1301     uint32 DLLGCR;
1302     uint32 ACDLLCR;
1303     uint32 PTR[3];
1304     uint32 ACIOCR;
1305     uint32 DXCCR;
1306     uint32 DSGCR;
1307     uint32 DCR;
1308     PHY_TIMING_T phy_timing;
1309     uint32 ODTCR;
1310     uint32 DTAR;
1311     uint32 ZQ0CR0;
1312     uint32 ZQ1CR0;
1313 }PUBL_REG_T;
1314
1315 typedef struct SET_REG_Tag
1316 {
1317     uint32 addr;
1318     uint32 val;
1319 }SET_REG_T;
1320
1321 typedef struct BACKUP_REG_Tag
1322 {
1323     uint32 tag;
1324     /* any addr = 0xFFFFFFFF, indicate invalid */
1325     uint32 pctlAddr[CH_MAX];
1326     PCTL_REG_T pctl;
1327     uint32 publAddr[CH_MAX];
1328     PUBL_REG_T publ;
1329     PUBL_DQS_REG dqs[CH_MAX];
1330     uint32 nocAddr[CH_MAX];
1331     MSCH_REG   noc[CH_MAX];
1332
1333     uint32 pllpdAddr;
1334     uint32 pllpdMask;
1335     uint32 pllpdVal;
1336
1337     uint32 dpllmodeAddr;
1338     uint32 dpllSlowMode;
1339     uint32 dpllNormalMode;
1340     uint32 dpllResetAddr;
1341     uint32 dpllReset;
1342     uint32 dpllDeReset;
1343     uint32 dpllConAddr;
1344     uint32 dpllCon[4];
1345     uint32 dpllLockAddr;
1346     uint32 dpllLockMask;
1347     uint32 dpllLockVal;
1348
1349     uint32 ddrPllSrcDivAddr;
1350     uint32 ddrPllSrcDiv;
1351
1352     uint32 retenDisAddr;
1353     uint32 retenDisVal;
1354     uint32 retenStAddr;
1355     uint32 retenStMask;
1356     uint32 retenStVal;
1357
1358     /* ddr relative grf register */
1359     uint32 grfRegCnt;     //if no grf, set 0
1360     SET_REG_T grf[3];        //SET_REG_T grf[grfRegCnt];
1361
1362     /* other ddr relative register */
1363     //uint32 otherRegCnt; // if = 0xFFFFFFFF, indicate invalid
1364     //SET_REG_T other[grfRegCnt];
1365     uint32 endTag;         //must = 0xFFFFFFFF
1366 }BACKUP_REG_T;
1367
1368 typedef struct CHANNEL_INFO_Tag
1369 {
1370     //inited data
1371     uint32        chNum;  //channel number,0:channel a; 1:channel b;
1372     pDDR_REG_T    pDDR_Reg;
1373     pDDRPHY_REG_T pPHY_Reg;
1374     pMSCH_REG     pMSCH_Reg;
1375     //need init data
1376     DRAM_TYPE     mem_type; // =DRAM_MAX, channel invalid
1377     uint32        ddr_speed_bin;    // used for ddr3 only
1378     uint32        ddr_capability_per_die;  // one chip cs capability
1379 }CH_INFO,*pCH_INFO;
1380
1381 struct ddr_freq_t {
1382     unsigned long screen_ft_us;
1383     unsigned long long t0;
1384     unsigned long long t1;
1385     unsigned long t2;
1386 };
1387
1388 typedef struct STRIDE_INFO_Tag
1389 {
1390     uint32  size;
1391     uint32  halfCap;
1392 }STRIDE_INFO;
1393
1394 static const STRIDE_INFO   gStrideInfo[]={
1395     {0x10000000,0x10000000},  // 256
1396     {0x20000000,0x20000000},  // 512
1397     {0x40000000,0x40000000},  // 1G
1398     {0x80000000,0x80000000},  // 2G
1399
1400     {128,0x20000000},
1401     {256,0x20000000},
1402     {512,0x20000000},
1403     {4096,0x20000000},
1404
1405     {128,0x40000000},
1406     {256,0x40000000},
1407     {512,0x40000000},
1408     {4096,0x40000000},
1409
1410     {128,0x80000000},
1411     {256,0x80000000},
1412     {512,0x80000000},
1413     {4096,0x80000000},
1414
1415     {128,0x60000000},
1416     {256,0x60000000},
1417     {512,0x60000000},
1418     {4096,0x60000000},
1419
1420     {0,0x20000000},
1421     {0,0x40000000},
1422     {0,0x80000000},
1423     {0,0x80000000},  // 4GB
1424
1425     {0,0},  //reserved
1426     {0,0},  //reserved
1427
1428     {0,0},
1429     {128,0},
1430 };
1431
1432 CH_INFO DEFINE_PIE_DATA(ddr_ch[2]);
1433 static pCH_INFO p_ddr_ch[2];    //only used in kern, not pie
1434 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
1435 static BACKUP_REG_T *p_ddr_reg;
1436 static __attribute__((aligned(4096))) uint32 ddr_data_training_buf[32+8192/4];  //data in two channel even use max stride
1437 uint32 DEFINE_PIE_DATA(ddr_freq);
1438 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
1439
1440 /***********************************
1441  * ARCH Relative Data and Function
1442  ***********************************/
1443 static __sramdata uint32 clkr;
1444 static __sramdata uint32 clkf;
1445 static __sramdata uint32 clkod;
1446 uint32 DEFINE_PIE_DATA(ddr_select_gpll_div); // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1447 static uint32 *p_ddr_select_gpll_div;
1448
1449 static void __sramfunc ddr_delayus(uint32 us);
1450
1451 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
1452 {
1453     uint32 ret = 0;
1454
1455      // freq = (Fin/NR)*NF/OD
1456     if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1)             // DPLL Normal mode
1457         ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x1fff)+1)    // NF = 2*(CLKF+1)
1458                 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1)           // NR = CLKR+1
1459                 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xF)+1));             // OD = 2^CLKOD
1460     else
1461         ret = 24;
1462
1463     return ret;
1464 }
1465
1466 /*****************************************
1467 NR   NO     NF               Fout                       freq Step     finally use
1468 1    8      12.5 - 62.5      37.5MHz  - 187.5MHz        3MHz          50MHz   <= 150MHz
1469 1    6      12.5 - 62.5      50MHz    - 250MHz          4MHz          150MHz  <= 200MHz
1470 1    4      12.5 - 62.5      75MHz    - 375MHz          6MHz          200MHz  <= 300MHz
1471 1    2      12.5 - 62.5      150MHz   - 750MHz          12MHz         300MHz  <= 600MHz
1472 1    1      12.5 - 62.5      300MHz   - 1500MHz         24MHz         600MHz  <= 1200MHz
1473 ******************************************/
1474 static uint32 __sramfunc ddr_set_pll_rk3188_plus(uint32 nMHz, uint32 set)
1475 {
1476     uint32 ret = 0;
1477     int delay = 1000;
1478
1479     if(nMHz == 24)
1480     {
1481         ret = 24;
1482         goto out;
1483     }
1484
1485     if(!set)
1486     {
1487         if(nMHz <= 150)
1488         {
1489             clkod = 8;
1490         }
1491         else if(nMHz <= 200)
1492         {
1493             clkod = 6;
1494         }
1495         else if(nMHz <= 300)
1496         {
1497             clkod = 4;
1498         }
1499         else if(nMHz <= 600)
1500         {
1501             clkod = 2;
1502         }
1503         else
1504         {
1505             clkod = 1;
1506         }
1507         clkr = 1;
1508         clkf=(nMHz*clkr*clkod)/24;
1509         ret = (24*clkf)/(clkr*clkod);
1510     }
1511     else
1512     {
1513         SET_PLL_MODE(DPLL,0);            //PLL slow-mode
1514         dsb();
1515
1516         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
1517         ddr_delayus(1);
1518         pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
1519         pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
1520         pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
1521         ddr_delayus(1);
1522         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
1523         dsb();
1524         while (delay > 0)
1525         {
1526             ddr_delayus(1);
1527             if (GET_DPLL_LOCK_STATUS())
1528                 break;
1529             delay--;
1530         }
1531
1532         if(set == 1)
1533             SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1534         SET_PLL_MODE(DPLL,1);            //PLL normal
1535         dsb();
1536     }
1537     dsb();
1538 out:
1539     return ret;
1540 }
1541
1542 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1543 {
1544     return ddr_set_pll_rk3188_plus(nMHz,set);
1545 }
1546 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1547 static uint32 (*p_ddr_set_pll)(uint32 nMHz, uint32 set);
1548
1549 static void __sramfunc idle_port(void)
1550 {
1551     int i;
1552     uint32 clk_gate[14];
1553
1554     //save clock gate status
1555     for(i=0;i<14;i++)
1556         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1557
1558     //enable all clock gate for request idle
1559     for(i=0;i<14;i++)
1560         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1561
1562     pPMU_Reg->PMU_IDLE_REQ |= idle_req_dma_cfg;
1563     dsb();
1564     while(((pPMU_Reg->PMU_IDLE_ST) & idle_dma) == 0);
1565
1566     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
1567     {
1568         pPMU_Reg->PMU_IDLE_REQ |= idle_req_peri_cfg;
1569         dsb();
1570         while( (pPMU_Reg->PMU_IDLE_ST & idle_peri) == 0 );
1571     }
1572
1573     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
1574     {
1575         pPMU_Reg->PMU_IDLE_REQ |= idle_req_vio_cfg;
1576         dsb();
1577         while( (pPMU_Reg->PMU_IDLE_ST & idle_vio) == 0 );
1578     }
1579
1580     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
1581     {
1582         pPMU_Reg->PMU_IDLE_REQ |= idle_req_video_cfg;
1583         dsb();
1584         while( (pPMU_Reg->PMU_IDLE_ST & idle_video) == 0 );
1585     }
1586
1587     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
1588     {
1589         pPMU_Reg->PMU_IDLE_REQ |= idle_req_gpu_cfg;
1590         dsb();
1591         while( (pPMU_Reg->PMU_IDLE_ST & idle_gpu) == 0 );
1592     }
1593
1594     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_hevc_pwr_st) == 0 )
1595     {
1596         pPMU_Reg->PMU_IDLE_REQ |= idle_req_hevc_cfg;
1597         dsb();
1598         while( (pPMU_Reg->PMU_IDLE_ST & idle_hevc) == 0 );
1599     }
1600
1601     pPMU_Reg->PMU_IDLE_REQ |= idle_req_core_cfg;
1602     dsb();
1603     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) == 0 );
1604
1605     //resume clock gate status
1606     for(i=0;i<14;i++)
1607         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1608 }
1609
1610 static void __sramfunc deidle_port(void)
1611 {
1612     int i;
1613     uint32 clk_gate[14];
1614
1615     //save clock gate status
1616     for(i=0;i<14;i++)
1617         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1618
1619     //enable all clock gate for request idle
1620     for(i=0;i<14;i++)
1621         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1622
1623     pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_dma_cfg;
1624     dsb();
1625     while( (pPMU_Reg->PMU_IDLE_ST & idle_dma) != 0 );
1626
1627     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
1628     {
1629         pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_peri_cfg;
1630         dsb();
1631         while( (pPMU_Reg->PMU_IDLE_ST & idle_peri) != 0 );
1632     }
1633
1634     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
1635     {
1636         pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_vio_cfg;
1637         dsb();
1638         while( (pPMU_Reg->PMU_IDLE_ST & idle_vio) != 0 );
1639     }
1640
1641     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
1642     {
1643         pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_video_cfg;
1644         dsb();
1645         while( (pPMU_Reg->PMU_IDLE_ST & idle_video) != 0 );
1646     }
1647
1648     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
1649     {
1650         pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_gpu_cfg;
1651         dsb();
1652         while( (pPMU_Reg->PMU_IDLE_ST & idle_gpu) != 0 );
1653     }
1654
1655     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_hevc_pwr_st) == 0 )
1656     {
1657         pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_hevc_cfg;
1658         dsb();
1659         while( (pPMU_Reg->PMU_IDLE_ST & idle_hevc) != 0 );
1660     }
1661
1662     pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_core_cfg;
1663     dsb();
1664     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) != 0 );
1665
1666     //resume clock gate status
1667     for(i=0;i<14;i++)
1668         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1669
1670 }
1671
1672 /***********************************
1673  * Only DDR Relative Function
1674  ***********************************/
1675
1676 /****************************************************************************
1677 Internal sram us delay function
1678 Cpu highest frequency is 1.6 GHz
1679 1 cycle = 1/1.6 ns
1680 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1681 *****************************************************************************/
1682 __sramdata volatile uint32 loops_per_us;
1683
1684 #define LPJ_100MHZ  999456UL
1685
1686 static void __sramfunc ddr_delayus(uint32 us)
1687 {
1688     do
1689     {
1690         volatile unsigned int i = (loops_per_us*us);
1691         if (i < 7) i = 7;
1692         barrier();
1693         asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1694     } while (0);
1695 }
1696
1697 void PIE_FUNC(ddr_copy)(uint32 *pDest, uint32 *pSrc, uint32 words)
1698 {
1699     uint32 i;
1700
1701     for(i=0; i<words; i++)
1702     {
1703         pDest[i] = pSrc[i];
1704     }
1705 }
1706 EXPORT_PIE_SYMBOL(FUNC(ddr_copy));
1707
1708 static void ddr_get_datatraing_addr(uint32 *pdtar)
1709 {
1710     uint32          addr;
1711     uint32          stride;
1712     uint32          strideSize;
1713     uint32          halfCap;
1714     uint32          ch,chCnt;
1715     uint32          socAddr[2];
1716     uint32          chAddr[2];
1717     uint32          col;
1718     uint32          row;
1719     uint32          bank;
1720     uint32          bw;
1721     uint32          conf;
1722
1723     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1724     {
1725         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1726         {
1727             chCnt++;
1728         }
1729     }
1730
1731     // caculate aglined physical address
1732     addr =  __pa((unsigned long)ddr_data_training_buf);
1733     ddr_print("addr=0x%x\n",addr);
1734     if(addr&0x3F)
1735     {
1736         addr += (64-(addr&0x3F));  // 64byte align
1737     }
1738     addr -= DRAM_PHYS;
1739     if(chCnt > 1)
1740     {
1741         //find stride info
1742         stride = READ_DDR_STRIDE();
1743         strideSize = gStrideInfo[stride].size;
1744         halfCap = gStrideInfo[stride].halfCap;
1745         ddr_print("stride=%d, size=%d, halfcap=%x\n", stride,strideSize,halfCap);
1746         //get soc addr
1747         if(addr & strideSize)  // odd stride size
1748         {
1749             socAddr[0] = addr + strideSize;
1750             socAddr[1] = addr;
1751         }
1752         else
1753         {
1754             socAddr[0] = addr;
1755             socAddr[1] = addr + strideSize;
1756         }
1757         ddr_print("socAddr[0]=0x%x, socAddr[1]=0x%x\n", socAddr[0], socAddr[1]);
1758         if((stride >= 0x10) && (stride <= 0x13))  // 3GB stride
1759         {
1760             //conver to ch addr
1761             if(addr < 0x40000000)
1762             {
1763                 chAddr[0] = socAddr[0];
1764                 chAddr[1] = socAddr[1] - strideSize;
1765             }
1766             else if(addr < 0x80000000)
1767             {
1768                 chAddr[0] = socAddr[0] - 0x40000000 + strideSize;
1769                 chAddr[1] = socAddr[1] - 0x40000000;
1770             }
1771             else if(addr < 0xA0000000)
1772             {
1773                 chAddr[0] = socAddr[0] - 0x40000000;
1774                 chAddr[1] = socAddr[1] - 0x40000000 - strideSize;
1775             }
1776             else
1777             {
1778                 chAddr[0] = socAddr[0] - 0x60000000 + strideSize;
1779                 chAddr[1] = socAddr[1] - 0x60000000;
1780             }
1781         }
1782         else
1783         {
1784             //conver to ch addr
1785             if(addr <  halfCap)
1786             {
1787                 chAddr[0] = socAddr[0];
1788                 chAddr[1] = socAddr[1] - strideSize;
1789             }
1790             else
1791             {
1792                 chAddr[0] = socAddr[0] - halfCap + strideSize;
1793                 chAddr[1] = socAddr[1] - halfCap;
1794             }
1795         }
1796         ddr_print("chAddr[0]=0x%x, chAddr[1]=0x%x\n", chAddr[0], chAddr[1]);
1797     }
1798     else
1799     {
1800         chAddr[0] = addr;
1801         chAddr[1] = addr;
1802     }
1803
1804     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1805     {
1806         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1807         {
1808             // find out col£¬row£¬bank,config
1809             row = READ_ROW_INFO(ch,0);
1810             bank = READ_BK_INFO(ch);
1811             col = READ_COL_INFO(ch);
1812             bw = READ_BW_INFO(ch);
1813             conf = p_ddr_ch[ch]->pMSCH_Reg->ddrconf;
1814             // according different address mapping, caculate DTAR register value
1815             pdtar[ch] = 0;
1816             pdtar[ch] |= ((chAddr[ch])>>bw) & ((0x1<<col)-1);  // col
1817             pdtar[ch] |= (((chAddr[ch])>>(bw+col+((ddr_cfg_2_rbc[conf]>>2)&0x3))) & ((0x1<<row)-1)) << 12;  // row
1818             if(((ddr_cfg_2_rbc[conf]>>7)&0x3)==3)
1819             {
1820                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col+row)) & ((0x1<<bank)-1))  << 28);  // bank
1821             }
1822             else
1823             {
1824                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col)) & 0x7) << 28);  // bank
1825             }
1826         }
1827     }
1828     ddr_print("dtar[0]=0x%x, dtar[1]=0x%x\n", pdtar[0], pdtar[1]);
1829 }
1830
1831 static __sramfunc void ddr_reset_dll(uint32 ch)
1832 {
1833     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1834     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1835
1836     pPHY_Reg->ACDLLCR &= ~0x40000000;
1837     pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1838     pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1839     if(!(pDDR_Reg->PPCFG & 1))
1840     {
1841         pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1842         pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1843     }
1844     ddr_delayus(1);
1845     pPHY_Reg->ACDLLCR |= 0x40000000;
1846     pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1847     pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1848     if(!(pDDR_Reg->PPCFG & 1))
1849     {
1850         pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1851         pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1852     }
1853     ddr_delayus(1);
1854 }
1855
1856 static __sramfunc void ddr_move_to_Lowpower_state(uint32 ch)
1857 {
1858     volatile uint32 value;
1859     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1860
1861     while(1)
1862     {
1863         value = pDDR_Reg->STAT.b.ctl_stat;
1864         if(value == Low_power)
1865         {
1866             break;
1867         }
1868         switch(value)
1869         {
1870             case Init_mem:
1871                 pDDR_Reg->SCTL = CFG_STATE;
1872                 dsb();
1873                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1874             case Config:
1875                 pDDR_Reg->SCTL = GO_STATE;
1876                 dsb();
1877                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1878             case Access:
1879                 pDDR_Reg->SCTL = SLEEP_STATE;
1880                 dsb();
1881                 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1882                 break;
1883             default:  //Transitional state
1884                 break;
1885         }
1886     }
1887 }
1888
1889 static __sramfunc void ddr_move_to_Access_state(uint32 ch)
1890 {
1891     volatile uint32 value;
1892     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1893     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1894
1895     //set auto self-refresh idle
1896     pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00) | DATA(ddr_sr_idle) | (1<<31);
1897     dsb();
1898
1899     while(1)
1900     {
1901         value = pDDR_Reg->STAT.b.ctl_stat;
1902         if((value == Access)
1903            || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1904         {
1905             break;
1906         }
1907         switch(value)
1908         {
1909             case Low_power:
1910                 pDDR_Reg->SCTL = WAKEUP_STATE;
1911                 dsb();
1912                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1913                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1914                 break;
1915             case Init_mem:
1916                 pDDR_Reg->SCTL = CFG_STATE;
1917                 dsb();
1918                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1919             case Config:
1920                 pDDR_Reg->SCTL = GO_STATE;
1921                 dsb();
1922                 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1923                       || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1924                 break;
1925             default:  //Transitional state
1926                 break;
1927         }
1928     }
1929     /* de_hw_wakeup :enable auto sr if sr_idle != 0 */
1930     DDR_HW_WAKEUP(ch,0);
1931 }
1932
1933 static __sramfunc void ddr_move_to_Config_state(uint32 ch)
1934 {
1935     volatile uint32 value;
1936     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1937     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1938
1939     /* hw_wakeup :disable auto sr */
1940     DDR_HW_WAKEUP(ch,1);
1941         dsb();
1942
1943     while(1)
1944     {
1945         value = pDDR_Reg->STAT.b.ctl_stat;
1946         if(value == Config)
1947         {
1948             break;
1949         }
1950         switch(value)
1951         {
1952             case Low_power:
1953                 pDDR_Reg->SCTL = WAKEUP_STATE;
1954                 dsb();
1955                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1956                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1957             case Access:
1958             case Init_mem:
1959                 pDDR_Reg->SCTL = CFG_STATE;
1960                 dsb();
1961                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1962                 break;
1963             default:  //Transitional state
1964                 break;
1965         }
1966     }
1967 }
1968
1969 //arg°üÀ¨bank_addrºÍcmd_addr
1970 static void __sramfunc ddr_send_command(uint32 ch, uint32 rank, uint32 cmd, uint32 arg)
1971 {
1972     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1973
1974     pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1975     dsb();
1976     while(pDDR_Reg->MCMD & start_cmd);
1977 }
1978
1979 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
1980 //0  DTT³É¹¦
1981 //!0 DTTÊ§°Ü
1982 static uint32 __sramfunc ddr_data_training(uint32 ch)
1983 {
1984     uint32        value,cs,i,byte=2;
1985     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1986     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1987
1988     // disable auto refresh
1989     value = pDDR_Reg->TREFI;
1990     pDDR_Reg->TREFI = 0;
1991     dsb();
1992     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
1993        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
1994     {
1995         // passive window
1996         pPHY_Reg->PGCR |= (1<<1);
1997     }
1998     // clear DTDONE status
1999     pPHY_Reg->PIR |= CLRSR;
2000     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2001     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18);  //use cs0 dtt
2002     // trigger DTT
2003     pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
2004     dsb();
2005     // wait echo byte DTDONE
2006     while((pPHY_Reg->DATX8[0].DXGSR[0] & 1) != 1);
2007     while((pPHY_Reg->DATX8[1].DXGSR[0] & 1) != 1);
2008     if(!(pDDR_Reg->PPCFG & 1))
2009     {
2010         while((pPHY_Reg->DATX8[2].DXGSR[0] & 1) != 1);
2011         while((pPHY_Reg->DATX8[3].DXGSR[0] & 1) != 1);
2012         byte=4;
2013     }
2014     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18);  //restore cs
2015     for(i=0;i<byte;i++)
2016     {
2017         pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))
2018                                       | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)
2019                                       | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
2020     }
2021     // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×î³¤Ê±¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
2022     if(cs > 1)
2023     {
2024         ddr_send_command(ch,cs, REF_cmd, 0);
2025         ddr_send_command(ch,cs, REF_cmd, 0);
2026         ddr_send_command(ch,cs, REF_cmd, 0);
2027         ddr_send_command(ch,cs, REF_cmd, 0);
2028     }
2029     else
2030     {
2031         ddr_send_command(ch,cs, REF_cmd, 0);
2032         ddr_send_command(ch,cs, REF_cmd, 0);
2033     }
2034     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
2035        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
2036     {
2037         // active window
2038         pPHY_Reg->PGCR &= ~(1<<1);
2039     }
2040     // resume auto refresh
2041     pDDR_Reg->TREFI = value;
2042
2043     if(pPHY_Reg->PGSR & DTERR)
2044     {
2045         return (-1);
2046     }
2047     else
2048     {
2049         return 0;
2050     }
2051 }
2052
2053 static void __sramfunc ddr_set_dll_bypass(uint32 ch, uint32 freq)
2054 {
2055     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2056     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2057
2058     if(freq<=150)
2059     {
2060         pPHY_Reg->DLLGCR &= ~(1<<23);
2061         pPHY_Reg->ACDLLCR |= 0x80000000;
2062         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2063         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2064         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2065         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2066         pPHY_Reg->PIR |= DLLBYP;
2067     }
2068     else if(freq<=250)
2069     {
2070         pPHY_Reg->DLLGCR |= (1<<23);
2071         pPHY_Reg->ACDLLCR |= 0x80000000;
2072         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2073         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2074         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2075         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2076         pPHY_Reg->PIR |= DLLBYP;
2077     }
2078     else
2079     {
2080         pPHY_Reg->DLLGCR &= ~(1<<23);
2081         pPHY_Reg->ACDLLCR &= ~0x80000000;
2082         pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
2083         pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
2084         if(!(pDDR_Reg->PPCFG & 1))
2085         {
2086             pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
2087             pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
2088         }
2089         pPHY_Reg->PIR &= ~DLLBYP;
2090     }
2091 }
2092
2093 static noinline uint32 ddr_get_parameter(uint32 nMHz)
2094 {
2095     uint32 tmp;
2096     uint32 ret = 0;
2097     uint32 al;
2098     uint32 bl,bl_tmp;
2099     uint32 cl;
2100     uint32 cwl;
2101     PCTL_TIMING_T *p_pctl_timing=&(p_ddr_reg->pctl.pctl_timing);
2102     PHY_TIMING_T  *p_publ_timing=&(p_ddr_reg->publ.phy_timing);
2103     NOC_TIMING_T  *p_noc_timing=&(p_ddr_reg->noc[0].ddrtiming);
2104     NOC_ACTIVATE_T  *p_noc_activate=&(p_ddr_reg->noc[0].activate);
2105     uint32 ch;
2106     uint32 mem_type;
2107     uint32 ddr_speed_bin=DDR3_DEFAULT;
2108     uint32 ddr_capability_per_die=0;
2109
2110     for(ch=0;ch<CH_MAX;ch++)
2111     {
2112         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
2113         {
2114             mem_type = p_ddr_ch[ch]->mem_type;
2115             if(ddr_speed_bin == DDR3_DEFAULT)
2116             {
2117                 ddr_speed_bin = p_ddr_ch[ch]->ddr_speed_bin;
2118             }
2119             else
2120             {
2121                 ddr_speed_bin = (ddr_speed_bin > p_ddr_ch[ch]->ddr_speed_bin) ? ddr_speed_bin : p_ddr_ch[ch]->ddr_speed_bin;
2122             }
2123             if(ddr_capability_per_die == 0)
2124             {
2125                 ddr_capability_per_die = p_ddr_ch[ch]->ddr_capability_per_die;
2126             }
2127             else
2128             {
2129                 ddr_capability_per_die = (ddr_capability_per_die > p_ddr_ch[ch]->ddr_capability_per_die) ? ddr_capability_per_die : p_ddr_ch[ch]->ddr_capability_per_die;
2130             }
2131             break;
2132         }
2133     }
2134
2135     p_pctl_timing->togcnt1u = nMHz;
2136     p_pctl_timing->togcnt100n = nMHz/10;
2137     p_pctl_timing->tinit = 200;
2138     p_pctl_timing->trsth = 500;
2139
2140     if(mem_type == DDR3)
2141     {
2142         if(ddr_speed_bin > DDR3_DEFAULT){
2143             ret = -1;
2144             goto out;
2145         }
2146
2147         #define DDR3_tREFI_7_8_us    (78)  //unit 100ns
2148         #define DDR3_tMRD            (4)   //tCK
2149         #define DDR3_tRFC_512Mb      (90)  //ns
2150         #define DDR3_tRFC_1Gb        (110) //ns
2151         #define DDR3_tRFC_2Gb        (160) //ns
2152         #define DDR3_tRFC_4Gb        (300) //ns
2153         #define DDR3_tRFC_8Gb        (350) //ns
2154         #define DDR3_tRTW            (2)   //register min valid value
2155         #define DDR3_tRAS            (37)  //ns
2156         #define DDR3_tRRD            (10)  //ns
2157         #define DDR3_tRTP            (7)   //ns
2158         #define DDR3_tWR             (15)  //ns
2159         #define DDR3_tWTR            (7)   //ns
2160         #define DDR3_tXP             (7)   //ns
2161         #define DDR3_tXPDLL          (24)  //ns
2162         #define DDR3_tZQCS           (80)  //ns
2163         #define DDR3_tZQCSI          (0)   //ns
2164         #define DDR3_tDQS            (1)   //tCK
2165         #define DDR3_tCKSRE          (10)  //ns
2166         #define DDR3_tCKE_400MHz     (7)   //ns
2167         #define DDR3_tCKE_533MHz     (6)   //ns
2168         #define DDR3_tMOD            (15)  //ns
2169         #define DDR3_tRSTL           (100) //ns
2170         #define DDR3_tZQCL           (320) //ns
2171         #define DDR3_tDLLK           (512) //tCK
2172
2173         al = 0;
2174         bl = 8;
2175         if(nMHz <= 330)
2176         {
2177             tmp = 0;
2178         }
2179         else if(nMHz<=400)
2180         {
2181             tmp = 1;
2182         }
2183         else if(nMHz<=533)
2184         {
2185             tmp = 2;
2186         }
2187         else if(nMHz<=666)
2188         {
2189             tmp = 3;
2190         }
2191         else if(nMHz<=800)
2192         {
2193             tmp = 4;
2194         }
2195         else if(nMHz<=933)
2196         {
2197             tmp = 5;
2198         }
2199         else
2200         {
2201             tmp = 6;
2202         }
2203
2204         if(nMHz < 300)       //when dll bypss cl = cwl = 6;
2205         {
2206             cl = 6;
2207             cwl = 6;
2208         }
2209         else
2210         {
2211             cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
2212             cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
2213         }
2214         if(cl == 0)
2215             ret = -4;
2216         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2217         {
2218             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
2219         }
2220         else
2221         {
2222             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
2223         }
2224         p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
2225         p_publ_timing->mr[3] = 0;
2226         /**************************************************
2227          * PCTL Timing
2228          **************************************************/
2229         /*
2230          * tREFI, average periodic refresh interval, 7.8us
2231          */
2232         p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
2233         /*
2234          * tMRD, 4 tCK
2235          */
2236         p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
2237         p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
2238         /*
2239          * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
2240          */
2241         if(ddr_capability_per_die <= 0x4000000)         // 512Mb 90ns
2242         {
2243             tmp = DDR3_tRFC_512Mb;
2244         }
2245         else if(ddr_capability_per_die <= 0x8000000)    // 1Gb 110ns
2246         {
2247             tmp = DDR3_tRFC_1Gb;
2248         }
2249         else if(ddr_capability_per_die <= 0x10000000)   // 2Gb 160ns
2250         {
2251             tmp = DDR3_tRFC_2Gb;
2252         }
2253         else if(ddr_capability_per_die <= 0x20000000)   // 4Gb 300ns
2254         {
2255             tmp = DDR3_tRFC_4Gb;
2256         }
2257         else    // 8Gb  350ns
2258         {
2259             tmp = DDR3_tRFC_8Gb;
2260         }
2261         p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2262         p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000);
2263         /*
2264          * tXSR, =tDLLK=512 tCK
2265          */
2266         p_pctl_timing->texsr = DDR3_tDLLK;
2267         p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
2268         /*
2269          * tRP=CL
2270          */
2271         p_pctl_timing->trp = cl;
2272         p_publ_timing->dtpr0.b.tRP = cl;
2273         /*
2274          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2275          */
2276         p_noc_timing->b.WrToMiss = (cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl);
2277         /*
2278          * tRC=tRAS+tRP
2279          */
2280         p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2281         p_noc_timing->b.ActToAct = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2282         p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2283
2284         p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
2285         p_publ_timing->dtpr1.b.tRTW = 0;
2286         p_noc_timing->b.RdToWr = (cl+2-cwl);
2287         p_pctl_timing->tal = al;
2288         p_pctl_timing->tcl = cl;
2289         p_pctl_timing->tcwl = cwl;
2290         /*
2291          * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
2292          */
2293         p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
2294         p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000);
2295         /*
2296          * tRCD=CL
2297          */
2298         p_pctl_timing->trcd = cl;
2299         p_publ_timing->dtpr0.b.tRCD = cl;
2300         /*
2301          * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2302          *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2303          *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2304          *
2305          */
2306         tmp = ((DDR3_tRRD*nMHz+999)/1000);
2307         if(tmp < 4)
2308         {
2309             tmp = 4;
2310         }
2311         p_pctl_timing->trrd = (tmp&0xF);
2312         p_publ_timing->dtpr0.b.tRRD = tmp;
2313         p_noc_activate->b.Rrd = tmp;
2314         /*
2315          * tRTP, max(4 tCK,7.5ns)
2316          */
2317         tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2318         if(tmp < 4)
2319         {
2320             tmp = 4;
2321         }
2322         p_pctl_timing->trtp = tmp&0xF;
2323         p_publ_timing->dtpr0.b.tRTP = tmp;
2324         /*
2325          * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2326          */
2327         p_noc_timing->b.RdToMiss = (tmp+cl+cl-(bl>>1));
2328         /*
2329          * tWR, 15ns
2330          */
2331         tmp = ((DDR3_tWR*nMHz+999)/1000);
2332         p_pctl_timing->twr = tmp&0x1F;
2333         if(tmp<9)
2334         {
2335             tmp = tmp - 4;
2336         }
2337         else
2338         {
2339             tmp += (tmp&0x1) ? 1:0;
2340             tmp = tmp>>1;
2341         }
2342         bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2343         p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2344
2345         /*
2346          * tWTR, max(4 tCK,7.5ns)
2347          */
2348         tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2349         if(tmp < 4)
2350         {
2351             tmp = 4;
2352         }
2353         p_pctl_timing->twtr = tmp&0xF;
2354         p_publ_timing->dtpr0.b.tWTR = tmp;
2355         /*
2356          * WrToRd=WL+tWTR
2357          */
2358         p_noc_timing->b.WrToRd = (tmp+cwl);
2359         /*
2360          * tXP, max(3 tCK, 7.5ns)(<933MHz)
2361          */
2362         tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2363         if(tmp < 3)
2364         {
2365             tmp = 3;
2366         }
2367         p_pctl_timing->txp = tmp&0x7;
2368         /*
2369          * tXPDLL, max(10 tCK,24ns)
2370          */
2371         tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2372         if(tmp < 10)
2373         {
2374             tmp = 10;
2375         }
2376         p_pctl_timing->txpdll = tmp & 0x3F;
2377         p_publ_timing->dtpr2.b.tXP = tmp;
2378         /*
2379          * tZQCS, max(64 tCK, 80ns)
2380          */
2381         tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2382         if(tmp < 64)
2383         {
2384             tmp = 64;
2385         }
2386         p_pctl_timing->tzqcs = tmp&0x7F;
2387         /*
2388          * tZQCSI,
2389          */
2390         p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2391         /*
2392          * tDQS,
2393          */
2394         p_pctl_timing->tdqs = DDR3_tDQS;
2395         /*
2396          * tCKSRE, max(5 tCK, 10ns)
2397          */
2398         tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2399         if(tmp < 5)
2400         {
2401             tmp = 5;
2402         }
2403         p_pctl_timing->tcksre = tmp & 0x1F;
2404         /*
2405          * tCKSRX, max(5 tCK, 10ns)
2406          */
2407         p_pctl_timing->tcksrx = tmp & 0x1F;
2408         /*
2409          * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2410          */
2411         if(nMHz>=533)
2412         {
2413             tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2414         }
2415         else
2416         {
2417             tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2418         }
2419         if(tmp < 3)
2420         {
2421             tmp = 3;
2422         }
2423         p_pctl_timing->tcke = tmp & 0x7;
2424         /*
2425          * tCKESR, =tCKE + 1tCK
2426          */
2427         p_pctl_timing->tckesr = (tmp+1)&0xF;
2428         p_publ_timing->dtpr2.b.tCKE = tmp+1;
2429         /*
2430          * tMOD, max(12 tCK,15ns)
2431          */
2432         tmp = ((DDR3_tMOD*nMHz+999)/1000);
2433         if(tmp < 12)
2434         {
2435             tmp = 12;
2436         }
2437         p_pctl_timing->tmod = tmp&0x1F;
2438         p_publ_timing->dtpr1.b.tMOD = (tmp-12);
2439         /*
2440          * tRSTL, 100ns
2441          */
2442         p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2443         /*
2444          * tZQCL, max(256 tCK, 320ns)
2445          */
2446         tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2447         if(tmp < 256)
2448         {
2449             tmp = 256;
2450         }
2451         p_pctl_timing->tzqcl = tmp&0x3FF;
2452         /*
2453          * tMRR, 0 tCK
2454          */
2455         p_pctl_timing->tmrr = 0;
2456         /*
2457          * tDPD, 0
2458          */
2459         p_pctl_timing->tdpd = 0;
2460
2461         /**************************************************
2462          * PHY Timing
2463          **************************************************/
2464         /*
2465          * tCCD, BL/2 for DDR2 and 4 for DDR3
2466          */
2467         p_publ_timing->dtpr0.b.tCCD = 0;
2468         /*
2469          * tDQSCKmax,5.5ns
2470          */
2471         p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2472         /*
2473          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2474          *         1:ODT may not be turned on until one clock after the read post-amble
2475          */
2476         p_publ_timing->dtpr1.b.tRTODT = 1;
2477         /*
2478          * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page)   50ns(533MHz 2KB page)
2479          */
2480         tmp = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000);
2481         p_publ_timing->dtpr1.b.tFAW = tmp;
2482         p_noc_activate->b.Fawbank = 1;
2483         p_noc_activate->b.Faw = tmp;
2484         /*
2485          * tAOND_tAOFD
2486          */
2487         p_publ_timing->dtpr1.b.tAOND = 0;
2488         /*
2489          * tDLLK,512 tCK
2490          */
2491         p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2492         /**************************************************
2493          * NOC Timing
2494          **************************************************/
2495         p_noc_timing->b.BurstLen = (bl>>1);
2496     }
2497     else if(mem_type == LPDDR2)
2498     {
2499         #define LPDDR2_tREFI_3_9_us    (38)  //unit 100ns
2500         #define LPDDR2_tREFI_7_8_us    (78)  //unit 100ns
2501         #define LPDDR2_tMRD            (5)   //tCK
2502         #define LPDDR2_tRFC_8Gb        (210)  //ns
2503         #define LPDDR2_tRFC_4Gb        (130)  //ns
2504         #define LPDDR2_tRPpb_4_BANK             (24)  //ns
2505         #define LPDDR2_tRPab_SUB_tRPpb_4_BANK   (0)   //ns
2506         #define LPDDR2_tRPpb_8_BANK             (24)  //ns
2507         #define LPDDR2_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2508         #define LPDDR2_tRTW          (1)   //tCK register min valid value
2509         #define LPDDR2_tRAS          (42)  //ns
2510         #define LPDDR2_tRCD          (24)  //ns
2511         #define LPDDR2_tRRD          (10)  //ns
2512         #define LPDDR2_tRTP          (7)   //ns
2513         #define LPDDR2_tWR           (15)  //ns
2514         #define LPDDR2_tWTR_GREAT_200MHz         (7)  //ns
2515         #define LPDDR2_tWTR_LITTLE_200MHz        (10) //ns
2516         #define LPDDR2_tXP           (7)  //ns
2517         #define LPDDR2_tXPDLL        (0)
2518         #define LPDDR2_tZQCS         (90) //ns
2519         #define LPDDR2_tZQCSI        (0)
2520         #define LPDDR2_tDQS          (1)
2521         #define LPDDR2_tCKSRE        (1)  //tCK
2522         #define LPDDR2_tCKSRX        (2)  //tCK
2523         #define LPDDR2_tCKE          (3)  //tCK
2524         #define LPDDR2_tMOD          (0)
2525         #define LPDDR2_tRSTL         (0)
2526         #define LPDDR2_tZQCL         (360)  //ns
2527         #define LPDDR2_tMRR          (2)    //tCK
2528         #define LPDDR2_tCKESR        (15)   //ns
2529         #define LPDDR2_tDPD_US       (500)  //us
2530         #define LPDDR2_tFAW_GREAT_200MHz    (50)  //ns
2531         #define LPDDR2_tFAW_LITTLE_200MHz   (60)  //ns
2532         #define LPDDR2_tDLLK         (2)  //tCK
2533         #define LPDDR2_tDQSCK_MAX    (3)  //tCK
2534         #define LPDDR2_tDQSCK_MIN    (0)  //tCK
2535         #define LPDDR2_tDQSS         (1)  //tCK
2536
2537         uint32 trp_tmp;
2538         uint32 trcd_tmp;
2539         uint32 tras_tmp;
2540         uint32 trtp_tmp;
2541         uint32 twr_tmp;
2542
2543         al = 0;
2544         if(nMHz>=200)
2545         {
2546             bl = 4;  //you can change burst here
2547         }
2548         else
2549         {
2550             bl = 8;  // freq < 200MHz, BL fixed 8
2551         }
2552         /*     1066 933 800 667 533 400 333
2553          * RL,   8   7   6   5   4   3   3
2554          * WL,   4   4   3   2   2   1   1
2555          */
2556         if(nMHz<=200)
2557         {
2558             cl = 3;
2559             cwl = 1;
2560             p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2561         }
2562         else if(nMHz<=266)
2563         {
2564             cl = 4;
2565             cwl = 2;
2566             p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2567         }
2568         else if(nMHz<=333)
2569         {
2570             cl = 5;
2571             cwl = 2;
2572             p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2573         }
2574         else if(nMHz<=400)
2575         {
2576             cl = 6;
2577             cwl = 3;
2578             p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2579         }
2580         else if(nMHz<=466)
2581         {
2582             cl = 7;
2583             cwl = 4;
2584             p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2585         }
2586         else //(nMHz<=1066)
2587         {
2588             cl = 8;
2589             cwl = 4;
2590             p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2591         }
2592         p_publ_timing->mr[3] = LPDDR2_DS_34;
2593         p_publ_timing->mr[0] = 0;
2594         /**************************************************
2595          * PCTL Timing
2596          **************************************************/
2597         /*
2598          * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2599          */
2600         if(ddr_capability_per_die >= 0x10000000)   // 2Gb
2601         {
2602             p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2603         }
2604         else
2605         {
2606             p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2607         }
2608
2609         /*
2610          * tMRD, (=tMRW), 5 tCK
2611          */
2612         p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2613         p_publ_timing->dtpr0.b.tMRD = 3;
2614         /*
2615          * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2616          */
2617         if(ddr_capability_per_die >= 0x40000000)   // 8Gb
2618         {
2619             p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2620             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000);
2621             /*
2622              * tXSR, max(2tCK,tRFC+10ns)
2623              */
2624             tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
2625         }
2626         else
2627         {
2628             p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2629             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000);
2630             tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
2631         }
2632         if(tmp<2)
2633         {
2634             tmp=2;
2635         }
2636         p_pctl_timing->texsr = tmp&0x3FF;
2637         p_publ_timing->dtpr2.b.tXS = tmp;
2638
2639         /*
2640          * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
2641          */
2642         //if(pPHY_Reg->DCR.b.DDR8BNK)
2643         if(1)
2644         {
2645             trp_tmp = ((LPDDR2_tRPpb_8_BANK*nMHz+999)/1000);
2646             if(trp_tmp<3)
2647             {
2648                 trp_tmp=3;
2649             }
2650             p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
2651         }
2652         else
2653         {
2654             trp_tmp = ((LPDDR2_tRPpb_4_BANK*nMHz+999)/1000);
2655             if(trp_tmp<3)
2656             {
2657                 trp_tmp=3;
2658             }
2659             p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
2660         }
2661         p_publ_timing->dtpr0.b.tRP = trp_tmp;
2662         /*
2663          * tRAS, max(3tCK,42ns)
2664          */
2665         tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
2666         if(tras_tmp<3)
2667         {
2668             tras_tmp=3;
2669         }
2670         p_pctl_timing->tras = (tras_tmp&0x3F);
2671         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
2672
2673         /*
2674          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
2675          */
2676         trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
2677         if(trcd_tmp<3)
2678         {
2679             trcd_tmp=3;
2680         }
2681         p_pctl_timing->trcd = (trcd_tmp&0xF);
2682         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
2683
2684         /*
2685          * tRTP, max(2tCK, 7.5ns)
2686          */
2687         trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2688         if(trtp_tmp<2)
2689         {
2690             trtp_tmp = 2;
2691         }
2692         p_pctl_timing->trtp = trtp_tmp&0xF;
2693         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
2694
2695         /*
2696          * tWR, max(3tCK,15ns)
2697          */
2698         twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
2699         if(twr_tmp<3)
2700         {
2701             twr_tmp=3;
2702         }
2703         p_pctl_timing->twr = twr_tmp&0x1F;
2704         bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2705         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
2706
2707         /*
2708          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2709          */
2710         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
2711         /*
2712          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2713          */
2714         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
2715         /*
2716          * tRC=tRAS+tRP
2717          */
2718         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
2719         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
2720         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
2721
2722         /*
2723          * RdToWr=(cl+2-cwl)
2724          */
2725         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
2726         p_publ_timing->dtpr1.b.tRTW = 0;
2727         p_noc_timing->b.RdToWr = (cl+2-cwl);
2728         p_pctl_timing->tal = al;
2729         p_pctl_timing->tcl = cl;
2730         p_pctl_timing->tcwl = cwl;
2731         /*
2732          * tRRD, max(2tCK,10ns)
2733          */
2734         tmp=((LPDDR2_tRRD*nMHz+999)/1000);
2735         if(tmp<2)
2736         {
2737             tmp=2;
2738         }
2739         p_pctl_timing->trrd = (tmp&0xF);
2740         p_publ_timing->dtpr0.b.tRRD = tmp;
2741         p_noc_activate->b.Rrd = tmp;
2742         /*
2743          * tWTR, max(2tCK, 7.5ns(533-266MHz)  10ns(200-166MHz))
2744          */
2745         if(nMHz > 200)
2746         {
2747             tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2748         }
2749         else
2750         {
2751             tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2752         }
2753         if(tmp<2)
2754         {
2755             tmp=2;
2756         }
2757         p_pctl_timing->twtr = tmp&0xF;
2758         p_publ_timing->dtpr0.b.tWTR = tmp;
2759         /*
2760          * WrToRd=WL+tWTR
2761          */
2762         p_noc_timing->b.WrToRd = (cwl+tmp);
2763         /*
2764          * tXP, max(2tCK,7.5ns)
2765          */
2766         tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
2767         if(tmp<2)
2768         {
2769             tmp=2;
2770         }
2771         p_pctl_timing->txp = tmp&0x7;
2772         p_publ_timing->dtpr2.b.tXP = tmp;
2773         /*
2774          * tXPDLL, 0ns
2775          */
2776         p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2777         /*
2778          * tZQCS, 90ns
2779          */
2780         p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2781         /*
2782          * tZQCSI,
2783          */
2784         //if(pDDR_Reg->MCFG &= lpddr2_s4)
2785         if(1)
2786         {
2787             p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2788         }
2789         else
2790         {
2791             p_pctl_timing->tzqcsi = 0;
2792         }
2793         /*
2794          * tDQS,
2795          */
2796         p_pctl_timing->tdqs = LPDDR2_tDQS;
2797         /*
2798          * tCKSRE, 1 tCK
2799          */
2800         p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2801         /*
2802          * tCKSRX, 2 tCK
2803          */
2804         p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2805         /*
2806          * tCKE, 3 tCK
2807          */
2808         p_pctl_timing->tcke = LPDDR2_tCKE;
2809         p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2810         /*
2811          * tMOD, 0 tCK
2812          */
2813         p_pctl_timing->tmod = LPDDR2_tMOD;
2814         p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2815         /*
2816          * tRSTL, 0 tCK
2817          */
2818         p_pctl_timing->trstl = LPDDR2_tRSTL;
2819         /*
2820          * tZQCL, 360ns
2821          */
2822         p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2823         /*
2824          * tMRR, 2 tCK
2825          */
2826         p_pctl_timing->tmrr = LPDDR2_tMRR;
2827         /*
2828          * tCKESR, max(3tCK,15ns)
2829          */
2830         tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
2831         if(tmp < 3)
2832         {
2833             tmp = 3;
2834         }
2835         p_pctl_timing->tckesr = tmp&0xF;
2836         /*
2837          * tDPD, 500us
2838          */
2839         p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2840
2841         /**************************************************
2842          * PHY Timing
2843          **************************************************/
2844         /*
2845          * tCCD, BL/2 for DDR2 and 4 for DDR3
2846          */
2847         p_publ_timing->dtpr0.b.tCCD = 0;
2848         /*
2849          * tDQSCKmax,5.5ns
2850          */
2851         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2852         /*
2853          * tDQSCKmin,2.5ns
2854          */
2855         p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2856         /*
2857          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2858          *         1:ODT may not be turned on until one clock after the read post-amble
2859          */
2860         p_publ_timing->dtpr1.b.tRTODT = 1;
2861         /*
2862          * tFAW,max(8tCK, 50ns(200-533MHz)  60ns(166MHz))
2863          */
2864         if(nMHz>=200)
2865         {
2866             tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
2867         }
2868         else
2869         {
2870             tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
2871         }
2872         if(tmp<8)
2873         {
2874             tmp=8;
2875         }
2876         p_publ_timing->dtpr1.b.tFAW = tmp;
2877         p_noc_activate->b.Fawbank = 1;
2878         p_noc_activate->b.Faw = tmp;
2879         /*
2880          * tAOND_tAOFD
2881          */
2882         p_publ_timing->dtpr1.b.tAOND = 0;
2883         /*
2884          * tDLLK,0
2885          */
2886         p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2887         /**************************************************
2888          * NOC Timing
2889          **************************************************/
2890         p_noc_timing->b.BurstLen = (bl>>1);
2891     }
2892     else if(mem_type == LPDDR3)
2893     {
2894         #define LPDDR3_tREFI_3_9_us    (38)  //unit 100ns
2895         #define LPDDR3_tMRD            (10)   //tCK
2896         #define LPDDR3_tRFC_8Gb        (210)  //ns
2897         #define LPDDR3_tRFC_4Gb        (130)  //ns
2898         #define LPDDR3_tRPpb_8_BANK             (24)  //ns
2899         #define LPDDR3_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2900         #define LPDDR3_tRTW          (1)   //tCK register min valid value
2901         #define LPDDR3_tRAS          (42)  //ns
2902         #define LPDDR3_tRCD          (24)  //ns
2903         #define LPDDR3_tRRD          (10)  //ns
2904         #define LPDDR3_tRTP          (7)   //ns
2905         #define LPDDR3_tWR           (15)  //ns
2906         #define LPDDR3_tWTR          (7)  //ns
2907         #define LPDDR3_tXP           (7)  //ns
2908         #define LPDDR3_tXPDLL        (0)
2909         #define LPDDR3_tZQCS         (90) //ns
2910         #define LPDDR3_tZQCSI        (0)
2911         #define LPDDR3_tDQS          (1)
2912         #define LPDDR3_tCKSRE        (2)  //tCK
2913         #define LPDDR3_tCKSRX        (2)  //tCK
2914         #define LPDDR3_tCKE          (3)  //tCK
2915         #define LPDDR3_tMOD          (0)
2916         #define LPDDR3_tRSTL         (0)
2917         #define LPDDR3_tZQCL         (360)  //ns
2918         #define LPDDR3_tMRR          (4)    //tCK
2919         #define LPDDR3_tCKESR        (15)   //ns
2920         #define LPDDR3_tDPD_US       (500)   //us
2921         #define LPDDR3_tFAW          (50)  //ns
2922         #define LPDDR3_tDLLK         (2)  //tCK
2923         #define LPDDR3_tDQSCK_MAX    (3)  //tCK
2924         #define LPDDR3_tDQSCK_MIN    (0)  //tCK
2925         #define LPDDR3_tDQSS         (1)  //tCK
2926
2927         uint32 trp_tmp;
2928         uint32 trcd_tmp;
2929         uint32 tras_tmp;
2930         uint32 trtp_tmp;
2931         uint32 twr_tmp;
2932
2933         al = 0;
2934         bl = 8;
2935         /* Only support Write Latency Set A here
2936          *     1066 933 800 733 667 600 533 400 166
2937          * RL,   16  14  12  11  10  9   8   6   3
2938          * WL,   8   8   6   6   6   5   4   3   1
2939          */
2940         if(nMHz<=166)
2941         {
2942             cl = 3;
2943             cwl = 1;
2944             p_publ_timing->mr[2] = LPDDR3_RL3_WL1;
2945         }
2946         else if(nMHz<=400)
2947         {
2948             cl = 6;
2949             cwl = 3;
2950             p_publ_timing->mr[2] = LPDDR3_RL6_WL3;
2951         }
2952         else if(nMHz<=533)
2953         {
2954             cl = 8;
2955             cwl = 4;
2956             p_publ_timing->mr[2] = LPDDR3_RL8_WL4;
2957         }
2958         else if(nMHz<=600)
2959         {
2960             cl = 9;
2961             cwl = 5;
2962             p_publ_timing->mr[2] = LPDDR3_RL9_WL5;
2963         }
2964         else if(nMHz<=667)
2965         {
2966             cl = 10;
2967             cwl = 6;
2968             p_publ_timing->mr[2] = LPDDR3_RL10_WL6;
2969         }
2970         else if(nMHz<=733)
2971         {
2972             cl = 11;
2973             cwl = 6;
2974             p_publ_timing->mr[2] = LPDDR3_RL11_WL6;
2975         }
2976         else if(nMHz<=800)
2977         {
2978             cl = 12;
2979             cwl = 6;
2980             p_publ_timing->mr[2] = LPDDR3_RL12_WL6;
2981         }
2982         else if(nMHz<=933)
2983         {
2984             cl = 14;
2985             cwl = 8;
2986             p_publ_timing->mr[2] = LPDDR3_RL14_WL8;
2987         }
2988         else //(nMHz<=1066)
2989         {
2990             cl = 16;
2991             cwl = 8;
2992             p_publ_timing->mr[2] = LPDDR3_RL16_WL8;
2993         }
2994         p_publ_timing->mr[3] = LPDDR3_DS_34;
2995         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2996         {
2997             p_publ_timing->mr11 = LPDDR3_ODT_DIS;
2998         }
2999         else
3000         {
3001             p_publ_timing->mr11 = LPDDR3_ODT_240;
3002         }
3003         p_publ_timing->mr[0] = 0;
3004         /**************************************************
3005          * PCTL Timing
3006          **************************************************/
3007         /*
3008          * tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb)
3009          */
3010         p_pctl_timing->trefi = LPDDR3_tREFI_3_9_us;
3011
3012         /*
3013          * tMRD, (=tMRW), 10 tCK
3014          */
3015         p_pctl_timing->tmrd = LPDDR3_tMRD & 0x7;
3016         p_publ_timing->dtpr0.b.tMRD = 3;  //max value
3017         /*
3018          * tRFC, 130ns(4Gb) 210ns(>4Gb)
3019          */
3020         if(ddr_capability_per_die > 0x20000000)   // >4Gb
3021         {
3022             p_pctl_timing->trfc = (LPDDR3_tRFC_8Gb*nMHz+999)/1000;
3023             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_8Gb*nMHz+999)/1000);
3024             /*
3025              * tXSR, max(2tCK,tRFC+10ns)
3026              */
3027             tmp=(((LPDDR3_tRFC_8Gb+10)*nMHz+999)/1000);
3028         }
3029         else
3030         {
3031             p_pctl_timing->trfc = (LPDDR3_tRFC_4Gb*nMHz+999)/1000;
3032             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_4Gb*nMHz+999)/1000);
3033             tmp=(((LPDDR3_tRFC_4Gb+10)*nMHz+999)/1000);
3034         }
3035         if(tmp<2)
3036         {
3037             tmp=2;
3038         }
3039         p_pctl_timing->texsr = tmp&0x3FF;
3040         p_publ_timing->dtpr2.b.tXS = tmp;
3041
3042         /*
3043          * tRP, max(3tCK, 18ns(Fast) 21ns(Typ) 27ns(Slow))
3044          */
3045         //if(pPHY_Reg->DCR.b.DDR8BNK)
3046         if(1)
3047         {
3048             trp_tmp = ((LPDDR3_tRPpb_8_BANK*nMHz+999)/1000);
3049             if(trp_tmp<3)
3050             {
3051                 trp_tmp=3;
3052             }
3053             p_pctl_timing->trp = ((((LPDDR3_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
3054         }
3055         p_publ_timing->dtpr0.b.tRP = trp_tmp;
3056         /*
3057          * tRAS, max(3tCK,42ns)
3058          */
3059         tras_tmp=((LPDDR3_tRAS*nMHz+999)/1000);
3060         if(tras_tmp<3)
3061         {
3062             tras_tmp=3;
3063         }
3064         p_pctl_timing->tras = (tras_tmp&0x3F);
3065         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
3066
3067         /*
3068          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
3069          */
3070         trcd_tmp = ((LPDDR3_tRCD*nMHz+999)/1000);
3071         if(trcd_tmp<3)
3072         {
3073             trcd_tmp=3;
3074         }
3075         p_pctl_timing->trcd = (trcd_tmp&0xF);
3076         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
3077
3078         /*
3079          * tRTP, max(4tCK, 7.5ns)
3080          */
3081         trtp_tmp = ((LPDDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
3082         if(trtp_tmp<4)
3083         {
3084             trtp_tmp = 4;
3085         }
3086         p_pctl_timing->trtp = trtp_tmp&0xF;
3087         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
3088
3089         /*
3090          * tWR, max(4tCK,15ns)
3091          */
3092         twr_tmp=((LPDDR3_tWR*nMHz+999)/1000);
3093         if(twr_tmp<4)
3094         {
3095             twr_tmp=4;
3096         }
3097         p_pctl_timing->twr = twr_tmp&0x1F;
3098         bl_tmp = LPDDR3_BL8;
3099         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
3100
3101         /*
3102          * WrToMiss=WL*tCK + tWR + tRP + tRCD
3103          */
3104         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
3105         /*
3106          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
3107          */
3108         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
3109         /*
3110          * tRC=tRAS+tRP
3111          */
3112         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
3113         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
3114         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
3115
3116         /*
3117          * RdToWr=(cl+2-cwl)
3118          */
3119         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
3120         p_publ_timing->dtpr1.b.tRTW = 0;
3121         p_noc_timing->b.RdToWr = (cl+2-cwl);
3122         p_pctl_timing->tal = al;
3123         p_pctl_timing->tcl = cl;
3124         p_pctl_timing->tcwl = cwl;
3125         /*
3126          * tRRD, max(2tCK,10ns)
3127          */
3128         tmp=((LPDDR3_tRRD*nMHz+999)/1000);
3129         if(tmp<2)
3130         {
3131             tmp=2;
3132         }
3133         p_pctl_timing->trrd = (tmp&0xF);
3134         p_publ_timing->dtpr0.b.tRRD = tmp;
3135         p_noc_activate->b.Rrd = tmp;
3136         /*
3137          * tWTR, max(4tCK, 7.5ns)
3138          */
3139         tmp=((LPDDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
3140         if(tmp<4)
3141         {
3142             tmp=4;
3143         }
3144         p_pctl_timing->twtr = tmp&0xF;
3145         p_publ_timing->dtpr0.b.tWTR = tmp;
3146         /*
3147          * WrToRd=WL+tWTR
3148          */
3149         p_noc_timing->b.WrToRd = (cwl+tmp);
3150         /*
3151          * tXP, max(3tCK,7.5ns)
3152          */
3153         tmp=((LPDDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
3154         if(tmp<3)
3155         {
3156             tmp=3;
3157         }
3158         p_pctl_timing->txp = tmp&0x7;
3159         p_publ_timing->dtpr2.b.tXP = tmp;
3160         /*
3161          * tXPDLL, 0ns
3162          */
3163         p_pctl_timing->txpdll = LPDDR3_tXPDLL;
3164         /*
3165          * tZQCS, 90ns
3166          */
3167         p_pctl_timing->tzqcs = ((LPDDR3_tZQCS*nMHz+999)/1000)&0x7F;
3168         /*
3169          * tZQCSI,
3170          */
3171         p_pctl_timing->tzqcsi = LPDDR3_tZQCSI;
3172         /*
3173          * tDQS,
3174          */
3175         p_pctl_timing->tdqs = LPDDR3_tDQS;
3176         /*
3177          * tCKSRE=tCPDED, 2 tCK
3178          */
3179         p_pctl_timing->tcksre = LPDDR3_tCKSRE;
3180         /*
3181          * tCKSRX, 2 tCK
3182          */
3183         p_pctl_timing->tcksrx = LPDDR3_tCKSRX;
3184         /*
3185          * tCKE, (max 7.5ns,3 tCK)
3186          */
3187         tmp=((7*nMHz+(nMHz>>1)+999)/1000);
3188         if(tmp<LPDDR3_tCKE)
3189         {
3190             tmp=LPDDR3_tCKE;
3191         }
3192         p_pctl_timing->tcke = tmp;
3193         p_publ_timing->dtpr2.b.tCKE = tmp;
3194         /*
3195          * tMOD, 0 tCK
3196          */
3197         p_pctl_timing->tmod = LPDDR3_tMOD;
3198         p_publ_timing->dtpr1.b.tMOD = LPDDR3_tMOD;
3199         /*
3200          * tRSTL, 0 tCK
3201          */
3202         p_pctl_timing->trstl = LPDDR3_tRSTL;
3203         /*
3204          * tZQCL, 360ns
3205          */
3206         p_pctl_timing->tzqcl = ((LPDDR3_tZQCL*nMHz+999)/1000)&0x3FF;
3207         /*
3208          * tMRR, 4 tCK
3209          */
3210         p_pctl_timing->tmrr = LPDDR3_tMRR;
3211         /*
3212          * tCKESR, max(3tCK,15ns)
3213          */
3214         tmp = ((LPDDR3_tCKESR*nMHz+999)/1000);
3215         if(tmp < 3)
3216         {
3217             tmp = 3;
3218         }
3219         p_pctl_timing->tckesr = tmp&0xF;
3220         /*
3221          * tDPD, 500us
3222          */
3223         p_pctl_timing->tdpd = LPDDR3_tDPD_US;
3224
3225         /**************************************************
3226          * PHY Timing
3227          **************************************************/
3228         /*
3229          * tCCD, BL/2 for DDR2 and 4 for DDR3
3230          */
3231         p_publ_timing->dtpr0.b.tCCD = 0;
3232         /*
3233          * tDQSCKmax,5.5ns
3234          */
3235         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR3_tDQSCK_MAX;
3236         /*
3237          * tDQSCKmin,2.5ns
3238          */
3239         p_publ_timing->dtpr1.b.tDQSCK = LPDDR3_tDQSCK_MIN;
3240         /*
3241          * tRTODT, 0:ODT may be turned on immediately after read post-amble
3242          *         1:ODT may not be turned on until one clock after the read post-amble
3243          */
3244         p_publ_timing->dtpr1.b.tRTODT = 1;
3245         /*
3246          * tFAW,max(8tCK, 50ns)
3247          */
3248         tmp=((LPDDR3_tFAW*nMHz+999)/1000);
3249         if(tmp<8)
3250         {
3251             tmp=8;
3252         }
3253         p_publ_timing->dtpr1.b.tFAW = tmp;
3254         p_noc_activate->b.Fawbank = 1;
3255         p_noc_activate->b.Faw = tmp;
3256         /*
3257          * tAOND_tAOFD
3258          */
3259         p_publ_timing->dtpr1.b.tAOND = 0;
3260         /*
3261          * tDLLK,0
3262          */
3263         p_publ_timing->dtpr2.b.tDLLK = LPDDR3_tDLLK;
3264         /**************************************************
3265          * NOC Timing
3266          **************************************************/
3267         p_noc_timing->b.BurstLen = (bl>>1);
3268     }
3269
3270 out:
3271     return ret;
3272 }
3273
3274 static uint32 __sramfunc ddr_update_timing(uint32 ch)
3275 {
3276     uint32 i,bl_tmp=0;
3277     PCTL_TIMING_T *p_pctl_timing=&(DATA(ddr_reg).pctl.pctl_timing);
3278     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3279     NOC_TIMING_T  *p_noc_timing=&(DATA(ddr_reg).noc[0].ddrtiming);
3280     NOC_ACTIVATE_T  *p_noc_activate=&(DATA(ddr_reg).noc[0].activate);
3281     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3282     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3283     pMSCH_REG     pMSCH_Reg= DATA(ddr_ch[ch]).pMSCH_Reg;
3284
3285     FUNC(ddr_copy)((uint32 *)&(pDDR_Reg->TOGCNT1U), (uint32*)&(p_pctl_timing->togcnt1u), 34);
3286     FUNC(ddr_copy)((uint32 *)&(pPHY_Reg->DTPR[0]), (uint32*)&(p_publ_timing->dtpr0), 3);
3287     pMSCH_Reg->ddrtiming.d32 = (pMSCH_Reg->ddrtiming.b.BwRatio) | p_noc_timing->d32;
3288     pMSCH_Reg->activate.d32 = p_noc_activate->d32;
3289     // Update PCTL BL
3290     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3291     {
3292         bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3293         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
3294         if(DATA(ddr_freq) <= DDR3_DDR2_DLL_DISABLE_FREQ)
3295         {
3296             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-3;
3297         }
3298         else
3299         {
3300             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-2;
3301         }
3302         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL-1;
3303     }
3304     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3305     {
3306         if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
3307         {
3308             bl_tmp = mddr_lpddr2_bl_8;
3309         }
3310         else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3311         {
3312             bl_tmp = mddr_lpddr2_bl_4;
3313         }
3314         else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
3315         {
3316             bl_tmp = mddr_lpddr2_bl_16;
3317         }
3318         if((DATA(ddr_freq)>=200)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3319         {
3320             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3321         }
3322         else
3323         {
3324             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
3325         }
3326         i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
3327         pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8);  //tDQSCKmax-tDQSCK
3328         pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-1;
3329         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL;
3330     }
3331
3332     return 0;
3333 }
3334
3335 static uint32 __sramfunc ddr_update_mr(uint32 ch)
3336 {
3337     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3338     uint32         cs,dll_off;
3339     pDDRPHY_REG_T  pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3340
3341     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3342     dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
3343     FUNC(ddr_copy)((uint32 *)&(pPHY_Reg->MR[0]), (uint32*)&(p_publ_timing->mr[0]), 4);
3344     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3345     {
3346         if(DATA(ddr_freq)>DDR3_DDR2_DLL_DISABLE_FREQ)
3347         {
3348             if(dll_off)  // off -> on
3349             {
3350                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));  //DLL enable
3351                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET));  //DLL reset
3352                 ddr_delayus(2);  //at least 200 DDR cycle
3353                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3354             }
3355             else // on -> on
3356             {
3357                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
3358                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3359             }
3360         }
3361         else
3362         {
3363             pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3364             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));  //DLL disable
3365             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3366         }
3367         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
3368     }
3369     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3370     {
3371         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
3372         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
3373         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
3374         if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3375         {
3376             ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(11) | lpddr2_op((p_publ_timing->mr11)));
3377         }
3378     }
3379     else //mDDR
3380     {
3381         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3382         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
3383     }
3384     return 0;
3385 }
3386
3387 static void __sramfunc ddr_update_odt(uint32 ch)
3388 {
3389     uint32        cs,tmp;
3390     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3391     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3392
3393     //adjust DRV and ODT
3394     if((DATA(ddr_ch[ch]).mem_type == DDR3) || (DATA(ddr_ch[ch]).mem_type == LPDDR3))
3395     {
3396         if(DATA(ddr_freq) <= DDR3_DDR2_ODT_DISABLE_FREQ)
3397         {
3398             pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3399             pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3400             if(!(pDDR_Reg->PPCFG & 1))
3401             {
3402                 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3403                 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3404             }
3405         }
3406         else
3407         {
3408             pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9);  //dynamic RTT enable
3409             pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
3410             if(!(pDDR_Reg->PPCFG & 1))
3411             {
3412                 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
3413                 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
3414             }
3415         }
3416     }
3417     else
3418     {
3419         pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3420         pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3421         if(!(pDDR_Reg->PPCFG & 1))
3422         {
3423             pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3424             pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3425         }
3426     }
3427     if(DATA(ddr_ch[ch]).mem_type == LPDDR2)
3428     {
3429         tmp = GET_LPDDR2_DS_ODT();  //DS=34ohm,ODT=171ohm
3430     }
3431     else if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3432     {
3433         tmp = GET_LPDDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3434     }
3435     else
3436     {
3437         tmp = GET_DDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3438     }
3439     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3440     if(cs > 1)
3441     {
3442         pPHY_Reg->ZQ1CR[0] = tmp;
3443         dsb();
3444     }
3445     pPHY_Reg->ZQ0CR[0] = tmp;
3446     dsb();
3447 }
3448
3449 void PIE_FUNC(ddr_adjust_config)(void *arg)
3450 {
3451     uint32 value[CH_MAX];
3452     uint32 ch;
3453     pDDR_REG_T    pDDR_Reg;
3454     pDDRPHY_REG_T pPHY_Reg;
3455
3456     for(ch=0;ch<CH_MAX;ch++)
3457     {
3458         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3459         {
3460             value[ch] = ((uint32 *)arg)[ch];
3461             pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3462             pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3463
3464             //enter config state
3465             ddr_move_to_Config_state(ch);
3466
3467             //set data training address
3468             pPHY_Reg->DTAR = value[ch];
3469
3470             //set auto power down idle
3471             pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
3472
3473             //CKDV=00
3474             pPHY_Reg->PGCR &= ~(0x3<<12);
3475
3476             //enable the hardware low-power interface
3477             pDDR_Reg->SCFG.b.hw_low_power_en = 1;
3478
3479             if(pDDR_Reg->PPCFG & 1)
3480             {
3481                 pPHY_Reg->DATX8[2].DXGCR &= ~(1);          //disable byte
3482                 pPHY_Reg->DATX8[3].DXGCR &= ~(1);
3483                 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;  //disable DLL
3484                 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
3485             }
3486
3487             ddr_update_odt(ch);
3488
3489             //enter access state
3490             ddr_move_to_Access_state(ch);
3491         }
3492     }
3493 }
3494 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
3495
3496 static void ddr_adjust_config(void)
3497 {
3498     uint32 dtar[CH_MAX];
3499     uint32 i;
3500     volatile uint32 n;
3501     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3502
3503     //get data training address before idle port
3504     ddr_get_datatraing_addr(dtar);
3505
3506     /** 1. Make sure there is no host access */
3507     flush_cache_all();
3508     outer_flush_all();
3509     flush_tlb_all();
3510     isb();
3511
3512     for(i=0;i<SRAM_SIZE/4096;i++)
3513     {
3514         n=temp[1024*i];
3515         barrier();
3516     }
3517     for(i=0;i<CH_MAX;i++)
3518     {
3519         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3520         {
3521             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3522             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3523             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3524         }
3525     }
3526     n= pCRU_Reg->CRU_PLL_CON[0][0];
3527     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3528     n= READ_GRF_REG();
3529     dsb();
3530
3531     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
3532                     (void *)dtar,
3533                     rockchip_sram_stack);
3534     //disable unused channel
3535     for(i=0;i<CH_MAX;i++)
3536     {
3537         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3538         {
3539             //FIXME
3540         }
3541     }
3542 }
3543
3544 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
3545 {
3546     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3547     uint32 cs,ch;
3548     pDDR_REG_T    pDDR_Reg;
3549     pDDRPHY_REG_T pPHY_Reg;
3550
3551     for(ch=0;ch<CH_MAX;ch++)
3552     {
3553         pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3554         pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3555
3556         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3557         {
3558             ddr_move_to_Config_state(ch);
3559             pDDR_Reg->TZQCSI = 0;
3560             if((nMHz<=DDR3_DDR2_DLL_DISABLE_FREQ) && (DATA(ddr_ch[ch]).mem_type == DDR3))  // DLL disable
3561             {
3562                 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3563                 pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3564                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));
3565             }
3566             ddr_move_to_Lowpower_state(ch);
3567
3568             ddr_set_dll_bypass(ch,0);  //dll bypass
3569             SET_DDRPHY_CLKGATE(ch,1);  //disable DDR PHY clock
3570         }
3571     }
3572     ddr_delayus(1);
3573 }
3574
3575 static void __sramfunc ddr_selfrefresh_exit(void)
3576 {
3577     uint32 n,ch;
3578     pDDR_REG_T    pDDR_Reg;
3579     pDDRPHY_REG_T pPHY_Reg;
3580
3581     for(ch=0;ch<CH_MAX;ch++)
3582     {
3583         pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3584         pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3585
3586         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3587         {
3588             SET_DDRPHY_CLKGATE(ch,0);  //enable DDR PHY clock
3589             dsb();
3590             ddr_set_dll_bypass(ch,DATA(ddr_freq));
3591             ddr_reset_dll(ch);
3592             //ddr_delayus(10);   //wait DLL lock
3593
3594             ddr_move_to_Config_state(ch);
3595             ddr_update_timing(ch);
3596             ddr_update_mr(ch);
3597             ddr_update_odt(ch);
3598             n = ddr_data_training(ch);
3599             ddr_move_to_Access_state(ch);
3600             if(n!=0)
3601             {
3602                 sram_printascii("DTT failed!\n");
3603             }
3604         }
3605     }
3606 }
3607
3608 #if defined(CONFIG_ARCH_RK3066B)
3609 static __sramdata uint32 data8_dqstr[25][4];
3610 static __sramdata uint32 min_ddr_freq,dqstr_flag=false;
3611
3612 int ddr_get_datatraing_value_3168(bool end_flag,uint32 dqstr_value,uint32 min_freq)
3613 {
3614     if(end_flag == true)
3615     {
3616         dqstr_flag = true;    //complete learn data training value flag
3617         min_ddr_freq = min_freq;
3618         return 0;
3619     }
3620
3621     data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3622     data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3623     data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3624     data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3625
3626     ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3627         clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3628         data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3629     return 0;
3630 }
3631
3632 static void __sramfunc ddr_set_pll_enter_3168(uint32 freq_slew)
3633 {
3634     uint32 value_1u,value_100n;
3635     ddr_move_to_Config_state();
3636
3637     if(freq_slew == 1)
3638     {
3639         value_100n = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3640         value_1u = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3641         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3642         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3643         ddr_update_timing();
3644         ddr_update_mr();
3645         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = value_100n;
3646         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = value_1u;
3647     }
3648     else
3649     {
3650         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3651         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3652     }
3653
3654     pDDR_Reg->TZQCSI = 0;
3655     ddr_move_to_Lowpower_state();
3656
3657     ddr_set_dll_bypass(0);  //dll bypass
3658     SET_DDRPHY_CLKGATE(ch,1);  //disable DDR PHY clock
3659     dsb();
3660 }
3661
3662 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32 dqstr_value)
3663 {
3664     SET_DDRPHY_CLKGATE(ch,0);  //enable DDR PHY clock
3665     dsb();
3666     ddr_set_dll_bypass(DATA(ddr_freq));
3667     ddr_reset_dll();
3668
3669     if(dqstr_flag==true)
3670     {
3671         pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3672         pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3673         pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3674         pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3675     }
3676
3677     ddr_update_odt();
3678     ddr_move_to_Config_state();
3679     if(freq_slew == 1)
3680     {
3681         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3682         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3683         pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl.pctl_timing.tzqcsi;
3684     }
3685     else
3686     {
3687         ddr_update_timing();
3688         ddr_update_mr();
3689     }
3690     ddr_data_training();
3691     ddr_move_to_Access_state();
3692 }
3693 #endif
3694
3695 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3696 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew,uint32 dqstr_value)
3697 {
3698     /** 2. ddr enter self-refresh mode or precharge power-down mode */
3699     idle_port();
3700 #if defined(CONFIG_ARCH_RK3066B)
3701     ddr_set_pll_enter_3168(freq_slew);
3702 #else
3703     ddr_selfrefresh_enter(freq);
3704 #endif
3705
3706     /** 3. change frequence  */
3707     FUNC(ddr_set_pll)(freq,1);
3708     DATA(ddr_freq) = freq;
3709
3710     /** 5. Issues a Mode Exit command   */
3711 #if defined(CONFIG_ARCH_RK3066B)
3712     ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3713 #else
3714     ddr_selfrefresh_exit();
3715 #endif
3716     deidle_port();
3717     dsb();
3718 }
3719
3720 struct ddr_change_freq_sram_param {
3721     uint32 arm_freq;
3722     uint32 freq;
3723     uint32 freq_slew;
3724     uint32 dqstr_value;
3725 };
3726
3727 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
3728 {
3729     struct ddr_change_freq_sram_param *param = arg;
3730     loops_per_us = LPJ_100MHZ * param->arm_freq / 1000000;
3731     /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3732     ddr_SRE_2_SRX(param->freq, param->freq_slew, param->dqstr_value);
3733 }
3734 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
3735
3736 static noinline uint32 ddr_change_freq_sram(uint32 nMHz , struct ddr_freq_t ddr_freq_t)
3737 {
3738     uint32 freq;
3739     uint32 freq_slew=0;
3740     uint32 dqstr_value=0;
3741     unsigned long flags;
3742     struct ddr_change_freq_sram_param param;
3743     volatile uint32 n;
3744     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3745     uint32 i;
3746
3747 #if defined(CONFIG_ARCH_RK3066B)
3748     if(dqstr_flag==true)
3749     {
3750         dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
3751         freq_slew = (nMHz>ddr_freq)? 1 : 0;
3752     }
3753 #endif
3754
3755     param.arm_freq = ddr_get_pll_freq(APLL);
3756     freq=p_ddr_set_pll(nMHz,0);
3757
3758     ddr_get_parameter(freq);
3759
3760     /** 1. Make sure there is no host access */
3761     local_irq_save(flags);
3762     local_fiq_disable();
3763     flush_cache_all();
3764     outer_flush_all();
3765     flush_tlb_all();
3766     isb();
3767
3768 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3769     if(ddr_freq_t.screen_ft_us > 0)
3770     {
3771         ddr_freq_t.t1 = cpu_clock(0);
3772         ddr_freq_t.t2 = (uint32)(ddr_freq_t.t1 - ddr_freq_t.t0);   //ns
3773
3774         //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
3775         if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe))
3776         {
3777             freq = 0;
3778             goto end;
3779         }
3780         else
3781         {
3782             rk_fb_poll_wait_frame_complete();
3783         }
3784     }
3785 #endif
3786     for(i=0;i<SRAM_SIZE/4096;i++)
3787     {
3788         n=temp[1024*i];
3789         barrier();
3790     }
3791
3792     for(i=0;i<CH_MAX;i++)
3793     {
3794         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3795         {
3796             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3797             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3798             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3799         }
3800     }
3801     n= pCRU_Reg->CRU_PLL_CON[0][0];
3802     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3803     n= READ_GRF_REG();
3804     dsb();
3805
3806     param.freq = freq;
3807     param.freq_slew = freq_slew;
3808     param.dqstr_value = dqstr_value;
3809     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
3810                     &param,
3811                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SZIE);
3812
3813 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3814 end:
3815 #endif
3816     local_fiq_enable();
3817     local_irq_restore(flags);
3818     return freq;
3819 }
3820
3821 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
3822 static uint32 ddr_change_freq_gpll_dpll(uint32 nMHz)
3823 {
3824     uint32 gpll_freq,gpll_div;
3825     struct ddr_freq_t ddr_freq_t;
3826     ddr_freq_t.screen_ft_us = 0;
3827
3828     if(true == ddr_rk3188_dpll_is_good)
3829     {
3830         gpllvaluel = ddr_get_pll_freq(GPLL);
3831
3832         if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3833         {
3834             gpll_div = (gpllvaluel+nMHz-1)/nMHz;
3835             if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3836             {
3837                 gpll_freq = gpllvaluel/4;
3838                 gpll_div = 4;
3839             }
3840             else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3841             {
3842                 gpll_freq = gpllvaluel/2;
3843                 gpll_div = 2;
3844             }
3845             else        //200-400MHz  /1:200MHz-400MHz
3846             {
3847                 gpll_freq = gpllvaluel;
3848                 gpll_div = 1;
3849             }
3850
3851             *p_ddr_select_gpll_div=gpll_div;    //select GPLL
3852             ddr_change_freq_sram(gpll_freq,ddr_freq_t);
3853             *p_ddr_select_gpll_div=0;
3854
3855             p_ddr_set_pll(nMHz,0); //count DPLL
3856             p_ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3857         }
3858         else
3859         {
3860             ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3861         }
3862     }
3863
3864     return ddr_change_freq_sram(nMHz,ddr_freq_t);
3865
3866 }
3867 #endif
3868
3869 static int _ddr_change_freq(uint32 nMHz)
3870 {
3871         struct ddr_freq_t ddr_freq_t;
3872         //int test_count=0;
3873
3874         ddr_freq_t.screen_ft_us = 0;
3875         ddr_freq_t.t0 = 0;
3876         ddr_freq_t.t1 = 0;
3877 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3878         do
3879         {
3880                 if(rk_fb_poll_wait_frame_complete() == true)
3881                 {
3882                         ddr_freq_t.t0 = cpu_clock(0);
3883                         ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
3884
3885                         test_count++;
3886                         if(test_count > 10) //test 10 times
3887                         {
3888                                 ddr_freq_t.screen_ft_us = 0xfefefefe;
3889                                 dprintk(DEBUG_DDR,"%s:test_count exceed maximum!\n",__func__);
3890                         }
3891                         dprintk(DEBUG_VERBOSE,"%s:test_count=%d\n",__func__,test_count);
3892                         usleep_range(ddr_freq_t.screen_ft_us-test_count*1000,ddr_freq_t.screen_ft_us-test_count*1000);
3893
3894                         flush_cache_all();
3895                         outer_flush_all();
3896                         flush_tlb_all();
3897                 }
3898         }while(ddr_change_freq_sram(nMHz, ddr_freq_t)==0);
3899 #else
3900         return ddr_change_freq_sram(nMHz, ddr_freq_t);
3901 #endif
3902 }
3903
3904 static long _ddr_round_rate(uint32 nMHz)
3905 {
3906         return p_ddr_set_pll(nMHz, 0);
3907 }
3908
3909 static void _ddr_set_auto_self_refresh(bool en)
3910 {
3911     //set auto self-refresh idle
3912     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
3913 }
3914
3915 #define PERI_ACLK_DIV_MASK 0x1f
3916 #define PERI_ACLK_DIV_OFF 0
3917
3918 #define PERI_HCLK_DIV_MASK 0x3
3919 #define PERI_HCLK_DIV_OFF 8
3920
3921 #define PERI_PCLK_DIV_MASK 0x3
3922 #define PERI_PCLK_DIV_OFF 12
3923 static __sramdata u32 cru_sel32_sram;
3924 static void __sramfunc ddr_suspend(void)
3925 {
3926 #if 0
3927     u32 i;
3928     volatile u32 n;
3929     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3930     int pll_id;
3931
3932         pll_id=GET_DDR_PLL_SRC();
3933     /** 1. Make sure there is no host access */
3934     flush_cache_all();
3935     outer_flush_all();
3936     //flush_tlb_all();
3937
3938     for(i=0;i<SRAM_SIZE/4096;i++)
3939     {
3940         n=temp[1024*i];
3941         barrier();
3942     }
3943
3944     n= pDDR_Reg->SCFG.d32;
3945     n= pPHY_Reg->RIDR;
3946     n= pCRU_Reg->CRU_PLL_CON[0][0];
3947     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3948     n= *(volatile uint32_t *)SysSrv_DdrConf;
3949     n= READ_GRF_REG();
3950     dsb();
3951
3952     ddr_selfrefresh_enter(0);
3953
3954     SET_PLL_MODE(pll_id, 0);   //PLL slow-mode
3955     dsb();
3956     ddr_delayus(1);
3957     SET_PLL_PD(pll_id, 1);         //PLL power-down
3958     dsb();
3959     ddr_delayus(1);
3960     if(pll_id==GPLL)
3961     {
3962         cru_sel32_sram=   pCRU_Reg->CRU_CLKSEL_CON[10];
3963
3964         pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
3965                                    | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
3966                                    |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
3967     }
3968     pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29)));  //CKOE
3969 #endif
3970 }
3971
3972 static void __sramfunc ddr_resume(void)
3973 {
3974 #if 0
3975     int delay=1000;
3976     int pll_id;
3977
3978     pll_id=GET_DDR_PLL_SRC();
3979         pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29));  //CKOE
3980         dsb();
3981
3982         if(pll_id==GPLL)
3983         pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
3984
3985     SET_PLL_PD(pll_id, 0);         //PLL no power-down
3986     dsb();
3987     while (delay > 0)
3988     {
3989             ddr_delayus(1);
3990         if (GET_DPLL_LOCK_STATUS())
3991             break;
3992         delay--;
3993     }
3994
3995     SET_PLL_MODE(pll_id, 1);   //PLL normal
3996     dsb();
3997
3998     ddr_selfrefresh_exit();
3999 #endif
4000 }
4001
4002 //pArg:Ö¸ÕëÄÚÈÝ±íÊ¾pll pd or not¡£
4003 void ddr_reg_save(uint32 *pArg)
4004 {
4005     uint32        ch;
4006     pDDR_REG_T    pDDR_Reg=NULL;
4007     pDDRPHY_REG_T pPHY_Reg=NULL;
4008     pMSCH_REG     pMSCH_Reg;
4009
4010     p_ddr_reg->tag = 0x56313031;
4011     if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4012     {
4013         p_ddr_reg->pctlAddr[0] = RK3288_DDR_PCTL0_PHYS;
4014         p_ddr_reg->publAddr[0] = RK3288_DDR_PUBL0_PHYS;
4015         p_ddr_reg->nocAddr[0] = RK3288_SERVICE_BUS_PHYS;
4016         pDDR_Reg = p_ddr_ch[0]->pDDR_Reg;
4017         pPHY_Reg = p_ddr_ch[0]->pPHY_Reg;
4018     }
4019     else
4020     {
4021         p_ddr_reg->pctlAddr[0] = 0xFFFFFFFF;
4022         p_ddr_reg->publAddr[0] = 0xFFFFFFFF;
4023         p_ddr_reg->nocAddr[0] = 0xFFFFFFFF;
4024     }
4025     if(p_ddr_ch[1]->mem_type != DRAM_MAX)
4026     {
4027         p_ddr_reg->pctlAddr[1] = RK3288_DDR_PCTL1_PHYS;
4028         p_ddr_reg->publAddr[1] = RK3288_DDR_PUBL1_PHYS;
4029         p_ddr_reg->nocAddr[1] = RK3288_SERVICE_BUS_PHYS+0x80;
4030         if((pDDR_Reg == NULL) || (pPHY_Reg == NULL))
4031         {
4032             pDDR_Reg = p_ddr_ch[1]->pDDR_Reg;
4033             pPHY_Reg = p_ddr_ch[1]->pPHY_Reg;
4034         }
4035     }
4036     else
4037     {
4038         p_ddr_reg->pctlAddr[1] = 0xFFFFFFFF;
4039         p_ddr_reg->publAddr[1] = 0xFFFFFFFF;
4040         p_ddr_reg->nocAddr[1] = 0xFFFFFFFF;
4041     }
4042
4043     //PCTLR
4044     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint32*)&(p_ddr_reg->pctl.pctl_timing.togcnt1u), (uint32 *)&(pDDR_Reg->TOGCNT1U), 34);
4045     p_ddr_reg->pctl.SCFG = pDDR_Reg->SCFG.d32;
4046     p_ddr_reg->pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
4047     p_ddr_reg->pctl.MCFG1 = pDDR_Reg->MCFG1;
4048     p_ddr_reg->pctl.MCFG = pDDR_Reg->MCFG;
4049     p_ddr_reg->pctl.pctl_timing.ddrFreq = *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
4050     p_ddr_reg->pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
4051     p_ddr_reg->pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
4052     p_ddr_reg->pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
4053     p_ddr_reg->pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
4054     p_ddr_reg->pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
4055     p_ddr_reg->pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
4056     p_ddr_reg->pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
4057     p_ddr_reg->pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
4058     p_ddr_reg->pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
4059     p_ddr_reg->pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
4060     p_ddr_reg->pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
4061     p_ddr_reg->pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
4062     p_ddr_reg->pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
4063     p_ddr_reg->pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
4064     p_ddr_reg->pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
4065
4066     p_ddr_reg->pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
4067     p_ddr_reg->pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
4068     p_ddr_reg->pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
4069     p_ddr_reg->pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
4070     p_ddr_reg->pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
4071     p_ddr_reg->pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
4072     p_ddr_reg->pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
4073     p_ddr_reg->pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
4074     p_ddr_reg->pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
4075
4076     //PUBL
4077     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint32*)&(p_ddr_reg->publ.phy_timing.dtpr0), (uint32 *)&(pPHY_Reg->DTPR[0]), 7);
4078     p_ddr_reg->publ.PIR = pPHY_Reg->PIR;
4079     p_ddr_reg->publ.PGCR = pPHY_Reg->PGCR;
4080     p_ddr_reg->publ.DLLGCR = pPHY_Reg->DLLGCR;
4081     p_ddr_reg->publ.ACDLLCR = pPHY_Reg->ACDLLCR;
4082     p_ddr_reg->publ.PTR[0] = pPHY_Reg->PTR[0];
4083     p_ddr_reg->publ.PTR[1] = pPHY_Reg->PTR[1];
4084     p_ddr_reg->publ.PTR[2] = pPHY_Reg->PTR[2];
4085     p_ddr_reg->publ.ACIOCR = pPHY_Reg->ACIOCR;
4086     p_ddr_reg->publ.DXCCR = pPHY_Reg->DXCCR;
4087     p_ddr_reg->publ.DSGCR = pPHY_Reg->DSGCR;
4088     p_ddr_reg->publ.DCR = pPHY_Reg->DCR.d32;
4089     p_ddr_reg->publ.ODTCR = pPHY_Reg->ODTCR;
4090     p_ddr_reg->publ.DTAR = pPHY_Reg->DTAR;
4091     p_ddr_reg->publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
4092     p_ddr_reg->publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
4093
4094     for(ch=0;ch<CH_MAX;ch++)
4095     {
4096         if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4097         {
4098             pPHY_Reg = p_ddr_ch[ch]->pPHY_Reg;
4099             p_ddr_reg->dqs[ch].DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
4100             p_ddr_reg->dqs[ch].DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
4101             p_ddr_reg->dqs[ch].DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
4102             p_ddr_reg->dqs[ch].DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
4103
4104             p_ddr_reg->dqs[ch].DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
4105             p_ddr_reg->dqs[ch].DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
4106             p_ddr_reg->dqs[ch].DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
4107             p_ddr_reg->dqs[ch].DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
4108
4109             p_ddr_reg->dqs[ch].DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
4110             p_ddr_reg->dqs[ch].DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
4111             p_ddr_reg->dqs[ch].DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
4112             p_ddr_reg->dqs[ch].DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
4113
4114             p_ddr_reg->dqs[ch].DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
4115             p_ddr_reg->dqs[ch].DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
4116             p_ddr_reg->dqs[ch].DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
4117             p_ddr_reg->dqs[ch].DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
4118
4119             //NOC
4120             pMSCH_Reg= p_ddr_ch[ch]->pMSCH_Reg;
4121             p_ddr_reg->noc[ch].ddrconf = pMSCH_Reg->ddrconf;
4122             p_ddr_reg->noc[ch].ddrtiming.d32 = pMSCH_Reg->ddrtiming.d32;
4123             p_ddr_reg->noc[ch].ddrmode = pMSCH_Reg->ddrmode;
4124             p_ddr_reg->noc[ch].readlatency = pMSCH_Reg->readlatency;
4125             p_ddr_reg->noc[ch].activate.d32 = pMSCH_Reg->activate.d32;
4126             p_ddr_reg->noc[ch].devtodev = pMSCH_Reg->devtodev;
4127         }
4128     }
4129
4130     //PLLPD
4131     p_ddr_reg->pllpdAddr = (uint32_t)pArg;  //pll power-down tag addr
4132     p_ddr_reg->pllpdMask = 1;
4133     p_ddr_reg->pllpdVal = 1;
4134
4135     //DPLL
4136     p_ddr_reg->dpllmodeAddr = RK3288_CRU_PHYS + 0x50;  //APCRU_MODE_CON
4137     p_ddr_reg->dpllSlowMode = ((3<<4)<<16) | (0<<4);
4138     p_ddr_reg->dpllNormalMode = ((3<<4)<<16) | (1<<4);
4139     p_ddr_reg->dpllResetAddr = RK3288_CRU_PHYS + 0x1c; //APCRU_DPLL_CON3
4140     p_ddr_reg->dpllReset = (((0x1<<5)<<16) | (0x1<<5));
4141     p_ddr_reg->dpllDeReset = (((0x1<<5)<<16) | (0x0<<5));
4142     p_ddr_reg->dpllConAddr = RK3288_CRU_PHYS + 0x10;   //APCRU_DPLL_CON0
4143     p_ddr_reg->dpllCon[0] = pCRU_Reg->CRU_PLL_CON[DPLL][0] | (0xFFFF<<16);
4144     p_ddr_reg->dpllCon[1] = pCRU_Reg->CRU_PLL_CON[DPLL][1] | (0xFFFF<<16);
4145     p_ddr_reg->dpllCon[2] = pCRU_Reg->CRU_PLL_CON[DPLL][2] | (0xFFFF<<16);
4146     p_ddr_reg->dpllCon[3] = pCRU_Reg->CRU_PLL_CON[DPLL][3] | (0xFFFF<<16);
4147     p_ddr_reg->dpllLockAddr = RK3288_GRF_PHYS + 0x284;  //GRF_SOC_STATUS1
4148     p_ddr_reg->dpllLockMask = (1<<5);
4149     p_ddr_reg->dpllLockVal = (1<<5);
4150
4151     //SET_DDR_PLL_SRC
4152     p_ddr_reg->ddrPllSrcDivAddr = RK3288_CRU_PHYS + 0xc8;
4153     p_ddr_reg->ddrPllSrcDiv = (pCRU_Reg->CRU_CLKSEL_CON[26] & 0x7) | (0x7<<16);
4154
4155     p_ddr_reg->retenDisAddr = RK3288_PMU_PHYS+0x18;  //pmu_pwrmode_con
4156     p_ddr_reg->retenDisVal = (3<<22);  //OR operation
4157     p_ddr_reg->retenStAddr = RK3288_PMU_PHYS+0x1c;  //pmu_pwrmode_con
4158     p_ddr_reg->retenStMask = (1<<6);
4159     p_ddr_reg->retenStVal = (0<<6);
4160
4161     p_ddr_reg->grfRegCnt = 3;
4162     //DDR_16BIT,DDR_HW_WAKEUP,DDR_TYPE
4163     p_ddr_reg->grf[0].addr = RK3288_GRF_PHYS + 0x244;
4164     p_ddr_reg->grf[0].val = (pGRF_Reg->GRF_SOC_CON[0] & ((0x3<<8)|(0x3<<5)|(0x3<<3))) | (((0x3<<8)|(0x3<<5)|(0x3<<3))<<16);
4165
4166     //LPDDR_TYPE
4167     p_ddr_reg->grf[1].addr = RK3288_GRF_PHYS + 0x24c;
4168     p_ddr_reg->grf[1].val = (pGRF_Reg->GRF_SOC_CON[2] & (0x3f<<8)) | ((0x3f<<8)<<16);
4169
4170     //STRIDE
4171     p_ddr_reg->grf[2].addr = RK3288_SGRF_PHYS + 0x8;
4172     p_ddr_reg->grf[2].val = READ_DDR_STRIDE() | (0x1F<<16);
4173
4174     p_ddr_reg->endTag = 0xFFFFFFFF;
4175 }
4176
4177 __attribute__((aligned(4)))   uint32 ddr_reg_resume[]=
4178 {
4179 #include "ddr_reg_resume.inc"
4180 };
4181
4182 char * ddr_get_resume_code_info(u32 *size)
4183 {
4184     *size=sizeof(ddr_reg_resume);
4185
4186     return (char *)ddr_reg_resume;
4187
4188 }
4189 EXPORT_SYMBOL(ddr_get_resume_code_info);
4190
4191 char * ddr_get_resume_data_info(u32 *size)
4192 {
4193     *size=sizeof(DATA(ddr_reg));
4194     return (char *) kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4195 }
4196 EXPORT_SYMBOL(ddr_get_resume_data_info);
4197
4198
4199 static int ddr_init(uint32 dram_speed_bin, uint32 freq)
4200 {
4201     uint32 tmp;
4202     uint32 die=1;
4203     uint32 gsr,dqstr;
4204     struct clk *clk;
4205     uint32 ch,cap=0,cs_cap;
4206
4207     ddr_print("version 1.00 20140404 \n");
4208
4209     p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4210     p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
4211     //p_cpu_pause = kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
4212
4213     tmp = clk_get_rate(clk_get(NULL, "clk_ddr"))/1000000;
4214     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)) = tmp;
4215     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
4216
4217     for(ch=0;ch<CH_MAX;ch++)
4218     {
4219         p_ddr_ch[ch] = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_ch[ch]));
4220
4221         p_ddr_ch[ch]->chNum = ch;
4222         p_ddr_ch[ch]->pDDR_Reg = pDDR_REG(ch);
4223         p_ddr_ch[ch]->pPHY_Reg = pPHY_REG(ch);
4224         p_ddr_ch[ch]->pMSCH_Reg = pMSCH_REG(ch);
4225
4226         if(!(READ_CH_INFO()&(1<<ch)))
4227         {
4228             p_ddr_ch[ch]->mem_type = DRAM_MAX;
4229             continue;
4230         }
4231         else
4232         {
4233             if(ch)
4234             {
4235                 ddr_print("Channel b: \n");
4236             }
4237             else
4238             {
4239                 ddr_print("Channel a: \n");
4240             }
4241             tmp = p_ddr_ch[ch]->pPHY_Reg->DCR.b.DDRMD;
4242             if((tmp ==  LPDDR2) && (READ_DRAMTYPE_INFO() == 6))
4243             {
4244                 tmp = LPDDR3;
4245             }
4246             switch(tmp)
4247             {
4248                 case DDR3:
4249                     ddr_print("DDR3 Device\n");
4250                     break;
4251                 case LPDDR3:
4252                     ddr_print("LPDDR3 Device\n");
4253                     break;
4254                 case LPDDR2:
4255                     ddr_print("LPDDR2 Device\n");
4256                     break;
4257                 default:
4258                     ddr_print("Unkown Device\n");
4259                     tmp = DRAM_MAX;
4260                     break;
4261             }
4262             p_ddr_ch[ch]->mem_type = tmp;
4263             if(tmp == DRAM_MAX)
4264             {
4265                 p_ddr_ch[ch]->mem_type = DRAM_MAX;
4266                 continue;
4267             }
4268         }
4269
4270         p_ddr_ch[ch]->ddr_speed_bin = dram_speed_bin;
4271         //get capability per chip, not total size, used for calculate tRFC
4272         die = (8<<READ_BW_INFO(ch))/(8<<READ_DIE_BW_INFO(ch));
4273         cap = (1 << (READ_ROW_INFO(ch,0)+READ_COL_INFO(ch)+READ_BK_INFO(ch)+READ_BW_INFO(ch)));
4274         cs_cap = cap;
4275         if(READ_CS_INFO(ch) > 1)
4276         {
4277             cap += cap >> (READ_ROW_INFO(ch,0)-READ_ROW_INFO(ch,1));
4278         }
4279         if(READ_CH_ROW_INFO(ch))
4280         {
4281             cap = cap*3/4;
4282         }
4283         p_ddr_ch[ch]->ddr_capability_per_die = cs_cap/die;
4284         ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
4285                                                                         READ_BW_INFO(ch)*16,\
4286                                                                         READ_COL_INFO(ch), \
4287                                                                         (0x1<<(READ_BK_INFO(ch))), \
4288                                                                         READ_ROW_INFO(ch,0), \
4289                                                                         READ_CS_INFO(ch), \
4290                                                                         (cap>>20));
4291     }
4292
4293     ddr_adjust_config();
4294
4295     clk = clk_get(NULL, "clk_ddr");
4296     if (IS_ERR(clk)) {
4297         ddr_print("failed to get ddr clk\n");
4298         clk = NULL;
4299     }
4300     if(freq != 0)
4301         tmp = clk_set_rate(clk, 1000*1000*freq);
4302     else
4303         tmp = clk_set_rate(clk, clk_get_rate(clk));
4304     ddr_print("init success!!! freq=%luMHz\n", clk ? clk_get_rate(clk)/1000000 : freq);
4305
4306     for(ch=0;ch<CH_MAX;ch++)
4307     {
4308         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
4309         {
4310             if(ch)
4311             {
4312                 ddr_print("Channel b: \n");
4313             }
4314             else
4315             {
4316                 ddr_print("Channel a: \n");
4317             }
4318             for(tmp=0;tmp<4;tmp++)
4319             {
4320                 gsr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXGSR[0];
4321                 dqstr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXDQSTR;
4322                 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=%d,%d, DGSL=%d,%d extra clock, DGPS=%d,%d\n", \
4323                                                                     (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), \
4324                                                                     ((gsr>>13)&0x7), ((gsr>>16)&0x7),\
4325                                                                     (dqstr&0x7), ((dqstr>>3)&0x7),\
4326                                                                     ((((dqstr>>12)&0x3)+1)*90), ((((dqstr>>14)&0x3)+1)*90));
4327             }
4328             ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
4329                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
4330                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
4331                                                         p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]&0x3,\
4332                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
4333                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
4334                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>6)&0x3);
4335             ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
4336             ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
4337         }
4338     }
4339
4340     return 0;
4341 }
4342