2 * Function Driver for DDR controller
4 * Copyright (C) 2011-2014 Fuzhou Rockchip Electronics Co.,Ltd
12 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/clk.h>
17 #include <asm/cacheflush.h>
18 #include <asm/tlbflush.h>
19 #include <linux/cpu.h>
20 #include <dt-bindings/clock/ddr.h>
21 #include <linux/rockchip/cru.h>
22 #include <linux/rk_fb.h>
25 typedef uint32_t uint32;
27 #define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
28 /***********************************
29 * Global Control Macro
30 ***********************************/
31 //#define ENABLE_DDR_CLCOK_GPLL_PATH //for RK3188
33 #define DDR3_DDR2_ODT_DISABLE_FREQ (333)
34 #define DDR3_DDR2_DLL_DISABLE_FREQ (333)
35 #define SR_IDLE (0x3) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
36 #define PD_IDLE (0X40) //unit:DDR clk cycle, and 0 for disable auto power-down
38 //#if (DDR3_DDR2_ODT_DISABLE_FREQ > DDR3_DDR2_DLL_DISABLE_FREQ)
42 #define ddr_print(x...) printk( "DDR DEBUG: " x )
44 /***********************************
45 * ARCH Relative Macro and Struction
46 ***********************************/
47 #define SRAM_CODE_OFFSET rockchip_sram_virt
48 #define SRAM_SIZE rockchip_sram_size
54 #define pd_scu_pwr_st (1<<11)
55 #define pd_hevc_pwr_st (1<<10)
56 #define pd_gpu_pwr_st (1<<9)
57 #define pd_video_pwr_st (1<<8)
58 #define pd_vio_pwr_st (1<<7)
59 #define pd_peri_pwr_st (1<<6)
60 #define pd_bus_pwr_st (1<<5)
62 #define idle_req_hevc_cfg (1<<9)
63 #define idle_req_cpup_cfg (1<<8)
64 #define idle_req_dma_cfg (1<<7)
65 #define idle_req_alive_cfg (1<<6)
66 #define idle_req_core_cfg (1<<5)
67 #define idle_req_vio_cfg (1<<4)
68 #define idle_req_video_cfg (1<<3)
69 #define idle_req_gpu_cfg (1<<2)
70 #define idle_req_peri_cfg (1<<1)
71 #define idle_req_bus_cfg (1<<0)
74 #define idle_ack_hevc (1<<25)
75 #define idle_ack_cpup (1<<24)
76 #define idle_ack_dma (1<<23)
77 #define idle_ack_alive (1<<22)
78 #define idle_ack_core (1<<21)
79 #define idle_ack_vio (1<<20)
80 #define idle_ack_video (1<<19)
81 #define idle_ack_gpu (1<<18)
82 #define idle_ack_peir (1<<17)
83 #define idle_ack_bus (1<<16)
85 #define idle_hevc (1<<9)
86 #define idle_cpup (1<<8)
87 #define idle_dma (1<<7)
88 #define idle_alive (1<<6)
89 #define idle_core (1<<5)
90 #define idle_vio (1<<4)
91 #define idle_video (1<<3)
92 #define idle_gpu (1<<2)
93 #define idle_peri (1<<1)
94 #define idle_bus (1<<0)
100 #define ddrio_ret_de_req(ch) (1<<(21+(ch)))
101 #define ddrc_gating_en(ch) (1<<(19+(ch)))
102 #define ddrio_ret_en(ch) (1<<(17+(ch)))
103 #define sref_enter_en(ch) (1<<(15+(ch)))
106 #define SREF_EXIT (1<<26)
107 #define DDR_IO_PWRUP (1<<25)
110 typedef volatile struct tagPMU_FILE
112 uint32 PMU_WAKEUP_CFG[2];
113 uint32 PMU_PWRDN_CON;
117 uint32 PMU_PWRMODE_CON;
118 uint32 PMU_PWR_STATE;
121 uint32 PMU_STABL_CNT;
122 uint32 PMU_DDR0IO_PWRON_CNT;
123 uint32 PMU_DDR1IO_PWRON_CNT;
124 uint32 PMU_CORE_PWRDN_CNT;
125 uint32 PMU_CORE_PWRUP_CNT;
126 uint32 PMU_GPU_PWRDWN_CNT;
127 uint32 PMU_GPU_PWRUP_CNT;
128 uint32 PMU_WAKEUP_RST_CLR_CNT;
130 uint32 PMU_DDR_SREF_ST;
133 uint32 PMU_BOOT_ADDR_SEL;
136 uint32 PMU_GPIO0_A_PULL;
137 uint32 PMU_GPIO0_B_PULL;
138 uint32 PMU_GPIO0_C_PULL;
139 uint32 PMU_GPIO0_A_DRV;
140 uint32 PMU_GPIO0_B_DRV;
141 uint32 PMU_GPIO0_C_DRV;
143 uint32 PMU_GPIO0_SEL18;
144 uint32 PMU_GPIO0_A_IOMUX;
145 uint32 PMU_GPIO0_B_IOMUX;
146 uint32 PMU_GPIO0_C_IOMUX;
147 uint32 PMU_GPIO0_D_IOMUX;
148 uint32 PMU_PMU_SYS_REG[4];
149 }PMU_FILE, *pPMU_FILE;
154 typedef enum PLL_ID_Tag
163 #define PLL_RESET (((0x1<<5)<<16) | (0x1<<5))
164 #define PLL_DE_RESET (((0x1<<5)<<16) | (0x0<<5))
165 #define NR(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
166 #define NO(n) ((0xF<<16) | ((n)-1))
167 #define NF(n) ((0x1FFF<<16) | ((n)-1))
168 #define NB(n) ((0xFFF<<16) | ((n)-1))
171 typedef volatile struct tagCRU_STRUCT
173 uint32 CRU_PLL_CON[5][4];
175 uint32 reserved1[(0x60-0x54)/4];
176 uint32 CRU_CLKSEL_CON[43];
177 uint32 reserved2[(0x160-0x10c)/4];
178 uint32 CRU_CLKGATE_CON[19];
179 uint32 reserved3[(0x1b0-0x1ac)/4];
180 uint32 CRU_GLB_SRST_FST_VALUE;
181 uint32 CRU_GLB_SRST_SND_VALUE;
182 uint32 CRU_SOFTRST_CON[12];
184 uint32 CRU_GLB_CNT_TH;
185 uint32 CRU_TSADC_RST_CON;
186 uint32 reserved4[(0x200-0x1f4)/4];
187 uint32 CRU_SDMMC_CON[2];
188 uint32 CRU_SDIO0_CON[2];
189 uint32 CRU_SDIO1_CON[2];
190 uint32 CRU_EMMC_CON[2];
191 // other regigster unused in boot
192 } CRU_REG, *pCRU_REG;
198 typedef volatile struct tagREG_FILE
200 uint32 GRF_GPIO1A_IOMUX;
201 uint32 GRF_GPIO1B_IOMUX;
202 uint32 GRF_GPIO1C_IOMUX;
203 uint32 GRF_GPIO1D_IOMUX;
204 uint32 GRF_GPIO2A_IOMUX;
205 uint32 GRF_GPIO2B_IOMUX;
206 uint32 GRF_GPIO2C_IOMUX;
207 uint32 GRF_GPIO2D_IOMUX;
208 uint32 GRF_GPIO3A_IOMUX;
209 uint32 GRF_GPIO3B_IOMUX;
210 uint32 GRF_GPIO3C_IOMUX;
211 uint32 GRF_GPIO3DL_IOMUX;
212 uint32 GRF_GPIO3DH_IOMUX;
213 uint32 GRF_GPIO4AL_IOMUX;
214 uint32 GRF_GPIO4AH_IOMUX;
215 uint32 GRF_GPIO4BL_IOMUX;
216 uint32 GRF_GPIO4BH_IOMUX;
217 uint32 GRF_GPIO4C_IOMUX;
218 uint32 GRF_GPIO4D_IOMUX;
219 uint32 GRF_GPIO5A_IOMUX;
220 uint32 GRF_GPIO5B_IOMUX;
221 uint32 GRF_GPIO5C_IOMUX;
222 uint32 GRF_GPIO5D_IOMUX;
223 uint32 GRF_GPIO6A_IOMUX;
224 uint32 GRF_GPIO6B_IOMUX;
225 uint32 GRF_GPIO6C_IOMUX;
226 uint32 GRF_GPIO6D_IOMUX;
227 uint32 GRF_GPIO7A_IOMUX;
228 uint32 GRF_GPIO7B_IOMUX;
229 uint32 GRF_GPIO7CL_IOMUX;
230 uint32 GRF_GPIO7CH_IOMUX;
231 uint32 GRF_GPIO7D_IOMUX;
232 uint32 GRF_GPIO8A_IOMUX;
233 uint32 GRF_GPIO8B_IOMUX;
234 uint32 GRF_GPIO8C_IOMUX;
235 uint32 GRF_GPIO8D_IOMUX;
236 uint32 reserved1[(0x100-0x90)/4];
237 uint32 GRF_GPIO1L_SR;
238 uint32 GRF_GPIO1H_SR;
239 uint32 GRF_GPIO2L_SR;
240 uint32 GRF_GPIO2H_SR;
241 uint32 GRF_GPIO3L_SR;
242 uint32 GRF_GPIO3H_SR;
243 uint32 GRF_GPIO4L_SR;
244 uint32 GRF_GPIO4H_SR;
245 uint32 GRF_GPIO5L_SR;
246 uint32 GRF_GPIO5H_SR;
247 uint32 GRF_GPIO6L_SR;
248 uint32 GRF_GPIO6H_SR;
249 uint32 GRF_GPIO7L_SR;
250 uint32 GRF_GPIO7H_SR;
251 uint32 GRF_GPIO8L_SR;
252 uint32 GRF_GPIO8H_SR;
318 uint32 GRF_SOC_CON[15];
319 uint32 GRF_SOC_STATUS[23];
320 uint32 reserved2[(0x2e0-0x2dc)/4];
321 uint32 GRF_DMAC2_CON[4];
322 uint32 GRF_DDRC0_CON0;
323 uint32 GRF_DDRC1_CON0;
324 uint32 GRF_CPU_CON[5];
325 uint32 reserved3[(0x318-0x30c)/4];
326 uint32 GRF_CPU_STATUS0;
327 uint32 reserved4[(0x320-0x31c)/4];
328 uint32 GRF_UOC0_CON[5];
329 uint32 GRF_UOC1_CON[5];
330 uint32 GRF_UOC2_CON[4];
331 uint32 GRF_UOC3_CON[2];
332 uint32 GRF_UOC4_CON[2];
333 uint32 GRF_DLL_CON[3];
334 uint32 GRF_DLL_STATUS[3];
336 uint32 GRF_SARADC_TESTBIT;
337 uint32 GRF_TSADC_TESTBIT_L;
338 uint32 GRF_TSADC_TESTBIT_H;
339 uint32 GRF_OS_REG[4];
340 uint32 GRF_FAST_BOOT_ADDR;
341 uint32 GRF_SOC_CON15;
342 uint32 GRF_SOC_CON16;
343 } REG_FILE, *pREG_FILE;
349 #define INIT_STATE (0)
350 #define CFG_STATE (1)
352 #define SLEEP_STATE (3)
353 #define WAKEUP_STATE (4)
358 #define Config_req (2)
360 #define Access_req (4)
361 #define Low_power (5)
362 #define Low_power_entry_req (6)
363 #define Low_power_exit_req (7)
366 #define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
367 #define pd_idle(n) ((n)<<8)
368 #define mddr_en (2<<22)
369 #define lpddr2_en (3<<22)
370 #define ddr2_en (0<<5)
371 #define ddr3_en (1<<5)
372 #define lpddr2_s2 (0<<6)
373 #define lpddr2_s4 (1<<6)
374 #define mddr_lpddr2_bl_2 (0<<20)
375 #define mddr_lpddr2_bl_4 (1<<20)
376 #define mddr_lpddr2_bl_8 (2<<20)
377 #define mddr_lpddr2_bl_16 (3<<20)
378 #define ddr2_ddr3_bl_4 (0)
379 #define ddr2_ddr3_bl_8 (1)
380 #define tfaw_cfg(n) (((n)-4)<<18)
381 #define pd_exit_slow (0<<17)
382 #define pd_exit_fast (1<<17)
383 #define pd_type(n) ((n)<<16)
384 #define two_t_en(n) ((n)<<3)
385 #define bl8int_en(n) ((n)<<2)
386 #define cke_or_en(n) ((n)<<1)
389 #define power_up_start (1<<0)
392 #define power_up_done (1<<0)
395 #define dfi_init_complete (1<<0)
398 #define cmd_tstat (1<<0)
401 #define cmd_tstat_en (1<<1)
404 #define Deselect_cmd (0)
414 #define lpddr2_op(n) ((n)<<12)
415 #define lpddr2_ma(n) ((n)<<4)
417 #define bank_addr(n) ((n)<<17)
418 #define cmd_addr(n) ((n)<<4)
420 #define start_cmd (1u<<31)
422 typedef union STAT_Tag
427 unsigned ctl_stat : 3;
428 unsigned reserved3 : 1;
429 unsigned lp_trig : 3;
430 unsigned reserved7_31 : 25;
434 typedef union SCFG_Tag
439 unsigned hw_low_power_en : 1;
440 unsigned reserved1_5 : 5;
441 unsigned nfifo_nif1_dis : 1;
442 unsigned reserved7 : 1;
443 unsigned bbflags_timing : 4;
444 unsigned reserved12_31 : 20;
448 /* DDR Controller register struct */
449 typedef volatile struct DDR_REG_Tag
451 //Operational State, Control, and Status Registers
452 SCFG_T SCFG; //State Configuration Register
453 volatile uint32 SCTL; //State Control Register
454 STAT_T STAT; //State Status Register
455 volatile uint32 INTRSTAT; //Interrupt Status Register
456 uint32 reserved0[(0x40-0x10)/4];
457 //Initailization Control and Status Registers
458 volatile uint32 MCMD; //Memory Command Register
459 volatile uint32 POWCTL; //Power Up Control Registers
460 volatile uint32 POWSTAT; //Power Up Status Register
461 volatile uint32 CMDTSTAT; //Command Timing Status Register
462 volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
463 uint32 reserved1[(0x60-0x54)/4];
464 volatile uint32 MRRCFG0; //MRR Configuration 0 Register
465 volatile uint32 MRRSTAT0; //MRR Status 0 Register
466 volatile uint32 MRRSTAT1; //MRR Status 1 Register
467 uint32 reserved2[(0x7c-0x6c)/4];
468 //Memory Control and Status Registers
469 volatile uint32 MCFG1; //Memory Configuration 1 Register
470 volatile uint32 MCFG; //Memory Configuration Register
471 volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
472 volatile uint32 MSTAT; //Memory Status Register
473 volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
475 //DTU Control and Status Registers
476 volatile uint32 DTUPDES; //DTU Status Register
477 volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
478 volatile uint32 DTUNE; //DTU Number of Errors Register
479 volatile uint32 DTUPRD0; //DTU Parallel Read 0
480 volatile uint32 DTUPRD1; //DTU Parallel Read 1
481 volatile uint32 DTUPRD2; //DTU Parallel Read 2
482 volatile uint32 DTUPRD3; //DTU Parallel Read 3
483 volatile uint32 DTUAWDT; //DTU Address Width
484 uint32 reserved4[(0xc0-0xb4)/4];
485 //Memory Timing Registers
486 volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
487 volatile uint32 TINIT; //t_init Timing Register
488 volatile uint32 TRSTH; //Reset High Time Register
489 volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
490 volatile uint32 TREFI; //t_refi Timing Register
491 volatile uint32 TMRD; //t_mrd Timing Register
492 volatile uint32 TRFC; //t_rfc Timing Register
493 volatile uint32 TRP; //t_rp Timing Register
494 volatile uint32 TRTW; //t_rtw Timing Register
495 volatile uint32 TAL; //AL Latency Register
496 volatile uint32 TCL; //CL Timing Register
497 volatile uint32 TCWL; //CWL Register
498 volatile uint32 TRAS; //t_ras Timing Register
499 volatile uint32 TRC; //t_rc Timing Register
500 volatile uint32 TRCD; //t_rcd Timing Register
501 volatile uint32 TRRD; //t_rrd Timing Register
502 volatile uint32 TRTP; //t_rtp Timing Register
503 volatile uint32 TWR; //t_wr Timing Register
504 volatile uint32 TWTR; //t_wtr Timing Register
505 volatile uint32 TEXSR; //t_exsr Timing Register
506 volatile uint32 TXP; //t_xp Timing Register
507 volatile uint32 TXPDLL; //t_xpdll Timing Register
508 volatile uint32 TZQCS; //t_zqcs Timing Register
509 volatile uint32 TZQCSI; //t_zqcsi Timing Register
510 volatile uint32 TDQS; //t_dqs Timing Register
511 volatile uint32 TCKSRE; //t_cksre Timing Register
512 volatile uint32 TCKSRX; //t_cksrx Timing Register
513 volatile uint32 TCKE; //t_cke Timing Register
514 volatile uint32 TMOD; //t_mod Timing Register
515 volatile uint32 TRSTL; //Reset Low Timing Register
516 volatile uint32 TZQCL; //t_zqcl Timing Register
517 volatile uint32 TMRR; //t_mrr Timing Register
518 volatile uint32 TCKESR; //t_ckesr Timing Register
519 volatile uint32 TDPD; //t_dpd Timing Register
520 uint32 reserved5[(0x180-0x148)/4];
521 //ECC Configuration, Control, and Status Registers
522 volatile uint32 ECCCFG; //ECC Configuration Register
523 volatile uint32 ECCTST; //ECC Test Register
524 volatile uint32 ECCCLR; //ECC Clear Register
525 volatile uint32 ECCLOG; //ECC Log Register
526 uint32 reserved6[(0x200-0x190)/4];
527 //DTU Control and Status Registers
528 volatile uint32 DTUWACTL; //DTU Write Address Control Register
529 volatile uint32 DTURACTL; //DTU Read Address Control Register
530 volatile uint32 DTUCFG; //DTU Configuration Control Register
531 volatile uint32 DTUECTL; //DTU Execute Control Register
532 volatile uint32 DTUWD0; //DTU Write Data 0
533 volatile uint32 DTUWD1; //DTU Write Data 1
534 volatile uint32 DTUWD2; //DTU Write Data 2
535 volatile uint32 DTUWD3; //DTU Write Data 3
536 volatile uint32 DTUWDM; //DTU Write Data Mask
537 volatile uint32 DTURD0; //DTU Read Data 0
538 volatile uint32 DTURD1; //DTU Read Data 1
539 volatile uint32 DTURD2; //DTU Read Data 2
540 volatile uint32 DTURD3; //DTU Read Data 3
541 volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
542 volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
543 volatile uint32 DTUEAF; //DTU Error Address FIFO
544 //DFI Control Registers
545 volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
546 volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
547 volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
548 volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
549 //DFI Write Data Registers
550 volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
551 volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
552 uint32 reserved7[(0x260-0x258)/4];
553 volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
554 volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
555 uint32 reserved8[(0x270-0x268)/4];
556 //DFI Update Registers
557 volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
558 volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
559 volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
560 volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
561 volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
562 volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
563 volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
565 volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
566 volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
567 volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
568 uint32 reserved10[(0x2ac-0x29c)/4];
569 volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
570 volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
571 volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
572 volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
573 volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
574 //DFI Status Registers
575 volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
576 volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
577 volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
579 volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
580 volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
581 volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
582 volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
583 volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
584 uint32 reserved12[(0x2f0-0x2e4)/4];
585 //DFI Low Power Registers
586 volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
587 uint32 reserved13[(0x300-0x2f4)/4];
588 //DFI Training 2 Registers
589 volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
590 volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
591 volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
592 volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
593 volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
594 volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
595 volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
596 volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
597 volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
598 volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
599 volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
600 volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
601 volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
602 volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
603 volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
604 volatile uint32 DFITRCMD; //DFI Training Command Register
605 uint32 reserved14[(0x3f8-0x340)/4];
606 //IP Status Registers
607 volatile uint32 IPVR; //IP Version Register
608 volatile uint32 IPTR; //IP Type Register
609 }DDR_REG_T, *pDDR_REG_T;
616 #define DLLSRST (1<<1)
617 #define DLLLOCK (1<<2)
619 #define ITMSRST (1<<4)
620 #define DRAMRST (1<<5)
621 #define DRAMINIT (1<<6)
623 #define EYETRN (1<<8)
625 #define DLLBYP (1<<17)
626 #define CTLDINIT (1<<18)
627 #define CLRSR (1<<28)
628 #define LOCKBYP (1<<29)
629 #define ZCALBYP (1<<30)
630 #define INITBYP (1u<<31)
633 #define DFTLMT(n) ((n)<<3)
634 #define DFTCMP(n) ((n)<<2)
635 #define DQSCFG(n) ((n)<<1)
636 #define ITMDMD(n) ((n)<<0)
637 #define RANKEN(n) ((n)<<18)
641 #define DLDONE (1<<1)
642 #define ZCDONE (1<<2)
643 #define DIDONE (1<<3)
644 #define DTDONE (1<<4)
646 #define DTIERR (1<<6)
647 #define DFTERR (1<<7)
651 #define tITMSRST(n) ((n)<<18)
652 #define tDLLLOCK(n) ((n)<<6)
653 #define tDLLSRST(n) ((n)<<0)
656 #define tDINIT1(n) ((n)<<19)
657 #define tDINIT0(n) ((n)<<0)
660 #define tDINIT3(n) ((n)<<17)
661 #define tDINIT2(n) ((n)<<0)
664 #define DQSGE(n) ((n)<<8)
665 #define DQSGX(n) ((n)<<5)
667 typedef union DCR_Tag
673 unsigned DDR8BNK : 1;
676 unsigned DDRTYPE : 2;
677 unsigned reserved10_26 : 17;
686 typedef volatile struct DATX8_REG_Tag
688 volatile uint32 DXGCR; //DATX8 General Configuration Register
689 volatile uint32 DXGSR[2]; //DATX8 General Status Register
690 volatile uint32 DXDLLCR; //DATX8 DLL Control Register
691 volatile uint32 DXDQTR; //DATX8 DQ Timing Register
692 volatile uint32 DXDQSTR; //DATX8 DQS Timing Register
693 uint32 reserved[0x80-0x76];
696 /* DDR PHY register struct */
697 typedef volatile struct DDRPHY_REG_Tag
699 volatile uint32 RIDR; //Revision Identification Register
700 volatile uint32 PIR; //PHY Initialization Register
701 volatile uint32 PGCR; //PHY General Configuration Register
702 volatile uint32 PGSR; //PHY General Status Register
703 volatile uint32 DLLGCR; //DLL General Control Register
704 volatile uint32 ACDLLCR; //AC DLL Control Register
705 volatile uint32 PTR[3]; //PHY Timing Registers 0-2
706 volatile uint32 ACIOCR; //AC I/O Configuration Register
707 volatile uint32 DXCCR; //DATX8 Common Configuration Register
708 volatile uint32 DSGCR; //DDR System General Configuration Register
709 DCR_T DCR; //DRAM Configuration Register
710 volatile uint32 DTPR[3]; //DRAM Timing Parameters Register 0-2
711 volatile uint32 MR[4]; //Mode Register 0-3
712 volatile uint32 ODTCR; //ODT Configuration Register
713 volatile uint32 DTAR; //Data Training Address Register
714 volatile uint32 DTDR[2]; //Data Training Data Register 0-1
716 uint32 reserved1[0x30-0x18];
717 uint32 DCU[0x38-0x30];
718 uint32 reserved2[0x40-0x38];
719 uint32 BIST[0x51-0x40];
720 uint32 reserved3[0x60-0x51];
722 volatile uint32 ZQ0CR[2]; //ZQ 0 Impedance Control Register 0-1
723 volatile uint32 ZQ0SR[2]; //ZQ 0 Impedance Status Register 0-1
724 volatile uint32 ZQ1CR[2]; //ZQ 1 Impedance Control Register 0-1
725 volatile uint32 ZQ1SR[2]; //ZQ 1 Impedance Status Register 0-1
726 volatile uint32 ZQ2CR[2]; //ZQ 2 Impedance Control Register 0-1
727 volatile uint32 ZQ2SR[2]; //ZQ 2 Impedance Status Register 0-1
728 volatile uint32 ZQ3CR[2]; //ZQ 3 Impedance Control Register 0-1
729 volatile uint32 ZQ3SR[2]; //ZQ 3 Impedance Status Register 0-1
731 DATX8_REG_T DATX8[9]; //DATX8 Register
732 }DDRPHY_REG_T, *pDDRPHY_REG_T;
734 typedef union NOC_TIMING_Tag
739 unsigned ActToAct : 6;
740 unsigned RdToMiss : 6;
741 unsigned WrToMiss : 6;
742 unsigned BurstLen : 3;
745 unsigned BwRatio : 1;
749 typedef union NOC_ACTIVATE_Tag
754 unsigned Rrd : 4; //bit[0:3]
755 unsigned Faw : 6; //bit[4:9]
756 unsigned Fawbank : 1; //bit 10
757 unsigned reserved : 21;
761 typedef volatile struct MSCH_REG_Tag
763 volatile uint32 coreid;
764 volatile uint32 revisionid;
765 volatile uint32 ddrconf;
766 volatile NOC_TIMING_T ddrtiming;
767 volatile uint32 ddrmode;
768 volatile uint32 readlatency;
769 uint32 reserved1[(0x38-0x18)/4];
770 volatile NOC_ACTIVATE_T activate;
771 volatile uint32 devtodev;
772 }MSCH_REG, *pMSCH_REG;
775 #define DRAM_PHYS (0) //DRAM Channel a physical address start
776 #define pPMU_Reg ((pPMU_FILE)RK_PMU_VIRT)
777 #define pCRU_Reg ((pCRU_REG)RK_CRU_VIRT)
778 #define pGRF_Reg ((pREG_FILE)RK_GRF_VIRT)
779 #define pDDR_REG(ch) ((ch) ? ((pDDR_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)):((pDDR_REG_T)RK_DDR_VIRT))
780 #define pPHY_REG(ch) ((ch) ? ((pDDRPHY_REG_T)(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)) : ((pDDRPHY_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE)))
781 #define pMSCH_REG(ch) ((ch)? ((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT+0x80)):((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT)))
782 #define GET_DDR3_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
783 #define GET_LPDDR2_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
784 #define GET_LPDDR3_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
785 #define DDR_GET_RANK_2_ROW15() (0)
786 #define DDR_GET_BANK_2_RANK() (0)
787 #define DDR_HW_WAKEUP(ch,en) do{pGRF_Reg->GRF_SOC_CON[0] = (1<<(16+5+ch)) | (en<<(5+ch));}while(0)
788 #define READ_GRF_REG() (pGRF_Reg->GRF_SOC_CON[0])
789 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS[1] & (1<<5))
790 #define SET_DDR_PLL_SRC(src, div) do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<2))<<16)|(src<<2)| div;}while(0)
791 #define GET_DDR_PLL_SRC() ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<2)) ? GPLL : DPLL)
792 #define DDR_GPLL_CLK_GATE(en) do{pCRU_Reg->CRU_CLKGATE_CON[0] = 0x02000000 | (en<<9);}while(0)
793 #define SET_DDRPHY_CLKGATE(ch,dis) do{pCRU_Reg->CRU_CLKGATE_CON[4] = ((0x1<<(12+ch))<<16) | (dis<<(12+ch));}while(0)
794 #define READ_DDR_STRIDE() (readl_relaxed(RK_SGRF_VIRT+0x8) &0x1F)
796 #define READ_CH_CNT() (1+((pPMU_Reg->PMU_PMU_SYS_REG[2]>>12)&0x1))
797 #define READ_CH_INFO() ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>28)&0x3)
798 #define READ_CH_ROW_INFO(ch) ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>(30+(ch)))&0x1) //row_3_4:0=normal, 1=6Gb or 12Gb
800 #define SET_PLL_MODE(pll, mode) do{pCRU_Reg->CRU_MODE_CON = ((mode<<((pll)*4))|(0x3<<(16+(pll)*4)));}while(0)
801 #define SET_PLL_PD(pll, pd) do{pCRU_Reg->CRU_PLL_CON[pll][3] = ((0x1<<1)<<16) | (pd<<1);}while(0)
803 #define READ_DRAMTYPE_INFO() ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>13)&0x7)
804 #define READ_CS_INFO(ch) ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(11+(ch)*16))&0x1)+1)
805 #define READ_BW_INFO(ch) (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(2+(ch)*16))&0x3))
806 #define READ_COL_INFO(ch) (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(9+(ch)*16))&0x3))
807 #define READ_BK_INFO(ch) (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(8+(ch)*16))&0x1))
808 #define READ_ROW_INFO(ch,cs) (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(6-(2*cs)+(ch)*16))&0x3))
809 #define READ_DIE_BW_INFO(ch) (2>>((pPMU_Reg->PMU_PMU_SYS_REG[2]>>((ch)*16))&0x3))
811 static const uint16_t ddr_cfg_2_rbc[] =
813 /****************************/
814 // [8:7] bank(n:n bit bank)
816 // [3:2] bank(n:n bit bank)
818 /****************************/
819 //all config have (13col,3bank,16row,1cs)
820 //bank, row, bank, col col bank row(32bit)
821 ((3<<7)|(3<<4)|(0<<2)|2), // 0 11 8 15
822 ((0<<7)|(1<<4)|(3<<2)|1), // 1 10 8 13
823 ((0<<7)|(2<<4)|(3<<2)|1), // 2 10 8 14
824 ((0<<7)|(3<<4)|(3<<2)|1), // 3 10 8 15
825 ((0<<7)|(4<<4)|(3<<2)|1), // 4 10 8 16
826 ((0<<7)|(1<<4)|(3<<2)|2), // 5 11 8 13 // 32bit not use
827 ((0<<7)|(2<<4)|(3<<2)|2), // 6 11 8 14
828 ((0<<7)|(3<<4)|(3<<2)|2), // 7 11 8 15
829 ((0<<7)|(1<<4)|(3<<2)|0), // 8 9 8 13
830 ((0<<7)|(2<<4)|(3<<2)|0), // 9 9 8 14
831 ((0<<7)|(3<<4)|(3<<2)|0), // 10 9 8 15
832 ((0<<7)|(2<<4)|(2<<2)|0), // 11 9 4 14
833 ((0<<7)|(1<<4)|(2<<2)|1), // 12 10 4 13
834 ((0<<7)|(0<<4)|(2<<2)|2), // 13 11 4 12
835 ((3<<7)|(4<<4)|(0<<2)|1), // 14 10 8 16 / 10, 4,15 / 10, 8, 15
836 ((0<<7)|(4<<4)|(3<<2)|2), // 15 11 8 16
839 /***********************************
841 ***********************************/
842 //MR0 (Device Information)
843 #define LPDDR2_DAI (0x1) // 0:DAI complete, 1:DAI still in progress
844 #define LPDDR2_DI (0x1<<1) // 0:S2 or S4 SDRAM, 1:NVM
845 #define LPDDR2_DNVI (0x1<<2) // 0:DNV not supported, 1:DNV supported
846 #define LPDDR2_RZQI (0x3<<3) // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
847 // 10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.
849 //MR1 (Device Feature)
850 #define LPDDR2_BL4 (0x2)
851 #define LPDDR2_BL8 (0x3)
852 #define LPDDR2_BL16 (0x4)
853 #define LPDDR2_nWR(n) (((n)-2)<<5)
855 //MR2 (Device Feature 2)
856 #define LPDDR2_RL3_WL1 (0x1)
857 #define LPDDR2_RL4_WL2 (0x2)
858 #define LPDDR2_RL5_WL2 (0x3)
859 #define LPDDR2_RL6_WL3 (0x4)
860 #define LPDDR2_RL7_WL4 (0x5)
861 #define LPDDR2_RL8_WL4 (0x6)
863 //MR3 (IO Configuration 1)
864 #define LPDDR2_DS_34 (0x1)
865 #define LPDDR2_DS_40 (0x2)
866 #define LPDDR2_DS_48 (0x3)
867 #define LPDDR2_DS_60 (0x4)
868 #define LPDDR2_DS_80 (0x6)
869 #define LPDDR2_DS_120 (0x7) //optional
871 //MR4 (Device Temperature)
872 #define LPDDR2_tREF_MASK (0x7)
873 #define LPDDR2_4_tREF (0x1)
874 #define LPDDR2_2_tREF (0x2)
875 #define LPDDR2_1_tREF (0x3)
876 #define LPDDR2_025_tREF (0x5)
877 #define LPDDR2_025_tREF_DERATE (0x6)
879 #define LPDDR2_TUF (0x1<<7)
881 //MR8 (Basic configuration 4)
882 #define LPDDR2_S4 (0x0)
883 #define LPDDR2_S2 (0x1)
884 #define LPDDR2_N (0x2)
885 #define LPDDR2_Density(mr8) (8<<(((mr8)>>2)&0xf)) // Unit:MB
886 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
889 #define LPDDR2_ZQINIT (0xFF)
890 #define LPDDR2_ZQCL (0xAB)
891 #define LPDDR2_ZQCS (0x56)
892 #define LPDDR2_ZQRESET (0xC3)
894 //MR16 (PASR Bank Mask)
896 #define LPDDR2_PASR_Full (0x0)
897 #define LPDDR2_PASR_1_2 (0x1)
898 #define LPDDR2_PASR_1_4 (0x2)
899 #define LPDDR2_PASR_1_8 (0x3)
901 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
903 //MR32 (DQ Calibration Pattern A)
905 //MR40 (DQ Calibration Pattern B)
907 /***********************************
909 ***********************************/
910 //MR0 (Device Information)
911 #define LPDDR3_DAI (0x1) // 0:DAI complete, 1:DAI still in progress
912 #define LPDDR3_RZQI (0x3<<3) // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
913 // 10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.
914 #define LPDDR3_WL_SUPOT (1<<6) // 0:DRAM does not support WL(Set B), 1:DRAM support WL(Set B)
915 #define LPDDR3_RL3_SUPOT (1<<7) // 0:DRAM does not support RL=3,nWR=3,WL=1; 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
917 //MR1 (Device Feature)
918 #define LPDDR3_BL8 (0x3)
919 #define LPDDR3_nWR(n) ((n)<<5)
921 //MR2 (Device Feature 2)
923 #define LPDDR3_RL3_WL1 (0x1) // <=166MHz,optional
924 #define LPDDR3_RL6_WL3 (0x4) // <=400MHz
925 #define LPDDR3_RL8_WL4 (0x6) // <=533MHz
926 #define LPDDR3_RL9_WL5 (0x7) // <=600MHz
927 #define LPDDR3_RL10_WL6 (0x8) // <=667MHz,default
928 #define LPDDR3_RL11_WL6 (0x9) // <=733MHz
929 #define LPDDR3_RL12_WL6 (0xa) // <=800MHz
930 #define LPDDR3_RL14_WL8 (0xc) // <=933MHz
931 #define LPDDR3_RL16_WL8 (0xe) // <=1066MHz
933 //#define LPDDR3_RL3_WL1 (0x1) // <=166MHz,optional
934 //#define LPDDR3_RL6_WL3 (0x4) // <=400MHz
935 //#define LPDDR3_RL8_WL4 (0x6) // <=533MHz
936 //#define LPDDR3_RL9_WL5 (0x7) // <=600MHz
937 #define LPDDR3_RL10_WL8 (0x8) // <=667MHz,default
938 #define LPDDR3_RL11_WL9 (0x9) // <=733MHz
939 #define LPDDR3_RL12_WL9 (0xa) // <=800MHz
940 #define LPDDR3_RL14_WL11 (0xc) // <=933MHz
941 #define LPDDR3_RL16_WL13 (0xe) // <=1066MHz
943 #define LPDDR3_nWRE (1<<4) // 1:enable nWR programming > 9(defualt)
944 #define LPDDR3_WL_S (1<<6) // 1:Select WL Set B
945 #define LPDDR3_WR_LEVEL (1<<7) // 1:enable
947 //MR3 (IO Configuration 1)
948 #define LPDDR3_DS_34 (0x1)
949 #define LPDDR3_DS_40 (0x2)
950 #define LPDDR3_DS_48 (0x3)
951 #define LPDDR3_DS_60 (0x4) //reserved
952 #define LPDDR3_DS_80 (0x6) //reserved
953 #define LPDDR3_DS_34D_40U (0x9)
954 #define LPDDR3_DS_40D_48U (0xa)
955 #define LPDDR3_DS_34D_48U (0xb)
957 //MR4 (Device Temperature)
958 #define LPDDR3_tREF_MASK (0x7)
959 #define LPDDR3_LT_EXED (0x0) // SDRAM Low temperature operating limit exceeded
960 #define LPDDR3_4_tREF (0x1)
961 #define LPDDR3_2_tREF (0x2)
962 #define LPDDR3_1_tREF (0x3)
963 #define LPDDR3_05_tREF (0x4)
964 #define LPDDR3_025_tREF (0x5)
965 #define LPDDR3_025_tREF_DERATE (0x6)
966 #define LPDDR3_HT_EXED (0x7) // SDRAM High temperature operating limit exceeded
968 #define LPDDR3_TUF (0x1<<7) // 1:value has changed since last read of MR4
970 //MR8 (Basic configuration 4)
971 #define LPDDR3_S8 (0x3)
972 #define LPDDR3_Density(mr8) (8<<((mr8>>2)&0xf)) // Unit:MB
973 #define LPDDR3_IO_Width(mr8) (32>>((mr8>>6)&0x3))
976 #define LPDDR3_ZQINIT (0xFF)
977 #define LPDDR3_ZQCL (0xAB)
978 #define LPDDR3_ZQCS (0x56)
979 #define LPDDR3_ZQRESET (0xC3)
982 #define LPDDR3_ODT_60 (1) //optional for 1333 and 1600
983 #define LPDDR3_ODT_120 (2)
984 #define LPDDR3_ODT_240 (3)
985 #define LPDDR3_ODT_DIS (0)
987 //MR16 (PASR Bank Mask)
989 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
991 //MR32 (DQ Calibration Pattern A)
993 //MR40 (DQ Calibration Pattern B)
995 /***********************************
997 ***********************************/
1000 #define DDR3_BC4_8 (1)
1001 #define DDR3_BC4 (2)
1002 #define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
1003 #define DDR3_WR(n) (((n)&0x7)<<9)
1004 #define DDR3_DLL_RESET (1<<8)
1005 #define DDR3_DLL_DeRESET (0<<8)
1008 #define DDR3_DLL_ENABLE (0)
1009 #define DDR3_DLL_DISABLE (1)
1010 #define DDR3_MR1_AL(n) (((n)&0x3)<<3)
1012 #define DDR3_DS_40 (0)
1013 #define DDR3_DS_34 (1<<1)
1014 #define DDR3_Rtt_Nom_DIS (0)
1015 #define DDR3_Rtt_Nom_60 (1<<2)
1016 #define DDR3_Rtt_Nom_120 (1<<6)
1017 #define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
1020 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
1021 #define DDR3_Rtt_WR_DIS (0)
1022 #define DDR3_Rtt_WR_60 (1<<9)
1023 #define DDR3_Rtt_WR_120 (2<<9)
1025 /***********************************
1027 ***********************************/
1028 //MR; //Mode Register
1029 #define DDR2_BL4 (2)
1030 #define DDR2_BL8 (3)
1031 #define DDR2_CL(n) (((n)&0x7)<<4)
1032 #define DDR2_WR(n) ((((n)-1)&0x7)<<9)
1033 #define DDR2_DLL_RESET (1<<8)
1034 #define DDR2_DLL_DeRESET (0<<8)
1036 //EMR; //Extended Mode Register
1037 #define DDR2_DLL_ENABLE (0)
1038 #define DDR2_DLL_DISABLE (1)
1040 #define DDR2_STR_FULL (0)
1041 #define DDR2_STR_REDUCE (1<<1)
1042 #define DDR2_AL(n) (((n)&0x7)<<3)
1043 #define DDR2_Rtt_Nom_DIS (0)
1044 #define DDR2_Rtt_Nom_150 (0x40)
1045 #define DDR2_Rtt_Nom_75 (0x4)
1046 #define DDR2_Rtt_Nom_50 (0x44)
1048 /***********************************
1050 ***********************************/
1051 #define mDDR_BL2 (1)
1052 #define mDDR_BL4 (2)
1053 #define mDDR_BL8 (3)
1054 #define mDDR_CL(n) (((n)&0x7)<<4)
1056 #define mDDR_DS_Full (0)
1057 #define mDDR_DS_1_2 (1<<5)
1058 #define mDDR_DS_1_4 (2<<5)
1059 #define mDDR_DS_1_8 (3<<5)
1060 #define mDDR_DS_3_4 (4<<5)
1062 static const uint8_t ddr3_cl_cwl[22][7]={
1063 /*speed 0~330 331~400 401~533 534~666 667~800 801~933 934~1066
1064 * tCK >3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07
1065 * cl<<4, cwl cl<<4, cwl cl<<4, cwl */
1066 {((5<<4)|5), ((5<<4)|5), 0 , 0, 0, 0, 0}, //DDR3_800D (5-5-5)
1067 {((5<<4)|5), ((6<<4)|5), 0 , 0, 0, 0, 0}, //DDR3_800E (6-6-6)
1069 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), 0, 0, 0, 0}, //DDR3_1066E (6-6-6)
1070 {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), 0, 0, 0, 0}, //DDR3_1066F (7-7-7)
1071 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), 0, 0, 0, 0}, //DDR3_1066G (8-8-8)
1073 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7), 0, 0, 0}, //DDR3_1333F (7-7-7)
1074 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7), 0, 0, 0}, //DDR3_1333G (8-8-8)
1075 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((9<<4)|7), 0, 0, 0}, //DDR3_1333H (9-9-9)
1076 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), 0, 0, 0}, //DDR3_1333J (10-10-10)
1078 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7), ((8<<4)|8), 0, 0}, //DDR3_1600G (8-8-8)
1079 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7), ((9<<4)|8), 0, 0}, //DDR3_1600H (9-9-9)
1080 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7), ((10<<4)|8), 0, 0}, //DDR3_1600J (10-10-10)
1081 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), ((11<<4)|8), 0, 0}, //DDR3_1600K (11-11-11)
1083 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7), ((9<<4)|8), ((11<<4)|9), 0}, //DDR3_1866J (10-10-10)
1084 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7), ((10<<4)|8), ((11<<4)|9), 0}, //DDR3_1866K (11-11-11)
1085 {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7), ((11<<4)|8), ((12<<4)|9), 0}, //DDR3_1866L (12-12-12)
1086 {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), ((11<<4)|8), ((13<<4)|9), 0}, //DDR3_1866M (13-13-13)
1088 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7), ((9<<4)|8), ((10<<4)|9), ((11<<4)|10)}, //DDR3_2133K (11-11-11)
1089 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7), ((9<<4)|8), ((11<<4)|9), ((12<<4)|10)}, //DDR3_2133L (12-12-12)
1090 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7), ((10<<4)|8), ((12<<4)|9), ((13<<4)|10)}, //DDR3_2133M (13-13-13)
1091 {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7), ((11<<4)|8), ((13<<4)|9), ((14<<4)|10)}, //DDR3_2133N (14-14-14)
1093 {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), ((11<<4)|8), ((13<<4)|9), ((14<<4)|10)} //DDR3_DEFAULT
1096 static const uint16_t ddr3_tRC_tFAW[22]={
1098 ((50<<8)|50), //DDR3_800D (5-5-5)
1099 ((53<<8)|50), //DDR3_800E (6-6-6)
1101 ((49<<8)|50), //DDR3_1066E (6-6-6)
1102 ((51<<8)|50), //DDR3_1066F (7-7-7)
1103 ((53<<8)|50), //DDR3_1066G (8-8-8)
1105 ((47<<8)|45), //DDR3_1333F (7-7-7)
1106 ((48<<8)|45), //DDR3_1333G (8-8-8)
1107 ((50<<8)|45), //DDR3_1333H (9-9-9)
1108 ((51<<8)|45), //DDR3_1333J (10-10-10)
1110 ((45<<8)|40), //DDR3_1600G (8-8-8)
1111 ((47<<8)|40), //DDR3_1600H (9-9-9)
1112 ((48<<8)|40), //DDR3_1600J (10-10-10)
1113 ((49<<8)|40), //DDR3_1600K (11-11-11)
1115 ((45<<8)|35), //DDR3_1866J (10-10-10)
1116 ((46<<8)|35), //DDR3_1866K (11-11-11)
1117 ((47<<8)|35), //DDR3_1866L (12-12-12)
1118 ((48<<8)|35), //DDR3_1866M (13-13-13)
1120 ((44<<8)|35), //DDR3_2133K (11-11-11)
1121 ((45<<8)|35), //DDR3_2133L (12-12-12)
1122 ((46<<8)|35), //DDR3_2133M (13-13-13)
1123 ((47<<8)|35), //DDR3_2133N (14-14-14)
1125 ((53<<8)|50) //DDR3_DEFAULT
1128 typedef enum DRAM_TYPE_Tag
1140 typedef struct PCTRL_TIMING_Tag
1143 //Memory Timing Registers
1144 uint32 togcnt1u; //Toggle Counter 1U Register
1145 uint32 tinit; //t_init Timing Register
1146 uint32 trsth; //Reset High Time Register
1147 uint32 togcnt100n; //Toggle Counter 100N Register
1148 uint32 trefi; //t_refi Timing Register
1149 uint32 tmrd; //t_mrd Timing Register
1150 uint32 trfc; //t_rfc Timing Register
1151 uint32 trp; //t_rp Timing Register
1152 uint32 trtw; //t_rtw Timing Register
1153 uint32 tal; //AL Latency Register
1154 uint32 tcl; //CL Timing Register
1155 uint32 tcwl; //CWL Register
1156 uint32 tras; //t_ras Timing Register
1157 uint32 trc; //t_rc Timing Register
1158 uint32 trcd; //t_rcd Timing Register
1159 uint32 trrd; //t_rrd Timing Register
1160 uint32 trtp; //t_rtp Timing Register
1161 uint32 twr; //t_wr Timing Register
1162 uint32 twtr; //t_wtr Timing Register
1163 uint32 texsr; //t_exsr Timing Register
1164 uint32 txp; //t_xp Timing Register
1165 uint32 txpdll; //t_xpdll Timing Register
1166 uint32 tzqcs; //t_zqcs Timing Register
1167 uint32 tzqcsi; //t_zqcsi Timing Register
1168 uint32 tdqs; //t_dqs Timing Register
1169 uint32 tcksre; //t_cksre Timing Register
1170 uint32 tcksrx; //t_cksrx Timing Register
1171 uint32 tcke; //t_cke Timing Register
1172 uint32 tmod; //t_mod Timing Register
1173 uint32 trstl; //Reset Low Timing Register
1174 uint32 tzqcl; //t_zqcl Timing Register
1175 uint32 tmrr; //t_mrr Timing Register
1176 uint32 tckesr; //t_ckesr Timing Register
1177 uint32 tdpd; //t_dpd Timing Register
1180 typedef union DTPR_0_Tag
1197 typedef union DTPR_1_Tag
1206 unsigned tRTODT : 1;
1207 unsigned reserved12_15 : 4;
1209 unsigned tDQSCK : 3;
1210 unsigned tDQSCKmax : 3;
1211 unsigned reserved30_31 : 2;
1215 typedef union DTPR_2_Tag
1223 unsigned tDLLK : 10;
1224 unsigned reserved29_31 : 3;
1228 typedef struct PHY_TIMING_Tag
1233 uint32 mr[4]; //LPDDR2 no MR0, mr[2] is mDDR MR1
1234 uint32 mr11; //for LPDDR3 only
1237 typedef struct PCTL_REG_Tag
1243 PCTL_TIMING_T pctl_timing;
1244 //DFI Control Registers
1245 uint32 DFITCTRLDELAY;
1248 uint32 DFIODTRANKMAP;
1249 //DFI Write Data Registers
1250 uint32 DFITPHYWRDATA;
1251 uint32 DFITPHYWRLAT;
1252 //DFI Read Data Registers
1253 uint32 DFITRDDATAEN;
1254 uint32 DFITPHYRDLAT;
1255 //DFI Update Registers
1256 uint32 DFITPHYUPDTYPE0;
1257 uint32 DFITPHYUPDTYPE1;
1258 uint32 DFITPHYUPDTYPE2;
1259 uint32 DFITPHYUPDTYPE3;
1260 uint32 DFITCTRLUPDMIN;
1261 uint32 DFITCTRLUPDMAX;
1262 uint32 DFITCTRLUPDDLY;
1265 uint32 DFITCTRLUPDI;
1266 //DFI Status Registers
1269 uint32 DFITDRAMCLKEN;
1270 uint32 DFITDRAMCLKDIS;
1272 //DFI Low Power Register
1276 typedef struct PUBL_DQS_REG_Tag
1299 typedef struct PUBL_REG_Tag
1310 PHY_TIMING_T phy_timing;
1317 typedef struct SET_REG_Tag
1323 typedef struct BACKUP_REG_Tag
1326 /* any addr = 0xFFFFFFFF, indicate invalid */
1327 uint32 pctlAddr[CH_MAX];
1329 uint32 publAddr[CH_MAX];
1331 PUBL_DQS_REG dqs[CH_MAX];
1332 uint32 nocAddr[CH_MAX];
1333 MSCH_REG noc[CH_MAX];
1339 uint32 dpllmodeAddr;
1340 uint32 dpllSlowMode;
1341 uint32 dpllNormalMode;
1342 uint32 dpllResetAddr;
1347 uint32 dpllLockAddr;
1348 uint32 dpllLockMask;
1351 uint32 ddrPllSrcDivAddr;
1352 uint32 ddrPllSrcDiv;
1354 uint32 retenDisAddr;
1360 /* ddr relative grf register */
1361 uint32 grfRegCnt; //if no grf, set 0
1362 SET_REG_T grf[3]; //SET_REG_T grf[grfRegCnt];
1364 /* other ddr relative register */
1365 //uint32 otherRegCnt; // if = 0xFFFFFFFF, indicate invalid
1366 //SET_REG_T other[grfRegCnt];
1367 uint32 endTag; //must = 0xFFFFFFFF
1370 typedef struct CHANNEL_INFO_Tag
1373 uint32 chNum; //channel number,0:channel a; 1:channel b;
1374 pDDR_REG_T pDDR_Reg;
1375 pDDRPHY_REG_T pPHY_Reg;
1376 pMSCH_REG pMSCH_Reg;
1378 DRAM_TYPE mem_type; // =DRAM_MAX, channel invalid
1379 uint32 ddr_speed_bin; // used for ddr3 only
1380 uint32 ddr_capability_per_die; // one chip cs capability
1384 unsigned long screen_ft_us;
1385 unsigned long long t0;
1386 unsigned long long t1;
1390 typedef struct STRIDE_INFO_Tag
1396 static const STRIDE_INFO gStrideInfo[]={
1397 {0x10000000,0x10000000}, // 256
1398 {0x20000000,0x20000000}, // 512
1399 {0x40000000,0x40000000}, // 1G
1400 {0x80000000,0x80000000}, // 2G
1425 {0,0x80000000}, // 4GB
1434 CH_INFO DEFINE_PIE_DATA(ddr_ch[2]);
1435 static pCH_INFO p_ddr_ch[2]; //only used in kern, not pie
1436 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
1437 static BACKUP_REG_T *p_ddr_reg;
1438 static __attribute__((aligned(4096))) uint32 ddr_data_training_buf[32+8192/4]; //data in two channel even use max stride
1439 uint32 DEFINE_PIE_DATA(ddr_freq);
1440 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
1442 /***********************************
1443 * ARCH Relative Data and Function
1444 ***********************************/
1445 static __sramdata uint32 clkr;
1446 static __sramdata uint32 clkf;
1447 static __sramdata uint32 clkod;
1448 uint32 DEFINE_PIE_DATA(ddr_select_gpll_div); // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1449 static uint32 *p_ddr_select_gpll_div;
1451 static void __sramfunc ddr_delayus(uint32 us);
1453 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id) //APLL-1;CPLL-2;DPLL-3;GPLL-4
1457 // freq = (Fin/NR)*NF/OD
1458 if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1) // DPLL Normal mode
1459 ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x1fff)+1) // NF = 2*(CLKF+1)
1460 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1) // NR = CLKR+1
1461 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xF)+1)); // OD = 2^CLKOD
1468 /*****************************************
1469 NR NO NF Fout freq Step finally use
1470 1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
1471 1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
1472 1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
1473 1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
1474 1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
1475 ******************************************/
1476 static uint32 __sramfunc ddr_set_pll_rk3188_plus(uint32 nMHz, uint32 set)
1493 else if(nMHz <= 200)
1497 else if(nMHz <= 300)
1501 else if(nMHz <= 600)
1510 clkf=(nMHz*clkr*clkod)/24;
1511 ret = (24*clkf)/(clkr*clkod);
1515 SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)-1)); //clk_ddr_src = GPLL
1517 SET_PLL_MODE(DPLL,0); //PLL slow-mode
1520 pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
1522 pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
1523 pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
1524 pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
1526 pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
1534 if (GET_DPLL_LOCK_STATUS())
1540 SET_DDR_PLL_SRC(0, 0); //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1541 SET_PLL_MODE(DPLL,1); //PLL normal
1549 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1551 return ddr_set_pll_rk3188_plus(nMHz,set);
1553 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1554 static uint32 (*p_ddr_set_pll)(uint32 nMHz, uint32 set);
1556 static void __sramfunc idle_port(void)
1559 uint32 clk_gate[14];
1561 pPMU_Reg->PMU_IDLE_REQ |= idle_req_core_cfg;
1563 while( (pPMU_Reg->PMU_IDLE_ST & idle_core) == 0 );
1565 //save clock gate status
1567 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1569 //enable all clock gate for request idle
1571 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1573 i = pPMU_Reg->PMU_PWRDN_ST;
1574 j = idle_req_dma_cfg;
1576 if ( (i & pd_peri_pwr_st) == 0 )
1578 j |= idle_req_peri_cfg;
1581 if ( (i & pd_video_pwr_st) == 0 )
1583 j |= idle_req_video_cfg;
1586 if ( (i & pd_gpu_pwr_st) == 0 )
1588 j |= idle_req_gpu_cfg;
1591 if ( (i & pd_hevc_pwr_st) == 0 )
1593 j |= idle_req_hevc_cfg;
1596 if ( (i & pd_vio_pwr_st) == 0 )
1598 j |= idle_req_vio_cfg;
1601 pPMU_Reg->PMU_IDLE_REQ |= j;
1603 while( (pPMU_Reg->PMU_IDLE_ST & j) != j );
1605 //resume clock gate status
1607 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
1610 static void __sramfunc deidle_port(void)
1613 uint32 clk_gate[14];
1615 //save clock gate status
1617 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1619 //enable all clock gate for request idle
1621 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1623 i = pPMU_Reg->PMU_PWRDN_ST;
1624 j = idle_req_dma_cfg;
1626 if ( (i & pd_peri_pwr_st) == 0 )
1628 j |= idle_req_peri_cfg;
1631 if ( (i & pd_video_pwr_st) == 0 )
1633 j |= idle_req_video_cfg;
1636 if ( (i & pd_gpu_pwr_st) == 0 )
1638 j |= idle_req_gpu_cfg;
1641 if ( (i & pd_hevc_pwr_st) == 0 )
1643 j |= idle_req_hevc_cfg;
1646 if ( (i & pd_vio_pwr_st) == 0 )
1648 j |= idle_req_vio_cfg;
1651 pPMU_Reg->PMU_IDLE_REQ &= ~j;
1653 while( (pPMU_Reg->PMU_IDLE_ST & j) != 0 );
1655 pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_core_cfg;
1657 while( (pPMU_Reg->PMU_IDLE_ST & idle_core) != 0 );
1659 //resume clock gate status
1661 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
1665 /***********************************
1666 * Only DDR Relative Function
1667 ***********************************/
1669 /****************************************************************************
1670 Internal sram us delay function
1671 Cpu highest frequency is 1.6 GHz
1673 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1674 *****************************************************************************/
1675 __sramdata volatile uint32 loops_per_us;
1677 #define LPJ_100MHZ 999456UL
1679 static void __sramfunc ddr_delayus(uint32 us)
1683 volatile unsigned int i = (loops_per_us*us);
1686 asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1690 void PIE_FUNC(ddr_copy)(uint64_t *pDest, uint64_t *pSrc, uint32 wword)
1694 for(i=0; i<wword; i++)
1699 EXPORT_PIE_SYMBOL(FUNC(ddr_copy));
1701 static void ddr_get_datatraing_addr(uint32 *pdtar)
1716 for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1718 if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1724 // caculate aglined physical address
1725 addr = __pa((unsigned long)ddr_data_training_buf);
1726 ddr_print("addr=0x%x\n",addr);
1729 addr += (64-(addr&0x3F)); // 64byte align
1735 stride = READ_DDR_STRIDE();
1736 strideSize = gStrideInfo[stride].size;
1737 halfCap = gStrideInfo[stride].halfCap;
1738 ddr_print("stride=%d, size=%d, halfcap=%x\n", stride,strideSize,halfCap);
1740 if(addr & strideSize) // odd stride size
1742 socAddr[0] = addr + strideSize;
1748 socAddr[1] = addr + strideSize;
1750 ddr_print("socAddr[0]=0x%x, socAddr[1]=0x%x\n", socAddr[0], socAddr[1]);
1751 if((stride >= 0x10) && (stride <= 0x13)) // 3GB stride
1754 if(addr < 0x40000000)
1756 chAddr[0] = socAddr[0];
1757 chAddr[1] = socAddr[1] - strideSize;
1759 else if(addr < 0x80000000)
1761 chAddr[0] = socAddr[0] - 0x40000000 + strideSize;
1762 chAddr[1] = socAddr[1] - 0x40000000;
1764 else if(addr < 0xA0000000)
1766 chAddr[0] = socAddr[0] - 0x40000000;
1767 chAddr[1] = socAddr[1] - 0x40000000 - strideSize;
1771 chAddr[0] = socAddr[0] - 0x60000000 + strideSize;
1772 chAddr[1] = socAddr[1] - 0x60000000;
1780 chAddr[0] = socAddr[0];
1781 chAddr[1] = socAddr[1] - strideSize;
1785 chAddr[0] = socAddr[0] - halfCap + strideSize;
1786 chAddr[1] = socAddr[1] - halfCap;
1789 ddr_print("chAddr[0]=0x%x, chAddr[1]=0x%x\n", chAddr[0], chAddr[1]);
1797 for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1799 if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1801 // find out col£¬row£¬bank,config
1802 row = READ_ROW_INFO(ch,0);
1803 bank = READ_BK_INFO(ch);
1804 col = READ_COL_INFO(ch);
1805 bw = READ_BW_INFO(ch);
1806 conf = p_ddr_ch[ch]->pMSCH_Reg->ddrconf;
1807 // according different address mapping, caculate DTAR register value
1809 pdtar[ch] |= ((chAddr[ch])>>bw) & ((0x1<<col)-1); // col
1810 pdtar[ch] |= (((chAddr[ch])>>(bw+col+((ddr_cfg_2_rbc[conf]>>2)&0x3))) & ((0x1<<row)-1)) << 12; // row
1811 if(((ddr_cfg_2_rbc[conf]>>7)&0x3)==3)
1813 pdtar[ch] |= ((((chAddr[ch])>>(bw+col+row)) & ((0x1<<bank)-1)) << 28); // bank
1817 pdtar[ch] |= ((((chAddr[ch])>>(bw+col)) & 0x7) << 28); // bank
1821 ddr_print("dtar[0]=0x%x, dtar[1]=0x%x\n", pdtar[0], pdtar[1]);
1824 static __sramfunc void ddr_reset_dll(uint32 ch)
1826 pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1827 pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1829 pPHY_Reg->ACDLLCR &= ~0x40000000;
1830 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1831 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1832 if(!(pDDR_Reg->PPCFG & 1))
1834 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1835 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1838 pPHY_Reg->ACDLLCR |= 0x40000000;
1839 pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1840 pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1841 if(!(pDDR_Reg->PPCFG & 1))
1843 pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1844 pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1849 static __sramfunc void ddr_move_to_Lowpower_state(uint32 ch)
1851 register uint32 value;
1852 register pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1856 value = pDDR_Reg->STAT.b.ctl_stat;
1857 if(value == Low_power)
1864 pDDR_Reg->SCTL = CFG_STATE;
1866 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1868 pDDR_Reg->SCTL = GO_STATE;
1870 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1872 pDDR_Reg->SCTL = SLEEP_STATE;
1874 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1876 default: //Transitional state
1882 static __sramfunc void ddr_move_to_Access_state(uint32 ch)
1884 register uint32 value;
1885 register pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1886 register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1888 //set auto self-refresh idle
1889 pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00) | DATA(ddr_sr_idle) | (1<<31);
1894 value = pDDR_Reg->STAT.b.ctl_stat;
1895 if((value == Access)
1896 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1903 pDDR_Reg->SCTL = WAKEUP_STATE;
1905 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1906 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1909 pDDR_Reg->SCTL = CFG_STATE;
1911 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1913 pDDR_Reg->SCTL = GO_STATE;
1915 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1916 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1918 default: //Transitional state
1922 /* de_hw_wakeup :enable auto sr if sr_idle != 0 */
1923 DDR_HW_WAKEUP(ch,0);
1926 static __sramfunc void ddr_move_to_Config_state(uint32 ch)
1928 register uint32 value;
1929 register pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1930 register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1932 /* hw_wakeup :disable auto sr */
1933 DDR_HW_WAKEUP(ch,1);
1938 value = pDDR_Reg->STAT.b.ctl_stat;
1946 pDDR_Reg->SCTL = WAKEUP_STATE;
1948 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1949 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1952 pDDR_Reg->SCTL = CFG_STATE;
1954 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1956 default: //Transitional state
1962 //arg°üÀ¨bank_addrºÍcmd_addr
1963 static void __sramfunc ddr_send_command(uint32 ch, uint32 rank, uint32 cmd, uint32 arg)
1965 pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1967 pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1969 while(pDDR_Reg->MCMD & start_cmd);
1972 //¶ÔtypeÀàÐ͵ÄDDRµÄ¼¸¸öcs½øÐÐDTT
1975 static uint32 __sramfunc ddr_data_training_trigger(uint32 ch)
1978 pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1979 pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1981 // disable auto refresh
1982 pDDR_Reg->TREFI = 0;
1984 if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
1985 && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
1988 pPHY_Reg->PGCR |= (1<<1);
1990 // clear DTDONE status
1991 pPHY_Reg->PIR |= CLRSR;
1992 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
1993 pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18); //use cs0 dtt
1995 pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
1998 //¶ÔtypeÀàÐ͵ÄDDRµÄ¼¸¸öcs½øÐÐDTT
2001 static uint32 __sramfunc ddr_data_training(uint32 ch, uint32 cs)
2004 pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2005 pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2007 // wait echo byte DTDONE
2008 while((pPHY_Reg->DATX8[0].DXGSR[0] & 1) != 1);
2009 while((pPHY_Reg->DATX8[1].DXGSR[0] & 1) != 1);
2010 if(!(pDDR_Reg->PPCFG & 1))
2012 while((pPHY_Reg->DATX8[2].DXGSR[0] & 1) != 1);
2013 while((pPHY_Reg->DATX8[3].DXGSR[0] & 1) != 1);
2016 pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18); //restore cs
2019 pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))
2020 | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)
2021 | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
2023 // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×ʱ¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
2026 ddr_send_command(ch,cs, REF_cmd, 0);
2027 ddr_send_command(ch,cs, REF_cmd, 0);
2028 ddr_send_command(ch,cs, REF_cmd, 0);
2029 ddr_send_command(ch,cs, REF_cmd, 0);
2033 ddr_send_command(ch,cs, REF_cmd, 0);
2034 ddr_send_command(ch,cs, REF_cmd, 0);
2036 if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
2037 && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
2040 pPHY_Reg->PGCR &= ~(1<<1);
2042 // resume auto refresh
2043 pDDR_Reg->TREFI = DATA(ddr_reg).pctl.pctl_timing.trefi;
2045 if(pPHY_Reg->PGSR & DTERR)
2055 static void __sramfunc ddr_set_dll_bypass(uint32 ch, uint32 freq)
2057 pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2058 pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2062 pPHY_Reg->DLLGCR &= ~(1<<23);
2063 pPHY_Reg->ACDLLCR |= 0x80000000;
2064 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2065 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2066 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2067 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2068 pPHY_Reg->PIR |= DLLBYP;
2072 pPHY_Reg->DLLGCR |= (1<<23);
2073 pPHY_Reg->ACDLLCR |= 0x80000000;
2074 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2075 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2076 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2077 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2078 pPHY_Reg->PIR |= DLLBYP;
2082 pPHY_Reg->DLLGCR &= ~(1<<23);
2083 pPHY_Reg->ACDLLCR &= ~0x80000000;
2084 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
2085 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
2086 if(!(pDDR_Reg->PPCFG & 1))
2088 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
2089 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
2091 pPHY_Reg->PIR &= ~DLLBYP;
2095 static noinline uint32 ddr_get_parameter(uint32 nMHz)
2103 PCTL_TIMING_T *p_pctl_timing=&(p_ddr_reg->pctl.pctl_timing);
2104 PHY_TIMING_T *p_publ_timing=&(p_ddr_reg->publ.phy_timing);
2105 NOC_TIMING_T *p_noc_timing=&(p_ddr_reg->noc[0].ddrtiming);
2106 NOC_ACTIVATE_T *p_noc_activate=&(p_ddr_reg->noc[0].activate);
2109 uint32 ddr_speed_bin=DDR3_DEFAULT;
2110 uint32 ddr_capability_per_die=0;
2112 for(ch=0;ch<CH_MAX;ch++)
2114 if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
2116 mem_type = p_ddr_ch[ch]->mem_type;
2117 if(ddr_speed_bin == DDR3_DEFAULT)
2119 ddr_speed_bin = p_ddr_ch[ch]->ddr_speed_bin;
2123 ddr_speed_bin = (ddr_speed_bin > p_ddr_ch[ch]->ddr_speed_bin) ? ddr_speed_bin : p_ddr_ch[ch]->ddr_speed_bin;
2125 if(ddr_capability_per_die == 0)
2127 ddr_capability_per_die = p_ddr_ch[ch]->ddr_capability_per_die;
2131 ddr_capability_per_die = (ddr_capability_per_die > p_ddr_ch[ch]->ddr_capability_per_die) ? ddr_capability_per_die : p_ddr_ch[ch]->ddr_capability_per_die;
2137 p_pctl_timing->togcnt1u = nMHz;
2138 p_pctl_timing->togcnt100n = nMHz/10;
2139 p_pctl_timing->tinit = 200;
2140 p_pctl_timing->trsth = 500;
2142 if(mem_type == DDR3)
2144 if(ddr_speed_bin > DDR3_DEFAULT){
2149 #define DDR3_tREFI_7_8_us (78) //unit 100ns
2150 #define DDR3_tMRD (4) //tCK
2151 #define DDR3_tRFC_512Mb (90) //ns
2152 #define DDR3_tRFC_1Gb (110) //ns
2153 #define DDR3_tRFC_2Gb (160) //ns
2154 #define DDR3_tRFC_4Gb (300) //ns
2155 #define DDR3_tRFC_8Gb (350) //ns
2156 #define DDR3_tRTW (2) //register min valid value
2157 #define DDR3_tRAS (37) //ns
2158 #define DDR3_tRRD (10) //ns
2159 #define DDR3_tRTP (7) //ns
2160 #define DDR3_tWR (15) //ns
2161 #define DDR3_tWTR (7) //ns
2162 #define DDR3_tXP (7) //ns
2163 #define DDR3_tXPDLL (24) //ns
2164 #define DDR3_tZQCS (80) //ns
2165 #define DDR3_tZQCSI (0) //ns
2166 #define DDR3_tDQS (1) //tCK
2167 #define DDR3_tCKSRE (10) //ns
2168 #define DDR3_tCKE_400MHz (7) //ns
2169 #define DDR3_tCKE_533MHz (6) //ns
2170 #define DDR3_tMOD (15) //ns
2171 #define DDR3_tRSTL (100) //ns
2172 #define DDR3_tZQCL (320) //ns
2173 #define DDR3_tDLLK (512) //tCK
2206 if(nMHz < 300) //when dll bypss cl = cwl = 6;
2213 cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
2214 cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
2218 if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2220 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
2224 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
2226 p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
2227 p_publ_timing->mr[3] = 0;
2228 /**************************************************
2230 **************************************************/
2232 * tREFI, average periodic refresh interval, 7.8us
2234 p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
2238 p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
2239 p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
2241 * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
2243 if(ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
2245 tmp = DDR3_tRFC_512Mb;
2247 else if(ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
2249 tmp = DDR3_tRFC_1Gb;
2251 else if(ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
2253 tmp = DDR3_tRFC_2Gb;
2255 else if(ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
2257 tmp = DDR3_tRFC_4Gb;
2261 tmp = DDR3_tRFC_8Gb;
2263 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2264 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000);
2266 * tXSR, =tDLLK=512 tCK
2268 p_pctl_timing->texsr = DDR3_tDLLK;
2269 p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
2273 p_pctl_timing->trp = cl;
2274 p_publ_timing->dtpr0.b.tRP = cl;
2276 * WrToMiss=WL*tCK + tWR + tRP + tRCD
2278 p_noc_timing->b.WrToMiss = (cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl);
2282 p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2283 p_noc_timing->b.ActToAct = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2284 p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2286 p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
2287 p_publ_timing->dtpr1.b.tRTW = 0;
2288 p_noc_timing->b.RdToWr = (cl+2-cwl);
2289 p_pctl_timing->tal = al;
2290 p_pctl_timing->tcl = cl;
2291 p_pctl_timing->tcwl = cwl;
2293 * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
2295 p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
2296 p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000);
2300 p_pctl_timing->trcd = cl;
2301 p_publ_timing->dtpr0.b.tRCD = cl;
2303 * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2304 * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2305 * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2308 tmp = ((DDR3_tRRD*nMHz+999)/1000);
2313 p_pctl_timing->trrd = (tmp&0xF);
2314 p_publ_timing->dtpr0.b.tRRD = tmp;
2315 p_noc_activate->b.Rrd = tmp;
2317 * tRTP, max(4 tCK,7.5ns)
2319 tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2324 p_pctl_timing->trtp = tmp&0xF;
2325 p_publ_timing->dtpr0.b.tRTP = tmp;
2327 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2329 p_noc_timing->b.RdToMiss = (tmp+cl+cl-(bl>>1));
2333 tmp = ((DDR3_tWR*nMHz+999)/1000);
2334 p_pctl_timing->twr = tmp&0x1F;
2341 tmp += (tmp&0x1) ? 1:0;
2344 bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2345 p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2348 * tWTR, max(4 tCK,7.5ns)
2350 tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2355 p_pctl_timing->twtr = tmp&0xF;
2356 p_publ_timing->dtpr0.b.tWTR = tmp;
2360 p_noc_timing->b.WrToRd = (tmp+cwl);
2362 * tXP, max(3 tCK, 7.5ns)(<933MHz)
2364 tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2369 p_pctl_timing->txp = tmp&0x7;
2371 * tXPDLL, max(10 tCK,24ns)
2373 tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2378 p_pctl_timing->txpdll = tmp & 0x3F;
2379 p_publ_timing->dtpr2.b.tXP = tmp;
2381 * tZQCS, max(64 tCK, 80ns)
2383 tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2388 p_pctl_timing->tzqcs = tmp&0x7F;
2392 p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2396 p_pctl_timing->tdqs = DDR3_tDQS;
2398 * tCKSRE, max(5 tCK, 10ns)
2400 tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2405 p_pctl_timing->tcksre = tmp & 0x1F;
2407 * tCKSRX, max(5 tCK, 10ns)
2409 p_pctl_timing->tcksrx = tmp & 0x1F;
2411 * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2415 tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2419 tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2425 p_pctl_timing->tcke = tmp & 0x7;
2427 * tCKESR, =tCKE + 1tCK
2429 p_pctl_timing->tckesr = (tmp+1)&0xF;
2430 p_publ_timing->dtpr2.b.tCKE = tmp+1;
2432 * tMOD, max(12 tCK,15ns)
2434 tmp = ((DDR3_tMOD*nMHz+999)/1000);
2439 p_pctl_timing->tmod = tmp&0x1F;
2440 p_publ_timing->dtpr1.b.tMOD = (tmp-12);
2444 p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2446 * tZQCL, max(256 tCK, 320ns)
2448 tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2453 p_pctl_timing->tzqcl = tmp&0x3FF;
2457 p_pctl_timing->tmrr = 0;
2461 p_pctl_timing->tdpd = 0;
2463 /**************************************************
2465 **************************************************/
2467 * tCCD, BL/2 for DDR2 and 4 for DDR3
2469 p_publ_timing->dtpr0.b.tCCD = 0;
2473 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2475 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2476 * 1:ODT may not be turned on until one clock after the read post-amble
2478 p_publ_timing->dtpr1.b.tRTODT = 1;
2480 * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page) 50ns(533MHz 2KB page)
2482 tmp = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000);
2483 p_publ_timing->dtpr1.b.tFAW = tmp;
2484 p_noc_activate->b.Fawbank = 1;
2485 p_noc_activate->b.Faw = tmp;
2489 p_publ_timing->dtpr1.b.tAOND = 0;
2493 p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2494 /**************************************************
2496 **************************************************/
2497 p_noc_timing->b.BurstLen = (bl>>1);
2499 else if(mem_type == LPDDR2)
2501 #define LPDDR2_tREFI_3_9_us (39) //unit 100ns
2502 #define LPDDR2_tREFI_7_8_us (78) //unit 100ns
2503 #define LPDDR2_tMRD (5) //tCK
2504 #define LPDDR2_tRFC_8Gb (210) //ns
2505 #define LPDDR2_tRFC_4Gb (130) //ns
2506 #define LPDDR2_tRPpb_4_BANK (24) //ns
2507 #define LPDDR2_tRPab_SUB_tRPpb_4_BANK (0) //ns
2508 #define LPDDR2_tRPpb_8_BANK (24) //ns
2509 #define LPDDR2_tRPab_SUB_tRPpb_8_BANK (3) //ns
2510 #define LPDDR2_tRTW (1) //tCK register min valid value
2511 #define LPDDR2_tRAS (42) //ns
2512 #define LPDDR2_tRCD (24) //ns
2513 #define LPDDR2_tRRD (10) //ns
2514 #define LPDDR2_tRTP (7) //ns
2515 #define LPDDR2_tWR (15) //ns
2516 #define LPDDR2_tWTR_GREAT_200MHz (7) //ns
2517 #define LPDDR2_tWTR_LITTLE_200MHz (10) //ns
2518 #define LPDDR2_tXP (7) //ns
2519 #define LPDDR2_tXPDLL (0)
2520 #define LPDDR2_tZQCS (90) //ns
2521 #define LPDDR2_tZQCSI (0)
2522 #define LPDDR2_tDQS (1)
2523 #define LPDDR2_tCKSRE (1) //tCK
2524 #define LPDDR2_tCKSRX (2) //tCK
2525 #define LPDDR2_tCKE (3) //tCK
2526 #define LPDDR2_tMOD (0)
2527 #define LPDDR2_tRSTL (0)
2528 #define LPDDR2_tZQCL (360) //ns
2529 #define LPDDR2_tMRR (2) //tCK
2530 #define LPDDR2_tCKESR (15) //ns
2531 #define LPDDR2_tDPD_US (500) //us
2532 #define LPDDR2_tFAW_GREAT_200MHz (50) //ns
2533 #define LPDDR2_tFAW_LITTLE_200MHz (60) //ns
2534 #define LPDDR2_tDLLK (2) //tCK
2535 #define LPDDR2_tDQSCK_MAX (3) //tCK
2536 #define LPDDR2_tDQSCK_MIN (0) //tCK
2537 #define LPDDR2_tDQSS (1) //tCK
2548 bl = 4; //you can change burst here
2552 bl = 8; // freq < 200MHz, BL fixed 8
2554 /* 1066 933 800 667 533 400 333
2562 p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2568 p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2574 p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2580 p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2586 p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2592 p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2594 p_publ_timing->mr[3] = LPDDR2_DS_34;
2595 p_publ_timing->mr[0] = 0;
2596 /**************************************************
2598 **************************************************/
2600 * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2602 if(ddr_capability_per_die >= 0x10000000) // 2Gb
2604 p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2608 p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2612 * tMRD, (=tMRW), 5 tCK
2614 p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2615 p_publ_timing->dtpr0.b.tMRD = 3;
2617 * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2619 if(ddr_capability_per_die >= 0x40000000) // 8Gb
2621 p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2622 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000);
2624 * tXSR, max(2tCK,tRFC+10ns)
2626 tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
2630 p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2631 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000);
2632 tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
2638 p_pctl_timing->texsr = tmp&0x3FF;
2639 p_publ_timing->dtpr2.b.tXS = tmp;
2642 * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
2644 //if(pPHY_Reg->DCR.b.DDR8BNK)
2647 trp_tmp = ((LPDDR2_tRPpb_8_BANK*nMHz+999)/1000);
2652 p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
2656 trp_tmp = ((LPDDR2_tRPpb_4_BANK*nMHz+999)/1000);
2661 p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
2663 p_publ_timing->dtpr0.b.tRP = trp_tmp;
2665 * tRAS, max(3tCK,42ns)
2667 tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
2672 p_pctl_timing->tras = (tras_tmp&0x3F);
2673 p_publ_timing->dtpr0.b.tRAS = tras_tmp;
2676 * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
2678 trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
2683 p_pctl_timing->trcd = (trcd_tmp&0xF);
2684 p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
2687 * tRTP, max(2tCK, 7.5ns)
2689 trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2694 p_pctl_timing->trtp = trtp_tmp&0xF;
2695 p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
2698 * tWR, max(3tCK,15ns)
2700 twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
2705 p_pctl_timing->twr = twr_tmp&0x1F;
2706 bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2707 p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
2710 * WrToMiss=WL*tCK + tWR + tRP + tRCD
2712 p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
2714 * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2716 p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
2720 p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
2721 p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
2722 p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
2727 p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
2728 p_publ_timing->dtpr1.b.tRTW = 0;
2729 p_noc_timing->b.RdToWr = (cl+2-cwl);
2730 p_pctl_timing->tal = al;
2731 p_pctl_timing->tcl = cl;
2732 p_pctl_timing->tcwl = cwl;
2734 * tRRD, max(2tCK,10ns)
2736 tmp=((LPDDR2_tRRD*nMHz+999)/1000);
2741 p_pctl_timing->trrd = (tmp&0xF);
2742 p_publ_timing->dtpr0.b.tRRD = tmp;
2743 p_noc_activate->b.Rrd = tmp;
2745 * tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz))
2749 tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2753 tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2759 p_pctl_timing->twtr = tmp&0xF;
2760 p_publ_timing->dtpr0.b.tWTR = tmp;
2764 p_noc_timing->b.WrToRd = (cwl+tmp);
2766 * tXP, max(2tCK,7.5ns)
2768 tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
2773 p_pctl_timing->txp = tmp&0x7;
2774 p_publ_timing->dtpr2.b.tXP = tmp;
2778 p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2782 p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2786 //if(pDDR_Reg->MCFG &= lpddr2_s4)
2789 p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2793 p_pctl_timing->tzqcsi = 0;
2798 p_pctl_timing->tdqs = LPDDR2_tDQS;
2802 p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2806 p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2810 p_pctl_timing->tcke = LPDDR2_tCKE;
2811 p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2815 p_pctl_timing->tmod = LPDDR2_tMOD;
2816 p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2820 p_pctl_timing->trstl = LPDDR2_tRSTL;
2824 p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2828 p_pctl_timing->tmrr = LPDDR2_tMRR;
2830 * tCKESR, max(3tCK,15ns)
2832 tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
2837 p_pctl_timing->tckesr = tmp&0xF;
2841 p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2843 /**************************************************
2845 **************************************************/
2847 * tCCD, BL/2 for DDR2 and 4 for DDR3
2849 p_publ_timing->dtpr0.b.tCCD = 0;
2853 p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2857 p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2859 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2860 * 1:ODT may not be turned on until one clock after the read post-amble
2862 p_publ_timing->dtpr1.b.tRTODT = 1;
2864 * tFAW,max(8tCK, 50ns(200-533MHz) 60ns(166MHz))
2868 tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
2872 tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
2878 p_publ_timing->dtpr1.b.tFAW = tmp;
2879 p_noc_activate->b.Fawbank = 1;
2880 p_noc_activate->b.Faw = tmp;
2884 p_publ_timing->dtpr1.b.tAOND = 0;
2888 p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2889 /**************************************************
2891 **************************************************/
2892 p_noc_timing->b.BurstLen = (bl>>1);
2894 else if(mem_type == LPDDR3)
2896 #define LPDDR3_tREFI_3_9_us (39) //unit 100ns
2897 #define LPDDR3_tMRD (10) //tCK
2898 #define LPDDR3_tRFC_8Gb (210) //ns
2899 #define LPDDR3_tRFC_4Gb (130) //ns
2900 #define LPDDR3_tRPpb_8_BANK (24) //ns
2901 #define LPDDR3_tRPab_SUB_tRPpb_8_BANK (3) //ns
2902 #define LPDDR3_tRTW (1) //tCK register min valid value
2903 #define LPDDR3_tRAS (42) //ns
2904 #define LPDDR3_tRCD (24) //ns
2905 #define LPDDR3_tRRD (10) //ns
2906 #define LPDDR3_tRTP (7) //ns
2907 #define LPDDR3_tWR (15) //ns
2908 #define LPDDR3_tWTR (7) //ns
2909 #define LPDDR3_tXP (7) //ns
2910 #define LPDDR3_tXPDLL (0)
2911 #define LPDDR3_tZQCS (90) //ns
2912 #define LPDDR3_tZQCSI (0)
2913 #define LPDDR3_tDQS (1)
2914 #define LPDDR3_tCKSRE (2) //tCK
2915 #define LPDDR3_tCKSRX (2) //tCK
2916 #define LPDDR3_tCKE (3) //tCK
2917 #define LPDDR3_tMOD (0)
2918 #define LPDDR3_tRSTL (0)
2919 #define LPDDR3_tZQCL (360) //ns
2920 #define LPDDR3_tMRR (4) //tCK
2921 #define LPDDR3_tCKESR (15) //ns
2922 #define LPDDR3_tDPD_US (500) //us
2923 #define LPDDR3_tFAW (50) //ns
2924 #define LPDDR3_tDLLK (2) //tCK
2925 #define LPDDR3_tDQSCK_MAX (3) //tCK
2926 #define LPDDR3_tDQSCK_MIN (0) //tCK
2927 #define LPDDR3_tDQSS (1) //tCK
2937 /* Only support Write Latency Set A here
2938 * 1066 933 800 733 667 600 533 400 166
2939 * RL, 16 14 12 11 10 9 8 6 3
2940 * WL, 8 8 6 6 6 5 4 3 1
2946 p_publ_timing->mr[2] = LPDDR3_RL3_WL1;
2952 p_publ_timing->mr[2] = LPDDR3_RL6_WL3;
2958 p_publ_timing->mr[2] = LPDDR3_RL8_WL4;
2964 p_publ_timing->mr[2] = LPDDR3_RL9_WL5;
2970 p_publ_timing->mr[2] = LPDDR3_RL10_WL6;
2976 p_publ_timing->mr[2] = LPDDR3_RL11_WL6;
2982 p_publ_timing->mr[2] = LPDDR3_RL12_WL6;
2988 p_publ_timing->mr[2] = LPDDR3_RL14_WL8;
2994 p_publ_timing->mr[2] = LPDDR3_RL16_WL8;
2996 p_publ_timing->mr[3] = LPDDR3_DS_34;
2997 if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2999 p_publ_timing->mr11 = LPDDR3_ODT_DIS;
3003 p_publ_timing->mr11 = LPDDR3_ODT_240;
3005 p_publ_timing->mr[0] = 0;
3006 /**************************************************
3008 **************************************************/
3010 * tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb)
3012 p_pctl_timing->trefi = LPDDR3_tREFI_3_9_us;
3015 * tMRD, (=tMRW), 10 tCK
3017 p_pctl_timing->tmrd = LPDDR3_tMRD & 0x7;
3018 p_publ_timing->dtpr0.b.tMRD = 3; //max value
3020 * tRFC, 130ns(4Gb) 210ns(>4Gb)
3022 if(ddr_capability_per_die > 0x20000000) // >4Gb
3024 p_pctl_timing->trfc = (LPDDR3_tRFC_8Gb*nMHz+999)/1000;
3025 p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_8Gb*nMHz+999)/1000);
3027 * tXSR, max(2tCK,tRFC+10ns)
3029 tmp=(((LPDDR3_tRFC_8Gb+10)*nMHz+999)/1000);
3033 p_pctl_timing->trfc = (LPDDR3_tRFC_4Gb*nMHz+999)/1000;
3034 p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_4Gb*nMHz+999)/1000);
3035 tmp=(((LPDDR3_tRFC_4Gb+10)*nMHz+999)/1000);
3041 p_pctl_timing->texsr = tmp&0x3FF;
3042 p_publ_timing->dtpr2.b.tXS = tmp;
3045 * tRP, max(3tCK, 18ns(Fast) 21ns(Typ) 27ns(Slow))
3047 //if(pPHY_Reg->DCR.b.DDR8BNK)
3050 trp_tmp = ((LPDDR3_tRPpb_8_BANK*nMHz+999)/1000);
3055 p_pctl_timing->trp = ((((LPDDR3_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
3057 p_publ_timing->dtpr0.b.tRP = trp_tmp;
3059 * tRAS, max(3tCK,42ns)
3061 tras_tmp=((LPDDR3_tRAS*nMHz+999)/1000);
3066 p_pctl_timing->tras = (tras_tmp&0x3F);
3067 p_publ_timing->dtpr0.b.tRAS = tras_tmp;
3070 * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
3072 trcd_tmp = ((LPDDR3_tRCD*nMHz+999)/1000);
3077 p_pctl_timing->trcd = (trcd_tmp&0xF);
3078 p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
3081 * tRTP, max(4tCK, 7.5ns)
3083 trtp_tmp = ((LPDDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
3088 p_pctl_timing->trtp = trtp_tmp&0xF;
3089 p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
3092 * tWR, max(4tCK,15ns)
3094 twr_tmp=((LPDDR3_tWR*nMHz+999)/1000);
3099 p_pctl_timing->twr = twr_tmp&0x1F;
3100 bl_tmp = LPDDR3_BL8;
3101 p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
3104 * WrToMiss=WL*tCK + tWR + tRP + tRCD
3106 p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
3108 * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
3110 p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
3114 p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
3115 p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
3116 p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
3121 p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
3122 p_publ_timing->dtpr1.b.tRTW = 0;
3123 p_noc_timing->b.RdToWr = (cl+2-cwl);
3124 p_pctl_timing->tal = al;
3125 p_pctl_timing->tcl = cl;
3126 p_pctl_timing->tcwl = cwl;
3128 * tRRD, max(2tCK,10ns)
3130 tmp=((LPDDR3_tRRD*nMHz+999)/1000);
3135 p_pctl_timing->trrd = (tmp&0xF);
3136 p_publ_timing->dtpr0.b.tRRD = tmp;
3137 p_noc_activate->b.Rrd = tmp;
3139 * tWTR, max(4tCK, 7.5ns)
3141 tmp=((LPDDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
3146 p_pctl_timing->twtr = tmp&0xF;
3147 p_publ_timing->dtpr0.b.tWTR = tmp;
3151 p_noc_timing->b.WrToRd = (cwl+tmp);
3153 * tXP, max(3tCK,7.5ns)
3155 tmp=((LPDDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
3160 p_pctl_timing->txp = tmp&0x7;
3161 p_publ_timing->dtpr2.b.tXP = tmp;
3165 p_pctl_timing->txpdll = LPDDR3_tXPDLL;
3169 p_pctl_timing->tzqcs = ((LPDDR3_tZQCS*nMHz+999)/1000)&0x7F;
3173 p_pctl_timing->tzqcsi = LPDDR3_tZQCSI;
3177 p_pctl_timing->tdqs = LPDDR3_tDQS;
3179 * tCKSRE=tCPDED, 2 tCK
3181 p_pctl_timing->tcksre = LPDDR3_tCKSRE;
3185 p_pctl_timing->tcksrx = LPDDR3_tCKSRX;
3187 * tCKE, (max 7.5ns,3 tCK)
3189 tmp=((7*nMHz+(nMHz>>1)+999)/1000);
3194 p_pctl_timing->tcke = tmp;
3195 p_publ_timing->dtpr2.b.tCKE = tmp;
3199 p_pctl_timing->tmod = LPDDR3_tMOD;
3200 p_publ_timing->dtpr1.b.tMOD = LPDDR3_tMOD;
3204 p_pctl_timing->trstl = LPDDR3_tRSTL;
3208 p_pctl_timing->tzqcl = ((LPDDR3_tZQCL*nMHz+999)/1000)&0x3FF;
3212 p_pctl_timing->tmrr = LPDDR3_tMRR;
3214 * tCKESR, max(3tCK,15ns)
3216 tmp = ((LPDDR3_tCKESR*nMHz+999)/1000);
3221 p_pctl_timing->tckesr = tmp&0xF;
3225 p_pctl_timing->tdpd = LPDDR3_tDPD_US;
3227 /**************************************************
3229 **************************************************/
3231 * tCCD, BL/2 for DDR2 and 4 for DDR3
3233 p_publ_timing->dtpr0.b.tCCD = 0;
3237 p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR3_tDQSCK_MAX;
3241 p_publ_timing->dtpr1.b.tDQSCK = LPDDR3_tDQSCK_MIN;
3243 * tRTODT, 0:ODT may be turned on immediately after read post-amble
3244 * 1:ODT may not be turned on until one clock after the read post-amble
3246 p_publ_timing->dtpr1.b.tRTODT = 1;
3248 * tFAW,max(8tCK, 50ns)
3250 tmp=((LPDDR3_tFAW*nMHz+999)/1000);
3255 p_publ_timing->dtpr1.b.tFAW = tmp;
3256 p_noc_activate->b.Fawbank = 1;
3257 p_noc_activate->b.Faw = tmp;
3261 p_publ_timing->dtpr1.b.tAOND = 0;
3265 p_publ_timing->dtpr2.b.tDLLK = LPDDR3_tDLLK;
3266 /**************************************************
3268 **************************************************/
3269 p_noc_timing->b.BurstLen = (bl>>1);
3276 static uint32 __sramfunc ddr_update_timing(uint32 ch)
3279 PCTL_TIMING_T *p_pctl_timing=&(DATA(ddr_reg).pctl.pctl_timing);
3280 PHY_TIMING_T *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3281 NOC_TIMING_T *p_noc_timing=&(DATA(ddr_reg).noc[0].ddrtiming);
3282 NOC_ACTIVATE_T *p_noc_activate=&(DATA(ddr_reg).noc[0].activate);
3283 pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3284 pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3285 pMSCH_REG pMSCH_Reg= DATA(ddr_ch[ch]).pMSCH_Reg;
3287 FUNC(ddr_copy)((uint64_t *)&(pDDR_Reg->TOGCNT1U), (uint64_t*)&(p_pctl_timing->togcnt1u), 17);
3288 pPHY_Reg->DTPR[0] = p_publ_timing->dtpr0.d32;
3289 pPHY_Reg->DTPR[1] = p_publ_timing->dtpr1.d32;
3290 pPHY_Reg->DTPR[2] = p_publ_timing->dtpr2.d32;
3291 pMSCH_Reg->ddrtiming.d32 = (pMSCH_Reg->ddrtiming.b.BwRatio) | p_noc_timing->d32;
3292 pMSCH_Reg->activate.d32 = p_noc_activate->d32;
3294 if(DATA(ddr_ch[ch]).mem_type == DDR3)
3296 bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3297 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
3298 if(DATA(ddr_freq) <= DDR3_DDR2_DLL_DISABLE_FREQ)
3300 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-3;
3304 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
3306 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
3308 else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3310 if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
3312 bl_tmp = mddr_lpddr2_bl_8;
3314 else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3316 bl_tmp = mddr_lpddr2_bl_4;
3318 else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
3320 bl_tmp = mddr_lpddr2_bl_16;
3322 if((DATA(ddr_freq)>=200)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3324 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3328 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
3330 i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
3331 pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8); //tDQSCKmax-tDQSCK
3332 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-1;
3333 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL;
3339 static uint32 __sramfunc ddr_update_mr(uint32 ch)
3341 PHY_TIMING_T *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3343 pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3345 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3346 dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
3347 FUNC(ddr_copy)((uint64_t *)&(pPHY_Reg->MR[0]), (uint64_t*)&(p_publ_timing->mr[0]), 2);
3348 if(DATA(ddr_ch[ch]).mem_type == DDR3)
3350 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
3351 if(DATA(ddr_freq)>DDR3_DDR2_DLL_DISABLE_FREQ)
3353 if(dll_off) // off -> on
3355 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1]))); //DLL enable
3356 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
3357 ddr_delayus(1); //at least 200 DDR cycle
3358 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3362 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
3363 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3368 pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3369 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE)); //DLL disable
3370 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3373 else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3375 ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
3376 ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
3377 ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
3378 if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3380 ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(11) | lpddr2_op((p_publ_timing->mr11)));
3385 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3386 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
3391 static void __sramfunc ddr_update_odt(uint32 ch)
3394 pDDR_REG_T pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3395 pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3397 //adjust DRV and ODT
3398 if((DATA(ddr_ch[ch]).mem_type == DDR3) || (DATA(ddr_ch[ch]).mem_type == LPDDR3))
3400 if(DATA(ddr_freq) <= DDR3_DDR2_ODT_DISABLE_FREQ)
3402 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
3403 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3404 if(!(pDDR_Reg->PPCFG & 1))
3406 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3407 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3412 pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9); //dynamic RTT enable
3413 pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
3414 if(!(pDDR_Reg->PPCFG & 1))
3416 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
3417 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
3423 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
3424 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3425 if(!(pDDR_Reg->PPCFG & 1))
3427 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3428 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3431 if(DATA(ddr_ch[ch]).mem_type == LPDDR2)
3433 tmp = GET_LPDDR2_DS_ODT(); //DS=34ohm,ODT=171ohm
3435 else if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3437 tmp = GET_LPDDR3_DS_ODT(); //DS=34ohm,ODT=171ohm
3441 tmp = GET_DDR3_DS_ODT(); //DS=34ohm,ODT=171ohm
3443 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3446 pPHY_Reg->ZQ1CR[0] = tmp;
3449 pPHY_Reg->ZQ0CR[0] = tmp;
3453 void PIE_FUNC(ddr_adjust_config)(void *arg)
3455 uint32 value[CH_MAX];
3457 pDDR_REG_T pDDR_Reg;
3458 pDDRPHY_REG_T pPHY_Reg;
3460 for(ch=0;ch<CH_MAX;ch++)
3462 if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3464 value[ch] = ((uint32 *)arg)[ch];
3465 pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3466 pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3468 //enter config state
3469 ddr_move_to_Config_state(ch);
3471 //set data training address
3472 pPHY_Reg->DTAR = value[ch];
3474 //set auto power down idle
3475 pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
3478 pPHY_Reg->PGCR &= ~(0x3<<12);
3480 //enable the hardware low-power interface
3481 pDDR_Reg->SCFG.b.hw_low_power_en = 1;
3483 if(pDDR_Reg->PPCFG & 1)
3485 pPHY_Reg->DATX8[2].DXGCR &= ~(1); //disable byte
3486 pPHY_Reg->DATX8[3].DXGCR &= ~(1);
3487 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000; //disable DLL
3488 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
3493 //enter access state
3494 ddr_move_to_Access_state(ch);
3498 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
3500 static void ddr_adjust_config(void)
3502 uint32 dtar[CH_MAX];
3505 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3507 //get data training address before idle port
3508 ddr_get_datatraing_addr(dtar);
3510 /** 1. Make sure there is no host access */
3516 for(i=0;i<SRAM_SIZE/4096;i++)
3521 for(i=0;i<CH_MAX;i++)
3523 if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3525 n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3526 n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3527 n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3530 n= pCRU_Reg->CRU_PLL_CON[0][0];
3531 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3535 call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
3537 rockchip_sram_stack);
3538 //disable unused channel
3539 for(i=0;i<CH_MAX;i++)
3541 if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3548 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
3551 pDDR_REG_T pDDR_Reg;
3552 pDDRPHY_REG_T pPHY_Reg;
3554 for(ch=0;ch<CH_MAX;ch++)
3556 pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3557 pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3559 if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3561 ddr_move_to_Lowpower_state(ch);
3562 pDDR_Reg->TZQCSI = 0;
3567 #if defined(CONFIG_ARCH_RK3066B)
3568 static __sramdata uint32 data8_dqstr[25][4];
3569 static __sramdata uint32 min_ddr_freq,dqstr_flag=false;
3571 int ddr_get_datatraing_value_3168(bool end_flag,uint32 dqstr_value,uint32 min_freq)
3573 if(end_flag == true)
3575 dqstr_flag = true; //complete learn data training value flag
3576 min_ddr_freq = min_freq;
3580 data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3581 data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3582 data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3583 data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3585 ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3586 clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3587 data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3591 static void __sramfunc ddr_set_pll_enter_3168(uint32 freq_slew)
3593 uint32 value_1u,value_100n;
3594 ddr_move_to_Config_state();
3598 value_100n = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3599 value_1u = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3600 DATA(ddr_reg).pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3601 DATA(ddr_reg).pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3602 ddr_update_timing();
3604 DATA(ddr_reg).pctl.pctl_timing.togcnt100n = value_100n;
3605 DATA(ddr_reg).pctl.pctl_timing.togcnt1u = value_1u;
3609 pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3610 pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3613 pDDR_Reg->TZQCSI = 0;
3614 ddr_move_to_Lowpower_state();
3616 ddr_set_dll_bypass(0); //dll bypass
3617 SET_DDRPHY_CLKGATE(ch,1); //disable DDR PHY clock
3621 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32 dqstr_value)
3623 SET_DDRPHY_CLKGATE(ch,0); //enable DDR PHY clock
3625 ddr_set_dll_bypass(DATA(ddr_freq));
3628 if(dqstr_flag==true)
3630 pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3631 pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3632 pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3633 pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3637 ddr_move_to_Config_state();
3640 pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3641 pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3642 pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl.pctl_timing.tzqcsi;
3646 ddr_update_timing();
3649 ddr_data_training();
3650 ddr_move_to_Access_state();
3654 static void __sramfunc ddr_chb_update_timing_odt(void)
3656 ddr_set_dll_bypass(1,0); //always use dll bypass
3657 ddr_update_timing(1);
3661 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3662 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew,uint32 dqstr_value)
3667 /** 2. ddr enter self-refresh mode or precharge power-down mode */
3669 #if defined(CONFIG_ARCH_RK3066B)
3670 ddr_set_pll_enter_3168(freq_slew);
3672 ddr_selfrefresh_enter(freq);
3675 /** 3. change frequence */
3676 FUNC(ddr_set_pll)(freq,1);
3677 DATA(ddr_freq) = freq;
3679 /** 5. Issues a Mode Exit command */
3680 #if defined(CONFIG_ARCH_RK3066B)
3681 ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3683 //ddr_selfrefresh_exit();
3684 if(DATA(ddr_ch[1]).mem_type != DRAM_MAX)
3686 ddr_chb_update_timing_odt();
3688 ddr_set_dll_bypass(0,0); //always use dll bypass
3689 ddr_update_timing(0);
3691 FUNC(ddr_set_pll)(freq,2);
3692 for(ch=0;ch<CH_MAX;ch++)
3694 if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3696 ddr_set_dll_bypass(ch,DATA(ddr_freq));
3698 //ddr_delayus(10); //wait DLL lock
3700 ddr_move_to_Config_state(ch);
3702 cs[ch] = ddr_data_training_trigger(ch);
3705 for(ch=0;ch<CH_MAX;ch++)
3707 if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3709 n = ddr_data_training(ch,cs[ch]);
3710 ddr_move_to_Access_state(ch);
3713 sram_printascii("DTT failed!\n");
3722 struct ddr_change_freq_sram_param {
3729 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
3731 struct ddr_change_freq_sram_param *param = arg;
3732 loops_per_us = LPJ_100MHZ * param->arm_freq / 1000000;
3733 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3734 ddr_SRE_2_SRX(param->freq, param->freq_slew, param->dqstr_value);
3736 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
3738 static int dclk_div;
3739 static noinline uint32 ddr_change_freq_sram(uint32 nMHz , struct ddr_freq_t ddr_freq_t)
3743 uint32 dqstr_value=0;
3744 unsigned long flags;
3745 struct ddr_change_freq_sram_param param;
3747 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3751 #if defined(CONFIG_ARCH_RK3066B)
3752 if(dqstr_flag==true)
3754 dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
3755 freq_slew = (nMHz>ddr_freq)? 1 : 0;
3759 dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(29)) >> 8) & 0xff;
3761 param.arm_freq = ddr_get_pll_freq(APLL);
3762 gpllvaluel = ddr_get_pll_freq(GPLL);
3763 if((200 < gpllvaluel) ||( gpllvaluel <1600)) //GPLL:200MHz~1600MHz
3765 if( gpllvaluel > 800) //800-1600MHz /4:200MHz-400MHz
3767 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 4;
3769 else if( gpllvaluel > 400) //400-800MHz /2:200MHz-400MHz
3771 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 2;
3773 else //200-400MHz /1:200MHz-400MHz
3775 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 1;
3780 ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3782 freq=p_ddr_set_pll(nMHz,0);
3784 ddr_get_parameter(freq);
3786 /** 1. Make sure there is no host access */
3787 local_irq_save(flags);
3788 local_fiq_disable();
3794 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3795 if(ddr_freq_t.screen_ft_us > 0)
3797 ddr_freq_t.t1 = cpu_clock(0);
3798 ddr_freq_t.t2 = (uint32)(ddr_freq_t.t1 - ddr_freq_t.t0); //ns
3800 //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
3801 if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe))
3808 rk_fb_poll_wait_frame_complete();
3812 for(i=0;i<SRAM_SIZE/4096;i++)
3818 for(i=0;i<CH_MAX;i++)
3820 if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3822 n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3823 n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3824 n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3827 n= pCRU_Reg->CRU_PLL_CON[0][0];
3828 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3833 param.freq_slew = freq_slew;
3834 param.dqstr_value = dqstr_value;
3835 cru_writel(0 |CRU_W_MSK_SETBITS(0xff,8,0xff), RK3288_CRU_CLKSELS_CON(29));
3836 call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
3838 rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SZIE);
3839 cru_writel(0 |CRU_W_MSK_SETBITS(dclk_div,8,0xff), RK3288_CRU_CLKSELS_CON(29));
3840 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3844 local_irq_restore(flags);
3848 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
3849 static uint32 ddr_change_freq_gpll_dpll(uint32 nMHz)
3851 uint32 gpll_freq,gpll_div;
3852 struct ddr_freq_t ddr_freq_t;
3853 ddr_freq_t.screen_ft_us = 0;
3855 if(true == ddr_rk3188_dpll_is_good)
3857 gpllvaluel = ddr_get_pll_freq(GPLL);
3859 if((200 < gpllvaluel) ||( gpllvaluel <1600)) //GPLL:200MHz~1600MHz
3861 gpll_div = (gpllvaluel+nMHz-1)/nMHz;
3862 if( gpllvaluel > 800) //800-1600MHz /4:200MHz-400MHz
3864 gpll_freq = gpllvaluel/4;
3867 else if( gpllvaluel > 400) //400-800MHz /2:200MHz-400MHz
3869 gpll_freq = gpllvaluel/2;
3872 else //200-400MHz /1:200MHz-400MHz
3874 gpll_freq = gpllvaluel;
3878 *p_ddr_select_gpll_div=gpll_div; //select GPLL
3879 ddr_change_freq_sram(gpll_freq,ddr_freq_t);
3880 *p_ddr_select_gpll_div=0;
3882 p_ddr_set_pll(nMHz,0); //count DPLL
3883 p_ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3887 ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3891 return ddr_change_freq_sram(nMHz,ddr_freq_t);
3896 static int _ddr_change_freq(uint32 nMHz)
3898 struct ddr_freq_t ddr_freq_t;
3901 ddr_freq_t.screen_ft_us = 0;
3904 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3907 if(rk_fb_poll_wait_frame_complete() == true)
3909 ddr_freq_t.t0 = cpu_clock(0);
3910 ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
3913 if(test_count > 10) //test 10 times
3915 ddr_freq_t.screen_ft_us = 0xfefefefe;
3917 usleep_range(ddr_freq_t.screen_ft_us-test_count*1000,ddr_freq_t.screen_ft_us-test_count*1000);
3923 }while(ddr_change_freq_sram(nMHz, ddr_freq_t)==0);
3925 return ddr_change_freq_sram(nMHz, ddr_freq_t);
3929 static long _ddr_round_rate(uint32 nMHz)
3931 return p_ddr_set_pll(nMHz, 0);
3934 static void _ddr_set_auto_self_refresh(bool en)
3936 //set auto self-refresh idle
3937 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
3940 #define PERI_ACLK_DIV_MASK 0x1f
3941 #define PERI_ACLK_DIV_OFF 0
3943 #define PERI_HCLK_DIV_MASK 0x3
3944 #define PERI_HCLK_DIV_OFF 8
3946 #define PERI_PCLK_DIV_MASK 0x3
3947 #define PERI_PCLK_DIV_OFF 12
3948 static __sramdata u32 cru_sel32_sram;
3949 static void __sramfunc ddr_suspend(void)
3954 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3957 pll_id=GET_DDR_PLL_SRC();
3958 /** 1. Make sure there is no host access */
3963 for(i=0;i<SRAM_SIZE/4096;i++)
3969 n= pDDR_Reg->SCFG.d32;
3971 n= pCRU_Reg->CRU_PLL_CON[0][0];
3972 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3973 n= *(volatile uint32_t *)SysSrv_DdrConf;
3977 ddr_selfrefresh_enter(0);
3979 SET_PLL_MODE(pll_id, 0); //PLL slow-mode
3982 SET_PLL_PD(pll_id, 1); //PLL power-down
3987 cru_sel32_sram= pCRU_Reg->CRU_CLKSEL_CON[10];
3989 pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
3990 | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
3991 |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
3993 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29))); //CKOE
3997 static void __sramfunc ddr_resume(void)
4003 pll_id=GET_DDR_PLL_SRC();
4004 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29)); //CKOE
4008 pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
4010 SET_PLL_PD(pll_id, 0); //PLL no power-down
4014 if (GET_DPLL_LOCK_STATUS())
4020 SET_PLL_MODE(pll_id, 1); //PLL normal
4023 ddr_selfrefresh_exit();
4027 //pArg:Ö¸ÕëÄÚÈݱíʾpll pd or not¡£
4028 void ddr_reg_save(uint32 *pArg)
4031 pDDR_REG_T pDDR_Reg=NULL;
4032 pDDRPHY_REG_T pPHY_Reg=NULL;
4033 pMSCH_REG pMSCH_Reg;
4035 p_ddr_reg->tag = 0x56313031;
4036 if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4038 p_ddr_reg->pctlAddr[0] = RK3288_DDR_PCTL0_PHYS;
4039 p_ddr_reg->publAddr[0] = RK3288_DDR_PUBL0_PHYS;
4040 p_ddr_reg->nocAddr[0] = RK3288_SERVICE_BUS_PHYS;
4041 pDDR_Reg = p_ddr_ch[0]->pDDR_Reg;
4042 pPHY_Reg = p_ddr_ch[0]->pPHY_Reg;
4046 p_ddr_reg->pctlAddr[0] = 0xFFFFFFFF;
4047 p_ddr_reg->publAddr[0] = 0xFFFFFFFF;
4048 p_ddr_reg->nocAddr[0] = 0xFFFFFFFF;
4050 if(p_ddr_ch[1]->mem_type != DRAM_MAX)
4052 p_ddr_reg->pctlAddr[1] = RK3288_DDR_PCTL1_PHYS;
4053 p_ddr_reg->publAddr[1] = RK3288_DDR_PUBL1_PHYS;
4054 p_ddr_reg->nocAddr[1] = RK3288_SERVICE_BUS_PHYS+0x80;
4055 if((pDDR_Reg == NULL) || (pPHY_Reg == NULL))
4057 pDDR_Reg = p_ddr_ch[1]->pDDR_Reg;
4058 pPHY_Reg = p_ddr_ch[1]->pPHY_Reg;
4063 p_ddr_reg->pctlAddr[1] = 0xFFFFFFFF;
4064 p_ddr_reg->publAddr[1] = 0xFFFFFFFF;
4065 p_ddr_reg->nocAddr[1] = 0xFFFFFFFF;
4069 (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->pctl.pctl_timing.togcnt1u), (uint64_t *)&(pDDR_Reg->TOGCNT1U), 17);
4070 p_ddr_reg->pctl.SCFG = pDDR_Reg->SCFG.d32;
4071 p_ddr_reg->pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
4072 p_ddr_reg->pctl.MCFG1 = pDDR_Reg->MCFG1;
4073 p_ddr_reg->pctl.MCFG = pDDR_Reg->MCFG;
4074 p_ddr_reg->pctl.pctl_timing.ddrFreq = *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
4075 p_ddr_reg->pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
4076 p_ddr_reg->pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
4077 p_ddr_reg->pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
4078 p_ddr_reg->pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
4079 p_ddr_reg->pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
4080 p_ddr_reg->pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
4081 p_ddr_reg->pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
4082 p_ddr_reg->pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
4083 p_ddr_reg->pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
4084 p_ddr_reg->pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
4085 p_ddr_reg->pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
4086 p_ddr_reg->pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
4087 p_ddr_reg->pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
4088 p_ddr_reg->pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
4089 p_ddr_reg->pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
4091 p_ddr_reg->pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
4092 p_ddr_reg->pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
4093 p_ddr_reg->pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
4094 p_ddr_reg->pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
4095 p_ddr_reg->pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
4096 p_ddr_reg->pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
4097 p_ddr_reg->pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
4098 p_ddr_reg->pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
4099 p_ddr_reg->pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
4102 p_ddr_reg->publ.phy_timing.dtpr0.d32 = pPHY_Reg->DTPR[0];
4103 (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->publ.phy_timing.dtpr1), (uint64_t *)&(pPHY_Reg->DTPR[1]), 3);
4104 p_ddr_reg->publ.PIR = pPHY_Reg->PIR;
4105 p_ddr_reg->publ.PGCR = pPHY_Reg->PGCR;
4106 p_ddr_reg->publ.DLLGCR = pPHY_Reg->DLLGCR;
4107 p_ddr_reg->publ.ACDLLCR = pPHY_Reg->ACDLLCR;
4108 p_ddr_reg->publ.PTR[0] = pPHY_Reg->PTR[0];
4109 p_ddr_reg->publ.PTR[1] = pPHY_Reg->PTR[1];
4110 p_ddr_reg->publ.PTR[2] = pPHY_Reg->PTR[2];
4111 p_ddr_reg->publ.ACIOCR = pPHY_Reg->ACIOCR;
4112 p_ddr_reg->publ.DXCCR = pPHY_Reg->DXCCR;
4113 p_ddr_reg->publ.DSGCR = pPHY_Reg->DSGCR;
4114 p_ddr_reg->publ.DCR = pPHY_Reg->DCR.d32;
4115 p_ddr_reg->publ.ODTCR = pPHY_Reg->ODTCR;
4116 p_ddr_reg->publ.DTAR = pPHY_Reg->DTAR;
4117 p_ddr_reg->publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
4118 p_ddr_reg->publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
4120 for(ch=0;ch<CH_MAX;ch++)
4122 if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4124 pPHY_Reg = p_ddr_ch[ch]->pPHY_Reg;
4125 p_ddr_reg->dqs[ch].DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
4126 p_ddr_reg->dqs[ch].DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
4127 p_ddr_reg->dqs[ch].DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
4128 p_ddr_reg->dqs[ch].DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
4130 p_ddr_reg->dqs[ch].DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
4131 p_ddr_reg->dqs[ch].DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
4132 p_ddr_reg->dqs[ch].DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
4133 p_ddr_reg->dqs[ch].DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
4135 p_ddr_reg->dqs[ch].DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
4136 p_ddr_reg->dqs[ch].DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
4137 p_ddr_reg->dqs[ch].DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
4138 p_ddr_reg->dqs[ch].DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
4140 p_ddr_reg->dqs[ch].DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
4141 p_ddr_reg->dqs[ch].DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
4142 p_ddr_reg->dqs[ch].DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
4143 p_ddr_reg->dqs[ch].DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
4146 pMSCH_Reg= p_ddr_ch[ch]->pMSCH_Reg;
4147 p_ddr_reg->noc[ch].ddrconf = pMSCH_Reg->ddrconf;
4148 p_ddr_reg->noc[ch].ddrtiming.d32 = pMSCH_Reg->ddrtiming.d32;
4149 p_ddr_reg->noc[ch].ddrmode = pMSCH_Reg->ddrmode;
4150 p_ddr_reg->noc[ch].readlatency = pMSCH_Reg->readlatency;
4151 p_ddr_reg->noc[ch].activate.d32 = pMSCH_Reg->activate.d32;
4152 p_ddr_reg->noc[ch].devtodev = pMSCH_Reg->devtodev;
4157 p_ddr_reg->pllpdAddr = (uint32_t)pArg; //pll power-down tag addr
4158 p_ddr_reg->pllpdMask = 1;
4159 p_ddr_reg->pllpdVal = 1;
4162 p_ddr_reg->dpllmodeAddr = RK3288_CRU_PHYS + 0x50; //APCRU_MODE_CON
4163 p_ddr_reg->dpllSlowMode = ((3<<4)<<16) | (0<<4);
4164 p_ddr_reg->dpllNormalMode = ((3<<4)<<16) | (1<<4);
4165 p_ddr_reg->dpllResetAddr = RK3288_CRU_PHYS + 0x1c; //APCRU_DPLL_CON3
4166 p_ddr_reg->dpllReset = (((0x1<<5)<<16) | (0x1<<5));
4167 p_ddr_reg->dpllDeReset = (((0x1<<5)<<16) | (0x0<<5));
4168 p_ddr_reg->dpllConAddr = RK3288_CRU_PHYS + 0x10; //APCRU_DPLL_CON0
4169 p_ddr_reg->dpllCon[0] = pCRU_Reg->CRU_PLL_CON[DPLL][0] | (0xFFFF<<16);
4170 p_ddr_reg->dpllCon[1] = pCRU_Reg->CRU_PLL_CON[DPLL][1] | (0xFFFF<<16);
4171 p_ddr_reg->dpllCon[2] = pCRU_Reg->CRU_PLL_CON[DPLL][2] | (0xFFFF<<16);
4172 p_ddr_reg->dpllCon[3] = pCRU_Reg->CRU_PLL_CON[DPLL][3] | (0xFFFF<<16);
4173 p_ddr_reg->dpllLockAddr = RK3288_GRF_PHYS + 0x284; //GRF_SOC_STATUS1
4174 p_ddr_reg->dpllLockMask = (1<<5);
4175 p_ddr_reg->dpllLockVal = (1<<5);
4178 p_ddr_reg->ddrPllSrcDivAddr = RK3288_CRU_PHYS + 0xc8;
4179 p_ddr_reg->ddrPllSrcDiv = (pCRU_Reg->CRU_CLKSEL_CON[26] & 0x7) | (0x7<<16);
4181 p_ddr_reg->retenDisAddr = RK3288_PMU_PHYS+0x18; //pmu_pwrmode_con
4182 p_ddr_reg->retenDisVal = (3<<21); //OR operation
4183 p_ddr_reg->retenStAddr = RK3288_PMU_PHYS+0x1c; //pmu_pwrmode_con
4184 p_ddr_reg->retenStMask = (1<<6);
4185 p_ddr_reg->retenStVal = (0<<6);
4187 p_ddr_reg->grfRegCnt = 3;
4188 //DDR_16BIT,DDR_HW_WAKEUP,DDR_TYPE
4189 p_ddr_reg->grf[0].addr = RK3288_GRF_PHYS + 0x244;
4190 p_ddr_reg->grf[0].val = (pGRF_Reg->GRF_SOC_CON[0] & ((0x3<<8)|(0x3<<5)|(0x3<<3))) | (((0x3<<8)|(0x3<<5)|(0x3<<3))<<16);
4193 p_ddr_reg->grf[1].addr = RK3288_GRF_PHYS + 0x24c;
4194 p_ddr_reg->grf[1].val = (pGRF_Reg->GRF_SOC_CON[2] & (0x3f<<8)) | ((0x3f<<8)<<16);
4197 p_ddr_reg->grf[2].addr = RK3288_SGRF_PHYS + 0x8;
4198 p_ddr_reg->grf[2].val = READ_DDR_STRIDE() | (0x1F<<16);
4200 p_ddr_reg->endTag = 0xFFFFFFFF;
4203 __attribute__((aligned(4))) uint32 ddr_reg_resume[]=
4205 #include "ddr_reg_resume.inc"
4208 char * ddr_get_resume_code_info(u32 *size)
4210 *size=sizeof(ddr_reg_resume);
4212 return (char *)ddr_reg_resume;
4215 EXPORT_SYMBOL(ddr_get_resume_code_info);
4217 char * ddr_get_resume_data_info(u32 *size)
4219 *size=sizeof(DATA(ddr_reg));
4220 return (char *) kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4222 EXPORT_SYMBOL(ddr_get_resume_data_info);
4225 static int ddr_init(uint32 dram_speed_bin, uint32 freq)
4231 uint32 ch,cap=0,cs_cap;
4233 ddr_print("version 1.00 20140404 \n");
4235 p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4236 p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
4237 //p_cpu_pause = kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
4239 tmp = clk_get_rate(clk_get(NULL, "clk_ddr"))/1000000;
4240 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)) = tmp;
4241 *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
4243 for(ch=0;ch<CH_MAX;ch++)
4245 p_ddr_ch[ch] = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_ch[ch]));
4247 p_ddr_ch[ch]->chNum = ch;
4248 p_ddr_ch[ch]->pDDR_Reg = pDDR_REG(ch);
4249 p_ddr_ch[ch]->pPHY_Reg = pPHY_REG(ch);
4250 p_ddr_ch[ch]->pMSCH_Reg = pMSCH_REG(ch);
4252 if(!(READ_CH_INFO()&(1<<ch)))
4254 p_ddr_ch[ch]->mem_type = DRAM_MAX;
4261 ddr_print("Channel b: \n");
4265 ddr_print("Channel a: \n");
4267 tmp = p_ddr_ch[ch]->pPHY_Reg->DCR.b.DDRMD;
4268 if((tmp == LPDDR2) && (READ_DRAMTYPE_INFO() == 6))
4275 ddr_print("DDR3 Device\n");
4278 ddr_print("LPDDR3 Device\n");
4281 ddr_print("LPDDR2 Device\n");
4284 ddr_print("Unkown Device\n");
4288 p_ddr_ch[ch]->mem_type = tmp;
4291 p_ddr_ch[ch]->mem_type = DRAM_MAX;
4296 p_ddr_ch[ch]->ddr_speed_bin = dram_speed_bin;
4297 //get capability per chip, not total size, used for calculate tRFC
4298 die = (8<<READ_BW_INFO(ch))/(8<<READ_DIE_BW_INFO(ch));
4299 cap = (1 << (READ_ROW_INFO(ch,0)+READ_COL_INFO(ch)+READ_BK_INFO(ch)+READ_BW_INFO(ch)));
4301 if(READ_CS_INFO(ch) > 1)
4303 cap += cap >> (READ_ROW_INFO(ch,0)-READ_ROW_INFO(ch,1));
4305 if(READ_CH_ROW_INFO(ch))
4309 p_ddr_ch[ch]->ddr_capability_per_die = cs_cap/die;
4310 ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
4311 READ_BW_INFO(ch)*16,\
4312 READ_COL_INFO(ch), \
4313 (0x1<<(READ_BK_INFO(ch))), \
4314 READ_ROW_INFO(ch,0), \
4319 ddr_adjust_config();
4321 clk = clk_get(NULL, "clk_ddr");
4323 ddr_print("failed to get ddr clk\n");
4327 tmp = clk_set_rate(clk, 1000*1000*freq);
4329 tmp = clk_set_rate(clk, clk_get_rate(clk));
4330 ddr_print("init success!!! freq=%luMHz\n", clk ? clk_get_rate(clk)/1000000 : freq);
4332 for(ch=0;ch<CH_MAX;ch++)
4334 if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
4338 ddr_print("Channel b: \n");
4342 ddr_print("Channel a: \n");
4344 for(tmp=0;tmp<4;tmp++)
4346 gsr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXGSR[0];
4347 dqstr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXDQSTR;
4348 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=%d,%d, DGSL=%d,%d extra clock, DGPS=%d,%d\n", \
4349 (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), \
4350 ((gsr>>13)&0x7), ((gsr>>16)&0x7),\
4351 (dqstr&0x7), ((dqstr>>3)&0x7),\
4352 ((((dqstr>>12)&0x3)+1)*90), ((((dqstr>>14)&0x3)+1)*90));
4354 ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
4355 (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
4356 (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
4357 p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]&0x3,\
4358 (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
4359 (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
4360 (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>6)&0x3);
4361 ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
4362 ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>15)&0x1F);